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Hi, this is a great job. I have a question, did you use the xilinx hls tool to complete the hdl language development? If I want to migration the verilog or vhdl code to other platform such as Altera FPGA , could this code still work?
The text was updated successfully, but these errors were encountered:
Hi, this is a great job. I have a question, did you use the xilinx hls tool to complete the hdl language development? If I want to migration the verilog or vhdl code to other platform such as Altera FPGA , could this code still work?
The text was updated successfully, but these errors were encountered: