From f8a7bee61373e794a1575d99433e944d82082950 Mon Sep 17 00:00:00 2001 From: Kerry Wang Date: Fri, 1 Oct 2021 11:30:55 -0400 Subject: [PATCH] cleaned up temp files, moved ADbasic code to subfolder --- ADBASIC.BAS | 353 ------- ADWINGUI_comment.txt | Bin 3640 -> 0 bytes ADbasic/TransferData.TB1 | Bin 0 -> 5020 bytes .../TransferData.bas | 75 +- ADbasic_tester_bySeth.BAS | 45 - DDStest.arr | Bin 247786 -> 0 bytes DDStest.pan | Bin 112428 -> 0 bytes GUIDesign.c | 5 +- TransferData.TA1 | Bin 17301 -> 0 bytes TransferData.TA1.feb17 | Bin 14613 -> 0 bytes TransferData.TA1.feb20 | Bin 15489 -> 0 bytes TransferData.TA1.nogood | Bin 14247 -> 0 bytes TransferData.TA1.nov14_2005 | Bin 14247 -> 0 bytes TransferData.TA1.old.works | Bin 14613 -> 0 bytes TransferData_Apr7_2006.BAS | 347 ------- TransferData_August02_2010.BAK | 353 ------- TransferData_August02_2010.TB1 | Bin 5228 -> 0 bytes TransferData_August02_2010.bas | 353 ------- TransferData_FEB17_2006.BAS | 346 ------- TransferData_July14_2009.TB1 | Bin 6940 -> 0 bytes TransferData_July14_2009.bas | 343 ------- TransferData_July2_2009.TB1 | Bin 6940 -> 0 bytes TransferData_July6_2009.TB1 | Bin 6940 -> 0 bytes TransferData_June19_2009.TB1 | Bin 6940 -> 0 bytes TransferData_June30_2006.BAS | 347 ------- TransferData_June30_2006.TA1 | Bin 17301 -> 0 bytes TransferData_May25_2012.BAK | 353 ------- TransferData_May25_2012.TB1 | Bin 4908 -> 0 bytes TransferData_Nov7_2005.BAS | 322 ------- TransferData_tmp.TA1 | Bin 14079 -> 0 bytes davetest.arr | Bin 243941 -> 0 bytes davetest.pan | Bin 112496 -> 0 bytes ddstranslator.c.bak | 912 ------------------ dtcon.config | 72 -- dtex.export | 69 -- lasttest.pan | Bin 33752 -> 0 bytes optimizeadwin.ABP | 3 - 37 files changed, 41 insertions(+), 4257 deletions(-) delete mode 100644 ADBASIC.BAS delete mode 100644 ADWINGUI_comment.txt create mode 100644 ADbasic/TransferData.TB1 rename TransferData_May25_2012.bas => ADbasic/TransferData.bas (86%) delete mode 100644 ADbasic_tester_bySeth.BAS delete mode 100644 DDStest.arr delete mode 100644 DDStest.pan delete mode 100644 TransferData.TA1 delete mode 100644 TransferData.TA1.feb17 delete mode 100644 TransferData.TA1.feb20 delete mode 100644 TransferData.TA1.nogood delete mode 100644 TransferData.TA1.nov14_2005 delete mode 100644 TransferData.TA1.old.works delete mode 100644 TransferData_Apr7_2006.BAS delete mode 100644 TransferData_August02_2010.BAK delete mode 100644 TransferData_August02_2010.TB1 delete mode 100644 TransferData_August02_2010.bas delete mode 100644 TransferData_FEB17_2006.BAS delete mode 100644 TransferData_July14_2009.TB1 delete mode 100644 TransferData_July14_2009.bas delete mode 100644 TransferData_July2_2009.TB1 delete mode 100644 TransferData_July6_2009.TB1 delete mode 100644 TransferData_June19_2009.TB1 delete mode 100644 TransferData_June30_2006.BAS delete mode 100644 TransferData_June30_2006.TA1 delete mode 100644 TransferData_May25_2012.BAK delete mode 100644 TransferData_May25_2012.TB1 delete mode 100644 TransferData_Nov7_2005.BAS delete mode 100644 TransferData_tmp.TA1 delete mode 100644 davetest.arr delete mode 100644 davetest.pan delete mode 100644 ddstranslator.c.bak delete mode 100644 dtcon.config delete mode 100644 dtex.export delete mode 100644 lasttest.pan delete mode 100644 optimizeadwin.ABP diff --git a/ADBASIC.BAS b/ADBASIC.BAS deleted file mode 100644 index 1ad4195..0000000 --- a/ADBASIC.BAS +++ /dev/null @@ -1,353 +0,0 @@ -**************************************** -* Prozeßnummer = 1 -* Delay = 1000 -* Eventsource = 0 -* Number of Loops = 0 -* Priorität = 0 -* Version = 1 -* FastStop = 0 -* AdbasicVersion = 4000001 -* ATSRAM = 0 -* OPT_LEVEL = 0 -* SAVECOMPIL = 0 -**************************************** -#include ADwpad.inc -#include Adwpda.inc -#include Adwpdio.inc -#include adwinpro.inc -dim i,j,k,lightcount,litup,eventcount,delaymultinuse as long -dim DATA_1[5000000] as long -dim DATA_2[5000000] as long -dim data_3[5000000] as float -dim data_4[100] as long ' a list of which channels are reset to zero on completion -dim value as float -dim counts,maxcount,updates,i,j,k as long -dim ch as long -dim val,val_lower,val_upper,val_lower2,val_upper2 as long -dim tempval as long -dim dataline,clock, ioupdate,ioreset,masterreset as long -dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long -dim digitallow as long -dim delay,delayinuse as long -dim numbertoskip as long -dim leddelay as float -dim digitalactive,digital2active as long - -Function V(value) as float - V=(value+10)/20*65535 -ENDFUNCTION - -SUB Light_LED(lit) as - SELECTCASE lit - CASE 1 - SETLED(2,da,0) - SETLED(1,dio,1) - CASE 2 - SETLED(1,dio,0) - SetLED(2,dio,1) - CASE 3 - SETLED(2,dio,0) - SETLED(3,ext,1) - CASE 4 - SETLED(3,ext,0) - SETLED(4,ad,1) - CASE 5 - SETLED(4,ad,0) - SETLED(1,da,1) - CASE 6 - SETLED(1,da,0) - SETLED(2,da,1) - CASE 8 - SETLED(2,da,0) - SETLED(1,da,1) - CASE 9 - SETLED(1,da,0) - SetLED(4,ad,1) - CASE 10 - SETLED(4,ad,0) - SETLED(3,ext,1) - CASE 11 - SETLED(3,ext,0) - SETLED(2,dio,1) - CASE 12 - SETLED(2,dio,0) - SETLED(1,dio,1) - CASE 13 - SETLED(1,dio,0) - 'SETLED(2,da,1) - ENDSELECT -ENDSUB - - - -INIT: - -'Jan 16/2004 -'expecting 3 arrays. -'Data_1: A list which specifies how many channels will be updated per event -'Data_2: A list of channels to be updates -'Data_3: A list of values for the channels - -'Data_2 and Data_3 have a 1:1 correspondence. -'Stepping through data2 and 3 is controlled by Data 1 -'Computer send an integer to Par_1. This tells us how many -'events to write. ) -'Channels 1-32 refer to Analog output lines -'Channel 101,102 refers to Digital output lines (16 bit word x2) -'Channel 103,104 refer to Digital output lines (16 bit word X2) -'channel 51-53 refers to digital output lines controlling the DDS -'DDS control lines are digital output lines -'Data line, read clock, io update , reset -' 0-3 data -' 4 I/O reset -' 5 update clock -' 6 master Reset -' 7 (maybe) RF switch -delay=PAR_2 ' 40000=>1ms -GlobalDelay=delay -'DDS digital line setup -dataline=31 ' data line -clock=30 ' data clock -ioupdate=29 ' update line. transfers data from buffer into registers -ioreset=28 ' resets input buffers -masterreset=27 - -'DDS2 digital lines (base 0) -dataline9858=21 -clock9858=22 -ioupdate9858=19 -'ioreset9858=23 -masterreset9858=18 - -DigProg1(1,65535) -DigProg2(1,65535) -DigProg1(2,65535) -DigProg2(2,65535) -DigProg1(3,65535) -DigProg2(3,65535) -'Configure cards for synchronous output -SYNCENABLE(1,dio,1) -SYNCENABLE(2,dio,1) -SYNCENABLE(3,dio,1) - -SYNCENABLE(1,da,1) -SYNCENABLE(2,da,1) -SYNCENABLE(3,da,1) -SYNCENABLE(4,da,1) - -numbertoskip=0 -counts=1 -maxcount=Par_1 -updates=1 -lightcount=0 -eventcount=0 -leddelay=8000000/GLOBALDELAY -Par_11=Data_1[1] -Par_12=Data_1[2] -Par_13=Data_1[3] -FPar_11=Data_2[1] -FPar_12=Data_2[2] -FPar_13=Data_2[3] -' Make sure the DDS lines are low. -DIGOUT_F(2,clock,0) -DIGOUT_F(2,dataline,0) -DIGOUT_F(2,ioreset,0) -DIGOUT_F(2,ioupdate,0) -DIGOUT_F(2,masterreset,0) - - -EVENT: -SYNCALL() 'Force synchronized output now. We are sending out the data programmed in the last cycle. -' THis way all the outputs are updated at the beginning of an event, which is well timed. -' Doing Syncall() at the end of an event causes the channel outputs to move around in time, depending on how many channels -' are being programmed. - -eventcount=eventcount+delaymultinuse -if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) -endif - -delayinuse=delay ' reset the GlobalDelay -if(Data_1[counts]<0) then ' if we see a negative number, interpret it as a multiplicative factor on the delay - delayinuse=delay*(-1*Data_1[counts]) - delaymultinuse=-1*Data_1[counts] -endif -GLOBALDELAY=delayinuse - - -' reset the variables controlling digital output. -digitalactive=0 -digital2active=0 -val_lower=0 -val_upper=0 -val_lower2=0 -val_upper2=0 -counts=counts+1 'Number of events so far - - -IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each elementof DATA_1 for an update - For i=1 to Data_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=Data_2[updates] - - '*****************Analog outs*********************** - if((ch>=1) and (ch<=32)) then - AnalogWrite(ch,Data_3[updates]) - endif - - '*****************DDS outs************************* - if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS1 - DDS1Write(Data_3[updates]) - endif - - if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS2 - DDS2Write(Data_3[updates]) - ENDIF 'end BB - - '***********************Digital outs********** - if(ch=101) then - val_lower=Data_3[updates] - DIG_WRITELATCH32(2,val_lower) - endif - - if(ch=102) then - val_upper=Data_3[updates] - DIG_WRITELATCH32(3,val_upper) - endif - - NEXT i 'B for loop -ENDIF 'A: -If(counts>=maxcount+1) then end - - -FINISH: -'Clear all channels -Par_3=counts -Par_4=maxcount - -'If (Data_4[27]=0) then - For i= 1 to 8 - if(Data_4[i]=1) then - WRITEDAC(1,i,V(0)) - ENDIF - if(Data_4[i+8]=1) then - WRITEDAC(2,i,V(0)) - ENDIF - if(Data_4[i+16]=1) then - WRITEDAC(3,i,V(0)) - ENDIF - if(Data_4[i+24]=1) then - WRITEDAC(4,i,V(0)) - ENDIF - Next i - 'set line 28 high... forget why... - DIG_WRITELATCH32(2,2^28) -'ENDIF - -Par_21=Data_4[16] -Par_20=1 -if(Data_4[16]=0) then - WRITEDAC(2,8,V(0)) -endif - -SYNCALL() - -'*************************************************** -SUB AnalogWrite(achannel, avalue) - if((achannel>=1)and(achannel<=8)) then - writedac(1,achannel,V(avalue)) - endif - - if((achannel>=9)and(achannel<=16)) then - writedac(2,achannel-8,V(avalue)) - endif - - if((achannel>=17)and(achannel<=24)) then - writedac(3,achannel-16,V(avalue)) - endif - - if((achannel>=25)and(achannel<=32)) then - writedac(4,achannel-24,V(avalue)) - endif -ENDSUB -'*************************************************** -SUB DDS1Write(digvalue) - dim tempval as long - dim dataline,clock,ioupdate,ioreset,masterreset as long - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - if(digvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = digvalue 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - ELSE - IF(digvalue=4) then 'write to the i/o reset pin to reset the buffer. - 'DIGOUT_F(2,ioreset,1) ' Currently disabled - 'DIGOUT_F(2,ioreset,0) - Else - IF(digvalue=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(digvalue=6) then - DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif -ENDSUB -'*************************************************** -SUB DDS2WRITE(dvalue) - dim tempval as long - dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - if(dvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = dvalue 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - ELSE - IF(dvalue=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 'DIGOUT_F(2,ioreset9858,0) - Else - IF(dvalue=5) then - DIGOUT_F(2,ioupdate9858,1) - DIGOUT_F(2,ioupdate9858,0) - Else - IF(dvalue=6) then - DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) - ENDIF - endif - endif - endif -ENDSUB diff --git a/ADWINGUI_comment.txt b/ADWINGUI_comment.txt deleted file mode 100644 index 6e43faf1248704d89a75f44f31745ef96f73ce64..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3640 zcmbVPQE%He5Z-fv{)c;8yN5JRnht2u2Srw0W3rUla*F{10$QSMt}?7N)M^`sjY0it{lAa}#>(S-)^|!Q8(wJ3= zFPCYd_d@Hm$TqCf++2cJ30A)Q{{8v0Z|NWDnoC|Wqbiu`!th)exVd;ex)|Ny|K;_& z@9Bf!`!7P~uhTjkr8`#T&g~VtlB`r~AEQ;OyvS(q`Lp+(KW9nn5*GEUQneA1>$j~{ zD#^j0jqevh;zeHQ#glvA3&UH_{|f+8!&Y#|BrjoA8zsRgz%2l?VIgORK~bqKm<@-l zt|~6g;j?^%Tv>h{I%XP+Rg@P3aw%b)|hxi+7v1xafx43}M$`bRQ zH;5sC1l1v-!>65wxj}=hTfg9@sfdN{#e)+0%fk}8AA&lbB;IX!-0WMJET?0x#adz^ z33x1hN!9snW1Dhp682N@S3^a(lmbhEEhsYT)b3dO-gks) zCDU23z;+7SN#ra!aFVPbpU4Zx9Oxa`I*l4n4n7gI?Uu=$I<(WGjyH!%Cq=cHI?GtB zg<<7AQWlkAt%oG!y_@QlrP^zFRJCox4Qd_rA;&hZu-1lG8dL!cscL-!>Yc;}e^sL7 zTyzsaWbVh)$$dDDj`VLcB~W_BasidnL<$rvl7S7+zPuu}be;(s^oi0HfA&9m(d67S zgs5DU)EfHX`eV`>)vf+=*8CpsnHix3L;#JeMNR8&){tp-uBYKfKQsw4MYSEsNcCd5TdGggQ{ks;1j`bDGzBo&$SdP21oqn{0 zOq)~df<5q4%g_PdB*@Jjo;U8xxMKT=?~~)Xn#7Yy7>tgcZ8zbpSA*8;LF?;5>&>9` z&7k$qp4BHs^)e$KIBlR&BUGW&Yl_<#ooqvPl3_eQd#>lTjAhnff>RbreAk;o4(C1F zVj~K?NtN|hx~P79_m3Zk%UM6bowrDW!4bF6J!hz4g9qFb#Br;r_#R1Hg9wqP`yDBj zeaPe|x~I7nx3ws9*LNY_VY(?a?|7}6aasSa5BEyT0!J#8jUEnIgK6T0=L54KTK48z z(>SwVj*bI$`-Bs!G>(O|rpO?d&>%F=!pvaoymRb{I&b@nfZ+ z360St=Q=mr^^#UjKcr4d+O>72w3)Wr?FK7V7eqD2D5FCB0U@XaNRtpED+~?LYMyiN zb@8%nUB#bW<@Nb^&--=G`#$&FP(sN3tLq3wdx+r&PY5K(O&}Mj{9Hh%9pnd9&PTBL zjGK_>F#j4zK2mUP#>IX!S1-N1L`}7vp$ERdp?bG&LYl#qlP}?BeeE9VU3-W1)mzHyi zS}I{I@=dX%TBrG~xjK6e;}$tKldzQ>p~YtSkbwRKf5y_0aP)7r*Ug6CNVBc{xWlvb zlX`ocZ%Uk1RgF~I#MtudJ^Ht1TA;)Bf2*Uv&t5khepSY1`@dDQ_1D?seAA{!)u7{l z(D6UGg#Ufe-{<&W-k(I-f9y}f@xRZ}|3CkWAH{#><+Cz=?9)c*vie4X--&*{a$gWL zRg;c?A?$C+-rpPY!OTXSl`S9S8_>7qgSKBcWK)n$Es{;>=PPWlU2OY??9z76SJ+*B zYj#H~?Y7^VU8B-&%SW`ElY43;`2b01MAn&+;JYv$G`##PpqmHg3|nd%A6Exh%+xrM^zQ$6R=eo+56ms$VNA!(oL z+B(>FiD)aG4HpDzyhi#W8d_cX@Nef?gSOln_qMuc!!JI=dNr>c2aap&uR$&sYNa#D zKN94?V{$$hYjvGUzC6!jBad6-aI1R;{<84MUOCPl74(b=>;onVV3HpgB!EFVV9>KK zjT}>Gm^^<8d|;OVb_IZCI|1~7 zN*U|cNUR&*>{=`FkU?jjJoHbAi468nUv#~s9;m5kB}@QpR?BI)Ngs6h2!?RtS-JWIZCVGe^tRnJcy?%J1VF(?k2D6 zIv>zS`L3)X=!DCySaEjKe-WHn5ocGK4+Qxj&xjChojivlZb92a#4Y!MxU|6Oi|$tn zgXFdiaY6<{a3W5(g z`d12?54l%%LA^ZZLcH`u4m!(vCZVS+PoEmO6aKo*MnU~yt@AtRPb|OP=3YJ1cn#WQsZDud{|>jg&tOonudZRV^r`%Vty%nM2sG9mt1TxldgY zLM}!54&>PmoD)T!y?`}4=y6THp9%73$K=UYHG9IROpA8Xbw7N_i`wZ+?X^?PtsIQB zle5ZI0{v;J-^$&n%-u}H>Ti*KJ#tpo*n9YT1wXR{zfyj53I1q>ys-q|sNny<_HQPC zGy6C5|7P(oZQt6{Eu~T}PT3s0e_@W@HOZXX&h^Q;?zfCMe+Xy8P(yS~=PBXigSb=C zyu=eP9|T6P$2q(73?CFx$|O$X{2xaB)7cQ+S7;>+{T8d=M(XwB{Nd~gu?uO=3XJ?a zdr}OdUsYhV20Bs`t~LrxNCol^{>%V>Mp=zdxT-4g^(|NF_wXyY$d2OJ2|ISGEju3K zamIdYTtzHw#ccaVYzTMUp=9;w@lvsq5Z&MpSC2s+H}zB73O}8wax43Ls%m6i z8PR5j7=Ccm7-I0H&+#R0`(ni;V@NnL$e3gdNwhbQVJ+V8P7LRNHMj8NUz_os5Q{o7 zM2A8~bSPdKLw2n6PW2PejW3c@+g^ThLUAh-%aoe^J(?{E?2kEl^i;G2fx+pLcH?e};=x&HQt=-O@8W|q>m`vY|S+4Po5_?`^N_Y`z{ zI+W|Ie1D_3m&y46?p>&9!pL>cp~!X5>6i94pDynGgCKl>5zU1)R8YQ)QOzy;*&J{( z2mCsNZ!3uf1)iGB`P;IS^1k73D-iNoy~tD9vqG5)1XnHMJz(+92|swNCC`ybS@SQ7 z5a!oZ%zsmdtqK1I%Vzd~P<+DQF7Kbf$Ezk0)Ov>!`!2Xjev?PUN(Fb-yvx3)%C)QT zZEki8kBq$>|F`=~Z~uJz-%8`CZNwSq#2&0}DqTI&9bUcs!5oqIVM2!A%|(Xam3Q9) z?kpw+9um3Uu4SbgHTwlYl!%QBEaKF7WXNkohCW|C>EP4>o~k}5>s#WKxokoWwC|6r ztE}4YX>I{dox26y3Uo)R4>-CHLieFEc0hN1aMk{J{pt$c`CHJz1{=r0#>a zpqoJV-S5{eYwP{GJCstU^1SLV4AZfxVamub@^sj<{*oZ$_+N@4hO0ffVc+31Xb%ks z4xbzL(P{f`mYw!(^c>}lhcEJQIo}2HeB3$rHO0Nn<4NH``^q@ZyaQ)k&X4kX1MBHg zN8eH3y`z!)R?wsOHBMf=i)iZ^MESX$u*L8fy%OPI-S3x{V($9sOA6w literal 0 HcmV?d00001 diff --git a/TransferData_May25_2012.bas b/ADbasic/TransferData.bas similarity index 86% rename from TransferData_May25_2012.bas rename to ADbasic/TransferData.bas index 6c89f00..cbdeee6 100644 --- a/TransferData_May25_2012.bas +++ b/ADbasic/TransferData.bas @@ -5,9 +5,10 @@ ' Control_long_Delays_for_Stop = No ' Priority = High ' Version = 1 -' ADbasic_Version = 5.0.5 +' ADbasic_Version = 6.3.1 ' Optimize = No -' Info_Last_Save = ORCHID ORCHID\labadmin +' Stacksize = 1000 +' Info_Last_Save = NIGHTSHADE NIGHTSHADE\labadmin '
#include ADwinPRO_ALL.inc 'Updated to new ADbasic code - Ben Sofka @@ -15,9 +16,9 @@ dim i,j,k,lightcount,litup,eventcount,delaymultinuse as long dim DATA_1[5000000] as long dim DATA_2[5000000] as long dim DATA_3[5000000] as float -dim DATA_4[100] as long ' a list of which channels are reset to zero on completion +dim DATA_4[100] as long ' a list of which channels are reset to zero on completion dim value as float -dim counts,maxcount,updates,i,j,k as long +dim counts,maxcount,updates as long dim ch as long dim val,val_lower,val_upper,val_lower2,val_upper2 as long dim tempval as long @@ -37,8 +38,8 @@ SUB Light_LED(lit) as SELECTCASE lit CASE 1 P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 2 + P2_SET_LED(1,1) + CASE 2 P2_SET_LED(1,0) P2_SET_LED(2,1) CASE 3 @@ -55,7 +56,7 @@ SUB Light_LED(lit) as P2_SET_LED(2,1) CASE 8 P2_SET_LED(2,0) - P2_SET_LED(1,1) + P2_SET_LED(1,1) CASE 9 P2_SET_LED(1,0) P2_SET_LED(4,1) @@ -102,10 +103,10 @@ INIT: delay=PAR_2 ' 300000=>1ms for T11 Processor: Updated July 14 2009 - Ben Sofka PROCESSDELAY=delay 'DDS digital line setup - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers + dataline=31 ' data line + clock=30 ' data clock + ioupdate=29 ' update line. transfers data from buffer into registers + ioreset=28 ' resets input buffers masterreset=27 'DDS2 digital lines (base 0) @@ -170,12 +171,12 @@ EVENT: eventcount=eventcount+delaymultinuse if(eventcount>leddelay) then - eventcount=0 + eventcount=0 if(litup=14) then litup=0 endif litup=litup+1 - Light_LED(litup) + Light_LED(litup) endif delayinuse=delay ' reset the PROCESSDELAY @@ -204,19 +205,19 @@ EVENT: updates=updates+1 ch=DATA_2[updates] - '*****************Analog outs*********************** + '*****************Analog outs*********************** if((ch>=1) and (ch<=32)) then AnalogWrite(ch,DATA_3[updates]) endif - + '*****************DDS outs************************* 'if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS1 ' DDS1Write(DATA_3[updates]) - 'endif - + 'endif + 'if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS2 ' DDS2Write(DATA_3[updates]) - 'ENDIF 'end BB + 'ENDIF 'end BB '***********************Digital outs********** if(ch=101) then @@ -228,9 +229,9 @@ EVENT: val_upper=DATA_3[updates] DIG_WRITELATCH32(2,val_upper) ' Seth Aubin, Aug. 2, 2010: "3" -->"2" endif - - NEXT i 'B for loop - ENDIF 'A: + + NEXT i 'B for loop + ENDIF 'A: If(counts>=maxcount+1) then end @@ -242,16 +243,16 @@ FINISH: 'If (Data_4[27]=0) then For i= 1 to 8 if(DATA_4[i]=1) then - P2_WRITE_DAC(1,i,V(0)) + P2_WRITE_DAC(1,i,V(0)) ENDIF if(DATA_4[i+8]=1) then - P2_WRITE_DAC(2,i,V(0)) + P2_WRITE_DAC(2,i,V(0)) ENDIF if(DATA_4[i+16]=1) then - P2_WRITE_DAC(3,i,V(0)) + P2_WRITE_DAC(3,i,V(0)) ENDIF if(DATA_4[i+24]=1) then - P2_WRITE_DAC(4,i,V(0)) + P2_WRITE_DAC(4,i,V(0)) ENDIF Next i @@ -268,15 +269,15 @@ SUB AnalogWrite(achannel, avalue) if((achannel>=1)and(achannel<=8)) then P2_WRITE_DAC(1,achannel,V(avalue)) endif - + if((achannel>=9)and(achannel<=16)) then P2_WRITE_DAC(2,achannel-8,V(avalue)) endif - + if((achannel>=17)and(achannel<=24)) then P2_WRITE_DAC(3,achannel-16,V(avalue)) endif - + if((achannel>=25)and(achannel<=32)) then P2_WRITE_DAC(4,achannel-24,V(avalue)) endif @@ -285,12 +286,12 @@ ENDSUB SUB DDS1Write(digvalue) dim tempval as long dim dataline,clock,ioupdate,ioreset,masterreset as long - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers + dataline=31 ' data line + clock=30 ' data clock + ioupdate=29 ' update line. transfers data from buffer into registers + ioreset=28 ' resets input buffers masterreset=27 - if(digvalue<=3) then ' write 2 bits to the data line of the DDS + if(digvalue<=3) then ' write 2 bits to the data line of the DDS tempval = digvalue 'have to convert to long first ' on Mar 25, we added opto-couplers to the DDS interfacing ' this adds a 500ns (roughly) delay to each update @@ -315,8 +316,8 @@ SUB DDS1Write(digvalue) IF(digvalue=6) then DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) + DIGOUT_F(2,masterreset,0) + DIGOUT_F(2,masterreset,0) ENDIF endif endif @@ -332,7 +333,7 @@ SUB DDS2WRITE(dvalue) ioupdate9858=19 'ioreset9858=23 masterreset9858=18 - if(dvalue<=3) then ' write 2 bits to the data line of the DDS + if(dvalue<=3) then ' write 2 bits to the data line of the DDS tempval = dvalue 'have to convert to long first DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) DIGOUT_F(2,clock9858,1) @@ -351,7 +352,7 @@ SUB DDS2WRITE(dvalue) Else IF(dvalue=6) then DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) + DIGOUT_F(2,masterreset9858,0) ENDIF endif endif diff --git a/ADbasic_tester_bySeth.BAS b/ADbasic_tester_bySeth.BAS deleted file mode 100644 index cbcb5f4..0000000 --- a/ADbasic_tester_bySeth.BAS +++ /dev/null @@ -1,45 +0,0 @@ -**************************************** -* Prozeßnummer = 1 -* Delay = 1000 -* Eventsource = 0 -* Number of Loops = 0 -* Priorität = 0 -* Version = 1 -* FastStop = 0 -* AdbasicVersion = 4000001 -* ATSRAM = 0 -* OPT_LEVEL = 1 -* SAVECOMPIL = 0 -**************************************** -#include ADwpad.inc -#include Adwpda.inc -#include Adwpdio.inc -#include adwinpro.inc - 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processnum = Load_Process("TransferData_May25_2012.TB1"); //Updated May 25, 2012 - Seth Aubin + Load_Process("ADbasic\\TransferData.TB1"); didprocess = 1; } @@ -737,9 +737,10 @@ void BuildUpdateList(double TMatrix[], struct AnalogTableValues AMat[NUMBERANALO // more debug info tstop = clock(); timeused = tstop - tstart; - Start_Process(processnum); sprintf(buff, "Time to transfer and start ADwin: %d", timeused); + Start_Process(1); // start the process on ADwin + GetMenuBarAttribute(menuHandle, MENU_PREFS_STREAM_SETTINGS, ATTR_CHECKED, &StreamSettings); if (StreamSettings == TRUE) { diff --git a/TransferData.TA1 b/TransferData.TA1 deleted file mode 100644 index 3a85e9bd75fa3f3a1a36e3d6c7ca4b2b8c255633..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 17301 zcmeHPU2Ggz6+ZXQ+73>r*N)S)Y0|DYP6;W6q@<)ju-&9_DQzez4Fy`Dfi`K0sN@z@ zcuFUEp@lv~f(l-c##MNUgec;LAGPEO^#MTALMW~VLI(YZhrx3 z(z{`J-;4HFotB{DS+4gihds+TJj+X+7Qgi1Y^P6Un`gP-vpnNjUhph`>$Lc#D?eZi z98L<@8v$wHc!4q!*-ZOY^jS~)mDDezzKQzf)HhP!K>Z5pkchL6I_^ThlsY~IeJyoF zgFZ#Qrn-Ryo`-0Mj6~*Z;iLqsY9X*~r#!^FlDVAcLG{dDag1nI;2#;3QbBvD7W#

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z1C@|f!y7W%Pab3$$WBr3br^De>D9kw%qS9M`S^`F@kng>V^-!WvUf9)Lym;Ke=*NF z0DH`A49nh+GiKJ9y_?7$_?wh11W5v)eT57W`}`&fF+xPoC%grycD=0evee}dgwHA?i%HIZk3GWNYri7)iW6> zvWsH}GO=8F{Z$X=qrz1W8Ip9>(5WYuw1VI+O7buYjZC>aFAoa&@`#SG19F)gG9u8IDc;mE4pL>1W17 zJ}(RBIhW$z_vGYxk?&B3PKIh(q`pY~0(Fbu)`?tjmYi?yo|rvyZ?c|I1ms -GlobalDelay=delay -'DDS digital line setup -dataline=31 ' data line -clock=30 ' data clock -ioupdate=29 ' update line. transfers data from buffer into registers -ioreset=28 ' resets input buffers -masterreset=27 - -'DDS2 digital lines (base 0) -dataline9858=21 -clock9858=22 -ioupdate9858=19 -'ioreset9858=23 -masterreset9858=18 - -DigProg1(1,65535) -DigProg2(1,65535) -DigProg1(2,65535) -DigProg2(2,65535) -DigProg1(3,65535) -DigProg2(3,65535) -'Configure cards for synchronous output -SYNCENABLE(1,dio,1) -SYNCENABLE(2,dio,1) -SYNCENABLE(3,dio,1) - -SYNCENABLE(1,da,1) -SYNCENABLE(2,da,1) -SYNCENABLE(3,da,1) -SYNCENABLE(4,da,1) - -numbertoskip=0 -counts=1 -maxcount=Par_1 -updates=1 -lightcount=0 -eventcount=0 -leddelay=8000000/GLOBALDELAY -Par_11=Data_1[1] -Par_12=Data_1[2] -Par_13=Data_1[3] -FPar_11=Data_2[1] -FPar_12=Data_2[2] -FPar_13=Data_2[3] -' Make sure the DDS lines are low. -DIGOUT_F(2,clock,0) -DIGOUT_F(2,dataline,0) -DIGOUT_F(2,ioreset,0) -DIGOUT_F(2,ioupdate,0) -DIGOUT_F(2,masterreset,0) - - -EVENT: -SYNCALL() 'Force synchronized output now. We are sending out the data programmed in the last cycle. -' THis way all the outputs are updated at the beginning of an event, which is well timed. -' Doing Syncall() at the end of an event causes the channel outputs to move around in time, depending on how many channels -' are being programmed. - -eventcount=eventcount+delaymultinuse -if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) -endif - -delayinuse=delay ' reset the GlobalDelay -if(Data_1[counts]<0) then ' if we see a negative number, interpret it as a multiplicative factor on the delay - delayinuse=delay*(-1*Data_1[counts]) - delaymultinuse=-1*Data_1[counts] -endif -GLOBALDELAY=delayinuse - - -' reset the variables controlling digital output. -digitalactive=0 -digital2active=0 -val_lower=0 -val_upper=0 -val_lower2=0 -val_upper2=0 -counts=counts+1 'Number of events so far - - -IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each elementof DATA_1 for an update - For i=1 to Data_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=Data_2[updates] - - '*****************Analog outs*********************** - if((ch>=1) and (ch<=32)) then - AnalogWrite(ch,Data_3[updates]) - endif - - '*****************DDS outs************************* - if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS1 - DDS1Write(Data_3[updates]) - endif - - if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS2 - DDS2Write(Data_3[updates]) - ENDIF 'end BB - - '***********************Digital outs********** - if(ch=101) then - val_lower=Data_3[updates] - DIG_WRITELATCH32(2,val_lower) - endif - - if(ch=102) then - val_upper=Data_3[updates] - DIG_WRITELATCH32(3,val_upper) - endif - - NEXT i 'B for loop -ENDIF 'A: -If(counts>=maxcount+1) then end - - -FINISH: -'Clear all channels -Par_3=counts -Par_4=maxcount - -'If (Data_4[27]=0) then - For i= 1 to 8 - if(Data_4[i]=1) then - WRITEDAC(1,i,V(0)) - ENDIF - if(Data_4[i+8]=1) then - WRITEDAC(2,i,V(0)) - ENDIF - if(Data_4[i+16]=1) then - WRITEDAC(3,i,V(0)) - ENDIF - if(Data_4[i+24]=1) then - WRITEDAC(4,i,V(0)) - ENDIF - Next i - 'set line 28 high... forget why... - DIG_WRITELATCH32(2,2^28) -'ENDIF - -SYNCALL() - -'*************************************************** -SUB AnalogWrite(achannel, avalue) - if((achannel>=1)and(achannel<=8)) then - writedac(1,achannel,V(avalue)) - endif - - if((achannel>=9)and(achannel<=16)) then - writedac(2,achannel-8,V(avalue)) - endif - - if((achannel>=17)and(achannel<=24)) then - writedac(3,achannel-16,V(avalue)) - endif - - if((achannel>=25)and(achannel<=32)) then - writedac(4,achannel-24,V(avalue)) - endif -ENDSUB -'*************************************************** -SUB DDS1Write(digvalue) - dim tempval as long - dim dataline,clock,ioupdate,ioreset,masterreset as long - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - if(digvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = digvalue 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - ELSE - IF(digvalue=4) then 'write to the i/o reset pin to reset the buffer. - 'DIGOUT_F(2,ioreset,1) ' Currently disabled - 'DIGOUT_F(2,ioreset,0) - Else - IF(digvalue=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(digvalue=6) then - DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif -ENDSUB -'*************************************************** -SUB DDS2WRITE(dvalue) - dim tempval as long - dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - if(dvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = dvalue 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - ELSE - IF(dvalue=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 'DIGOUT_F(2,ioreset9858,0) - Else - IF(dvalue=5) then - DIGOUT_F(2,ioupdate9858,1) - DIGOUT_F(2,ioupdate9858,0) - Else - IF(dvalue=6) then - DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) - ENDIF - endif - endif - endif -ENDSUB diff --git a/TransferData_August02_2010.BAK b/TransferData_August02_2010.BAK deleted file mode 100644 index 6789916..0000000 --- a/TransferData_August02_2010.BAK +++ /dev/null @@ -1,353 +0,0 @@ -' -' Process_Number = 1 -' Initial_Processdelay = 1000 -' Eventsource = Timer -' Control_long_Delays_for_Stop = No -' Priority = High -' Version = 1 -' ADbasic_Version = 5.0.5 -' Optimize = No -' Info_Last_Save = ORCHID ORCHID\labadmin -'

-#include ADwinPRO_ALL.inc -'Updated to new ADbasic code - Ben Sofka -dim i,j,k,lightcount,litup,eventcount,delaymultinuse as long -dim DATA_1[5000000] as long -dim DATA_2[5000000] as long -dim DATA_3[5000000] as float -dim DATA_4[100] as long ' a list of which channels are reset to zero on completion -dim value as float -dim counts,maxcount,updates,i,j,k as long -dim ch as long -dim val,val_lower,val_upper,val_lower2,val_upper2 as long -dim tempval as long -dim dataline,clock, ioupdate,ioreset,masterreset as long -dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long -dim digitallow as long -dim delay,delayinuse as long -dim numbertoskip as long -dim leddelay as float -dim digitalactive,digital2active as long - -Function V(value) as float - V=(value+10)/20*65535 -ENDFUNCTION - -SUB Light_LED(lit) as - SELECTCASE lit - CASE 1 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 2 - P2_SET_LED(1,0) - P2_SET_LED(2,1) - CASE 3 - P2_SET_LED(2,0) - P2_SET_LED(3,1) - CASE 4 - P2_SET_LED(3,0) - P2_SET_LED(4,1) - CASE 5 - P2_SET_LED(4,0) - P2_SET_LED(1,1) - CASE 6 - P2_SET_LED(1,0) - P2_SET_LED(2,1) - CASE 8 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 9 - P2_SET_LED(1,0) - P2_SET_LED(4,1) - CASE 10 - P2_SET_LED(4,0) - P2_SET_LED(3,1) - CASE 11 - P2_SET_LED(3,0) - P2_SET_LED(2,1) - CASE 12 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 13 - P2_SET_LED(1,0) - 'SETLED(2,da,1) - ENDSELECT -ENDSUB - - - -INIT: - - 'Jan 16/2004 - 'expecting 3 arrays. - 'Data_1: A list which specifies how many channels will be updated per event - 'Data_2: A list of channels to be updates - 'Data_3: A list of values for the channels - - 'Data_2 and Data_3 have a 1:1 correspondence. - 'Stepping through data2 and 3 is controlled by Data 1 - 'Computer send an integer to Par_1. This tells us how many - 'events to write. ) - 'Channels 1-32 refer to Analog output lines - 'Channel 101,102 refers to Digital output lines (16 bit word x2) - 'Channel 103,104 refer to Digital output lines (16 bit word X2) - 'channel 51-53 refers to digital output lines controlling the DDS - 'DDS control lines are digital output lines - 'Data line, read clock, io update , reset - ' 0-3 data - ' 4 I/O reset - ' 5 update clock - ' 6 master Reset - ' 7 (maybe) RF switch - delay=PAR_2 ' 300000=>1ms for T11 Processor: Updated July 14 2009 - Ben Sofka - PROCESSDELAY=delay - 'DDS digital line setup - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - - DigProg1(1,65535) - DigProg2(1,65535) - DigProg1(2,65535) - DigProg2(2,65535) - - ' Seth Aubin: removed these lines --> we do not have a 3rd DIO card - 'DigProg1(3,65535) - 'DigProg2(3,65535) - ' ------------------------------------------------------------------ - - 'Configure cards for synchronous output - SYNCENABLE(1,dio,1) - SYNCENABLE(2,dio,1) - - ' Seth Aubin: removed these lines --> we do not have a 3rd DIO card - 'SYNCENABLE(3,dio,1) - ' ------------------------------------------------------------------ - - SYNCENABLE(1,da,1) - SYNCENABLE(2,da,1) - SYNCENABLE(3,da,1) - SYNCENABLE(4,da,1) - - numbertoskip=0 - counts=1 - maxcount=PAR_1 - updates=1 - lightcount=0 - eventcount=0 - leddelay=8000000/PROCESSDELAY - PAR_11=DATA_1[1] - PAR_12=DATA_1[2] - PAR_13=DATA_1[3] - FPar_11=DATA_2[1] - FPar_12=DATA_2[2] - FPar_13=DATA_2[3] - ' Make sure the DDS lines are low. - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,0) - DIGOUT_F(2,ioreset,0) - DIGOUT_F(2,ioupdate,0) - DIGOUT_F(2,masterreset,0) - - -EVENT: - P2_SYNC_ALL(1111b) 'Force synchronized output now. We are sending out the data programmed in the last cycle. - ' THis way all the outputs are updated at the beginning of an event, which is well timed. - ' Doing Syncall() at the end of an event causes the channel outputs to move around in time, depending on how many channels - ' are being programmed. - - eventcount=eventcount+delaymultinuse - if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) - endif - - delayinuse=delay ' reset the PROCESSDELAY - if(DATA_1[counts]<0) then ' if we see a negative number, interpret it as a multiplicative factor on the delay - delayinuse=delay*(-1*DATA_1[counts]) - delaymultinuse=-1*DATA_1[counts] - endif - PROCESSDELAY=delayinuse - - - ' reset the variables controlling digital output. - digitalactive=0 - digital2active=0 - val_lower=0 - val_upper=0 - val_lower2=0 - val_upper2=0 - counts=counts+1 'Number of events so far - - ' Added by Seth Aubin on August 2, 2010. - DIG_LATCH(11b) 'required for operation of DIOs ... suppose to be like P2_SYNC_ALL - - - IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each elementof DATA_1 for an update - For i=1 to DATA_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=DATA_2[updates] - - '*****************Analog outs*********************** - if((ch>=1) and (ch<=32)) then - AnalogWrite(ch,DATA_3[updates]) - endif - - '*****************DDS outs************************* - 'if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS1 - ' DDS1Write(DATA_3[updates]) - 'endif - - 'if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS2 - ' DDS2Write(DATA_3[updates]) - 'ENDIF 'end BB - - '***********************Digital outs********** - if(ch=101) then - val_lower=DATA_3[updates] - DIG_WRITELATCH32(1,val_lower) ' Seth Aubin, Aug. 2, 2010: "2" -->"1" - endif - - 'if(ch=102) then - ' val_upper=DATA_3[updates] - ' DIG_WRITELATCH32(2,val_upper) ' Seth Aubin, Aug. 2, 2010: "3" -->"2" - 'endif - - NEXT i 'B for loop - ENDIF 'A: - If(counts>=maxcount+1) then end - - -FINISH: - 'Clear all channels - PAR_3=counts - PAR_4=maxcount - - 'If (Data_4[27]=0) then - For i= 1 to 8 - if(DATA_4[i]=1) then - P2_WRITE_DAC(1,i,V(0)) - ENDIF - if(DATA_4[i+8]=1) then - P2_WRITE_DAC(2,i,V(0)) - ENDIF - if(DATA_4[i+16]=1) then - P2_WRITE_DAC(3,i,V(0)) - ENDIF - if(DATA_4[i+24]=1) then - P2_WRITE_DAC(4,i,V(0)) - ENDIF - Next i - 'set line 28 high... forget why... - DIG_WRITELATCH32(2,2^28) - 'ENDIF - - P2_SYNC_ALL(1) - - '*************************************************** -SUB AnalogWrite(achannel, avalue) - if((achannel>=1)and(achannel<=8)) then - P2_WRITE_DAC(1,achannel,V(avalue)) - endif - - if((achannel>=9)and(achannel<=16)) then - P2_WRITE_DAC(2,achannel-8,V(avalue)) - endif - - if((achannel>=17)and(achannel<=24)) then - P2_WRITE_DAC(3,achannel-16,V(avalue)) - endif - - if((achannel>=25)and(achannel<=32)) then - P2_WRITE_DAC(4,achannel-24,V(avalue)) - endif -ENDSUB -'*************************************************** -SUB DDS1Write(digvalue) - dim tempval as long - dim dataline,clock,ioupdate,ioreset,masterreset as long - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - if(digvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = digvalue 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - ELSE - IF(digvalue=4) then 'write to the i/o reset pin to reset the buffer. - 'DIGOUT_F(2,ioreset,1) ' Currently disabled - 'DIGOUT_F(2,ioreset,0) - Else - IF(digvalue=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(digvalue=6) then - DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif -ENDSUB -'*************************************************** -SUB DDS2WRITE(dvalue) - dim tempval as long - dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - if(dvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = dvalue 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - ELSE - IF(dvalue=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 'DIGOUT_F(2,ioreset9858,0) - Else - IF(dvalue=5) then - DIGOUT_F(2,ioupdate9858,1) - DIGOUT_F(2,ioupdate9858,0) - Else - IF(dvalue=6) then - DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) - ENDIF - endif - endif - endif -ENDSUB diff --git a/TransferData_August02_2010.TB1 b/TransferData_August02_2010.TB1 deleted file mode 100644 index 3d1f569968efe032496f0b1e6f33989213038b2a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5228 zcmd5=ZERcB8Ges_9d1%PwVj*Hbu!{)QPq{UGzmzf%c-3xO*C*FJ558$_^?=7p>01} z#1Dj;OJS) zYi82WQtb~{d2_zruXEn_Jomk3M6~$UW@2dHR`3r`2qec5kPB3Lo#^tUHw(syaG^k#$7TuY`~ z4S#yamL)-Luv#A@mp(I=)#B+p4R88;nn>Rz=k+(no+fXU70AyFFW;|tqs{1(85fO4 zoZoNy#I1&pKVa?@-!yje2hD2HU{v#m%!H^n598_82MAtt+JgDzZFqZTzA&ea!%bYC8xn`LT~R8x ziLvF^7xdR;BG6&`U*qTx*nG3n|A6CvP1M%kZ;$62dUk0k$N!Y$e`*!~1JECE{4bqP zu;l-{G3?FuKj7&9pa0We$^W1r=$MjcU~2j{MYH>c#_vGiw9ZDeb(<-{;Inidy&W%)sAb=1|vn)O#@> zL#ze`of-J~gt@0Hw6J{nPYcWWi)Xsdqy4h}A1)e$BabsZx*2v|BHqO2!+D{^qgB!m zQP<>}4gYabsf(_$#ygwb^Wj&YQ+7tZavV4n-EswTxlj|E8~6($_K(Z?T%yT!X5jTj zB{BAdH4Znq=isXn9y=(<=I)F~+ik~Re4jsXmVR_V8;T0tD`t9;Ltf{e4uNmT$upl| zqMF}-np)q}ybdpLL-9MjDe$Hoooo3+;QMG*zH-}s{@`h9^L@@&juGYh0z3`A&8zWc zPYU+335*7I3Sg%nSSf&&Ibh}K*T$YzS(sh~Q2T+g0vH;Pb3& z=+pLolCthSb)xFY;b>dyKHC3wU3gOo&vDjk^HE@|7ns&2{9-5PBEh%MQ|pVsagOum zbBLqxk32rNM}I%xPZJ`}_hanW5tsYcGkh z=6T{DA!n?d-QeQOcrR4Vd-+RdUwG3*h93ltfKs4-&@RwGc2=+%w@aOPfp?n;y-rE+ zoP|3HCm;F*X?+gvl*i4NsZ)Foug~WFoG*!dN!t06)x{5{$5{n@uE@K{gFRGa#|5*- zo%D{b^KN~d@5ma0O}X5vwYN_8F(Ebu#Hc*pgm}wX5Jfl3^FHnttR+Nlxqos+17|O| z-^}l$Tel{OhC}r5`^VFFwI-=5i8wAIj_Nv@BW{wpA!UqjM8DOp#$qy0hqSy}yoh%`$y~vCbsz_-h`TO?JE{@Nv13)JC+xeJEu{@9mu8RxbrgVv+anBiu=PRblxj`ya)9i zo0XX1pynZ*R5EOIP1^A_HR-167ZB1@5oV!Q^3dDuh{t50~}Lw z$<7LO7v9sIL~1|U2-@9fIog4X?-k+~h4miq#Tf5#ybs8d^Fyx2kwaZ3<>q4NgJyNt zR%Oq~jI_0|{7Y?N`Q19RzpFt>*!GRYNJHiLsbZmxNH=)AassmWN;tDS|EsAAw|c0n zqDtN+Bi^XM|DWB^{{;LeP}E8v25?d zeZ74Qe+~EHU$Ku5?R_ZM+s8JRiQaDE!8q@kQrs27+ojGSe)t|tnbmqwspiLJ4r|p; z?H1=LEq-l%mshX;>pHsn&Fai*y86FF*I!L1fP5c8_nKDqYE=nO80suJA3z<2 zJ4^~)^&E{|^_+d}VB^`s!4CxSZiS*Q@G!yn4uwVCvY*WX6LY|-m+`G9?|z>5PUrm1 z*=bo<_?z=YyYvF@&7KqLOdz;^#oEKx+AG43wGDF3k$Kdbe^rDqzp-pSqr=vef2(CP zdswJG;cq#&NCZ5*WD?GU?6WO>|5Ge_FZ^^%p7r<*U|u6?9W4H{4RcFa)5wm2%5cw6 zTWHLQLpSQCZo6)puR}eMw(H7$sBaC($?@B$Wz9~(toL)LT~Dr;zdOXlI$7t=x@@d2 z*;YG+r*z&228*Bkdg$-PN#F<0H2{BTLqqY>@y_suHTUI6*3m?xpXFkspUK}b@~DMO z_-K;kxA6k{sL&%wjoH|v#2g%njd&}k9UMH&dn=Df43Ri!-ZG^HS`H<(^%j0~HAaAg zKfMXPYUN=^?-A%dD)mZig5KKT`a{Xu4P|Xmo*TD`4m z@rN=trTEmoG0G-pMwvpRxCf)2ElYwX@!OCgMk|f(QJ*I_8aVdyXr<@qXzj6AMt$sr zUFT&___ldY^7>;Jc(`<@1n$zL6YGtIgN>5|!h`nBNyNDoah3T|;x)j_PCB|y`Z~sA z+t;#_+v}$ -' Process_Number = 1 -' Initial_Processdelay = 1000 -' Eventsource = Timer -' Control_long_Delays_for_Stop = No -' Priority = High -' Version = 1 -' ADbasic_Version = 5.0.5 -' Optimize = No -' Info_Last_Save = ORCHID ORCHID\labadmin -'
-#include ADwinPRO_ALL.inc -'Updated to new ADbasic code - Ben Sofka -dim i,j,k,lightcount,litup,eventcount,delaymultinuse as long -dim DATA_1[5000000] as long -dim DATA_2[5000000] as long -dim DATA_3[5000000] as float -dim DATA_4[100] as long ' a list of which channels are reset to zero on completion -dim value as float -dim counts,maxcount,updates,i,j,k as long -dim ch as long -dim val,val_lower,val_upper,val_lower2,val_upper2 as long -dim tempval as long -dim dataline,clock, ioupdate,ioreset,masterreset as long -dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long -dim digitallow as long -dim delay,delayinuse as long -dim numbertoskip as long -dim leddelay as float -dim digitalactive,digital2active as long - -Function V(value) as float - V=(value+10)/20*65535 -ENDFUNCTION - -SUB Light_LED(lit) as - SELECTCASE lit - CASE 1 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 2 - P2_SET_LED(1,0) - P2_SET_LED(2,1) - CASE 3 - P2_SET_LED(2,0) - P2_SET_LED(3,1) - CASE 4 - P2_SET_LED(3,0) - P2_SET_LED(4,1) - CASE 5 - P2_SET_LED(4,0) - P2_SET_LED(1,1) - CASE 6 - P2_SET_LED(1,0) - P2_SET_LED(2,1) - CASE 8 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 9 - P2_SET_LED(1,0) - P2_SET_LED(4,1) - CASE 10 - P2_SET_LED(4,0) - P2_SET_LED(3,1) - CASE 11 - P2_SET_LED(3,0) - P2_SET_LED(2,1) - CASE 12 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 13 - P2_SET_LED(1,0) - 'SETLED(2,da,1) - ENDSELECT -ENDSUB - - - -INIT: - - 'Jan 16/2004 - 'expecting 3 arrays. - 'Data_1: A list which specifies how many channels will be updated per event - 'Data_2: A list of channels to be updates - 'Data_3: A list of values for the channels - - 'Data_2 and Data_3 have a 1:1 correspondence. - 'Stepping through data2 and 3 is controlled by Data 1 - 'Computer send an integer to Par_1. This tells us how many - 'events to write. ) - 'Channels 1-32 refer to Analog output lines - 'Channel 101,102 refers to Digital output lines (16 bit word x2) - 'Channel 103,104 refer to Digital output lines (16 bit word X2) - 'channel 51-53 refers to digital output lines controlling the DDS - 'DDS control lines are digital output lines - 'Data line, read clock, io update , reset - ' 0-3 data - ' 4 I/O reset - ' 5 update clock - ' 6 master Reset - ' 7 (maybe) RF switch - delay=PAR_2 ' 300000=>1ms for T11 Processor: Updated July 14 2009 - Ben Sofka - PROCESSDELAY=delay - 'DDS digital line setup - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - - DigProg1(1,65535) - DigProg2(1,65535) - DigProg1(2,65535) - DigProg2(2,65535) - - ' Seth Aubin: removed these lines --> we do not have a 3rd DIO card - 'DigProg1(3,65535) - 'DigProg2(3,65535) - ' ------------------------------------------------------------------ - - 'Configure cards for synchronous output - SYNCENABLE(1,dio,1) - SYNCENABLE(2,dio,1) - - ' Seth Aubin: removed these lines --> we do not have a 3rd DIO card - 'SYNCENABLE(3,dio,1) - ' ------------------------------------------------------------------ - - SYNCENABLE(1,da,1) - SYNCENABLE(2,da,1) - SYNCENABLE(3,da,1) - SYNCENABLE(4,da,1) - - numbertoskip=0 - counts=1 - maxcount=PAR_1 - updates=1 - lightcount=0 - eventcount=0 - leddelay=8000000/PROCESSDELAY - PAR_11=DATA_1[1] - PAR_12=DATA_1[2] - PAR_13=DATA_1[3] - FPar_11=DATA_2[1] - FPar_12=DATA_2[2] - FPar_13=DATA_2[3] - ' Make sure the DDS lines are low. - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,0) - DIGOUT_F(2,ioreset,0) - DIGOUT_F(2,ioupdate,0) - DIGOUT_F(2,masterreset,0) - - -EVENT: - P2_SYNC_ALL(1111b) 'Force synchronized output now. We are sending out the data programmed in the last cycle. - ' THis way all the outputs are updated at the beginning of an event, which is well timed. - ' Doing Syncall() at the end of an event causes the channel outputs to move around in time, depending on how many channels - ' are being programmed. - - eventcount=eventcount+delaymultinuse - if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) - endif - - delayinuse=delay ' reset the PROCESSDELAY - if(DATA_1[counts]<0) then ' if we see a negative number, interpret it as a multiplicative factor on the delay - delayinuse=delay*(-1*DATA_1[counts]) - delaymultinuse=-1*DATA_1[counts] - endif - PROCESSDELAY=delayinuse - - - ' reset the variables controlling digital output. - digitalactive=0 - digital2active=0 - val_lower=0 - val_upper=0 - val_lower2=0 - val_upper2=0 - counts=counts+1 'Number of events so far - - ' Added by Seth Aubin on August 2, 2010. - DIG_LATCH(1) 'required for operation of DIO 1 ..suppose to be like P2_SYNC_ALL - DIG_LATCH(2) 'required for operation of DIO 1 ..suppose to be like P2_SYNC_ALL - - IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each elementof DATA_1 for an update - For i=1 to DATA_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=DATA_2[updates] - - '*****************Analog outs*********************** - if((ch>=1) and (ch<=32)) then - AnalogWrite(ch,DATA_3[updates]) - endif - - '*****************DDS outs************************* - 'if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS1 - ' DDS1Write(DATA_3[updates]) - 'endif - - 'if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS2 - ' DDS2Write(DATA_3[updates]) - 'ENDIF 'end BB - - '***********************Digital outs********** - if(ch=101) then - val_lower=DATA_3[updates] - DIG_WRITELATCH32(1,val_lower) ' Seth Aubin, Aug. 2, 2010: "2" -->"1" - endif - - if(ch=102) then - val_upper=DATA_3[updates] - DIG_WRITELATCH32(2,val_upper) ' Seth Aubin, Aug. 2, 2010: "3" -->"2" - endif - - NEXT i 'B for loop - ENDIF 'A: - If(counts>=maxcount+1) then end - - -FINISH: - 'Clear all channels - PAR_3=counts - PAR_4=maxcount - - 'If (Data_4[27]=0) then - For i= 1 to 8 - if(DATA_4[i]=1) then - P2_WRITE_DAC(1,i,V(0)) - ENDIF - if(DATA_4[i+8]=1) then - P2_WRITE_DAC(2,i,V(0)) - ENDIF - if(DATA_4[i+16]=1) then - P2_WRITE_DAC(3,i,V(0)) - ENDIF - if(DATA_4[i+24]=1) then - P2_WRITE_DAC(4,i,V(0)) - ENDIF - Next i - 'set line 28 high... forget why... - DIG_WRITELATCH32(2,2^28) - 'ENDIF - - P2_SYNC_ALL(1) - - '*************************************************** -SUB AnalogWrite(achannel, avalue) - if((achannel>=1)and(achannel<=8)) then - P2_WRITE_DAC(1,achannel,V(avalue)) - endif - - if((achannel>=9)and(achannel<=16)) then - P2_WRITE_DAC(2,achannel-8,V(avalue)) - endif - - if((achannel>=17)and(achannel<=24)) then - P2_WRITE_DAC(3,achannel-16,V(avalue)) - endif - - if((achannel>=25)and(achannel<=32)) then - P2_WRITE_DAC(4,achannel-24,V(avalue)) - endif -ENDSUB -'*************************************************** -SUB DDS1Write(digvalue) - dim tempval as long - dim dataline,clock,ioupdate,ioreset,masterreset as long - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - if(digvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = digvalue 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - ELSE - IF(digvalue=4) then 'write to the i/o reset pin to reset the buffer. - 'DIGOUT_F(2,ioreset,1) ' Currently disabled - 'DIGOUT_F(2,ioreset,0) - Else - IF(digvalue=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(digvalue=6) then - DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif -ENDSUB -'*************************************************** -SUB DDS2WRITE(dvalue) - dim tempval as long - dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - if(dvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = dvalue 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - ELSE - IF(dvalue=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 'DIGOUT_F(2,ioreset9858,0) - Else - IF(dvalue=5) then - DIGOUT_F(2,ioupdate9858,1) - DIGOUT_F(2,ioupdate9858,0) - Else - IF(dvalue=6) then - DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) - ENDIF - endif - endif - endif -ENDSUB diff --git a/TransferData_FEB17_2006.BAS b/TransferData_FEB17_2006.BAS deleted file mode 100644 index af78212..0000000 --- a/TransferData_FEB17_2006.BAS +++ /dev/null @@ -1,346 +0,0 @@ -**************************************** -* Prozeßnummer = 1 -* Delay = 1000 -* Eventsource = 0 -* Number of Loops = 0 -* Priorität = 0 -* Version = 1 -* FastStop = 0 -* AdbasicVersion = 4000001 -* ATSRAM = 0 -* OPT_LEVEL = 0 -* SAVECOMPIL = 0 -**************************************** -#include ADwpad.inc -#include Adwpda.inc -#include Adwpdio.inc -#include adwinpro.inc -dim i,j,k,lightcount,litup,eventcount,delaymultinuse as long -dim DATA_1[5000000] as long -dim DATA_2[5000000] as long -dim data_3[5000000] as float -dim data_4[30] as long ' a list of which channels are reset to zero on completion -dim value as float -dim counts,maxcount,updates,i,j,k as long -dim ch as long -dim val,val_lower,val_upper,val_lower2,val_upper2 as long -dim tempval as long -dim dataline,clock, ioupdate,ioreset,masterreset as long -dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long -dim digitallow as long -dim delay,delayinuse as long -dim numbertoskip as long -dim leddelay as float -dim digitalactive,digital2active as long -Function V(value) as float - V=(value+10)/20*65535 -ENDFUNCTION - -SUB Light_LED(lit) as - SELECTCASE lit - CASE 1 - SETLED(2,da,0) - SETLED(1,dio,1) - CASE 2 - SETLED(1,dio,0) - SetLED(2,dio,1) - CASE 3 - SETLED(2,dio,0) - SETLED(3,ext,1) - CASE 4 - SETLED(3,ext,0) - SETLED(4,ad,1) - CASE 5 - SETLED(4,ad,0) - SETLED(1,da,1) - CASE 6 - SETLED(1,da,0) - SETLED(2,da,1) - CASE 8 - SETLED(2,da,0) - SETLED(1,da,1) - CASE 9 - SETLED(1,da,0) - SetLED(4,ad,1) - CASE 10 - SETLED(4,ad,0) - SETLED(3,ext,1) - CASE 11 - SETLED(3,ext,0) - SETLED(2,dio,1) - CASE 12 - SETLED(2,dio,0) - SETLED(1,dio,1) - CASE 13 - SETLED(1,dio,0) - 'SETLED(2,da,1) - ENDSELECT -ENDSUB - -SUB AnalogWrite({achannel, avalue}) - - - -ENDSUB - - - - - - - -INIT: - -'Jan 16/2004 -'expecting 3 arrays. -'Data_1: A list which specifies how many channels will be updated per event -'Data_2: A list of channels to be updates -'Data_3: A list of values for the channels - -'Data_2 and Data_3 have a 1:1 correspondence. -'Stepping through data2 and 3 is controlled by Data 1 -'Computer send an integer to Par_1. This tells us how many -'events to write. ) -'Channels 1-32 refer to Analog output lines -'Channel 101,102 refers to Digital output lines (16 bit word x2) -'Channel 103,104 refer to Digital output lines (16 bit word X2) -'channel 51-53 refers to digital output lines controlling the DDS -'DDS control lines are digital output lines -'Data line, read clock, io update , reset -' 0-3 data -' 4 I/O reset -' 5 update clock -' 6 master Reset -' 7 (maybe) RF switch -delay=PAR_2 ' 40000=>1ms -GlobalDelay=delay -'DDS digital line setup -dataline=31 ' data line -clock=30 ' data clock -ioupdate=29 ' update line. transfers data from buffer into registers -ioreset=28 ' resets input buffers -masterreset=27 - -'DDS2 digital lines (base 0) -dataline9858=21 -clock9858=22 -ioupdate9858=19 -'ioreset9858=23 -masterreset9858=18 - -DigProg1(1,65535) -DigProg2(1,65535) -DigProg1(2,65535) -DigProg2(2,65535) -'Configure cards for synchronous output -SYNCENABLE(1,dio,1) -SYNCENABLE(2,dio,1) -SYNCENABLE(3,dio,1) - -SYNCENABLE(1,da,1) -SYNCENABLE(2,da,1) -SYNCENABLE(3,da,1) -SYNCENABLE(4,da,1) - -numbertoskip=0 -counts=1 -maxcount=Par_1 -updates=1 -lightcount=0 -eventcount=0 -leddelay=8000000/GLOBALDELAY -Par_11=Data_1[1] -Par_12=Data_1[2] -Par_13=Data_1[3] -FPar_11=Data_2[1] -FPar_12=Data_2[2] -FPar_13=Data_2[3] -' Make sure the DDS lines are low. -DIGOUT_F(2,clock,0) -DIGOUT_F(2,dataline,0) -DIGOUT_F(2,ioreset,0) -DIGOUT_F(2,ioupdate,0) -DIGOUT_F(2,masterreset,0) - - -EVENT: -digitalactive=0 -digital2active=0 -eventcount=eventcount+delaymultinuse -if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) -endif -' Careful with for loops. They always do at least 1 execution. -delayinuse=delay ' reset the GlobalDelay -' reset the variables controlling digital output. -digitalactive=0 -val_lower=0 -val_upper=0 -val_lower2=0 -val_upper2=0 - -SYNCALL() 'Force synchronized output now. We are sending out the data programmed in the last cycle. -' THis way all the outputs are updated at the beginning of an event, which is well timed. -' Doing Syncall() at the end of an event causes the channel outputs to move around in time, depending on how many channels -' are being programmed. -counts=counts+1 'Number of events so far -if(Data_1[counts]<0) then ' if we see a negative number, interpret it as a multiplicative factor on the delay - delayinuse=delay*(-1*Data_1[counts]) - delaymultinuse=-1*Data_1[counts] -endif -GLOBALDELAY=delayinuse - -IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each elementof DATA_1 for an update - For i=1 to Data_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=Data_2[updates] -'***************************************************DDS1 commands (Rb Evaporation)*********************** - if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS - if(Data_3[updates]<=3) then ' write 2 bits to the data line of the DDS - tempval = Data_3[updates] 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,clock,0) - - ELSE - IF(Data_3[updates]=4) then 'write to the i/o reset pin to reset the buffer. - 'DIGOUT_F(2,ioreset,1) ' Currently disabled - 'DIGOUT_F(2,ioreset,0) - Else - IF(data_3[updates]=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(data_3[updates]=6) then - DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif - ENDIF 'end AA -'***************************************************DDS2 commands ()*********************** - if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS - if(Data_3[updates]<=3) then ' write 2 bits to the data line of the DDS - tempval = Data_3[updates] 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,clock9858,0) - - ELSE - IF(Data_3[updates]=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 'DIGOUT_F(2,ioreset9858,0) - Else - IF(data_3[updates]=5) then - DIGOUT_F(2,ioupdate9858,1) - DIGOUT_F(2,ioupdate9858,0) - Else - IF(data_3[updates]=6) then - DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) - ENDIF - endif - endif - endif - ENDIF 'end BB -'***********************Digital outs********** - if(ch=101) then - val_lower=Data_3[updates] - digitalactive=1 - endif - if(ch=102) then - val_upper=Data_3[updates] - digitalactive=1 - endif - if(digitalactive=1) then - DIG_WRITELATCH32(2,val_lower+2^16*val_upper) - endif - - if(ch=103) then - val_lower2=Data_3[updates] - digital2active=1 - endif - if(ch=104) then - val_upper2=Data_3[updates] - digital2active=1 - endif - if(digital2active=1) then - DIG_WRITELATCH32(3,val_lower2+2^16*val_upper2) - endif -'*****************Analog outs*********************** - if((ch>=1)and(ch<=8)) then - writedac(1,ch,V(Data_3[updates])) - endif - - if((ch>=9)and(ch<=16)) then - writedac(2,ch-8,V(Data_3[updates])) - endif - - if((ch>=17)and(ch<=24)) then - writedac(3,ch-16,V(Data_3[updates])) - endif - - if((ch>=25)and(ch<=32)) then - writedac(4,ch-24,V(Data_3[updates])) - endif -'*******done all updates***** - NEXT i 'B for loop -ENDIF 'A: -If(counts>=maxcount+1) then end - - -FINISH: -'Clear all channels -Par_3=counts -Par_4=maxcount - -'If (Data_4[27]=0) then - For i =1 to 8 - if(Data_4[i]=1) then - WRITEDAC(1,i,V(0)) - ENDIF - if(Data_4[i+8]=1) then - WRITEDAC(2,i,V(0)) - ENDIF - if(Data_4[i+16]=1) then - WRITEDAC(3,i,V(0)) - ENDIF - if(Data_4[i+24]=1) then - WRITEDAC(4,i,V(0)) - ENDIF - Next i - 'set line 28 high... forget why... - DIG_WRITELATCH32(2,2^28) -'ENDIF -SYNCALL() diff --git a/TransferData_July14_2009.TB1 b/TransferData_July14_2009.TB1 deleted file mode 100644 index 124e1530ee830e5f96055f32763d824778857c6b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6940 zcmd5>eQZq3gQuF^_J zC00Rl?YykdO+XGG8{L4G*2$bubvS9OmQ|E(sHGj9P(j^RO&ikwsWep!Y^pkq*8AP} zp3Nf|DBC}^xZJOE&-vYR&$;K^7mg5e;@wq*L%p>E|KaCFVSPV}38naZ6OBd`2a0h# z2jXoOLQZ1*JPP}<_2qtM3{K4szo69ld~+uVVP)#L`GtI6;Xj_Y6W<;^khoh6CRWKL zA&JpMv+PLRxB4U{Es$ChB&Otn;j|b|+$mcV8$_D8n~f*m9^Of;0dAH!IN2&~<*k7R zw22a?b#horC^ouOwn>jFo%A-jQ`)H5X{~IRHYpKWBS)k`Wij>0i>2=>U9?*6lD?-n zs9SbOk1J8?lB3cSiZkiwosv8Y?4mR90`uUhNs?R0Zn9yA)pigtP z?X6-w;84fn+8FwN)>lO8=EY%dwvG_R1^zBcQF*v@{%(yf>-&9zcS~t~PUTN}w0^EO zvRmv95Ti`=Ra{r_cc=W|q2YJy{GA$Imf?5m_}u}Ge_ZS5YVYqBV>_zfC~H~71C{Fn8ko|CR0 z4S!KTH;dm%3G|a;XQ+tDwY;dcWl_2d?Q!*NMGdS(EtGxTwVvcLgWQ!jCpUG>u;=ABCwIgsxAErW%0{{VuOnA> zO55a^w4QhZM7>Wu(gyU~F&;o^6CR>uww)58AN5w;h64fhu9@!ndr%n&-6cGT@gUB* zkCN%0UyUmLA@7m-3x7T`pFcevI)?gM?LVEC`*v*Sl7Ur_Yog(LF6YZrJ{+iGIB0df zDeL>>1YaFkr1m@O%{kxeFY=uME9*NC2UcIix{SA;o9y`;f!%ClC|Y$|+?l*Xr;UL&rt@4ZZ35kAW$BEv9n!`r(qb#o8Sh6UKc_SZx>e=q(uXK_ zR6%?~+@OdX4#WwHIFUh|n0jOQ1%dOCR}rKfh%XfJ#ff;6M7(JgaGr=qttYg2w5Shv z-Ee`{43ef6#1UFO+)#{7t52RO#-bH07L9e7R%tH@zY5)#4L} z_>?sbe9;;wY^}M!npQnK7-(tUOddW}?OR!lXV5p74`$J_$H@)?FG=esk{q8-QL>YAe4ZnJ0iUO9 z22Fl-FOlJf9FabQ-KciE+$7B-E>`8N(l3=R-%3kLqU=6Gon-ZBO6o=FLwOLT9~jnW z$(^SWPuHiDbdxG?gySKrB5xuV*3Z~DKI`RP$;Zg4WKvq69FaDpWy+14%z}!k&HNOB zPG_N8<5>}$71JRhfmKXT`^}VV^b#|}O-upj%yIKO`ORc$Q&5g-HsK&`B(3*BewNw~o@}%q;LXCGU?Z6m&J*z7#(1lC6=rso3SPFcWN;3)f8~7A zFrO+jZ(Ki8W`4x5UM@2)8|MFC`8QgBBl$PNf1~}Em#^xyt5C>9IsOQL-~18&&I#n5 zPiJDR-*y2xWeDd|1OMShlTrt@N$toNw2Vfgf_$in3 zay#?&gh$)2wi`%I@~{+5zeHPM-h7@Xm(nlOHE37ldG0sqEPV`ZA-gDz82%pAH^#q`?XYf-_uu2=(u*n<2elBF-gZ-yBBn?dZ_X*xA1-7~_j|In z$JdC9^_;Vta(MTu`z~Bz`Y4R;(?E3RhtXbYWT>c z+P1+SY|@n4?xZgGNRG9y@(Vls!l~J^;LvI{|8~JISnObaf!KkukMa)qg-06`MAYyL zjGx2!Bf_ovcr~ll@sBai{NmP0<`*vM6%|Vt{352ed&-6T{3x@VqOaji*ju_M4Da&1@Fl$tuRg^-QjS;OHF!O#SPKPwYjv{s zNM5)!-Yi@in>zvj!Mm7^Iq~jAjz)O$m1S@6E6dCq+v{d#xBrzAX+2K@CeUz{lQ!^N zz|7j|4D#U&^3kLCHpz0kywov~aWteSD7TY38uEm6CugOO^c)oqI9{npBzT-BhqqMlwfMc71OpEOrs z4@#T<{%_OX|I65S@*rKpzD;CJ+P8_KY@v->T7iT0xAYZ0|J}ep3S-C*p;ssHkma?7 z^ZVO;%NISAA?(`+Awyqgf2&32XLGUB9_akQGE@QbRAJp^2;0|l$ zgr4W_mO3i;V4ko%SGi?ebT;maip$jeFjVJ@oV77CBEvnigB=j|bG^uQ3ulOg!QkY)8r zO2+WF44Dp9%J&Z0ESVwazN15xmc2useXkAKxP#goKYh@))^bRy*>_y>6@7}rm&Ww7 zUNO79Zmfq|P`@*Vb8g1DGJ7b}%An;A>AViv?imTLTg)9=S2J;ZosU8;2e}iF%R%l0 zSNZKw`)@yGr? z#C~VkAAj(>q*W?CBdbDjq4-c5P*$L@B`qjxQ9>x~C~=el6rCMxS8KDnts_iy_UhlJ Y7LKtw%K|z^!^&eQ#kHU6jeny4FJzp$tN;K2 diff --git a/TransferData_July14_2009.bas b/TransferData_July14_2009.bas deleted file mode 100644 index 3f52c74..0000000 --- a/TransferData_July14_2009.bas +++ /dev/null @@ -1,343 +0,0 @@ -' -' Process_Number = 1 -' Initial_Processdelay = 1000 -' Eventsource = Timer -' Control_long_Delays_for_Stop = No -' Priority = High -' Version = 1 -' ADbasic_Version = 5.0.5 -' Optimize = No -' Info_Last_Save = ORCHID ORCHID\labadmin -'
-#include ADwinPRO_ALL.inc -'Updated to new ADbasic code - Ben Sofka -dim i,j,k,lightcount,litup,eventcount,delaymultinuse as long -dim DATA_1[5000000] as long -dim DATA_2[5000000] as long -dim DATA_3[5000000] as float -dim DATA_4[100] as long ' a list of which channels are reset to zero on completion -dim value as float -dim counts,maxcount,updates,i,j,k as long -dim ch as long -dim val,val_lower,val_upper,val_lower2,val_upper2 as long -dim tempval as long -dim dataline,clock, ioupdate,ioreset,masterreset as long -dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long -dim digitallow as long -dim delay,delayinuse as long -dim numbertoskip as long -dim leddelay as float -dim digitalactive,digital2active as long - -Function V(value) as float - V=(value+10)/20*65535 -ENDFUNCTION - -SUB Light_LED(lit) as - SELECTCASE lit - CASE 1 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 2 - P2_SET_LED(1,0) - P2_SET_LED(2,1) - CASE 3 - P2_SET_LED(2,0) - P2_SET_LED(3,1) - CASE 4 - P2_SET_LED(3,0) - P2_SET_LED(4,1) - CASE 5 - P2_SET_LED(4,0) - P2_SET_LED(1,1) - CASE 6 - P2_SET_LED(1,0) - P2_SET_LED(2,1) - CASE 8 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 9 - P2_SET_LED(1,0) - P2_SET_LED(4,1) - CASE 10 - P2_SET_LED(4,0) - P2_SET_LED(3,1) - CASE 11 - P2_SET_LED(3,0) - P2_SET_LED(2,1) - CASE 12 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 13 - P2_SET_LED(1,0) - 'SETLED(2,da,1) - ENDSELECT -ENDSUB - - - -INIT: - - 'Jan 16/2004 - 'expecting 3 arrays. - 'Data_1: A list which specifies how many channels will be updated per event - 'Data_2: A list of channels to be updates - 'Data_3: A list of values for the channels - - 'Data_2 and Data_3 have a 1:1 correspondence. - 'Stepping through data2 and 3 is controlled by Data 1 - 'Computer send an integer to Par_1. This tells us how many - 'events to write. ) - 'Channels 1-32 refer to Analog output lines - 'Channel 101,102 refers to Digital output lines (16 bit word x2) - 'Channel 103,104 refer to Digital output lines (16 bit word X2) - 'channel 51-53 refers to digital output lines controlling the DDS - 'DDS control lines are digital output lines - 'Data line, read clock, io update , reset - ' 0-3 data - ' 4 I/O reset - ' 5 update clock - ' 6 master Reset - ' 7 (maybe) RF switch - delay=PAR_2 ' 300000=>1ms for T11 Processor: Updated July 14 2009 - Ben Sofka - PROCESSDELAY=delay - 'DDS digital line setup - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - - DigProg1(1,65535) - DigProg2(1,65535) - DigProg1(2,65535) - DigProg2(2,65535) - DigProg1(3,65535) - DigProg2(3,65535) - 'Configure cards for synchronous output - SYNCENABLE(1,dio,1) - SYNCENABLE(2,dio,1) - SYNCENABLE(3,dio,1) - - SYNCENABLE(1,da,1) - SYNCENABLE(2,da,1) - SYNCENABLE(3,da,1) - SYNCENABLE(4,da,1) - - numbertoskip=0 - counts=1 - maxcount=PAR_1 - updates=1 - lightcount=0 - eventcount=0 - leddelay=8000000/PROCESSDELAY - PAR_11=DATA_1[1] - PAR_12=DATA_1[2] - PAR_13=DATA_1[3] - FPar_11=DATA_2[1] - FPar_12=DATA_2[2] - FPar_13=DATA_2[3] - ' Make sure the DDS lines are low. - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,0) - DIGOUT_F(2,ioreset,0) - DIGOUT_F(2,ioupdate,0) - DIGOUT_F(2,masterreset,0) - - -EVENT: - P2_SYNC_ALL(1) 'Force synchronized output now. We are sending out the data programmed in the last cycle. - ' THis way all the outputs are updated at the beginning of an event, which is well timed. - ' Doing Syncall() at the end of an event causes the channel outputs to move around in time, depending on how many channels - ' are being programmed. - - eventcount=eventcount+delaymultinuse - if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) - endif - - delayinuse=delay ' reset the PROCESSDELAY - if(DATA_1[counts]<0) then ' if we see a negative number, interpret it as a multiplicative factor on the delay - delayinuse=delay*(-1*DATA_1[counts]) - delaymultinuse=-1*DATA_1[counts] - endif - PROCESSDELAY=delayinuse - - - ' reset the variables controlling digital output. - digitalactive=0 - digital2active=0 - val_lower=0 - val_upper=0 - val_lower2=0 - val_upper2=0 - counts=counts+1 'Number of events so far - - - IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each elementof DATA_1 for an update - For i=1 to DATA_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=DATA_2[updates] - - '*****************Analog outs*********************** - if((ch>=1) and (ch<=32)) then - AnalogWrite(ch,DATA_3[updates]) - endif - - '*****************DDS outs************************* - if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS1 - DDS1Write(DATA_3[updates]) - endif - - if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS2 - DDS2Write(DATA_3[updates]) - ENDIF 'end BB - - '***********************Digital outs********** - if(ch=101) then - val_lower=DATA_3[updates] - DIG_WRITELATCH32(2,val_lower) - endif - - if(ch=102) then - val_upper=DATA_3[updates] - DIG_WRITELATCH32(3,val_upper) - endif - - NEXT i 'B for loop - ENDIF 'A: - If(counts>=maxcount+1) then end - - -FINISH: - 'Clear all channels - PAR_3=counts - PAR_4=maxcount - - 'If (Data_4[27]=0) then - For i= 1 to 8 - if(DATA_4[i]=1) then - P2_WRITE_DAC(1,i,V(0)) - ENDIF - if(DATA_4[i+8]=1) then - P2_WRITE_DAC(2,i,V(0)) - ENDIF - if(DATA_4[i+16]=1) then - P2_WRITE_DAC(3,i,V(0)) - ENDIF - if(DATA_4[i+24]=1) then - P2_WRITE_DAC(4,i,V(0)) - ENDIF - Next i - 'set line 28 high... forget why... - DIG_WRITELATCH32(2,2^28) - 'ENDIF - - P2_SYNC_ALL(1) - - '*************************************************** -SUB AnalogWrite(achannel, avalue) - if((achannel>=1)and(achannel<=8)) then - P2_WRITE_DAC(1,achannel,V(avalue)) - endif - - if((achannel>=9)and(achannel<=16)) then - P2_WRITE_DAC(2,achannel-8,V(avalue)) - endif - - if((achannel>=17)and(achannel<=24)) then - P2_WRITE_DAC(3,achannel-16,V(avalue)) - endif - - if((achannel>=25)and(achannel<=32)) then - P2_WRITE_DAC(4,achannel-24,V(avalue)) - endif -ENDSUB -'*************************************************** -SUB DDS1Write(digvalue) - dim tempval as long - dim dataline,clock,ioupdate,ioreset,masterreset as long - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - if(digvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = digvalue 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - ELSE - IF(digvalue=4) then 'write to the i/o reset pin to reset the buffer. - 'DIGOUT_F(2,ioreset,1) ' Currently disabled - 'DIGOUT_F(2,ioreset,0) - Else - IF(digvalue=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(digvalue=6) then - DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif -ENDSUB -'*************************************************** -SUB DDS2WRITE(dvalue) - dim tempval as long - dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - if(dvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = dvalue 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - ELSE - IF(dvalue=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 'DIGOUT_F(2,ioreset9858,0) - Else - IF(dvalue=5) then - DIGOUT_F(2,ioupdate9858,1) - DIGOUT_F(2,ioupdate9858,0) - Else - IF(dvalue=6) then - DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) - ENDIF - endif - endif - endif -ENDSUB diff --git a/TransferData_July2_2009.TB1 b/TransferData_July2_2009.TB1 deleted file mode 100644 index 367afdf2124fafde3e35fbc4ac45dcb5b75f59ab..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6940 zcmd5>eQaCR6~E7Z4lk+g`r|pcPH3Dgs=Csad=v>PUhP=G+Qe~e=Yx<*VA@b^3~7`V zsY7jY?YxXcL1AU8XvH=(ZI$*9(u9_F6JlDy``!1R z-PhD@>Gls+Z|~Q+=lt%u=iGDd3r7e!@$M?Zq25}7|M2sou)ZI~gi`#yiAE!e1I0L= z1MxNsAty0@9)xWPa9Ru}?v$;G4I)k4&Bl{&5APJL&z+eiJe94|R^A$D zn8mmfrgd^yN+>qERJKWvD4p~+xl`Jx*lDe7mo_O8S|dlKL1i)Z$cv@#DP6Q$?vlQ* zIH+58NRKH|>XM_<vJl9(xdfr zwUOOocYqjWqOan*g1s_t>eF}AN8Dc z{b=}$`ng&BPD-Gk3_C+bOs?fctu2evU1*Q1XDe#hl^Erqb5*wDg^hSM8!4^#q}K8t zeZ5CogSNKbqpiR0T5-fEyJ?~9>#p@Aj~V2yyg9k4V}?C1zd5-hM!AhQCs#Jg^?x0? zvQye7$E5Yd6Ck)lIN2j@K))U10hBi3K}u%ZDG~ZnZ^dmm5K!-$>7Ks_m4VP*!UGr& z;+*>^neO@3sL~(u9+|)J=Ogp^)6=12sIS%j(`mVH$966mSOvKz8m{MZzC7i_fhvZB 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0 -* SAVECOMPIL = 0 -**************************************** -#include ADwpad.inc -#include Adwpda.inc -#include Adwpdio.inc -#include adwinpro.inc -dim i,j,k,lightcount,litup,eventcount,delaymultinuse as long -dim DATA_1[5000000] as long -dim DATA_2[5000000] as long -dim data_3[5000000] as float -dim data_4[100] as long ' a list of which channels are reset to zero on completion -dim value as float -dim counts,maxcount,updates,i,j,k as long -dim ch as long -dim val,val_lower,val_upper,val_lower2,val_upper2 as long -dim tempval as long -dim dataline,clock, ioupdate,ioreset,masterreset as long -dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long -dim digitallow as long -dim delay,delayinuse as long -dim numbertoskip as long -dim leddelay as float -dim digitalactive,digital2active as long - -Function V(value) as float - V=(value+10)/20*65535 -ENDFUNCTION - -SUB Light_LED(lit) as - SELECTCASE lit - CASE 1 - SETLED(2,da,0) - SETLED(1,dio,1) - CASE 2 - SETLED(1,dio,0) - SetLED(2,dio,1) - CASE 3 - SETLED(2,dio,0) - SETLED(3,ext,1) - CASE 4 - SETLED(3,ext,0) - SETLED(4,ad,1) - CASE 5 - SETLED(4,ad,0) - SETLED(1,da,1) - CASE 6 - SETLED(1,da,0) - SETLED(2,da,1) - CASE 8 - SETLED(2,da,0) - SETLED(1,da,1) - CASE 9 - SETLED(1,da,0) - SetLED(4,ad,1) - CASE 10 - SETLED(4,ad,0) - SETLED(3,ext,1) - CASE 11 - SETLED(3,ext,0) - SETLED(2,dio,1) - CASE 12 - SETLED(2,dio,0) - SETLED(1,dio,1) - CASE 13 - SETLED(1,dio,0) - 'SETLED(2,da,1) - ENDSELECT -ENDSUB - - - -INIT: - -'Jan 16/2004 -'expecting 3 arrays. -'Data_1: A list which specifies how many channels will be updated per event -'Data_2: A list of channels to be updates -'Data_3: A list of values for the channels - -'Data_2 and Data_3 have a 1:1 correspondence. -'Stepping through data2 and 3 is controlled by Data 1 -'Computer send an integer to Par_1. This tells us how many -'events to write. ) -'Channels 1-32 refer to Analog output lines -'Channel 101,102 refers to Digital output lines (16 bit word x2) -'Channel 103,104 refer to Digital output lines (16 bit word X2) -'channel 51-53 refers to digital output lines controlling the DDS -'DDS control lines are digital output lines -'Data line, read clock, io update , reset -' 0-3 data -' 4 I/O reset -' 5 update clock -' 6 master Reset -' 7 (maybe) RF switch -delay=PAR_2 ' 40000=>1ms -GlobalDelay=delay -'DDS digital line setup -dataline=31 ' data line -clock=30 ' data clock -ioupdate=29 ' update line. transfers data from buffer into registers -ioreset=28 ' resets input buffers -masterreset=27 - -'DDS2 digital lines (base 0) -dataline9858=21 -clock9858=22 -ioupdate9858=19 -'ioreset9858=23 -masterreset9858=18 - -DigProg1(1,65535) -DigProg2(1,65535) -DigProg1(2,65535) -DigProg2(2,65535) -DigProg1(3,65535) -DigProg2(3,65535) -'Configure cards for synchronous output -SYNCENABLE(1,dio,1) -SYNCENABLE(2,dio,1) -SYNCENABLE(3,dio,1) - -SYNCENABLE(1,da,1) -SYNCENABLE(2,da,1) -SYNCENABLE(3,da,1) -SYNCENABLE(4,da,1) - -numbertoskip=0 -counts=1 -maxcount=Par_1 -updates=1 -lightcount=0 -eventcount=0 -leddelay=8000000/GLOBALDELAY -Par_11=Data_1[1] -Par_12=Data_1[2] -Par_13=Data_1[3] -FPar_11=Data_2[1] -FPar_12=Data_2[2] -FPar_13=Data_2[3] -' Make sure the DDS lines are low. -DIGOUT_F(2,clock,0) -DIGOUT_F(2,dataline,0) -DIGOUT_F(2,ioreset,0) -DIGOUT_F(2,ioupdate,0) -DIGOUT_F(2,masterreset,0) - - -EVENT: -SYNCALL() 'Force synchronized output now. We are sending out the data programmed in the last cycle. -' THis way all the outputs are updated at the beginning of an event, which is well timed. -' Doing Syncall() at the end of an event causes the channel outputs to move around in time, depending on how many channels -' are being programmed. - -eventcount=eventcount+delaymultinuse -if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) -endif - -delayinuse=delay ' reset the GlobalDelay -if(Data_1[counts]<0) then ' if we see a negative number, interpret it as a multiplicative factor on the delay - delayinuse=delay*(-1*Data_1[counts]) - delaymultinuse=-1*Data_1[counts] -endif -GLOBALDELAY=delayinuse - - -' reset the variables controlling digital output. -digitalactive=0 -digital2active=0 -val_lower=0 -val_upper=0 -val_lower2=0 -val_upper2=0 -counts=counts+1 'Number of events so far - - -IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each elementof DATA_1 for an update - For i=1 to Data_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=Data_2[updates] - - '*****************Analog outs*********************** - if((ch>=1) and (ch<=32)) then - AnalogWrite(ch,Data_3[updates]) - endif - - '*****************DDS outs************************* - if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS1 - DDS1Write(Data_3[updates]) - endif - - if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS2 - DDS2Write(Data_3[updates]) - ENDIF 'end BB - - '***********************Digital outs********** - if(ch=101) then - val_lower=Data_3[updates] - DIG_WRITELATCH32(2,val_lower) - endif - - if(ch=102) then - val_upper=Data_3[updates] - DIG_WRITELATCH32(3,val_upper) - endif - - NEXT i 'B for loop -ENDIF 'A: -If(counts>=maxcount+1) then end - - -FINISH: -'Clear all channels -Par_3=counts -Par_4=maxcount - -'If (Data_4[27]=0) then - For i= 1 to 8 - if(Data_4[i]=1) then - WRITEDAC(1,i,V(0)) - ENDIF - if(Data_4[i+8]=1) then - WRITEDAC(2,i,V(0)) - ENDIF - if(Data_4[i+16]=1) then - WRITEDAC(3,i,V(0)) - ENDIF - if(Data_4[i+24]=1) then - WRITEDAC(4,i,V(0)) - ENDIF - Next i - 'set line 28 high... forget why... - DIG_WRITELATCH32(2,2^28) -'ENDIF - -SYNCALL() - -'*************************************************** -SUB AnalogWrite(achannel, avalue) - if((achannel>=1)and(achannel<=8)) then - writedac(1,achannel,V(avalue)) - endif - - if((achannel>=9)and(achannel<=16)) then - writedac(2,achannel-8,V(avalue)) - endif - - if((achannel>=17)and(achannel<=24)) then - writedac(3,achannel-16,V(avalue)) - endif - - if((achannel>=25)and(achannel<=32)) then - writedac(4,achannel-24,V(avalue)) - endif -ENDSUB -'*************************************************** -SUB DDS1Write(digvalue) - dim tempval as long - dim dataline,clock,ioupdate,ioreset,masterreset as long - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - if(digvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = digvalue 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - ELSE - IF(digvalue=4) then 'write to the i/o reset pin to reset the buffer. - 'DIGOUT_F(2,ioreset,1) ' Currently disabled - 'DIGOUT_F(2,ioreset,0) - Else - IF(digvalue=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(digvalue=6) then - DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif -ENDSUB -'*************************************************** -SUB DDS2WRITE(dvalue) - dim tempval as long - dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - if(dvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = dvalue 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - ELSE - IF(dvalue=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 'DIGOUT_F(2,ioreset9858,0) - Else - IF(dvalue=5) then - DIGOUT_F(2,ioupdate9858,1) - DIGOUT_F(2,ioupdate9858,0) - Else - IF(dvalue=6) then - DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) - ENDIF - endif - endif - endif -ENDSUB diff --git a/TransferData_June30_2006.TA1 b/TransferData_June30_2006.TA1 deleted file mode 100644 index 3a85e9bd75fa3f3a1a36e3d6c7ca4b2b8c255633..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 17301 zcmeHPU2Ggz6+ZXQ+73>r*N)S)Y0|DYP6;W6q@<)ju-&9_DQzez4Fy`Dfi`K0sN@z@ zcuFUEp@lv~f(l-c##MNUgec;LAGPEO^#MTALMW~VLI(YZhrx3 z(z{`J-;4HFotB{DS+4gihds+TJj+X+7Qgi1Y^P6Un`gP-vpnNjUhph`>$Lc#D?eZi z98L<@8v$wHc!4q!*-ZOY^jS~)mDDezzKQzf)HhP!K>Z5pkchL6I_^ThlsY~IeJyoF zgFZ#Qrn-Ryo`-0Mj6~*Z;iLqsY9X*~r#!^FlDVAcLG{dDag1nI;2#;3QbBvD7W#

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-#include ADwinPRO_ALL.inc -'Updated to new ADbasic code - Ben Sofka -dim i,j,k,lightcount,litup,eventcount,delaymultinuse as long -dim DATA_1[5000000] as long -dim DATA_2[5000000] as long -dim DATA_3[5000000] as float -dim DATA_4[100] as long ' a list of which channels are reset to zero on completion -dim value as float -dim counts,maxcount,updates,i,j,k as long -dim ch as long -dim val,val_lower,val_upper,val_lower2,val_upper2 as long -dim tempval as long -dim dataline,clock, ioupdate,ioreset,masterreset as long -dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long -dim digitallow as long -dim delay,delayinuse as long -dim numbertoskip as long -dim leddelay as float -dim digitalactive,digital2active as long - -Function V(value) as float - V=(value+10)/20*65535 -ENDFUNCTION - -SUB Light_LED(lit) as - SELECTCASE lit - CASE 1 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 2 - P2_SET_LED(1,0) - P2_SET_LED(2,1) - CASE 3 - P2_SET_LED(2,0) - P2_SET_LED(3,1) - CASE 4 - P2_SET_LED(3,0) - P2_SET_LED(4,1) - CASE 5 - P2_SET_LED(4,0) - P2_SET_LED(1,1) - CASE 6 - P2_SET_LED(1,0) - P2_SET_LED(2,1) - CASE 8 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 9 - P2_SET_LED(1,0) - P2_SET_LED(4,1) - CASE 10 - P2_SET_LED(4,0) - P2_SET_LED(3,1) - CASE 11 - P2_SET_LED(3,0) - P2_SET_LED(2,1) - CASE 12 - P2_SET_LED(2,0) - P2_SET_LED(1,1) - CASE 13 - P2_SET_LED(1,0) - 'SETLED(2,da,1) - ENDSELECT -ENDSUB - - - -INIT: - - 'Jan 16/2004 - 'expecting 3 arrays. - 'Data_1: A list which specifies how many channels will be updated per event - 'Data_2: A list of channels to be updates - 'Data_3: A list of values for the channels - - 'Data_2 and Data_3 have a 1:1 correspondence. - 'Stepping through data2 and 3 is controlled by Data 1 - 'Computer send an integer to Par_1. This tells us how many - 'events to write. ) - 'Channels 1-32 refer to Analog output lines - 'Channel 101,102 refers to Digital output lines (16 bit word x2) - 'Channel 103,104 refer to Digital output lines (16 bit word X2) - 'channel 51-53 refers to digital output lines controlling the DDS - 'DDS control lines are digital output lines - 'Data line, read clock, io update , reset - ' 0-3 data - ' 4 I/O reset - ' 5 update clock - ' 6 master Reset - ' 7 (maybe) RF switch - delay=PAR_2 ' 300000=>1ms for T11 Processor: Updated July 14 2009 - Ben Sofka - PROCESSDELAY=delay - 'DDS digital line setup - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - - DigProg1(1,65535) - DigProg2(1,65535) - DigProg1(2,65535) - DigProg2(2,65535) - - ' Seth Aubin: removed these lines --> we do not have a 3rd DIO card - 'DigProg1(3,65535) - 'DigProg2(3,65535) - ' ------------------------------------------------------------------ - - 'Configure cards for synchronous output - SYNCENABLE(1,dio,1) - SYNCENABLE(2,dio,1) - - ' Seth Aubin: removed these lines --> we do not have a 3rd DIO card - 'SYNCENABLE(3,dio,1) - ' ------------------------------------------------------------------ - - SYNCENABLE(1,da,1) - SYNCENABLE(2,da,1) - SYNCENABLE(3,da,1) - SYNCENABLE(4,da,1) - - numbertoskip=0 - counts=1 - maxcount=PAR_1 - updates=1 - lightcount=0 - eventcount=0 - leddelay=8000000/PROCESSDELAY - PAR_11=DATA_1[1] - PAR_12=DATA_1[2] - PAR_13=DATA_1[3] - FPar_11=DATA_2[1] - FPar_12=DATA_2[2] - FPar_13=DATA_2[3] - ' Make sure the DDS lines are low. - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,0) - DIGOUT_F(2,ioreset,0) - DIGOUT_F(2,ioupdate,0) - DIGOUT_F(2,masterreset,0) - - -EVENT: - P2_SYNC_ALL(1111b) 'Force synchronized output now. We are sending out the data programmed in the last cycle. - ' THis way all the outputs are updated at the beginning of an event, which is well timed. - ' Doing Syncall() at the end of an event causes the channel outputs to move around in time, depending on how many channels - ' are being programmed. - - eventcount=eventcount+delaymultinuse - if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) - endif - - delayinuse=delay ' reset the PROCESSDELAY - if(DATA_1[counts]<0) then ' if we see a negative number, interpret it as a multiplicative factor on the delay - delayinuse=delay*(-1*DATA_1[counts]) - delaymultinuse=-1*DATA_1[counts] - endif - PROCESSDELAY=delayinuse - - - ' reset the variables controlling digital output. - digitalactive=0 - digital2active=0 - val_lower=0 - val_upper=0 - val_lower2=0 - val_upper2=0 - counts=counts+1 'Number of events so far - - ' Added by Seth Aubin on August 2, 2010. - DIG_LATCH(1) 'required for operation of DIO 1 ..suppose to be like P2_SYNC_ALL - DIG_LATCH(2) 'required for operation of DIO 1 ..suppose to be like P2_SYNC_ALL - - IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each elementof DATA_1 for an update - For i=1 to DATA_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=DATA_2[updates] - - '*****************Analog outs*********************** - if((ch>=1) and (ch<=32)) then - AnalogWrite(ch,DATA_3[updates]) - endif - - '*****************DDS outs************************* - 'if(ch=51) then 'AA: is ch=51, then act on the code to write to the DDS1 - ' DDS1Write(DATA_3[updates]) - 'endif - - 'if(ch=52) then 'BB: is ch=52, then write 2 bits to the DDS2 - ' DDS2Write(DATA_3[updates]) - 'ENDIF 'end BB - - '***********************Digital outs********** - if(ch=101) then - val_lower=DATA_3[updates] - DIG_WRITELATCH32(1,val_lower) ' Seth Aubin, Aug. 2, 2010: "2" -->"1" - endif - - if(ch=102) then - val_upper=DATA_3[updates] - DIG_WRITELATCH32(2,val_upper) ' Seth Aubin, Aug. 2, 2010: "3" -->"2" - endif - - NEXT i 'B for loop - ENDIF 'A: - If(counts>=maxcount+1) then end - - -FINISH: - 'Clear all channels - PAR_3=counts - PAR_4=maxcount - - 'If (Data_4[27]=0) then - For i= 1 to 8 - if(DATA_4[i]=1) then - P2_WRITE_DAC(1,i,V(0)) - ENDIF - if(DATA_4[i+8]=1) then - P2_WRITE_DAC(2,i,V(0)) - ENDIF - if(DATA_4[i+16]=1) then - P2_WRITE_DAC(3,i,V(0)) - ENDIF - if(DATA_4[i+24]=1) then - P2_WRITE_DAC(4,i,V(0)) - ENDIF - Next i - 'set line 28 high... forget why... - DIG_WRITELATCH32(2,2^28) - 'ENDIF - - P2_SYNC_ALL(1) - - '*************************************************** -SUB AnalogWrite(achannel, avalue) - if((achannel>=1)and(achannel<=8)) then - P2_WRITE_DAC(1,achannel,V(avalue)) - endif - - if((achannel>=9)and(achannel<=16)) then - P2_WRITE_DAC(2,achannel-8,V(avalue)) - endif - - if((achannel>=17)and(achannel<=24)) then - P2_WRITE_DAC(3,achannel-16,V(avalue)) - endif - - if((achannel>=25)and(achannel<=32)) then - P2_WRITE_DAC(4,achannel-24,V(avalue)) - endif -ENDSUB -'*************************************************** -SUB DDS1Write(digvalue) - dim tempval as long - dim dataline,clock,ioupdate,ioreset,masterreset as long - dataline=31 ' data line - clock=30 ' data clock - ioupdate=29 ' update line. transfers data from buffer into registers - ioreset=28 ' resets input buffers - masterreset=27 - if(digvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = digvalue 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - ELSE - IF(digvalue=4) then 'write to the i/o reset pin to reset the buffer. - 'DIGOUT_F(2,ioreset,1) ' Currently disabled - 'DIGOUT_F(2,ioreset,0) - Else - IF(digvalue=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(digvalue=6) then - DIGOUT_F(2,masterreset,1) ' Leave this doubled as the reset pulse needs to be > 800ns - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif -ENDSUB -'*************************************************** -SUB DDS2WRITE(dvalue) - dim tempval as long - dim dataline9858,clock9858,ioupdate9858,ioreset9858,masterreset9858 as long - 'DDS2 digital lines (base 0) - dataline9858=21 - clock9858=22 - ioupdate9858=19 - 'ioreset9858=23 - masterreset9858=18 - if(dvalue<=3) then ' write 2 bits to the data line of the DDS - tempval = dvalue 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - ELSE - IF(dvalue=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 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-SYNCENABLE(1,dio,1) -SYNCENABLE(2,dio,1) -SYNCENABLE(1,da,1) -SYNCENABLE(2,da,1) -SYNCENABLE(3,da,1) - -numbertoskip=0 -counts=1 -maxcount=Par_1 -updates=1 -lightcount=0 -eventcount=0 -leddelay=8000000/GLOBALDELAY -Par_11=Data_1[1] -Par_12=Data_1[2] -Par_13=Data_1[3] -FPar_11=Data_2[1] -FPar_12=Data_2[2] -FPar_13=Data_2[3] -DIGOUT_F(2,clock,0) -DIGOUT_F(2,dataline,0) -DIGOUT_F(2,ioreset,0) -DIGOUT_F(2,ioupdate,0) -DIGOUT_F(2,masterreset,0) - - -EVENT: -digitalactive=0 -digital2active=0 -eventcount=eventcount+1 -if(eventcount>leddelay) then - eventcount=0 - if(litup=14) then - litup=0 - endif - litup=litup+1 - Light_LED(litup) -endif - ' Careful with for loops. They always do at least 1 execution. -delayinuse=delay - -digitalactive=0 -val_lower=0 -val_upper=0 -val_lower2=0 -val_upper2=0 -SYNCALL() -counts=counts+1 -if(Data_1[counts]<0) then - delayinuse=delay*(-1*Data_1[counts]) -endif -GLOBALDELAY=delayinuse - -IF((99>DATA_1[counts]) and (DATA_1[counts]>=1)) then 'A:Check each element for an update - For i=1 to Data_1[counts] 'B: Loop over number of updates at this time - updates=updates+1 - ch=Data_2[updates] -'***************************************************DDS1 commands (Rb Evaporation)*********************** - if(ch=51) then 'AA: is ch=31, then write 2 bits to the DDS - if(Data_3[updates]<=3) then ' write 2 bits to the data line of the DDS - tempval = Data_3[updates] 'have to convert to long first - ' on Mar 25, we added opto-couplers to the DDS interfacing - ' this adds a 500ns (roughly) delay to each update - ' 3 updates takes 500ns, so each one opto-coupler delay is - '160 ns different from another, timing will be ruined. - ' so, double each line so pulses are 1us instead - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,dataline,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,dataline,(tempval and 1)) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,1) - DIGOUT_F(2,clock,0) - DIGOUT_F(2,clock,0) - - ELSE - IF(Data_3[updates]=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset,1) - 'DIGOUT_F(2,ioreset,0) - Else - IF(data_3[updates]=5) then - DIGOUT_F(2,ioupdate,1) - DIGOUT_F(2,ioupdate,0) - Else - IF(data_3[updates]=6) then - DIGOUT_F(2,masterreset,1) - DIGOUT_F(2,masterreset,0) - ENDIF - endif - endif - endif - ENDIF 'end AA -'***************************************************DDS2 commands ()*********************** - if(ch=52) then 'AA: is ch=31, then write 2 bits to the DDS - if(Data_3[updates]<=3) then ' write 2 bits to the data line of the DDS - tempval = Data_3[updates] 'have to convert to long first - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,dataline9858,SHIFT_RIGHT((tempval and 2),1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,dataline9858,(tempval and 1)) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,1) - DIGOUT_F(2,clock9858,0) - DIGOUT_F(2,clock9858,0) - - ELSE - IF(Data_3[updates]=4) then 'write to the i/o update pin to transfer to registers - 'DIGOUT_F(2,ioreset9858,1) - 'DIGOUT_F(2,ioreset9858,0) - Else - IF(data_3[updates]=5) then - DIGOUT_F(2,ioupdate9858,1) - DIGOUT_F(2,ioupdate9858,0) - Else - IF(data_3[updates]=6) then - DIGOUT_F(2,masterreset9858,1) - DIGOUT_F(2,masterreset9858,0) - ENDIF - endif - endif - endif - ENDIF 'end AA -'***********************Digital outs********** - if(ch=101) then - val_lower=Data_3[updates] - digitalactive=1 - endif - if(ch=102) then - val_upper=Data_3[updates] - digitalactive=1 - endif - if(digitalactive=1) then - DIG_WRITELATCH32(2,val_lower+2^16*val_upper) - endif - if(ch=103) then - val_lower2=Data_3[updates] - digital2active=1 - endif - if(ch=104) then - val_upper2=Data_3[updates] - digital2active=1 - endif - if(digital2active=1) then -' DIG_WRITELATCH32(2,val_lower2) - DIG_WRITELATCH32(3,val_lower2+2^16*val_upper2) - endif -'*****************Analog outs*********************** - if((ch>=1)and(ch<=8)) then - writedac(1,ch,V(Data_3[updates])) - endif - - if((ch>=9)and(ch<=16)) then - writedac(2,ch-8,V(Data_3[updates])) - endif - - if((ch>=17)and(ch<=24)) then - writedac(3,ch-16,V(Data_3[updates])) - endif - - if((ch>=25)and(ch<=32)) then - writedac(4,ch-24,V(Data_3[updates])) - endif -'*******done all updates***** - NEXT i 'B for loop -ENDIF 'A: -If(counts>=maxcount+1) then end - - -FINISH: -'Clear all channels -Par_3=counts -Par_4=maxcount - -'If (Data_4[27]=0) then - For i =1 to 8 - if(Data_4[i]=1) then - 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-/****************************************************************************** -Command Sequence Manipulation Tools -******************************************************************************/ - -/* for each 1-byte command there is an associated index, which corresponds to -the time at which the command should be executed, measured in multiples of the -ADWIN event period -*/ -typedef struct dds_cmd_sequence_struct { - /* the two arrays are always at the same length, cmd_array_size */ - unsigned char* cmds; /* array of compiled cmds */ - unsigned long* times; /* event index for the cmds */ - unsigned long array_size; - unsigned long num_written; /* portion of array currently filled */ -} dds_cmd_sequence_struct; - - - -/* heap-allocate a fresh dds_cmd_sequence_struct, initialised to empty */ -static dds_cmds_ptr new_dds_cmd_sequence () { - dds_cmds_ptr newstruct; - - newstruct = malloc(sizeof(struct dds_cmd_sequence_struct)); - newstruct->cmds = NULL; - newstruct->times = NULL; - newstruct->array_size = 0; - newstruct->num_written = 0; - return newstruct; -} - -void free_dds_cmd_sequence (dds_cmds_ptr dead_cmds) { - if (dead_cmds != NULL) { - if (dead_cmds->cmds != NULL) { - free(dead_cmds->cmds); - } - if (dead_cmds->times != NULL) { - free(dead_cmds->times); - } - /* don't bother resetting the struct fields since it's going to get - freed immediately */ - free(dead_cmds); - } -} - -/* Fetch the ADWIN command value for the specified index in the sequence, -or return -1 if none is available - -Need to return int to allow for the -1 (search failed flag) - -Use binary search, but be careful never to decrement below 0, even in the -case where the search fails at the zeroth index. Decrementing an unsigned # -causes wraparound, a bad array index, and then general protection fault. - -This function is publicly accessible, so needs to check for NULL pointers -*/ -int get_dds_cmd (dds_cmds_ptr cmd_sequence, unsigned long event_index) -{ - unsigned long lbound, ubound, mid; - unsigned long* times; - - if(cmd_sequence == NULL) return -1; - - times = cmd_sequence->times; - lbound = 0; - ubound = cmd_sequence->num_written; - /* if array is empty, ubound==0 and search is skipped */ - - /* search space is lbound <= i < ubound, as in usual for-loop convention */ - while(lbound < ubound) - { - /* lbound <= mid < ubound because of integer divide, so it's within - search space and a safe array index - */ - mid = (lbound + ubound) / 2; - - if(times[mid] == event_index) - return (int) cmd_sequence->cmds[mid]; - else if(times[mid] < event_index) - lbound = mid + 1; - else - ubound = mid; - /* N.B.: the search space is narrowed at each pass, since mid is always - * excluded, either by incrementing the (inclusive) lower bound past it - * or by reducing the (exclusive) upper bound to it. - * This guarantees search convergence. - * Also, we never decrement anything below the (known-good) lbound, - * so we can't wraparound by decrementing 0 - */ - } - - /* lbound==ubound so search space is empty */ - return -1; -} - -/* -Ensure the cmd_array can contain _at least_ min_size -commands. Doubles the array size every time it grows to give amortized -constant-time performance. - -Never pass in a null pointer (the outside world doesn't have access to this -function, so we can guarantee this just for the code in this file). -*/ -static void check_cmd_array_size (dds_cmds_ptr cmd_sequence, - unsigned long min_size) { - unsigned long new_size; - - /* fast check for common case, skips rest of function */ - if(min_size > cmd_sequence->array_size) { - /* if we need to grow, grow to larger of min_size or 2* current size */ - new_size = 2 * cmd_sequence->array_size; - new_size = min_size > new_size ? min_size : new_size; - - /* realloc to new size */ - cmd_sequence->cmds = realloc(cmd_sequence->cmds, - new_size*sizeof(unsigned char)); - cmd_sequence->times = realloc(cmd_sequence->times, - new_size*sizeof(unsigned long)); - cmd_sequence->array_size = new_size; - } -} - -/* -Add a single instruction byte to the command sequence, taking care of resizing - -cmd_sequence: (pointer to) sequence to which the instruction should be added - -cmd_time: the time (measured in update periods) at which the instruction -is to be sent, with the special value NEXT_AVAILABLE meaning "as soon as -possible after the previous command" - -cmd_byte: the byte to be interpreted by the ADWIN - -Return value: the next available command time - -start_index needs to be greater than previous indices so that the index -sequence is monotonically increasing (needed for lookup to work properly). -Should always be ok as long as we construct the commands in chronological order - -Never pass in a NULL cmd_sequence (locally-maintained invariant) -*/ -#define NEXT_AVAILABLE ULONG_MAX -static unsigned long append_byte (dds_cmds_ptr cmd_seq, - unsigned long cmd_time, - unsigned char cmd_byte) -{ - unsigned long next_avail; - - if (cmd_seq->num_written) { /* non-empty sequence */ - /* one event period past the last-specified time */ - next_avail = cmd_seq->times[cmd_seq->num_written - 1] + 1; - } else { /* empty sequence, start at 0 */ - next_avail = 0; - } - - if (cmd_time == NEXT_AVAILABLE) { - cmd_time = next_avail; - } else { /* specific time requested */ - if(cmd_time < next_avail) { - // printf("WARNING: tried to send a DDS command before the previous " - // "one had completed.\n" - // "Deferring to next available time slot\n"); - cmd_time = next_avail; - } /* else specific request was ok, leave it */ - } - - - check_cmd_array_size(cmd_seq, ++(cmd_seq->num_written)); - - /* we've already incremented num_written, so num_written-1 is the - index to fill in - */ - cmd_seq->times[cmd_seq->num_written - 1] = cmd_time; - cmd_seq->cmds[cmd_seq->num_written - 1] = cmd_byte; - return cmd_time + 1; -} - -/* Append the sequence of commands needed to send instr_byte over the -serial connection to the DDS, starting at "time" (in event periods). - -Return value: the next available command time - -cmd_seq is never NULL (locally maintained invariant) -*/ -static unsigned long append_serial_byte (dds_cmds_ptr cmd_seq, - unsigned long time, - unsigned char instr_byte) -{ - /* send byte 2 bits at a time, starting with the MSB. */ - append_byte(cmd_seq, time, (instr_byte>>6) & 0x03); - append_byte(cmd_seq, NEXT_AVAILABLE, (instr_byte>>4) & 0x03); - append_byte(cmd_seq, NEXT_AVAILABLE, (instr_byte>>2) & 0x03); - return append_byte(cmd_seq, NEXT_AVAILABLE, instr_byte & 0x03); -} - -/****************************************************************************** -Wrappers for translating DDS commands - -Programming a register on the DDS involves sending 1 instruction byte giving -the address of the register to be modified, followed by the desired contents -of the register - -In the instruction byte, the most significant bit (first to be transmitted), -indicates whether this is a read or write (always a write for us), and the 4 -least significant bits are the address of the register to update. - -Instruction Byte Breakdown -Bit -MSB D6 D5 D4 D3 D2 D1 D0 -R/W X X X A3 A2 A1 A0 -Bit 7 controls whether read/write 0-> write 1-> read -A3-A0 define the register to access -******************************************************************************/ - -/* special command codes for ADWIN */ -#define IO_RESET 0x04 -#define UPDATE_CLOCK 0x05 -#define MASTER_RESET 0x06 - -/* serial addresses of the various registers */ -#define ADDR_PHASE_ADJUST_1 0x00 -#define ADDR_PHASE_ADJUST_2 0x01 - -/* low end of frequency ramp */ -#define ADDR_FREQ_TUNING_WORD_1 0x02 -/* high end of frequency ramp */ -#define ADDR_FREQ_TUNING_WORD_2 0x03 -/* frequency ramp step size */ -#define ADDR_DELTA_FREQ_WORD 0x04 - -#define ADDR_UPDATE_CLOCK 0x05 - -/* frequency ramp step time */ -#define ADDR_RAMPRATE_CLOCK 0x06 -/* assorted control functions, see below */ -#define ADDR_CONTROL_REGISTER 0x07 -/* output amplitude */ -#define ADDR_OSK_MULTIPLIER 0x08 -/* output amplitude ramping rate */ -#define ADDR_OSK_RAMPRATE 0x0A - -#define ADDR_CONTROL_DAC 0x0B - -/* Control Register bit assignments */ -/*31:29 Unused */ -#define CR_BIT_COMPARATOR_PD 28 /* Comparator power down (active high) */ -/* 27 Must always be written low! (otherwise DDS stops working) */ -#define CR_BIT_CONTROL_DAC_PD 26 /* Control DAC power down (active high) */ -#define CR_BIT_FULL_DAC_PD 25 /* Full DAC power down affects cosine DAC, - control DAC and reference */ -#define CR_BIT_DIGITAL_PD 24 /* Digital section power down */ -/* 23 Reserved, write 0 */ -#define CR_BIT_PLL_RANGE 22 /* PLL range bit, affects the VCO gain ? */ -#define CR_BIT_PLL_BYPASS 21 /* Use REFCLK directly without PLL multiplier */ -#define CR_BIT_PLL_MULT4 20 /* 20:16 PLL multiplier factor */ -#define CR_BIT_PLL_MULT3 19 /* must be in range [4,20] */ -#define CR_BIT_PLL_MULT2 18 -#define CR_BIT_PLL_MULT1 17 -#define CR_BIT_PLL_MULT0 16 -#define CR_BIT_CLR_ACC1 15 /* Clear accumulator 1 when written high */ -#define CR_BIT_CLR_ACCS 14 /* While high, locks accumulators 1 and 2 to zero */ -#define CR_BIT_TRIANGLE 13 /* Triangle bit: automatically ramp frequency back - and forth between the frequency tuning words */ - -/* 12 Don't care */ -#define CR_BIT_MODE2 11 /* 11:9 operating mode, see below */ -#define CR_BIT_MODE1 10 -#define CR_BIT_MODE0 9 -#define CR_BIT_INTERNAL_UPDATE 8 /*internal update active. - We want this low so that _we_ generate the - update clock signal */ -/* 7 Reserved, write to 0 */ -#define CR_BIT_INV_SINC_BYPASS 6 /* inverse sinc filter bypass */ -#define CR_BIT_OSK_ENABLE 5 /* OSK enable bit. Enable amplitude modulation */ -#define CR_BIT_INTERNAL_OSK 4 /* internal OSK override. Leave low so that our - amplitude settings are respected */ -/* 3:2 Reserved, write 0 */ -#define CR_BIT_LSB_FIRST 1 /* Serial port LSB first bit. - Leave to low (MSB first) */ -#define CR_BIT_SDO_ACTIVE 0 /* Serial port SDO active. - Leave low as we never read from the DDS. */ - -/* operating modes */ -#define MODE_SINGLE_TONE 0 -#define MODE_FSK 1 -#define MODE_RAMPED_FSK 2 -#define MODE_CHIRP 3 -#define MODE_BPSK 4 - -/* Shadow registers: -As the command sequence gets built up, these keep track of the state that -the DDS will be in at each point in the program. -Whenever any of these values gets changed, we set a flag, -and a single update_dds routine takes care of programming all the -flagged registers and sending the UPDATE_CLOCK command. - -This way we can accumulate incremental changes (eg to the control register), -set the flag, and when time comes to make use of those changes only the final -version of the register is programmed (this can't hurt us because the DDS only -pays attention to values in the i/o buffers when the UPDATE_CLOCK is sent). - -These arrays hold the most significant byte in the highest-numbered array -index, for ease in doing bit-addressing arithmetic. -*/ -typedef struct dds_shadow_struct { - unsigned char phase_adjust_reg_1[2]; - BOOL phase_adjust_reg_1_dirty; - unsigned char phase_adjust_reg_2[2]; - BOOL phase_adjust_reg_2_dirty; - unsigned char freq_tuning_word_1[6]; - BOOL freq_tuning_word_1_dirty; - unsigned char freq_tuning_word_2[6]; - BOOL freq_tuning_word_2_dirty; - unsigned char delta_freq_word[6]; - BOOL delta_freq_word_dirty; - unsigned char update_clock[4]; - BOOL update_clock_dirty; - unsigned char ramp_rate_clock[3]; - BOOL ramp_rate_clock_dirty; - unsigned char control_reg[4]; - BOOL control_reg_dirty; - unsigned char osk_multiplier[2]; - BOOL osk_multiplier_dirty; - unsigned char osk_ramp_rate[1]; - BOOL osk_ramp_rate_dirty; - unsigned char control_dac[2]; - BOOL control_dac_dirty; -} dds_shadow_struct; - -/* Append an i/o reset command to cmd_seq, to be executed at "time" (measured in -event periods. -Note that this has no effect on the internal state of the DDS. - -Return value: the next available command time - -cmd_seq is never NULL (locally maintained invariant) -*/ -static unsigned long io_reset (dds_cmds_ptr cmd_seq, - unsigned long time) -{ - return append_byte(cmd_seq, time, IO_RESET); -} - -/* Append a master reset command to cmd_seq to be executed at time (measured in -event periods). Update the shadow to represent the state of the DDS after the -reset. - -Return value: the next available command time - -cmd_seq and shadow are never NULL (locally maintained invariants) -*/ -static unsigned long master_reset (dds_cmds_ptr cmd_seq, - unsigned long time, - dds_shadow_struct* shadow) -{ - shadow->phase_adjust_reg_1[0] = 0x00; - shadow->phase_adjust_reg_1[1] = 0x00; - shadow->phase_adjust_reg_1_dirty = FALSE; - shadow->phase_adjust_reg_2[0] = 0x00; - shadow->phase_adjust_reg_2[1] = 0x00; - shadow->phase_adjust_reg_2_dirty = FALSE; - shadow->freq_tuning_word_1[0] = 0x00; - shadow->freq_tuning_word_1[1] = 0x00; - shadow->freq_tuning_word_1[2] = 0x00; - shadow->freq_tuning_word_1[3] = 0x00; - shadow->freq_tuning_word_1[4] = 0x00; - shadow->freq_tuning_word_1[5] = 0x00; - shadow->freq_tuning_word_1_dirty = FALSE; - shadow->freq_tuning_word_2[0] = 0x00; - shadow->freq_tuning_word_2[1] = 0x00; - shadow->freq_tuning_word_2[2] = 0x00; - shadow->freq_tuning_word_2[3] = 0x00; - shadow->freq_tuning_word_2[4] = 0x00; - shadow->freq_tuning_word_2[5] = 0x00; - shadow->freq_tuning_word_2_dirty = FALSE; - shadow->delta_freq_word[0] = 0x00; - shadow->delta_freq_word[1] = 0x00; - shadow->delta_freq_word[2] = 0x00; - shadow->delta_freq_word[3] = 0x00; - shadow->delta_freq_word[4] = 0x00; - shadow->delta_freq_word[5] = 0x00; - shadow->delta_freq_word_dirty = FALSE; - shadow->update_clock[0] = 0x40; - shadow->update_clock[1] = 0x00; - shadow->update_clock[2] = 0x00; - shadow->update_clock[3] = 0x00; - shadow->update_clock_dirty = FALSE; - shadow->ramp_rate_clock[0] = 0x00; - shadow->ramp_rate_clock[1] = 0x00; - shadow->ramp_rate_clock[2] = 0x00; - shadow->ramp_rate_clock_dirty = FALSE; - shadow->control_reg[0] = 0x20; - shadow->control_reg[1] = 0x01; - shadow->control_reg[2] = 0x64; - shadow->control_reg[3] = 0x10; - shadow->control_reg_dirty = FALSE; - shadow->osk_multiplier[0] = 0x00; - shadow->osk_multiplier[1] = 0x00; - shadow->osk_multiplier_dirty = FALSE; - shadow->osk_ramp_rate[0] = 0x80; - shadow->osk_ramp_rate_dirty = FALSE; - shadow->control_dac[0] = 0x00; - shadow->control_dac[1] = 0x00; - shadow->control_dac_dirty = FALSE; - - return append_byte(cmd_seq, time, MASTER_RESET); -} - -/* Append to cmd_seq instructions to update all modified registers in the -"shadow" bank, followed by an UPDATE_CLOCK command to start using the modified -values. The instructions will be scheduled to start at "time" (measured in -event periods) - -Return value: the next available command time - -cmd_seq and shadow are never NULL (locally maintained invariants) -*/ -static unsigned long update_dds (dds_cmds_ptr cmd_seq, - unsigned long time, - dds_shadow_struct* shadow) -{ - BOOL any_changes = FALSE; - /* for each dirty register in shadow, send out the address & data, MSB first - Have to manually keep track of time here because we don't know which - register, if any, will be first to be updated - */ - if (shadow->phase_adjust_reg_1_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_PHASE_ADJUST_1); - time = append_serial_byte(cmd_seq, time, shadow->phase_adjust_reg_1[1]); - time = append_serial_byte(cmd_seq, time, shadow->phase_adjust_reg_1[0]); - shadow->phase_adjust_reg_1_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->phase_adjust_reg_2_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_PHASE_ADJUST_2); - time = append_serial_byte(cmd_seq, time, shadow->phase_adjust_reg_2[1]); - time = append_serial_byte(cmd_seq, time, shadow->phase_adjust_reg_2[0]); - shadow->phase_adjust_reg_2_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->freq_tuning_word_1_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_FREQ_TUNING_WORD_1); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_1[5]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_1[4]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_1[3]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_1[2]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_1[1]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_1[0]); - shadow->freq_tuning_word_1_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->freq_tuning_word_2_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_FREQ_TUNING_WORD_2); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_2[5]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_2[4]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_2[3]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_2[2]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_2[1]); - time = append_serial_byte(cmd_seq, time, shadow->freq_tuning_word_2[0]); - shadow->freq_tuning_word_2_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->delta_freq_word_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_DELTA_FREQ_WORD); - time = append_serial_byte(cmd_seq, time, shadow->delta_freq_word[5]); - time = append_serial_byte(cmd_seq, time, shadow->delta_freq_word[4]); - time = append_serial_byte(cmd_seq, time, shadow->delta_freq_word[3]); - time = append_serial_byte(cmd_seq, time, shadow->delta_freq_word[2]); - time = append_serial_byte(cmd_seq, time, shadow->delta_freq_word[1]); - time = append_serial_byte(cmd_seq, time, shadow->delta_freq_word[0]); - shadow->delta_freq_word_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->update_clock_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_UPDATE_CLOCK); - time = append_serial_byte(cmd_seq, time, shadow->update_clock[3]); - time = append_serial_byte(cmd_seq, time, shadow->update_clock[2]); - time = append_serial_byte(cmd_seq, time, shadow->update_clock[1]); - time = append_serial_byte(cmd_seq, time, shadow->update_clock[0]); - shadow->update_clock_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->ramp_rate_clock_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_RAMPRATE_CLOCK); - time = append_serial_byte(cmd_seq, time, shadow->ramp_rate_clock[2]); - time = append_serial_byte(cmd_seq, time, shadow->ramp_rate_clock[1]); - time = append_serial_byte(cmd_seq, time, shadow->ramp_rate_clock[0]); - shadow->ramp_rate_clock_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->control_reg_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_CONTROL_REGISTER); - time = append_serial_byte(cmd_seq, time, shadow->control_reg[3]); - time = append_serial_byte(cmd_seq, time, shadow->control_reg[2]); - time = append_serial_byte(cmd_seq, time, shadow->control_reg[1]); - time = append_serial_byte(cmd_seq, time, shadow->control_reg[0]); - shadow->control_reg_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->osk_multiplier_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_OSK_MULTIPLIER); - time = append_serial_byte(cmd_seq, time, shadow->osk_multiplier[1]); - time = append_serial_byte(cmd_seq, time, shadow->osk_multiplier[0]); - shadow->osk_multiplier_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->osk_ramp_rate_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_OSK_RAMPRATE); - time = append_serial_byte(cmd_seq, time, shadow->osk_ramp_rate[0]); - shadow->osk_ramp_rate_dirty = FALSE; - any_changes = TRUE; - } - if (shadow->control_dac_dirty) { - time = append_serial_byte(cmd_seq, time, ADDR_CONTROL_DAC); - time = append_serial_byte(cmd_seq, time, shadow->control_dac[1]); - time = append_serial_byte(cmd_seq, time, shadow->control_dac[0]); - shadow->control_dac_dirty = FALSE; - any_changes = TRUE; - } - if (any_changes) { - return append_byte(cmd_seq, time, UPDATE_CLOCK); - } else { - return time; - } -} - -/* if necessary, modifies the control register in shadow so that -control_register[bit] has the same truth value as val - -shadow is never NULL -*/ -static void set_control_register_bit (dds_shadow_struct* shadow, - int bit, - int val) -{ - if (val) { /* want bit set */ - if (!((shadow->control_reg[bit/8] >> (bit % 8)) & 0x01)) { - shadow->control_reg[bit/8] |= 0x01 << (bit %8); - shadow->control_reg_dirty = TRUE; - } - } else { /* want bit clear */ - if (((shadow->control_reg[bit/8] >> (bit % 8)) & 0x01)) { - shadow->control_reg[bit/8] &= ~(0x01 << (bit % 8)); - shadow->control_reg_dirty = TRUE; - } - } -} - -static void set_PLL_mult (dds_shadow_struct* shadow, unsigned int pll_mult) -{ - /* make sure multiplier value is in range */ - pll_mult = pll_mult > 20 ? 20 : pll_mult; - pll_mult = pll_mult < 4 ? 4 : pll_mult; - - /* set_control_register_bit takes care of the dirty flag, modifies - only if necessary */ - set_control_register_bit(shadow, CR_BIT_PLL_MULT4, (pll_mult>>4) & 0x01); - set_control_register_bit(shadow, CR_BIT_PLL_MULT3, (pll_mult>>3) & 0x01); - set_control_register_bit(shadow, CR_BIT_PLL_MULT2, (pll_mult>>2) & 0x01); - set_control_register_bit(shadow, CR_BIT_PLL_MULT1, (pll_mult>>1) & 0x01); - set_control_register_bit(shadow, CR_BIT_PLL_MULT0, pll_mult & 0x01); -} - -static void set_operating_mode (dds_shadow_struct* shadow, unsigned int mode) -{ - /* make sure mode value is in range */ - mode = mode > 4 ? 4 : mode; - - /* set_control_register_bit takes care of the dirty flag, modifies - only if necessary */ - set_control_register_bit(shadow, CR_BIT_MODE2, (mode>>2) & 0x01); - set_control_register_bit(shadow, CR_BIT_MODE1, (mode>>1) & 0x01); - set_control_register_bit(shadow, CR_BIT_MODE0, mode & 0x01); -} - -/* Modify the shadow settings to give DDS output "amplitude" (where -MAX_AMPLITUDE corresponds to full output power). - -shadow is never NULL (locally maintained invariant) -*/ -static void set_amplitude (dds_shadow_struct* shadow, float amplitude) -{ - unsigned long osk_mult_setting; - - /* need manual OSK control for this to work */ - set_control_register_bit(shadow, CR_BIT_OSK_ENABLE, TRUE); - set_control_register_bit(shadow, CR_BIT_INTERNAL_OSK, FALSE); - - if (shadow->osk_ramp_rate[0] >= 3) { - /* The Output shaped keying function is really designed to ramp signals - on and off (to reduce high-frequency switching noise in communications - applications). - We "trick" it into giving us output amplitude control by setting the - ramp rate to a value less than 3. This stalls the ramp rate counter so that - instead of ramping up the osk multiplier to full power it simply holds it - constant. - This way, the osk multiplier acts as a fixed output amplitude setting - */ - shadow->osk_ramp_rate[0] = 0; - shadow->osk_ramp_rate_dirty = TRUE; - } - - /* The osk multiplier value is scaled out of 4095 (the 12 lower bits of the - register */ - osk_mult_setting = (4095*amplitude)/MAX_AMPLITUDE; - /* make sure value is in bounds */ - osk_mult_setting = osk_mult_setting > 4095 ? 4095 : osk_mult_setting; - - if (shadow->osk_multiplier[1] != (unsigned char) (osk_mult_setting >> 8) - || shadow->osk_multiplier[0] != (unsigned char) osk_mult_setting) { - /* setting has changed */ - shadow->osk_multiplier[1] = (unsigned char) (osk_mult_setting >> 8); - shadow->osk_multiplier[0] = (unsigned char) osk_mult_setting; - shadow->osk_multiplier_dirty = TRUE; - } -} - -/* Modify the DDS shadow registers to set the ramp rate clock for a frequency -sweep that takes delta_time seconds. - -sysclk is the DDS system clock frequency in MHz (refclk * PLL multiplier) - -shadow is never NULL -*/ -static void set_frequency_ramp_rate(dds_shadow_struct* shadow, - float delta_time, - float sysclk) -{ - - unsigned long ramp_rate; - unsigned char new_ramprate_reg[3]; - int i; - - /* output frequency steps every (ramp_rate + 1) * 2 system clock periods - so we want: - delta_time * STEP_GRANULARITY = step time = (ramp_rate + 1) * 2 / sysclk - - note the unit conversion from MHz to Hz for sysclk - */ - ramp_rate = (sysclk * 1e6) * delta_time * STEP_GRANULARITY / 2 - 1; - /* casts truncate high bits */ - new_ramprate_reg[2] = (unsigned char) (ramp_rate >> 16); - new_ramprate_reg[1] = (unsigned char) (ramp_rate >> 8); - new_ramprate_reg[0] = (unsigned char) ramp_rate; - - for (i = 0; i < 3; ++i) { - if (shadow->ramp_rate_clock[i] != new_ramprate_reg[i]) { - shadow->ramp_rate_clock[i] = new_ramprate_reg[i]; - shadow->ramp_rate_clock_dirty = TRUE; - } - } -} - -/* Take the desired frequency (in MHz) and set the 6-byte freq_reg to the -corresponding value. - -sysclk is the DDS system clock frequency, also in MHz - -Return TRUE if freq_reg had to be modified, FALSE otherwise - -freq_reg is never NULL -*/ -static BOOL convert_freq(unsigned char* freq_reg, - float frequency, - float sysclk) -{ - int i; - double shift_factor; - double frequency_ratio; - unsigned char new_byte_val; - BOOL was_modified = FALSE; - - /* The frequency is specified as a fixed-point 48-bit fraction according to - the following formula (freq * 2^48)/SYSCLK, where 2^48 is the phase - accumulator resolution - - the most significant byte is (freq/SYSCLCK * 2^8) (mod 256), - the second is freq/SYSCLCK * 2^16 (mod 256), - and so forth - */ - - frequency_ratio = frequency / sysclk; - - for (i = 5, shift_factor = 256; i >= 0; --i, shift_factor *= 256) { - /* cast to unsigned char takes care of modulus and truncation */ - new_byte_val = frequency_ratio * shift_factor; - if (freq_reg[i] != new_byte_val) { - freq_reg[i] = new_byte_val; - was_modified = TRUE; - } - } - return was_modified; -} - -/* sets up the two frequency tuning words, the delta frequency word and the -ramp rate clock register -*/ -static void set_frequency_registers(dds_shadow_struct* shadow, - float start_frequency, - float end_frequency, - float ramp_time, - float sysclk) -{ - float lowfreq, highfreq, freqstep; - - - if (start_frequency < end_frequency) { - lowfreq = start_frequency; - highfreq = end_frequency; - } else { - lowfreq = end_frequency; - highfreq = start_frequency; - } - freqstep = (highfreq - lowfreq) * STEP_GRANULARITY; - - /* only set the dirty flags if something was modified */ - set_frequency_ramp_rate(shadow, ramp_time, sysclk); - shadow->freq_tuning_word_1_dirty = - convert_freq(shadow->freq_tuning_word_1, lowfreq, sysclk); - shadow->freq_tuning_word_2_dirty = - convert_freq(shadow->freq_tuning_word_2, highfreq, sysclk); - shadow->delta_freq_word_dirty = - convert_freq(shadow->delta_freq_word, freqstep, sysclk); -} - - -/* Take a high-level specification dds_options of the behaviour of the -DDS over a time interval dds_options.delta_time and append to cmd_sequence -(with associated "shadow" bank) ADWIN instructions necessary to execute -this behaviour, starting at "time" (measured in event periods) - -Return the next available command time -*/ -static unsigned long execute_dds_settings(dds_cmds_ptr cmd_seq, - unsigned long time, - dds_shadow_struct* shadow, - ddsoptions_struct dds_options, - float sysclk) -{ - if (dds_options.is_stop) { - /* set 0.0 amplitude and power down unused sections of the DDS - Note that update_dds won't send anything if the DDS is already - stopped, so we aren't wasting instructions - */ - set_amplitude(shadow, 0.0); - set_control_register_bit(shadow, CR_BIT_CONTROL_DAC_PD, TRUE); - set_control_register_bit(shadow, CR_BIT_FULL_DAC_PD, TRUE); - set_control_register_bit(shadow, CR_BIT_DIGITAL_PD, TRUE); - return update_dds(cmd_seq, time, shadow); - } else { /* not stopped */ - set_operating_mode(shadow, MODE_RAMPED_FSK); - set_frequency_registers(shadow, - dds_options.start_frequency, - dds_options.end_frequency, - dds_options.delta_time, - sysclk); - set_amplitude(shadow, dds_options.amplitude); - /* power up necessary sections of the DDS */ - set_control_register_bit(shadow, CR_BIT_FULL_DAC_PD, FALSE); - set_control_register_bit(shadow, CR_BIT_DIGITAL_PD, FALSE); - set_control_register_bit(shadow, CR_BIT_INV_SINC_BYPASS, FALSE); - - /* reset the phase and frequency accumulators */ - set_control_register_bit(shadow, CR_BIT_CLR_ACCS, TRUE); - - /* The comparator output is hard-wired on the DDS board - to the FSK/BPSK/HOLD input pin, which controls the sweep. - - For a descending sweep, we want to start at the high frequency end (F2) - and go to the low-frequency end (F1), - so we need the FSK input to start high (while we set up) and flip low - (to start the ramp) - - N.B, the input value of the FSK input pin is the opposite of the logic - value of the "comparator power down" bit - - Vice-versa for an ascending sweep - */ - if (dds_options.start_frequency < dds_options.end_frequency) { - set_control_register_bit(shadow, CR_BIT_COMPARATOR_PD, TRUE); - update_dds(cmd_seq, time, shadow); - - /* unlock the accumulators and toggle the FSK input bit to start - the ramp to the higher frequency */ - set_control_register_bit(shadow, CR_BIT_CLR_ACCS, FALSE); - set_control_register_bit(shadow, CR_BIT_COMPARATOR_PD, FALSE); - return update_dds(cmd_seq, NEXT_AVAILABLE, shadow); - } else { /* descending sweep */ - set_control_register_bit(shadow, CR_BIT_COMPARATOR_PD, FALSE); - update_dds(cmd_seq, time, shadow); - - /* unlock the accumulators and toggle the FSK input bit to start - the ramp to the lower frequency */ - set_control_register_bit(shadow, CR_BIT_CLR_ACCS, FALSE); - set_control_register_bit(shadow, CR_BIT_COMPARATOR_PD, TRUE); - return update_dds(cmd_seq, NEXT_AVAILABLE, shadow); - } - } -} - - - -/* Create and return a sequence of 1-byte commands to send to the ADWIN at -specified times in order to have the DDS execute the high-level behaviour -specified in dds_settings - -The size of the dds_settings array is given by num_settings - -PLL_multiplier is the desired DDS clock multiplier (the DDS's system clock -will run at PLL_multiplier * refclk) - -refclk is the frequency (in MHz) of the DDS's external oscillator - -adwin_event_period is the time (in seconds) between adwin update events -*/ -dds_cmds_ptr create_dds_cmd_sequence(ddsoptions_struct* dds_settings, - unsigned long num_settings, - unsigned int PLL_multiplier, - float refclk, - float adwin_event_period) -{ - dds_cmds_ptr cmd_sequence = NULL; - dds_shadow_struct shadow; - - long i; - float idealtime; - float sysclk; - - if (dds_settings == NULL || num_settings < 1) { - return NULL; - } - - sysclk = refclk * PLL_multiplier; - - cmd_sequence = new_dds_cmd_sequence(); - - - /* start from a known DDS state */ - master_reset(cmd_sequence, 0, &shadow); - - /* changes from default settings: */ - set_PLL_mult(&shadow, PLL_multiplier); - set_control_register_bit(&shadow, CR_BIT_PLL_BYPASS, FALSE); - /* we want to control the update clock */ - set_control_register_bit(&shadow, CR_BIT_INTERNAL_UPDATE, FALSE); - - idealtime = 0.0; - - /* Normally settings get scheduled at idealtime, corresponding to the - settings on the front panel. If this is impossible (because previous - commands haven't completed), then append_byte will generate a warning. - However, we _know_ that the first batch of settings will be delayed until - after the initial reset and configuration, so we handle it specially here - to avoid the error message. - */ - execute_dds_settings(cmd_sequence, NEXT_AVAILABLE, &shadow, - dds_settings[1], sysclk); - - for (i=2; i<=num_settings; i++) { - //set the start time based on the start time - //and delta time of the previous element - idealtime += dds_settings[i-1].delta_time; - - execute_dds_settings(cmd_sequence, idealtime / adwin_event_period, - &shadow, dds_settings[i], sysclk); - } - - return cmd_sequence; -} - diff --git a/dtcon.config b/dtcon.config deleted file mode 100644 index 23710bb..0000000 --- a/dtcon.config +++ /dev/null @@ -1,72 +0,0 @@ -Analog Channels -Row,Channel,Name,tbias,tfcn,MaxVolts,MinVolts,Units -1,1,AN1,0.000000,1.000000,0.000000,10.000000,V -2,2,An2,-4.000000,1.200000,0.000000,10.000000,MHZ -3,3,AN3,-3.000000,2.000000,-1.000000,3.000000,G -4,0,,0.000000,1.000000,0.000000,0.000000, -5,0,,0.000000,1.000000,0.000000,0.000000, -6,0,,0.000000,1.000000,0.000000,0.000000, -7,0,,0.000000,1.000000,0.000000,0.000000, -8,0,,0.000000,1.000000,0.000000,0.000000, -9,0,,0.000000,1.000000,0.000000,0.000000, -10,0,,0.000000,1.000000,0.000000,0.000000, -11,0,,0.000000,1.000000,0.000000,0.000000, -12,0,,0.000000,1.000000,0.000000,0.000000, -13,0,,0.000000,1.000000,0.000000,0.000000, -14,0,,0.000000,1.000000,0.000000,0.000000, -15,0,,0.000000,1.000000,0.000000,0.000000, -16,0,,0.000000,1.000000,0.000000,0.000000, -17,0,,0.000000,1.000000,0.000000,0.000000, -18,0,,0.000000,1.000000,0.000000,0.000000, -19,0,,0.000000,1.000000,0.000000,0.000000, -20,0,,0.000000,1.000000,0.000000,0.000000, -21,0,,0.000000,1.000000,0.000000,0.000000, -22,0,,0.000000,1.000000,0.000000,0.000000, -23,0,,0.000000,1.000000,0.000000,0.000000, -24,0,,0.000000,1.000000,0.000000,0.000000, -25,0,,0.000000,1.000000,0.000000,0.000000, -26,0,,0.000000,1.000000,0.000000,0.000000, -27,0,,0.000000,1.000000,0.000000,0.000000, -28,0,,0.000000,1.000000,0.000000,0.000000, -29,0,,0.000000,1.000000,0.000000,0.000000, -30,0,,0.000000,1.000000,0.000000,0.000000, -31,0,,0.000000,1.000000,0.000000,0.000000, -32,0,,0.000000,1.000000,0.000000,0.000000, -Digital Channels -Row,Channel,Name -1,1,DIG1 -2,2,DIG2 -3,0, -4,0, -5,0, -6,0, -7,0, -8,0, -9,0, -10,0, -11,0, -12,0, -13,0, -14,0, -15,0, -16,0, -17,0, -18,0, -19,0, -20,0, -21,0, -22,0, -23,0, -24,0, -25,0, -26,0, -27,0, -28,0, -29,0, -30,0, -31,0, -32,0, -33,0, -34,0, -35,0, -36,0, diff --git a/dtex.export b/dtex.export deleted file mode 100644 index 62516d6..0000000 --- a/dtex.export +++ /dev/null @@ -1,69 +0,0 @@ -Time(ms),10.000000,5.000000,9.000000,70.000000,12.000000,13.000000 -AN1, 3.00, 3.00, 3.00, 2.00, 3.00, 4.00 -An2, 4.00, 4.00, 5.00, 6.00, 0.00, 0.00 -AN3, 2.00, 2.00, 3.00, 3.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -, 0.00, 0.00, 0.00, 0.00, 0.00, 0.00 -DDS,ma4.00_FA5.00_FB6.00,ma4.00_FA5.00_FB7.00,ma10.00_FA7.00_FB9.00,ma13.00_FA10.00_FB11.00,OFF,OFFDIG1,1,1,0,1,0,0 -DIG2,0,1,1,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,0,0,0,0,0 -,0,201334793,8,6619182,7340152,7471215 -,0,0,21873936,2091037893,656544,0 -,1,12,21875928,4,0,32770 -,0,0,0,0,0,0 diff --git a/lasttest.pan b/lasttest.pan deleted file mode 100644 index dfb6603c50dc7954e50c242d2905e56cd81c3a21..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 33752 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