From eb3b2ff0e47fb80ead5efd139183967a69e9d88c Mon Sep 17 00:00:00 2001 From: Sridhara Dasu Date: Wed, 29 Mar 2023 16:33:38 -0500 Subject: [PATCH 1/5] Update SridharaDasu.md --- _collaborators/SridharaDasu.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/_collaborators/SridharaDasu.md b/_collaborators/SridharaDasu.md index f72e91c..bdceeba 100644 --- a/_collaborators/SridharaDasu.md +++ b/_collaborators/SridharaDasu.md @@ -9,7 +9,7 @@ github-username: SridharaDasu photo: "/assets/images/team/Sridhara-Dasu.jpeg" shortname: SridharaDasu title: -website: https://www.physics.wisc.edu/directory/dasu-sridhara/ +website: [https://www.hep.wisc.edu/home/dasu/] presentations: --- From de747cdfda04a9a25cf42d25a7e4111b8e58fe8f Mon Sep 17 00:00:00 2001 From: Sridhara Dasu Date: Wed, 29 Mar 2023 16:34:33 -0500 Subject: [PATCH 2/5] Update SridharaDasu.md --- _collaborators/SridharaDasu.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/_collaborators/SridharaDasu.md b/_collaborators/SridharaDasu.md index bdceeba..c635da2 100644 --- a/_collaborators/SridharaDasu.md +++ b/_collaborators/SridharaDasu.md @@ -9,7 +9,7 @@ github-username: SridharaDasu photo: "/assets/images/team/Sridhara-Dasu.jpeg" shortname: SridharaDasu title: -website: [https://www.hep.wisc.edu/home/dasu/] +website: https://www.hep.wisc.edu/home/dasu/ presentations: --- From 98501982dc3149d3b9db6acb9b8bbf06608419b5 Mon Sep 17 00:00:00 2001 From: Sridhara Dasu Date: Mon, 23 Dec 2024 08:14:33 -0600 Subject: [PATCH 3/5] Pulled the original from tac-hep site --- pages/training-modules.md | 3 ++- pages/training-modules/{uw-gpu-fpga.md => uw-gpu.md} | 0 pages/training-modules/{uw-gpu-fpga => uw-gpu}/syllabus.md | 0 3 files changed, 2 insertions(+), 1 deletion(-) rename pages/training-modules/{uw-gpu-fpga.md => uw-gpu.md} (100%) rename pages/training-modules/{uw-gpu-fpga => uw-gpu}/syllabus.md (100%) diff --git a/pages/training-modules.md b/pages/training-modules.md index a08fa41..f54af52 100644 --- a/pages/training-modules.md +++ b/pages/training-modules.md @@ -11,7 +11,8 @@ title: Training Modules #### List of trainings * [Software Engineering for Scientific Computing](/training-modules/software-engineering) -* [GPU and FPGA training module](/training-modules/uw-gpu-fpga) +* [GPU FPGA training module](/training-modules/uw-gpu) +* [FPGA training module](/training-modules/uw-fpga) * [Data Analysis Systems and Facilities](/training-modules/analysis-systems-and-facilities) * [Scalable Infrastructure](/training-modules/scalable-infrastructure) diff --git a/pages/training-modules/uw-gpu-fpga.md b/pages/training-modules/uw-gpu.md similarity index 100% rename from pages/training-modules/uw-gpu-fpga.md rename to pages/training-modules/uw-gpu.md diff --git a/pages/training-modules/uw-gpu-fpga/syllabus.md b/pages/training-modules/uw-gpu/syllabus.md similarity index 100% rename from pages/training-modules/uw-gpu-fpga/syllabus.md rename to pages/training-modules/uw-gpu/syllabus.md From fa85fb2c3a9ccd3aa6283fb9ab89ac0a83800632 Mon Sep 17 00:00:00 2001 From: Sridhara Dasu Date: Mon, 23 Dec 2024 08:35:25 -0600 Subject: [PATCH 4/5] Removed FPGA modules --- pages/training-modules/uw-gpu.md | 60 +++++++++-------------- pages/training-modules/uw-gpu/syllabus.md | 54 +++----------------- 2 files changed, 29 insertions(+), 85 deletions(-) diff --git a/pages/training-modules/uw-gpu.md b/pages/training-modules/uw-gpu.md index 8a29db6..1ef6de3 100644 --- a/pages/training-modules/uw-gpu.md +++ b/pages/training-modules/uw-gpu.md @@ -1,44 +1,28 @@ --- -permalink: /training-modules/uw-gpu-fpga.html +permalink: /training-modules/uw-gpu.html layout: default -title: GPU FPGA training +title: GPU training --- -# GPU and FPGA training module +# GPU training module

-This training module aims to introduce the students to the concept of hardware accelerators and programming of heterogeneous systems. The training is split in two parts, one dedicated to GPU programming and the second dedicated to introduction to FPGAs and Xilinx Vivado High Level Synthesis (HLS) tool to develop firmware for FPGA. -The duration of this training is 1 semester (14 weeks). The detailed syllabus and series of lectures (as taught during Fall 2022) can be found below. +This training module aims to introduce the students to the concept of hardware accelerators and programming of heterogeneous systems. This training is dedicated to the usage of GPUs by programming in CUDA, and ALPAKA. +The duration of this training is 1 semester (14 weeks). The detailed syllabus and series of lectures can be found below.

-- [Course syllabus (2022)]({{ site.baseurl }}/training-modules/uw-gpu-fpga/syllabus) -- Series of lectures for GPU part: - - [Lecture 1]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_trainingModule_Week1_Lecture1.pdf) Introduction to hardware accelerators - - [Lecture 2]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_trainingModule_Week1_Lecture2.pdf) The GPU and its applications in HEP - - [Lecture 3]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_trainingModule_Week2_Lecture3.pdf) Introduction to C++ : Core syntax, variables operators, flow control instructions and functions. - - [Lecture 4]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_trainingModule_Week2_Lecture4.pdf) Introduction to C++ : Scopes and namespaces, compound data types and Object Orientation - - [Lecture 5]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_trainingModule_Week3_Lecture5.pdf) Introduction to CUDA : Nvidia GPU architecture and CUDA core syntax - - [Lecture 6]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_trainingModule_Week3_Lecture6.pdf) Introduction to CUDA : Memory managments, synchonization and error handling - - [Lecture 7]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_trainingModule_Week4_Lecture7.pdf) Introduction to CUDA : Coalesced memory access and performance considerations - - [Lecture 8]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_trainingModule_Week4_Lecture8.pdf) Introduction to CUDA : Shared memory, atomic operations and the default CUDA stream - - [Lecture 9]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/CUDA_STREAMS_2023.pdf) CUDA advanced topics : CUDA streams - - [Lecture 10]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023_Stdpar_Cpp.pdf) CUDA advanced topics : C++ standards - - [Lecture 11]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/Profiling_with_Intel_OneAPI-1.pdf) Profiling software with Intel OneAPI Toolset Profilers: Vtune and Advisor - - [Lecture 12]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/intro_CUDA_profiling-2.pdf) Introduction to Nvidia profiling tools : Nsight system and Nsight compute - - [Lecture 13]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/20230301-TACHEPManagedMemory.pdf) CUDA advanced topics : Managed memory - - [Lecture 14]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_An_introduction_to_alpaka_Part_1.pdf) Introduction to Alpaka : Performance portability, Alpaka platforms, devices, queues and events - - [Lecture 15]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/TAC-HEP_An_introduction_to_alpaka_Part_2.pdf) Introduction to Alpaka : Memory managment, device functions and kernels, work division - -- Series of lectures for FGPA/HLS part: - - [Lecture 1]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-21-FPGA-HLS-Lecture-1.pdf) Introduction to FPGA and its architecture - - [Lecture 2]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-22-FPGA-HLS-Lecture-2.pdf) FPGA: Parallelism in program execution - - [Lecture 3]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-28-FPGA-HLS-Lecture-3.pdf) FPGA: Clock Frequency, Latency, Pipelining - - [Lecture 4]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-29-FPGA-HLS-Lecture-4.pdf) Introduction to Vivado HLS, Setup - - [Lecture 5]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-04-FPGA-HLS-Lecture-5.pdf) Hands-on with vivado_hls, output review - - [Lecture 6]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-05-FPGA-HLS-Lecture-6.pdf) Hands-on with vivado_hls, Introduction to Pragmas - - [Lecture 7]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-11-FPGA-HLS-Lecture-7.pdf) Vivado HLS: Pragmas & more examples - - [Lecture 8]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-12-FPGA-HLS-Lecture-8.pdf) Vivado HLS: Pragma’s effect on performance - - [Lecture 9]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-18-FPGA-HLS-Lecture-9.pdf) Vivado HLS: More pragmas and Do’s & Don’ts - - [Lecture 10]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-19-FPGA-HLS-Lecture-10.pdf) Vivado HLS: More pragmas and HLS coding styles - - [Lecture 11]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-25-FPGA-HLS-Lecture-11.pdf) LHC, CMS Level-1 Trigger, Project - - [Lecture 12]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-26-FPGA-HLS-Lecture-12.pdf) Project: Re-designing RCT - - [Lecture 13]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-05-02-FPGA-HLS-Lecture-13.pdf) Introduction to VHDL - - [Lecture 14]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-05-03-FPGA-HLS-Lecture-14.pdf) Introduction to VHDL contd. +- [Course syllabus]({{ site.baseurl }}/training-modules/uw-gpu/syllabus) +- Series of lectures : + - [Lecture 1]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week1_Lecture1.pdf) Introduction to hardware accelerators + - [Lecture 2]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week1_Lecture2.pdf) The GPU and its applications in HEP + - [Lecture 3]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week2_Lecture3.pdf) Introduction to C++ : Core syntax, variables operators, flow control instructions and functions. + - [Lecture 4]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week2_Lecture4.pdf) Introduction to C++ : Scopes and namespaces, compound data types and Object Orientation + - [Lecture 5]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week3_Lecture5.pdf) Introduction to CUDA : Nvidia GPU architecture and CUDA core syntax + - [Lecture 6]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week3_Lecture6.pdf) Introduction to CUDA : Memory managments, synchonization and error handling + - [Lecture 7]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week4_Lecture7.pdf) Introduction to CUDA : Coalesced memory access and performance considerations + - [Lecture 8]({{ site.baseurl }}/assets/pdf/uw-gpu/TAC-HEP_trainingModule_Week4_Lecture8.pdf) Introduction to CUDA : Shared memory, atomic operations and the default CUDA stream + - [Lecture 9]({{ site.baseurl }}/404.html) CUDA advanced topics : CUDA streams + - [Lecture 10]({{ site.baseurl }}/404.html) CUDA advanced topics : C++ standards + - [Lecture 11]({{ site.baseurl }}/404.html) Profiling software with Intel OneAPI Toolset Profilers: Vtune and Advisor + - [Lecture 12]({{ site.baseurl }}/404.html) Introduction to Nvidia profiling tools : Nsight system and Nsight compute + - [Lecture 13]({{ site.baseurl }}/404.html) CUDA advanced topics : Managed memory + - [Lecture 14]({{ site.baseurl }}/404.html) Introduction to Alpaka : Performance portability, Alpaka platforms, devices, queues and events + - [Lecture 15]({{ site.baseurl }}/404.html) Introduction to Alpaka : Memory managment, device functions and kernels, work division diff --git a/pages/training-modules/uw-gpu/syllabus.md b/pages/training-modules/uw-gpu/syllabus.md index 2d8d9df..2df3cf6 100644 --- a/pages/training-modules/uw-gpu/syllabus.md +++ b/pages/training-modules/uw-gpu/syllabus.md @@ -1,18 +1,18 @@ --- -permalink: /training-modules/uw-gpu-fpga/syllabus.html +permalink: /training-modules/uw-gpu/syllabus.html layout: default title: Course syllabus ---

INSTITUTION NAME: University of Wisconsin–Madison

-

COURSE SUBJECT, NUMBER AND TITLE: TAC-HEP : GPU & FPGA training module 

+

COURSE SUBJECT, NUMBER AND TITLE: TAC-HEP : GPU training module 

CREDITS: 3 credits equivalent

COURSE DESCRIPTION:

-

Introduction to GPU and FPGA programming. Re-cap on the basics of C++, introduction to the CUDA programming model. Overview of FPGA, design flow, introduction High-Level synthesis and its applications

+

Introduction to GPU programming. Re-cap on the basics of C++, introduction to the CUDA and ALPAKA programming models.

REQUISITES:

  • Familiarity navigating through UNIX based OS. Familiarity with CLI. Elementary knowledge of C or C++.
    • -
  • Students need to set-up a Wisconsin computing account and have login access to one of the UW GPU nodes and cmstrigger01 machine with Xilinx Vivado tools. Students will be provided instructions for doing so prior to the start of the training.
    • +
  • Students need to set-up a Wisconsin computing account and have login access to one of the UW GPU nodes. Students will be provided instructions for doing so prior to the start of the training.

MEETING TIME AND LOCATION:

Zoom coordinates: 

@@ -24,7 +24,6 @@ title: Course syllabus

Wednesdays 11:00 – 12:00 PM (CT), 12:00 – 13:00 (EST), 18:00 – 19:00 (CERN) 

via zoom

Note: Subject to change in weeks 5-7 since some lectures will be given by guest lecturers who are experts in the field and may have time conflicts  

-

FPGA Module

Lectures: Tuesdays and Wednesday: 9:00 – 10:00 AM (CT), 10:00 – 11:00 AM (EST), 16:00 – 17:00 PM (CERN) via zoom

INSTRUCTIONAL MODALITY:

Virtual via zoom. There will be a combination of lectures and hands-on training.

@@ -40,18 +39,14 @@ title: Course syllabus

GPU module

Dr. Charis Kleio Koraka

charis.kleio.koraka@cern.ch

-

FPGA module

-

Dr. Varun Sharma

-

varun.sharma@cern.ch

COURSE LEARNING OUTCOMES:

-

Develop an understanding of the differences between different hardware (CPUs / GPUs / FPGAs). Get familiar with their use cases in HEP and develop the ability to identify the ideal hardware accelerator for different HEP applications. Become familiar with the CUDA programming model. Learn how to use and interpret the output of profiling tools. The second part or module will give an introduction to FPGAs and HLS and how to write algorithms for hardware.

+

Develop an understanding of the differences between different hardware (CPUs / GPUs). Get familiar with their use cases in HEP and develop the ability to identify the ideal hardware accelerator for different HEP applications. Become familiar with the CUDA and ALPAKA programming models. Learn how to use and interpret the output of profiling tools.

COURSE OVERVIEW:

REQUIRED TEXTBOOK, SOFTWARE AND OTHER COURSE MATERIALS:

  • No required textbook
    • -
  • All softwares will be installed in the available machines
    • +
  • All software will be installed on the available machines
-

HLS manual for reference:        https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/ug998-vivado-intro-fpga-design-hls.pdf

HOMEWORK AND OTHER ASSIGNMENTS:

GPU Module

Weekly assignments for the following weeks

@@ -59,9 +54,6 @@ title: Course syllabus

Week 3 : CUDA assignment

Week 4 : CUDA assignment

Weeks 5-7 : Project

-

FPGA Module

-

Week 2-4: Weekly assignments 

-

Week 5-7: Project

GRADING:

@@ -69,22 +61,18 @@ title: Course syllabus - - - -
  GPU moduleFPGA module
Weekly assignments  30%20%
Final project 20%30%
Overall  50 %50 %
@@ -96,7 +84,6 @@ title: Course syllabus
  • Each weekly assignment is due Friday of the next week (i.e. Week 2 assignment is due end of Week 3 on February the 10th)
  • Final project is due end (by Sunday) of week 7, Friday March 10th.
    • -

    FPGA Module

    • Each weekly assignment is due Friday of the next week 
    • Final project is due end (by Sunday) of week 7, Friday April 30th.
      • @@ -109,7 +96,7 @@ title: Course syllabus
    • Description of the CPU 
    • Hardware accelerators : types and applications
    • Description of the GPU 
      • -
    • GPU vs CPU / GPUs vs FPGAs
      • +
    • GPU vs CPU
    • Heterogeneous computing
    • Computing challenge in HEP
    • GPU applications in HEP
      • @@ -163,33 +150,6 @@ title: Course syllabus
    • Concurrency using non-default CUDA streams 
    -

    FPGA Module

    -

    Week 1

    -
      -
    • FPGA – Introduction, why do we need them? different options available in market;
      • -
    • Overview of FPGA architecture, programming model and FPGA parallelism vs processor architectures
      • -
    -

    Week 2

    -
      -
    • Digital systems: some important components used on the FPGAs like registers (flip-flops), DSPs, LUTs;
      • -
    • Basic concepts of Hardware design: Clock Frequency, Latency and Pipelining, Throughput
      • -
    - -

    Week 3-4

    -
      -
    • Vivado High-level Synthesis (HLS): Basic overview, understanding of HLS, its purpose, benefit and usage;
      • -
    • Mathematical Operations, Conditional statements, Loops, functions in HLS
      • -
    • HLS: Linear Algebra library functions, DSP library functions, C++ arbitrary precision types, datatypes for efficient hardware, Design analysis and optimisation and RTL verification;
      • -
    • Case study of trigger algorithms developed for the LHC experiments
      • -
    • Introduction to CMS experiment and Level-1 Trigger system
      • -
    • Basic introduction to VHDL and design flow
      • -
    • Quick introduction and guide to HLS4ML
      • -
    - -

    Week 5-6-7

    -
      -
    • Project: Write an algorithm in C/C++; use HLS to make a bit file which can be burned in hardware.
      • -

    Additional Read (if time permit) :

    -   Computation-centric Algorithms

    -   Control centric algorithms

    From 5c8e7cc2a9532818e6fc6066e4a6321af97c1d47 Mon Sep 17 00:00:00 2001 From: Sridhara Dasu Date: Mon, 23 Dec 2024 08:54:37 -0600 Subject: [PATCH 5/5] Updated FPGA part --- pages/training-modules.md | 2 +- pages/training-modules/uw-fpga.md | 27 ++++++ pages/training-modules/uw-fpga/syllabus.md | 100 +++++++++++++++++++++ 3 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 pages/training-modules/uw-fpga.md create mode 100644 pages/training-modules/uw-fpga/syllabus.md diff --git a/pages/training-modules.md b/pages/training-modules.md index f54af52..42154c4 100644 --- a/pages/training-modules.md +++ b/pages/training-modules.md @@ -11,7 +11,7 @@ title: Training Modules #### List of trainings * [Software Engineering for Scientific Computing](/training-modules/software-engineering) -* [GPU FPGA training module](/training-modules/uw-gpu) +* [GPU training module](/training-modules/uw-gpu) * [FPGA training module](/training-modules/uw-fpga) * [Data Analysis Systems and Facilities](/training-modules/analysis-systems-and-facilities) * [Scalable Infrastructure](/training-modules/scalable-infrastructure) diff --git a/pages/training-modules/uw-fpga.md b/pages/training-modules/uw-fpga.md new file mode 100644 index 0000000..25fb035 --- /dev/null +++ b/pages/training-modules/uw-fpga.md @@ -0,0 +1,27 @@ +--- +permalink: /training-modules/uw-fpga.html +layout: default +title: FPGA training +--- + +# FPGA training module +

    +This training module aims to introduce the students to the concept of FPGAs, programming them using a higher level language (C++) and synthesizing firmware. We use Xilinx platform. +The duration of this training is 1 semester (14 weeks). The detailed syllabus and series of lectures can be found below. +

    +- [Course syllabus]({{ site.baseurl }}/training-modules/uw-fpga/syllabus) +- Series of lectures : + - [Lecture 1]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-21-FPGA-HLS-Lecture-1.pdf) Introduction to FPGA and its architecture + - [Lecture 2]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-22-FPGA-HLS-Lecture-2.pdf) FPGA: Parallelism in program execution + - [Lecture 3]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-28-FPGA-HLS-Lecture-3.pdf) FPGA: Clock Frequency, Latency, Pipelining + - [Lecture 4]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-03-29-FPGA-HLS-Lecture-4.pdf) Introduction to Vivado HLS, Setup + - [Lecture 5]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-04-FPGA-HLS-Lecture-5.pdf) Hands-on with vivado_hls, output review + - [Lecture 6]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-05-FPGA-HLS-Lecture-6.pdf) Hands-on with vivado_hls, Introduction to Pragmas + - [Lecture 7]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-11-FPGA-HLS-Lecture-7.pdf) Vivado HLS: Pragmas & more examples + - [Lecture 8]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-12-FPGA-HLS-Lecture-8.pdf) Vivado HLS: Pragma’s effect on performance + - [Lecture 9]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-18-FPGA-HLS-Lecture-9.pdf) Vivado HLS: More pragmas and Do’s & Don’ts + - [Lecture 10]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-19-FPGA-HLS-Lecture-10.pdf) Vivado HLS: More pragmas and HLS coding styles + - [Lecture 11]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-25-FPGA-HLS-Lecture-11.pdf) LHC, CMS Level-1 Trigger, Project + - [Lecture 12]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-04-26-FPGA-HLS-Lecture-12.pdf) Project: Re-designing RCT + - [Lecture 13]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-05-02-FPGA-HLS-Lecture-13.pdf) Introduction to VHDL + - [Lecture 14]({{ site.baseurl }}/assets/pdf/uw-gpu-fpga/2023-05-03-FPGA-HLS-Lecture-14.pdf) Introduction to VHDL contd. diff --git a/pages/training-modules/uw-fpga/syllabus.md b/pages/training-modules/uw-fpga/syllabus.md new file mode 100644 index 0000000..55fd628 --- /dev/null +++ b/pages/training-modules/uw-fpga/syllabus.md @@ -0,0 +1,100 @@ +--- +permalink: /training-modules/uw-fpga/syllabus.html +layout: default +title: Course syllabus +--- + +

    INSTITUTION NAME: University of Wisconsin–Madison

    +

    COURSE SUBJECT, NUMBER AND TITLE: TAC-HEP : FPGA training module 

    +

    CREDITS: 3 credits equivalent

    +

    COURSE DESCRIPTION:

    +

    Introduction to FPGA programming. Overview of FPGA, design flow, introduction High-Level synthesis and its applications

    +

    REQUISITES:

    +
      +
    • Familiarity navigating through UNIX based OS. Familiarity with CLI. Elementary knowledge of C or C++.
      • +
    • Students need to set-up a Wisconsin computing account and have login access to cmstrigger01 machine with Xilinx Vivado tools. Students will be provided instructions for doing so prior to the start of the training.
      • +
    +

    MEETING TIME AND LOCATION:

    +

    Zoom coordinates: 

    +

    https://cern.zoom.us/j/69712006717?pwd=c0pqUGZxbUlFNkVRSWxHc24yL21tdz09

    +

    Meeting ID: 697 1200 6717

    + +

    FPGA Module

    +

    Lectures: Tuesdays and Wednesday: 9:00 – 10:00 AM (CT), 10:00 – 11:00 AM (EST), 16:00 – 17:00 PM (CERN) via zoom

    +

    INSTRUCTIONAL MODALITY:

    +

    Virtual via zoom. There will be a combination of lectures and hands-on training.

    +

    OFFICE HOURS:

    + +

    INSTRUCTOR CONTACT INFO:

    +

    Dr. Varun Sharma

    +

    varun.sharma@cern.ch

    +

    COURSE LEARNING OUTCOMES:

    +

    Develop an understanding of the differences between different hardware (CPUs / GPUs / FPGAs). Get familiar with their use cases in HEP and develop the ability to identify the ideal hardware accelerator for different HEP applications. Understand the role and capabilities of FPGAs and High Level Synthesis, and learn to write algorithms for hardware.

    +

    COURSE OVERVIEW:

    +

    REQUIRED TEXTBOOK, SOFTWARE AND OTHER COURSE MATERIALS:

    +
      +
    • No required textbook
      • +
    • All softwares will be installed in the available machines
      • +
    +

    HLS manual for reference:        https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/ug998-vivado-intro-fpga-design-hls.pdf

    +

    HOMEWORK AND OTHER ASSIGNMENTS:

    +

    Week 1-7: Weekly assignments 

    +

    Week 8-14: Project

    +

    GRADING:

    +
    + + + + + + + + + + + +
    Weekly assignments 50%
    Final project50%
    +
    +

    COURSE SCHEDULE/CALENDAR

    +

    Deadlines:

    +
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    • Each weekly assignment is due Friday of the next week 
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    • Final project is due end (by Sunday) of week 14, Friday April 30th.
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    TOPICS COVERED

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    Week 1

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    • FPGA – Introduction, why do we need them? different options available in market;
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    • Overview of FPGA architecture, programming model and FPGA parallelism vs processor architectures
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    Week 2

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    • Digital systems: some important components used on the FPGAs like registers (flip-flops), DSPs, LUTs;
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    • Basic concepts of Hardware design: Clock Frequency, Latency and Pipelining, Throughput
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    Week 3-4

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    • Vivado High-level Synthesis (HLS): Basic overview, understanding of HLS, its purpose, benefit and usage;
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    • Mathematical Operations, Conditional statements, Loops, functions in HLS
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    • HLS: Linear Algebra library functions, DSP library functions, C++ arbitrary precision types, datatypes for efficient hardware, Design analysis and optimisation and RTL verification;
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    • Case study of trigger algorithms developed for the LHC experiments
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    • Introduction to CMS experiment and Level-1 Trigger system
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    • Basic introduction to VHDL and design flow
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    • Quick introduction and guide to HLS4ML
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    Week 5-6-7

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    • Project: Write an algorithm in C/C++; use HLS to make a bit file which can be burned in hardware.
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    Additional Read (if time permit) :

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    -   Computation-centric Algorithms

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    -   Control centric algorithms

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    -   Integration of multiple programs