jit: Improve MMU efficiency in system simulation

[vacantron]

In the current flow of the JIT compilation, the simulation will be reverted back to the interpreter mode to deal with the translation of the virtual address to the physical address when reaching the memory operation (lw/sw) in the system simulation. This is going to have a significant impact to the performance due to the mode switching.

The one of the possible solutions is to implement the translation lookaside buffer (TLB). However, the situation mentioned above will still happen if the cache misses.