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test
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@ChinYikMing
ChinYikMing committed Oct 26, 2024
1 parent 25c3298 commit aeda753
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Showing 3 changed files with 52 additions and 49 deletions.
38 changes: 21 additions & 17 deletions src/emulate.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -176,8 +176,8 @@ RV_TRAP_LIST
rv->compressed = compress; \
rv->csr_cycle = cycle; \
rv->PC = PC; \
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, type##_MISALIGNED, \
IIF(IO)(addr, mask_or_pc)); \
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, type##_MISALIGNED, \
IIF(IO)(addr, mask_or_pc)); \
return false; \
}

Expand Down Expand Up @@ -667,7 +667,7 @@ static void block_translate(riscv_t *rv, block_t *block)
/* decode the instruction */
if (!rv_decode(ir, insn)) {
rv->compressed = is_compressed(insn);
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, INSN_MISALIGNED, insn);
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, INSN_MISALIGNED, insn);
break;
}
ir->impl = dispatch_table[ir->opcode];
Expand Down Expand Up @@ -1138,41 +1138,45 @@ static void __trap_handler(riscv_t *rv)

static void _trap_handler(riscv_t *rv)
{
uint32_t scause = rv->csr_scause;
uint32_t stval = rv->csr_stval;
uint32_t cause =
rv->priv_mode == RV_PRIV_S_MODE ? rv->csr_scause : rv->csr_mcause;
uint32_t tval =
rv->priv_mode == RV_PRIV_S_MODE ? rv->csr_stval : rv->csr_mtval;

switch (scause) {
switch (cause) {
#if !RV32_HAS(EXT_C)
case INSN_MISALIGNED:
rv_trap_insn_misaligned(rv, stval);
rv_trap_insn_misaligned(rv, tval);
break;
#endif /* EXT_C */
case ILLEGAL_INSN:
rv_trap_illegal_insn(rv, stval);
rv_trap_illegal_insn(rv, tval);
break;
case BREAKPOINT:
rv_trap_breakpoint(rv, stval);
rv_trap_breakpoint(rv, tval);
break;
case LOAD_MISALIGNED:
rv_trap_load_misaligned(rv, stval);
rv_trap_load_misaligned(rv, tval);
break;
case STORE_MISALIGNED:
rv_trap_store_misaligned(rv, stval);
rv_trap_store_misaligned(rv, tval);
break;
#if RV32_HAS(SYSTEM)
case PAGEFAULT_INSN:
rv_trap_pagefault_insn(rv, stval);
rv_trap_pagefault_insn(rv, tval);
break;
case PAGEFAULT_LOAD:
rv_trap_pagefault_load(rv, stval);
rv_trap_pagefault_load(rv, tval);
break;
case PAGEFAULT_STORE:
rv_trap_pagefault_store(rv, stval);
rv_trap_pagefault_store(rv, tval);
break;
#endif /* SYSTEM */
#if !RV32_HAS(SYSTEM)
case ECALL_M:
rv_trap_ecall_M(rv, stval);
rv_trap_ecall_M(rv, tval);
break;
#endif /* SYSTEM */
default:
__UNREACHABLE;
break;
Expand All @@ -1188,7 +1192,7 @@ void trap_handler(riscv_t *rv)
void ebreak_handler(riscv_t *rv)
{
assert(rv);
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, BREAKPOINT, rv->PC);
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, BREAKPOINT, rv->PC);
}

void ecall_handler(riscv_t *rv)
Expand All @@ -1198,7 +1202,7 @@ void ecall_handler(riscv_t *rv)
syscall_handler(rv);
rv->PC += 4;
#else
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, ECALL_M, 0);
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, ECALL_M, 0);
syscall_handler(rv);
#endif
}
Expand Down
53 changes: 26 additions & 27 deletions src/riscv.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -84,33 +84,6 @@ enum {
};
/* clang-format on */

enum TRAP_CODE {
INSN_MISALIGNED = 0,
ILLEGAL_INSN = 2,
BREAKPOINT = 3,
LOAD_MISALIGNED = 4,
STORE_MISALIGNED = 6,
PAGEFAULT_INSN = 12,
PAGEFAULT_LOAD = 13,
PAGEFAULT_STORE = 15,
ECALL_M = 11,
};

#define SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval) \
{ \
/* \
* To align rv32emu behavior with Spike \
* \
* If not in system mode, the __trap_handler \
* should be be invoked \
*/ \
IIF(RV32_HAS(SYSTEM))(rv->is_trapped = true, ); \
rv->csr_scause = scause; \
rv->csr_stval = stval; \
rv->io.on_trap(rv); \
}


#define MISA_SUPER (1 << ('S' - 'A'))
#define MISA_USER (1 << ('U' - 'A'))
#define MISA_I (1 << ('I' - 'A'))
Expand Down Expand Up @@ -285,6 +258,32 @@ enum TRAP_CODE {
#define RV_PRIV_M_MODE 3
#define RV_PRIV_IS_U_OR_S_MODE() (rv->priv_mode <= RV_PRIV_S_MODE)

enum TRAP_CODE {
INSN_MISALIGNED = 0,
ILLEGAL_INSN = 2,
BREAKPOINT = 3,
LOAD_MISALIGNED = 4,
STORE_MISALIGNED = 6,
PAGEFAULT_INSN = 12,
PAGEFAULT_LOAD = 13,
PAGEFAULT_STORE = 15,
ECALL_M = 11,
};

/* clang-format off */
#define SET_CAUSE_AND_TVAL_THEN_TRAP(rv, cause, tval) \
{ \
/* \
* To align rv32emu behavior with Spike \
* \
* If not in system mode, the __trap_handler \
* should be be invoked \
*/ \
IIF(RV32_HAS(SYSTEM))(rv->is_trapped = true;, ); \
rv->io.on_trap(rv); \
}
/* clang-format on */

/*
* SBI functions must return a pair of values:
*
Expand Down
10 changes: 5 additions & 5 deletions src/system.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -103,11 +103,11 @@ static uint32_t *mmu_walk(riscv_t *rv, const uint32_t addr, uint32_t *level)
break; \
} \
if (pte && (!(*pte & PTE_V))) { \
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
return false; \
} \
if (!(pte && (*pte & access_bits))) { \
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
return false; \
} \
/* \
Expand All @@ -122,7 +122,7 @@ static uint32_t *mmu_walk(riscv_t *rv, const uint32_t addr, uint32_t *level)
((SSTATUS_MXR & rv->csr_sstatus) && \
!((*pte & PTE_R) | (*pte & PTE_X)) && \
(access_bits == PTE_R)))) { \
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
return false; \
} \
/* \
Expand All @@ -131,12 +131,12 @@ static uint32_t *mmu_walk(riscv_t *rv, const uint32_t addr, uint32_t *level)
*/ \
if (pte && rv->priv_mode == RV_PRIV_S_MODE && \
!(SSTATUS_SUM & rv->csr_sstatus) && (*pte & PTE_U)) { \
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
return false; \
} \
/* PTE not found, map it in handler */ \
if (!pte) { \
SET_SCAUSE_AND_STVAL_THEN_TRAP(rv, scause, stval); \
SET_CAUSE_AND_TVAL_THEN_TRAP(rv, scause, stval); \
return false; \
} \
/* valid PTE */ \
Expand Down

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