soc-ice40-dmc-1-risc_v.si

// _____________________________________________________________________________
// |                                                                           |
// | DMC-1 TinyGPU, demo SOC with a RISC-V processor (ice-v dual)              |
// |                                                                           |
// | @sylefeb 2020-12-02                                                       |
// |___________________________________________________________________________|
// |                                                                           |
// |  License: CERN-OHL-S                                                      |
// |     A copy of the license full text is included in                        |
// |     the distribution, please refer to it for details.                     |
// |___________________________________________________________________________|

$$SIMUL_QPSRAM=nil

$$if MCH2022 or (SIMULATION and SIMUL_QPSRAM) then
  // overclocking at 66 MHz seems to be fine
  $$master_freq = 66
  $$uart_in_clock_freq_mhz = master_freq//2
  $include('../../common/qpsram2x.si')
  import('../../common/ice40_half_clock.v')
$$else
  // overclocking at 60 MHz seems to be fine (rarely fails to run)
  $$master_freq = 50
  $$uart_in_clock_freq_mhz = master_freq//2
  $include('../../common/spiflash2x.si')
  import('../../common/ice40_half_clock.v')
$$end

$include('../../common/uart.si')

// A small BRAM contains the bootloader (firmware/boot.c)
$$bram_depth         = 9
// Configure SPI screen (if used)
$$ST7789             = 1
// Use all 128KB of SPRAM
$$SPRAM_128K         = 1

$$if ICE40 then
import('../../common/icebrkr_$master_freq$_lock.v')
import('../../common/ice40_spram.v')
$$end

$$if SIMULATION then
$include('../../common/simulation_spram.si')
$$end

$include('../../GPUs/dmc-1/dmc-1.si')
$include('../../GPUs/dmc-1/command_queue.si')
$$if MCH2022 then
$include('../../GPUs/dmc-1/parallel_screen.si')
$$else
$include('../../GPUs/dmc-1/spi_screen.si')
$$end

// configuration for the ice-v-dual
$$ICEV_MULDIV        = 1
$$ICEV_FAST_SHIFT    = 1
$$ICEV_USERDATA      = 1
$$ICEV_ALU_LATCH     = 1
$$ICEV_STALL         = 1
$$Boot               = (1<<17)>>2  -- boot from BRAM, see bram_spram_32bits.si
$$addrW              = 17
//_                    ^^ 2^17 (128K) + 1 bit for BRAM + 1 bit for mapping
//_                    divided by 4 as we address 32 bits words
group bram_port_io {
  uint$addrW$ addr(0),
  uint4       wenable(0),
  uint32      rdata(0),
  uint32      wdata(0),
}

// pre-compilation script, embeds code within string for BRAM and outputs sdcard image
$$sdcard_image_pad_size = 0
$$dofile('../../../software/compile/ice40/pre_include_asm.lua')
$$code_size_bytes = init_data_bytes

$include('../../common/ice-v-dual.si')
$$clean_reset_width = 4
$include('../../common/clean_reset.si')
$include('bram_spram_32bits.si')

// --------------------------------------------------
// PLL for simulation
// --------------------------------------------------

$$if SIMULATION then
algorithm pll(
  output! uint1 clock4x,
  output  uint1 clock2x,
  output  uint1 clock1x,
) <autorun> {
  uint2 counter(0);
  always {
    clock4x =  clock;
    clock2x =  counter[0,1]; // x2 slower
    clock1x = ~counter[1,1]; // x4 slower
    counter =  counter + 1;
  }
}
$$end

// --------------------------------------------------
// A helper unit that converts the data available 2x pulse
// into a high signal (allows to cross 2x => 1x since once
// data starts coming, it comes at every 1x cycle
// --------------------------------------------------

unit adapterDataAvailable(
  input     uint1 valid,
  input     uint1 data_avail_pulse,
  output(!) uint1 data_avail_high)
{
  always {
    data_avail_high = ~valid ? 0 : (data_avail_high | data_avail_pulse);
  }
}

// --------------------------------------------------
// Design main
// --------------------------------------------------

unit main(
  output uint$NUM_LEDS$ leds,
$$if BUTTONS then
  input  uint$NUM_BTNS$ btns,
$$end
$$if UART then
  output uint1 uart_tx,
  input  uint1 uart_rx,
$$end
$$if QSPIFLASH then
  output  uint1 sf_clk,
  output  uint1 sf_csn,
  inout   uint1 sf_io0,
  inout   uint1 sf_io1,
  inout   uint1 sf_io2,
  inout   uint1 sf_io3,
$$end
$$if PSRAM then
  output  uint1 ram_clk,
  output  uint1 ram_csn,
  inout   uint1 ram_io0,
  inout   uint1 ram_io1,
  inout   uint1 ram_io2,
  inout   uint1 ram_io3,
$$end
$$if OLED then
  output  uint1 oled_clk,
  output  uint1 oled_mosi,
  output  uint1 oled_dc,
  output  uint1 oled_resn,
  output  uint1 oled_csn,
$$if VERILATOR then
  output uint2  spiscreen_driver(2/*ST7789*/),
  output uint10 spiscreen_width (320),
  output uint10 spiscreen_height(240),
$$end
$$end
$$if LCD then
  output uint8 lcd_d,
  output uint1 lcd_rs,
  output uint1 lcd_wr_n,
  output uint1 lcd_cs_n(0),
  output uint1 lcd_rst_n(1),
  input  uint1 lcd_mode,
  input  uint1 lcd_fmark,
$$end
)
$$if ICE40 then
<@clock1x,!rst2x> {

  uint1 clock2x = uninitialized;
  uint1 rst2x   = uninitialized;
  pll pllgen(
    clock_in  <: clock,
    clock_out :> clock2x,
    reset     :> rst2x
  );
  uint1 rst1x <: rst2x;
  uint1 clock1x = uninitialized;
  ice40_half_clock _(
    clock_in  <: clock2x,
    clock_out :> clock1x
  );

$$elseif SIMULATION then
<@clock1x> {
  uint1 clock1x = uninitialized;
  uint1 clock2x = uninitialized;
  uint1 clock4x = uninitialized;
  pll clkgen<@clock,!reset>(
    clock1x :> clock1x,
    clock2x :> clock2x,
    clock4x :> clock4x
  );
  uint1 rst1x <: reset;
  uint1 rst2x <: reset;
$$else
{
$$end

  // ==============================
  // RAM for CPU (SPRAM)
  bram_port_io mem_io_ram;
  bram_spram_32bits bram_ram(
    pram               <:> mem_io_ram
  );

  // ==============================
  // CPU
  uint32 user_data(0);
  bram_port_io mem_io_cpu;
  rv32i_cpu cpu(
    user_data        <:: user_data,
    mem              <:> mem_io_cpu,
  );

  // ==============================
  // GPU
  texmem_io     txm_io;
  DMC_1_gpu gpu(txm          <:>  txm_io,
                screen_ready <:   screen_ctrl.ready);

  // ==============================
  // screen display
  uint1 screen_valid(0);    uint1 screen_ready(0);
  uint1 screen_send_dc(0);  uint8 screen_send_byte(0);
  screen_controller screen_ctrl(
    screen_valid :> screen_valid,
    screen_ready <: screen_ready,
    send_dc      :> screen_send_dc,
    send_byte    :> screen_send_byte,
  );
  // ...

$$if MCH2022 then
  screen_driver screen(
    ready            :> screen_ready,
    screen_d         :> lcd_d,
    screen_dc        :> lcd_rs,
    screen_wrn       :> lcd_wr_n
  );
$$else -- not MCH2022
  uint1 o_mosi(0);
  uint1 o_clk(0);
  uint1 o_dc(0);
  uint1 o_resn(0);
  screen_driver screen<@clock2x,!rst2x,reginputs> (
    ready            :> screen_ready,
$$if VERILATOR then
    screen_mosi      :> oled_mosi,
    screen_clk       :> oled_clk,
    screen_dc        :> oled_dc,
$$else
    screen_mosi      :> o_mosi,
    screen_clk       :> o_clk,
    screen_dc        :> o_dc,
$$end
  );
$$if not SIMULATION then
   sb_io sbio1( clock <: clock2x, out  <: o_clk,  pin  :> oled_clk);
   sb_io sbio0( clock <: clock2x, out  <: o_mosi, pin  :> oled_mosi);
   sb_io sbio2( clock <: clock2x, out  <: o_dc,   pin  :> oled_dc);
   sb_io sbio3( clock <: clock1x, out  <: o_resn, pin  :> oled_resn);
$$end
$$end

  // ==============================
  // texture memory
$$if MCH2022 or (SIMULATION and SIMUL_QPSRAM) then
    qpsram_ram txm<@clock2x,!rst2x,reginputs> (
      ram_clk  :> ram_clk,  ram_csn :>  ram_csn,
      ram_io0 <:> ram_io0,  ram_io1 <:> ram_io1,
      ram_io2 <:> ram_io2,  ram_io3 <:> ram_io3,
    );
$$else -- not MCH2022
    spiflash_rom_core txm<@clock2x,!rst2x,reginputs> (
      sf_clk  :> sf_clk,    sf_csn  :> sf_csn,
      sf_io0 <:> sf_io0,    sf_io1 <:> sf_io1,
      sf_io2 <:> sf_io2,    sf_io3 <:> sf_io3,
    );
$$end
    // adapts the data available pulse across clock domains
    adapterDataAvailable dataAvail<@clock2x>(
      data_avail_pulse <: txm.rdata_available,
      data_avail_high  :> txm_io.data_available
    );

$$if SIMULATION then
  // for simulation, create dummy vars
  uint1 sf_csn(1);  uint1 sf_clk(0);  uint1 sf_io0(0);
  uint1 sf_io1(0);  uint1 sf_io2(0);  uint1 sf_io3(0);
  uint1 ram_csn(1); uint1 ram_clk(0); uint1 ram_io0(0);
  uint1 ram_io1(0); uint1 ram_io2(0); uint1 ram_io3(0);
$$end

  // ==============================
  // bust reads texture memory => RAM
  uint22 txm_burst_read_dst(0);
  uint1  txm_burst_read_active(0);
  uint32 txm_burst_data(0);
  uint5  txm_burst_data_cursor(0);
  uint1  txm_burst_data_available(0);
  uint22 txm_burst_len(0);

  // ==============================
  // UART
  uart_out uo;
  uart_in  ui;
$$if UART then
  uart_sender usend<reginputs>(
    io      <:> uo,
    uart_tx :>  uart_tx
  );
  uart_receiver urecv(
    io      <:> ui,
    uart_rx <:  uart_rx
  );
$$end

$$if SIMULATION then
  uint32 iter(0);
  uint32 last_iter(0);
$$end

  sameas(mem_io_cpu.addr)    prev_mem_addr(0);
  sameas(mem_io_cpu.wenable) prev_mem_wenable(0);
  sameas(mem_io_cpu.wdata)   prev_mem_wdata(0);

  // ==============================
  // command queue
  command_queue cmdq(current :> gpu.command);

  // ==============================
  // main 'loop'

  always {

    user_data[0,24] = {
                      gpu.pickedh,
                      ui.data_out,
$$if BUTTONS then
                      btns[0,3],
$$else
                      3b0,
$$end
                      1b0,
                      1b0,
                      cmdq.empty,
                      txm.busy | txm_burst_read_active,
                      ~cmdq.full
                      };

    // track CPU ram
    mem_io_cpu.rdata   = mem_io_ram.rdata;
    mem_io_ram.wdata   = txm_burst_read_active ? txm_burst_data
                                               : mem_io_cpu.wdata;
    mem_io_ram.wenable = mem_io_cpu.wenable | {4{txm_burst_data_available}};
    mem_io_ram.addr    = txm_burst_read_active ? txm_burst_read_dst
                                               : mem_io_cpu.addr;
    // track texture memory interface
    dataAvail.valid         = txm_io.in_ready | txm_burst_read_active;
    txm.in_ready            = txm_io.in_ready | txm_burst_read_active;
    txm.addr                = txm_burst_read_active ? txm.addr : txm_io.addr;
    txm_io.data             = txm.rdata;
    txm_io.busy             = txm.busy;
$$if MCH2022 then
    txm.wenable             = 0; // we never write to PSRAM
$$end
$$if SIMULATION then
    //if ((|mem_io_ram.wenable) & txm_burst_data_available) {
    //  __display("%d write",iter);
    //}
$$end
    // stall CPU on bursts
    cpu.stall_cpu       = txm_burst_read_active;
    // burst read
    if (txm_burst_read_active) {
      txm_burst_data    = txm_io.data_available ? {txm.rdata,txm_burst_data[8,24]}
                                                : txm_burst_data;
      txm_burst_data_cursor =
                          txm_burst_data_available ? 5b01000 :
                          txm_io.data_available    ? (txm_burst_data_cursor>>1)
                                                   : txm_burst_data_cursor;
      txm_burst_read_dst       = txm_burst_data_available
                               ? txm_burst_read_dst + 1 : txm_burst_read_dst;
      txm_burst_len            = txm_burst_data_available
                               ? txm_burst_len - 1      : txm_burst_len;
      txm_burst_read_active    = txm_burst_len != 0;
      txm_burst_data_available = txm_burst_data_cursor[0,1];
    }
    // GPU commands
    gpu           .valid    = 0;
    cmdq          .in_add   = 0;
    cmdq          .in_next  = 0;
    // screen interface
    screen_ctrl   .valid    = gpu.screen_valid;
    screen_ctrl   .in_data  = gpu.screen_valid
                            ? {1b1,gpu.screen_data} : prev_mem_wdata[0,17];
    screen.valid            = screen_valid;
    screen.data_or_command  = screen_send_dc;
    screen.byte             = screen_send_byte;
    // uart: maintain low, pulse on send
    uo.data_in_ready = 0;

$$if MCH2022 then
    lcd_cs_n  = 0; lcd_rst_n = 1; // maintain chip select and reset for screen
$$end

    // memory mapping
    if ((prev_mem_wenable != 0) & prev_mem_addr[16,1]) {
      switch (prev_mem_addr[2,4]) {
        case 4b0100: { // write a char from CPU (printf)
          // UART
          uo.data_in       = prev_mem_wdata[ 0,8];
          uo.data_in_ready = ~uo.busy;
$$if SIMULATION then
          __write("%c",prev_mem_wdata[ 0,8]);
$$end
        }
        case 4b0010: {
          switch (prev_mem_addr[0,2]) {
            case 2b00: { // LEDs from CPU
              leds = prev_mem_wdata[0,8];
$$if SIMULATION then
              // in simulation we use LEDs to track cycle usage and print
              // the number of cycles elapsed since the CPU last wrote to LEDs
              __display("(cycle %d) LEDs = %d | %d [elapsed %d]",iter,
                prev_mem_wdata[0,32],__signed( prev_mem_wdata),iter-last_iter);
              last_iter = iter;
              if (prev_mem_wdata == 32hffffffff) { __finish(); }
$$end
            }
            case 2b01: { // screen write from CPU
              screen_ctrl.valid = 1;
            }
            case 2b11: { // screen reset from CPU
$$if VERILATOR then
              oled_resn = ~ prev_mem_wdata[0,1];
$$elseif not MCH2022 then
              o_resn    = ~ prev_mem_wdata[0,1];
$$end
            }
            case 2b10: { // texture memory CPU read
              // NOTE1: assumes there cannot be collisions with
              //        the texture sampler ; CPU should not drive
              //        texture memory while draw calls are pending
              // NOTE2: CPU cannot write to RAM while the burst occurs,
              //        and should wait on user_data, txm.busy bit
              // NOTE3: destination addresses have to be 32-bits aligned
              uint1 len_else_dst    = prev_mem_wdata[31,1];
              // ^^^ bit 31 indicates whether we are setting the length (bytes)
              // or the destination address (in ram)
              uint1 src_and_trigger = prev_mem_wdata[30,1];
              // ^^^ bit 31 indicates whether we are setting the source (in tex
              // memory) or the destination address (in ram)
              // Set size, then destination, then source (triggers the burst)
              if (len_else_dst) {
                txm_burst_len       = prev_mem_wdata[2,22];
              } else {
                if (~src_and_trigger) {
                  txm_burst_read_dst  = prev_mem_wdata[2,22];
                }
              }
              txm.addr              = prev_mem_wdata[0,24];
              txm_burst_read_active = src_and_trigger; // start
              txm_burst_data_cursor = 5b10000;
$$if SIMULATION then
              //if (src_and_trigger) {
              //  __display("[cycle %d] BURST start, from @%x to @%x, len %d",iter,txm.addr,txm_burst_read_dst<<2,txm_burst_len);
              //}
$$end
            }
            default: { }
          }
        }
        case 4b0001: { // GPU commands
          if (prev_mem_addr[0,1]) {
            // received first half
            cmdq.in_command[32,32] = prev_mem_wdata[0,32];
          } else {
            // received second half
            cmdq.in_command[ 0,32] = prev_mem_wdata[0,32];
            // store in fifo
            cmdq.in_add = 1;
          }
        }
        case 4b1000: { // GPU commands in part
          switch (prev_mem_addr[6,4]) {
            // tex0 PARAMETER_PLANE_A     (2<<30) | ((ny) & 1023)  | (((uy) & 1023)<<10) | (((vy) & 1023)<<20)
            case 0: { // PARAMETER_PLANE_A_ny
              cmdq.in_command[$32+ 0$,10] = prev_mem_wdata[0,10];
            }
            case 1: { // PARAMETER_PLANE_A_uy
              cmdq.in_command[$32+10$,10] = prev_mem_wdata[0,10];
            }
            case 2: { // PARAMETER_PLANE_A_vy
              cmdq.in_command[$32+20$,10] = prev_mem_wdata[0,10];
              cmdq.in_command[$32+30$, 2] = 2b10;
            }
            // tex1 PARAMETER_PLANE_A_EX  (((du) & 16383)<<1) | (((dv) & 16383)<<15) | PARAMETER
            case 3: { // PARAMETER_PLANE_A_EX_du
              cmdq.in_command[$ 0+ 0$,17] = {prev_mem_wdata[0,16],1b0/*reset eoc*/};
            }
            case 4: { // PARAMETER_PLANE_A_EX_dv
              cmdq.in_command[$ 0+15$,16] = prev_mem_wdata[0,16];
              // store in fifo
              cmdq.in_command[$ 0+30$, 2] = 2b11; // PARAMETER
              cmdq.in_add = 1;
            }
            // tex0 PARAMETER_UV_OFFSET    (1<<30) | ((vo) & 16777215)
            case 5: { // PARAMETER_UV_OFFSET_v
              cmdq.in_command[$32+ 0$,24] = prev_mem_wdata[0,24];
              cmdq.in_command[$32+30$, 2] = 2b01;
            }
            // tex1 PARAMETER_UV_OFFSET_EX (((uo) & 16777215)<<1) | PARAMETER
            // #define LIGHTMAP_EN (1<<25)
            case 6: { // PARAMETER_UV_OFFSET_EX_u
              cmdq.in_command[$ 0+ 1$,24] = prev_mem_wdata[0,24];
            }
            case 7: { // PARAMETER_UV_OFFSET_EX_lmap
              cmdq.in_command[$ 0+25$, 1] = prev_mem_wdata[0,1];
              // store in fifo
              cmdq.in_command[$ 0+30$, 2] = 2b11; // PARAMETER
              cmdq.in_add = 1;
            }
            // tex0 COLDRAW_PLANE_B ((ded) & 65535) | ((dr) << 16)
            case 8: { // COLDRAW_PLANE_B_ded
              cmdq.in_command[$32+ 0$,16] = prev_mem_wdata[0,16];
            }
            case 9: { // COLDRAW_PLANE_B_dr
              cmdq.in_command[$32+16$,16] = prev_mem_wdata[0,16];
            }
            // tex1 COLDRAW_COL ((idx) | ((start&255)<<10) | ((end/*>=0*/)<<18) | ((light)<<26)) | PLANE
            case 10: { // COLDRAW_COL_texid
              cmdq.in_command[$ 0+ 0$,10] = prev_mem_wdata[0,10];
            }
            case 11: { // COLDRAW_COL_start
              cmdq.in_command[$ 0+10$, 8] = prev_mem_wdata[0, 8];
            }
            case 12: { // COLDRAW_COL_end
              cmdq.in_command[$ 0+18$, 8] = prev_mem_wdata[0, 8];
              // store in fifo
              cmdq.in_command[$ 0+30$, 2] = 2b01; // PLANE
              cmdq.in_add = 1;
            }
            case 13: { // COLDRAW_COL_light
              cmdq.in_command[$ 0+26$, 4] = prev_mem_wdata[0, 4];
            }
          }
        }
        default: { }
      }
    }

    // send next command to GPU
    gpu.valid    = gpu.ready & ~cmdq.empty;
    cmdq.in_next = gpu.ready & ~cmdq.empty;

    // refresh memory mappings with a one cycle latency to not pressure fmax
    prev_mem_addr    = mem_io_cpu.addr;
    prev_mem_wenable = mem_io_cpu.wenable;
    prev_mem_wdata   = mem_io_cpu.wdata;

    // uncomment to visualize GPU bound vs CPU bound
    //                          vvvvvvv    vvvvvvv
    // leds = {$NUM_LEDS-2$b0,cmdq.full,cmdq.empty};

$$if SIMULATION then
    //if (iter == 140000) { __finish(); }
    iter = iter + 1;
$$end

  }
}

// -------------------------