bram_spram_32bits.si

// @sylefeb 2020-12-22
//
// MIT license, see LICENSE_MIT in Silice repo root

/*

Dedicated memory for the IceBreaker Ice40 with SPRAM

Implements a memory space with:

if SPRAM_128K is *not* set then
  - 0x00000 to 0x0FFFF mapped to SPRAM (0-1)
  - 0x20000 to 0x27FFF mapped to bram (boot)

if SPRAM_128K is set then
  - 0x00000 to 0x0FFFF mapped to SPRAM (0-1)
  - 0x10000 to 0x1FFFF mapped to SPRAM (2-3)
  - 0x20000 to 0x27FFF mapped to bram (boot)

Two sprams are used, spram0 for bits 0-15, spram1 for bits 16-31

*/

$$if not bram_depth then
$$ if SIMULATION then
$$  bram_depth = 13
$$ else
$$  bram_depth = 11
$$ end
$$end

$$ bram_size  = 1<<bram_depth
$$ print('##### code size: ' .. code_size_bytes .. ' BRAM capacity: ' .. 4*bram_size .. '#####')

$$if bram_depth > 14 then error('bram larger than spram') end

$$if SPRAM_128K then
$$print('using SPRAM_128K')
$$end

$$config['bram_wmask_byte_wenable_width'] = 'data'

unit bram_spram_32bits(
  bram_port_io pram {
    input     addr,
    input     wenable,
    input     wdata,
    output(!) rdata
  }, // provided ram interface
) {

  bram uint32 mem<"bram_wmask_byte">[$bram_size$] = { file("build/code.img"), pad(uninitialized) };

  uint14 sp0_addr(0);
  uint16 sp0_data_in(0);
  uint1  sp0_wenable(0);
  uint4  sp0_wmask(0);
  uint16 sp0_data_out(0);

  uint14 sp1_addr(0);
  uint16 sp1_data_in(0);
  uint1  sp1_wenable(0);
  uint4  sp1_wmask(0);
  uint16 sp1_data_out(0);

$$if SPRAM_128K then
  uint14 sp2_addr(0);
  uint16 sp2_data_in(0);
  uint1  sp2_wenable(0);
  uint4  sp2_wmask(0);
  uint16 sp2_data_out(0);

  uint14 sp3_addr(0);
  uint16 sp3_data_in(0);
  uint1  sp3_wenable(0);
  uint4  sp3_wmask(0);
  uint16 sp3_data_out(0);
$$end

$$if SIMULATION then
  simulation_spram spram0(
$$else
  ice40_spram spram0(
    clock    <: clock,
$$end
    addr     <: sp0_addr,
    data_in  <: sp0_data_in,
    wenable  <: sp0_wenable,
    wmask    <: sp0_wmask,
    data_out :> sp0_data_out
  );

$$if SIMULATION then
  simulation_spram spram1(
$$else
  ice40_spram spram1(
    clock    <: clock,
$$end
    addr     <: sp1_addr,
    data_in  <: sp1_data_in,
    wenable  <: sp1_wenable,
    wmask    <: sp1_wmask,
    data_out :> sp1_data_out
  );

$$if SPRAM_128K then

$$if SIMULATION then
  simulation_spram spram2(
$$else
  ice40_spram spram2(
    clock    <: clock,
$$end
    addr     <: sp2_addr,
    data_in  <: sp2_data_in,
    wenable  <: sp2_wenable,
    wmask    <: sp2_wmask,
    data_out :> sp2_data_out
  );

$$if SIMULATION then
  simulation_spram spram3(
$$else
  ice40_spram spram3(
    clock    <: clock,
$$end
    addr     <: sp3_addr,
    data_in  <: sp3_data_in,
    wenable  <: sp3_wenable,
    wmask    <: sp3_wmask,
    data_out :> sp3_data_out
  );

$$end

  sameas(pram.addr) prev_addr(0);

  // track when address is in bram region and onto which entry
  uint1  in_bram            <:  pram.addr [15,1];
  uint1  prev_in_bram       <:: prev_addr [15,1];
$$if SPRAM_128K then
  uint1  in_spram_2         <:  pram.addr [14,1];
  uint1  prev_in_spram_2    <:: prev_addr [14,1];
$$end
  uint1  not_mapped         <:  ~pram.addr[16, 1]; // Note: memory mapped addresses flagged by bit 31
  uint14 sub_addr           <:   pram.addr[ 0,14]; // read addr next
  uint1  wen                <:   pram.wenable != 4b0;

  always {

    // result
    pram.rdata        = prev_in_bram ? (mem.rdata)
$$if SPRAM_128K then
                      : ( prev_in_spram_2
                          ? {sp3_data_out,sp2_data_out}
                          : {sp1_data_out,sp0_data_out}
                      );
$$else
                      : {sp1_data_out,sp0_data_out};
$$end

    // access bram
    mem.addr            = sub_addr;
    mem.wenable         = pram.wenable & {4{not_mapped & in_bram}};
    mem.wdata           = pram.wdata;

    // access sprams
    sp0_addr            = sub_addr;
    sp1_addr            = sub_addr;
    sp0_data_in         = pram.wdata[ 0,16];
    sp1_data_in         = pram.wdata[16,16];
$$if SPRAM_128K then
    sp0_wenable         = wen & ~in_bram & ~in_spram_2 & not_mapped;
    sp1_wenable         = wen & ~in_bram & ~in_spram_2 & not_mapped;
$$else
    sp0_wenable         = wen & ~in_bram & not_mapped;
    sp1_wenable         = wen & ~in_bram & not_mapped;
$$end
    sp0_wmask           = {pram.wenable[1,1],pram.wenable[1,1],
                           pram.wenable[0,1],pram.wenable[0,1]};
    sp1_wmask           = {pram.wenable[3,1],pram.wenable[3,1],
                           pram.wenable[2,1],pram.wenable[2,1]};
$$if SPRAM_128K then
    sp2_addr            = sub_addr;
    sp3_addr            = sub_addr;
    sp2_data_in         = pram.wdata[ 0,16];
    sp3_data_in         = pram.wdata[16,16];
    sp2_wenable         = wen & ~in_bram & in_spram_2 & not_mapped;
    sp3_wenable         = wen & ~in_bram & in_spram_2 & not_mapped;
    sp2_wmask           = {pram.wenable[1,1],pram.wenable[1,1],
                           pram.wenable[0,1],pram.wenable[0,1]};
    sp3_wmask           = {pram.wenable[3,1],pram.wenable[3,1],
                           pram.wenable[2,1],pram.wenable[2,1]};
$$end

    prev_addr           = pram.addr;

$$if VERBOSE then
    // __display("MEMORY @%x (%b) in_bram:%b not_mapped:%b",pram.addr<<2,pram.wenable,in_bram,not_mapped);
$$end

  }

}