From 67d7a3f1314486abdce19d944622356c62c1b486 Mon Sep 17 00:00:00 2001 From: phantom1003 Date: Fri, 13 Aug 2021 19:35:01 +0800 Subject: [PATCH] Add CDE test case --- README.md | 7 +- src/main/scala/FPGA/Configs.scala | 1 + src/main/scala/Playyard/CDETest.scala | 69 +++++++++++++++++++ .../{debugTest.scala => DebugTest.scala} | 0 4 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 src/main/scala/Playyard/CDETest.scala rename src/main/scala/Playyard/{debugTest.scala => DebugTest.scala} (100%) diff --git a/README.md b/README.md index f56ab49..197912f 100644 --- a/README.md +++ b/README.md @@ -30,13 +30,18 @@ This project will follow the lastest rocket-chip, the functions of each folder i Before you start compiling, you should already have sbt, vivado and a RISC-V toolchian. ```bash +# sbt install: https://www.scala-sbt.org/1.x/docs/Installing-sbt-on-Linux.html +# vivado install: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2020-2.html +# RISC-V toolchain: https://github.com/riscv-zju/riscv-rss-sdk + $ git clone https://github.com/riscv-zju/riscv-starship.git $ git submodule update --init --recursive --progress # set $RISCV to your toolchain path, not inclued bin $ make bitstream ``` -After these, you will find your bitstream under `build/vivado/obj`, named `TestHarness.bit`. +To use Intellij IDEA as your IDE, please install scala plugin and use [JDK 11](https://www.oracle.com/java/technologies/javase-jdk11-downloads.html) as your project SDK (at File - Project Structure). +After compiling, you will find your bitstream under `build/vivado/obj`, named `TestHarness.bit`. You can open `build/vivado/TestHarness.xpr` to program your FPGA device. But before loading the bitstream into the board, you should prepare the test image on a SD/TF card. > Note that the image should place on the 2048th selector of the SD card without filesystem. diff --git a/src/main/scala/FPGA/Configs.scala b/src/main/scala/FPGA/Configs.scala index d0d480e..c322af2 100644 --- a/src/main/scala/FPGA/Configs.scala +++ b/src/main/scala/FPGA/Configs.scala @@ -67,6 +67,7 @@ class StarshipFPGAConfig extends Config( val make = s"make -C firmware/zsbl ROOT_DIR=${path} img" println("[Leaving Starship] " + make) require (make.! == 0, "Failed to build bootrom") + println("[Starship Continue]") p.copy(hang = 0x10000, contentFileName = s"build/firmware/zsbl/bootrom.img") } }) diff --git a/src/main/scala/Playyard/CDETest.scala b/src/main/scala/Playyard/CDETest.scala new file mode 100644 index 0000000..345b1c3 --- /dev/null +++ b/src/main/scala/Playyard/CDETest.scala @@ -0,0 +1,69 @@ +package starship.playyard.cde + +import chisel3._ + +import freechips.rocketchip.config.{Config, Field, Parameters} + +case object TestKey1 extends Field[Int](-1) +case object TestKey2 extends Field[Int] +case object TestKey3 extends Field[Int](-3) +case object TestKey4 extends Field[Int] + +class TestConfig extends Config((site, here, up) => { + case TestKey1 => 0 +}) + + +object CDETest { + def main(args: Array[String]): Unit = { + + // Empty config + var p: Parameters = Parameters.empty + + // Parameter Access + assert(p(TestKey1) == p.apply(TestKey1)) + assert(p(TestKey1) == p.lift(TestKey1).get) + + // Default Value + assert(p(TestKey1) == -1) + try { p(TestKey4) } + catch { + case e: java.lang.IllegalArgumentException => println(s"TestKey4 == ${p.lift(TestKey4)}") + } + + // Alter + p = Parameters((site, here, up) => { + case TestKey1 => 1 + }) + p = p.alter((site, here, up) => { + case TestKey2 => 2 + }) + p = p.alterPartial({ + case TestKey3 => 3 + }) + p = p.alterMap(Map( + TestKey4 -> 4 + )) + assert(p(TestKey1) == 1) + assert(p(TestKey2) == 2) + assert(p(TestKey3) == 3) + assert(p(TestKey4) == 4) + + // site, here, up + p = Parameters((site, here, up) => { + case TestKey1 => 0 + }) ++ Parameters((site, here, up) => { + case TestKey1 => 1 + case TestKey2 => here(TestKey1, site) + 1 + case TestKey3 => up(TestKey4, site) - 1 + }) ++ Parameters((site, here, up) => { + case TestKey4 => site(TestKey1, site) + 4 + }) + assert(p(TestKey1) == 0) + assert(p(TestKey2) == 2) + assert(p(TestKey3) == 3) + assert(p(TestKey4) == 4) + + print("[CDETest] SUCCESS\n") + } +} diff --git a/src/main/scala/Playyard/debugTest.scala b/src/main/scala/Playyard/DebugTest.scala similarity index 100% rename from src/main/scala/Playyard/debugTest.scala rename to src/main/scala/Playyard/DebugTest.scala