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cpu.c
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/*--------------------------------------------------------------------------
**
** Copyright (c) 2003-2011, Tom Hunter
**
** Name: cpu.c
**
** Description:
** Perform emulation of CDC 6600 or CYBER class CPU.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License version 3 as
** published by the Free Software Foundation.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License version 3 for more details.
**
** You should have received a copy of the GNU General Public License
** version 3 along with this program in file "license-gpl-3.0.txt".
** If not, see <http://www.gnu.org/licenses/gpl-3.0.txt>.
**
**--------------------------------------------------------------------------
*/
/*
** -------------
** Include Files
** -------------
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "const.h"
#include "types.h"
#include "proto.h"
/*
** -----------------
** Private Constants
** -----------------
*/
/* Only enable this for testing to pass section 4.A of EJT (divide break-in test) */
#define CcSMM_EJT 1
/*
** CPU exit conditions.
*/
#define EcNone 00
#define EcAddressOutOfRange 01
#define EcOperandOutOfRange 02
#define EcIndefiniteOperand 04
/*
** ECS bank size taking into account the 5k reserve.
*/
#define EcsBankSize (131072 - 5120)
#define EsmBankSize 131072
/*
** -----------------------
** Private Macro Functions
** -----------------------
*/
/*
** -----------------------------------------
** Private Typedef and Structure Definitions
** -----------------------------------------
*/
typedef struct opDispatch
{
void (*execute)(void);
u8 length;
} OpDispatch;
/*
** ---------------------------
** Private Function Prototypes
** ---------------------------
*/
static void cpuOpIllegal(void);
static bool cpuCheckOpAddress(u32 address, u32 *location);
static void cpuFetchOpWord(u32 address, CpWord *data);
static void cpuVoidIwStack(u32 branchAddr);
static bool cpuReadMem(u32 address, CpWord *data);
static bool cpuWriteMem(u32 address, CpWord *data);
static void cpuRegASemantics(void);
static u32 cpuAddRa(u32 op);
static u32 cpuAdd18(u32 op1, u32 op2);
static u32 cpuAdd24(u32 op1, u32 op2);
static u32 cpuSubtract18(u32 op1, u32 op2);
static void cpuUemWord(bool writeToUem);
static void cpuEcsWord(bool writeToEcs);
static void cpuUemTransfer(bool writeToUem);
static void cpuEcsTransfer(bool writeToEcs);
static bool cpuCmuGetByte(u32 address, u32 pos, u8 *byte);
static bool cpuCmuPutByte(u32 address, u32 pos, u8 byte);
static void cpuCmuMoveIndirect(void);
static void cpuCmuMoveDirect(void);
static void cpuCmuCompareCollated(void);
static void cpuCmuCompareUncollated(void);
static void cpuFloatCheck(CpWord value);
static void cpuFloatExceptionHandler(void);
static void cpOp00(void);
static void cpOp01(void);
static void cpOp02(void);
static void cpOp03(void);
static void cpOp04(void);
static void cpOp05(void);
static void cpOp06(void);
static void cpOp07(void);
static void cpOp10(void);
static void cpOp11(void);
static void cpOp12(void);
static void cpOp13(void);
static void cpOp14(void);
static void cpOp15(void);
static void cpOp16(void);
static void cpOp17(void);
static void cpOp20(void);
static void cpOp21(void);
static void cpOp22(void);
static void cpOp23(void);
static void cpOp24(void);
static void cpOp25(void);
static void cpOp26(void);
static void cpOp27(void);
static void cpOp30(void);
static void cpOp31(void);
static void cpOp32(void);
static void cpOp33(void);
static void cpOp34(void);
static void cpOp35(void);
static void cpOp36(void);
static void cpOp37(void);
static void cpOp40(void);
static void cpOp41(void);
static void cpOp42(void);
static void cpOp43(void);
static void cpOp44(void);
static void cpOp45(void);
static void cpOp46(void);
static void cpOp47(void);
static void cpOp50(void);
static void cpOp51(void);
static void cpOp52(void);
static void cpOp53(void);
static void cpOp54(void);
static void cpOp55(void);
static void cpOp56(void);
static void cpOp57(void);
static void cpOp60(void);
static void cpOp61(void);
static void cpOp62(void);
static void cpOp63(void);
static void cpOp64(void);
static void cpOp65(void);
static void cpOp66(void);
static void cpOp67(void);
static void cpOp70(void);
static void cpOp71(void);
static void cpOp72(void);
static void cpOp73(void);
static void cpOp74(void);
static void cpOp75(void);
static void cpOp76(void);
static void cpOp77(void);
/*
** ----------------
** Public Variables
** ----------------
*/
CpWord *cpMem;
CpWord *extMem;
u32 ecsFlagRegister;
CpuContext cpu;
bool cpuStopped = TRUE;
u32 cpuMaxMemory;
u32 extMaxMemory;
/*
** -----------------
** Private Variables
** -----------------
*/
static FILE *cmHandle;
static FILE *ecsHandle;
static u8 opOffset;
static CpWord opWord;
static u8 opFm;
static u8 opI;
static u8 opJ;
static u8 opK;
static u8 opLength;
static u32 opAddress;
static u32 oldRegP;
static CpWord acc60;
static u32 acc18;
static u32 acc21;
static u32 acc24;
static bool floatException = FALSE;
static int debugCount = 0;
#if CcSMM_EJT
static int skipStep = 0;
#endif
/*
** Opcode decode and dispatch table.
*/
static OpDispatch decodeCpuOpcode[] =
{
cpOp00, 15,
cpOp01, 0,
cpOp02, 30,
cpOp03, 30,
cpOp04, 30,
cpOp05, 30,
cpOp06, 30,
cpOp07, 30,
cpOp10, 15,
cpOp11, 15,
cpOp12, 15,
cpOp13, 15,
cpOp14, 15,
cpOp15, 15,
cpOp16, 15,
cpOp17, 15,
cpOp20, 15,
cpOp21, 15,
cpOp22, 15,
cpOp23, 15,
cpOp24, 15,
cpOp25, 15,
cpOp26, 15,
cpOp27, 15,
cpOp30, 15,
cpOp31, 15,
cpOp32, 15,
cpOp33, 15,
cpOp34, 15,
cpOp35, 15,
cpOp36, 15,
cpOp37, 15,
cpOp40, 15,
cpOp41, 15,
cpOp42, 15,
cpOp43, 15,
cpOp44, 15,
cpOp45, 15,
cpOp46, 15,
cpOp47, 15,
cpOp50, 30,
cpOp51, 30,
cpOp52, 30,
cpOp53, 15,
cpOp54, 15,
cpOp55, 15,
cpOp56, 15,
cpOp57, 15,
cpOp60, 30,
cpOp61, 30,
cpOp62, 30,
cpOp63, 15,
cpOp64, 15,
cpOp65, 15,
cpOp66, 15,
cpOp67, 15,
cpOp70, 30,
cpOp71, 30,
cpOp72, 30,
cpOp73, 15,
cpOp74, 15,
cpOp75, 15,
cpOp76, 15,
cpOp77, 15
};
static u8 cpOp01Length[8] = { 30, 30, 30, 30, 15, 15, 15, 15 };
/*
**--------------------------------------------------------------------------
**
** Public Functions
**
**--------------------------------------------------------------------------
*/
/*--------------------------------------------------------------------------
** Purpose: Initialise CPU.
**
** Parameters: Name Description.
** model CPU model string
** memory configured central memory
** emBanks configured number of extended memory banks
**
** Returns: Nothing.
**
**------------------------------------------------------------------------*/
void cpuInit(char *model, u32 memory, u32 emBanks, ExtMemory emType)
{
u32 extBanksSize;
/*
** Allocate configured central memory.
*/
cpMem = calloc(memory, sizeof(CpWord));
if (cpMem == NULL)
{
fprintf(stderr, "Failed to allocate CPU memory\n");
exit(1);
}
cpuMaxMemory = memory;
switch (emType)
{
case ECS:
extBanksSize = EcsBankSize;
break;
case ESM:
extBanksSize = EsmBankSize;
break;
}
/*
** Allocate configured ECS memory.
*/
extMem = calloc(emBanks * extBanksSize, sizeof(CpWord));
if (extMem == NULL)
{
fprintf(stderr, "Failed to allocate ECS memory\n");
exit(1);
}
extMaxMemory = emBanks * extBanksSize;
/*
** Optionally read in persistent CM and ECS contents.
*/
if (*persistDir != '\0')
{
char fileName[256];
/*
** Try to open existing CM file.
*/
strcpy(fileName, persistDir);
strcat(fileName, "/cmStore");
cmHandle = fopen(fileName, "r+b");
if (cmHandle != NULL)
{
/*
** Read CM contents.
*/
if (fread(cpMem, sizeof(CpWord), cpuMaxMemory, cmHandle) != cpuMaxMemory)
{
printf("Unexpected length of CM backing file, clearing CM\n");
memset(cpMem, 0, cpuMaxMemory);
}
}
else
{
/*
** Create a new file.
*/
cmHandle = fopen(fileName, "w+b");
if (cmHandle == NULL)
{
fprintf(stderr, "Failed to create CM backing file\n");
exit(1);
}
}
/*
** Try to open existing ECS file.
*/
strcpy(fileName, persistDir);
strcat(fileName, "/ecsStore");
ecsHandle = fopen(fileName, "r+b");
if (ecsHandle != NULL)
{
/*
** Read ECS contents.
*/
if (fread(extMem, sizeof(CpWord), extMaxMemory, ecsHandle) != extMaxMemory)
{
printf("Unexpected length of ECS backing file, clearing ECS\n");
memset(extMem, 0, extMaxMemory);
}
}
else
{
/*
** Create a new file.
*/
ecsHandle = fopen(fileName, "w+b");
if (ecsHandle == NULL)
{
fprintf(stderr, "Failed to create ECS backing file\n");
exit(1);
}
}
}
/*
** Print a friendly message.
*/
printf("CPU model %s initialised (CM: %o, ECS: %o)\n", model, cpuMaxMemory, extMaxMemory);
}
/*--------------------------------------------------------------------------
** Purpose: Terminate CPU and optionally persist CM.
**
** Parameters: Name Description.
**
** Returns: Nothing.
**
**------------------------------------------------------------------------*/
void cpuTerminate(void)
{
/*
** Optionally save CM.
*/
if (cmHandle != NULL)
{
fseek(cmHandle, 0, SEEK_SET);
if (fwrite(cpMem, sizeof(CpWord), cpuMaxMemory, cmHandle) != cpuMaxMemory)
{
fprintf(stderr, "Error writing CM backing file\n");
}
fclose(cmHandle);
}
/*
** Optionally save ECS.
*/
if (ecsHandle != NULL)
{
fseek(ecsHandle, 0, SEEK_SET);
if (fwrite(extMem, sizeof(CpWord), extMaxMemory, ecsHandle) != extMaxMemory)
{
fprintf(stderr, "Error writing ECS backing file\n");
}
fclose(ecsHandle);
}
/*
** Free allocated memory.
*/
free(cpMem);
free(extMem);
}
/*--------------------------------------------------------------------------
** Purpose: Return CPU P register.
**
** Parameters: Name Description.
**
** Returns: Nothing.
**
**------------------------------------------------------------------------*/
u32 cpuGetP(void)
{
return((cpu.regP) & Mask18);
}
/*--------------------------------------------------------------------------
** Purpose: Read CPU memory from PP and verify that address is
** within limits.
**
** Parameters: Name Description.
** address Absolute CM address to read.
** data Pointer to 60 bit word which gets the data.
**
** Returns: Nothing
**
**------------------------------------------------------------------------*/
void cpuPpReadMem(u32 address, CpWord *data)
{
if ((features & HasNoCmWrap) != 0)
{
if (address < cpuMaxMemory)
{
*data = cpMem[address] & Mask60;
}
else
{
*data = (~((CpWord)0)) & Mask60;
}
}
else
{
address %= cpuMaxMemory;
*data = cpMem[address] & Mask60;
}
}
/*--------------------------------------------------------------------------
** Purpose: Write CPU memory from PP and verify that address is
** within limits.
**
** Parameters: Name Description.
** address Absolute CM address
** data 60 bit word which holds the data to be written.
**
** Returns: Nothing
**
**------------------------------------------------------------------------*/
void cpuPpWriteMem(u32 address, CpWord data)
{
if ((features & HasNoCmWrap) != 0)
{
if (address < cpuMaxMemory)
{
cpMem[address] = data & Mask60;
}
}
else
{
address %= cpuMaxMemory;
cpMem[address] = data & Mask60;
}
}
/*--------------------------------------------------------------------------
** Purpose: Perform exchange jump.
**
** Parameters: Name Description.
** addr Exchange jump address.
**
** Returns: TRUE if exchange jump can be performed, FALSE otherwise.
**
**------------------------------------------------------------------------*/
bool cpuExchangeJump(u32 addr)
{
CpuContext tmp;
CpWord *mem;
/*
** Only perform exchange jump on instruction boundary or when stopped.
*/
if (opOffset != 60 && !cpuStopped)
{
return(FALSE);
}
#if CcDebug == 1
traceExchange(&cpu, addr, "Old");
#endif
/*
** Clear any spurious address bits.
*/
addr &= Mask18;
/*
** Verify if exchange package is within configured memory.
*/
if (addr + 020 >= cpuMaxMemory)
{
/*
** Pretend that exchange worked, but the address is bad.
*/
return(TRUE);
}
/*
** Save current context.
*/
tmp = cpu;
/*
** Setup new context.
*/
mem = cpMem + addr;
cpu.regP = (u32)((*mem >> 36) & Mask18);
cpu.regA[0] = (u32)((*mem >> 18) & Mask18);
cpu.regB[0] = 0;
mem += 1;
cpu.regRaCm = (u32)((*mem >> 36) & Mask24);
cpu.regA[1] = (u32)((*mem >> 18) & Mask18);
cpu.regB[1] = (u32)((*mem ) & Mask18);
mem += 1;
cpu.regFlCm = (u32)((*mem >> 36) & Mask24);
cpu.regA[2] = (u32)((*mem >> 18) & Mask18);
cpu.regB[2] = (u32)((*mem ) & Mask18);
mem += 1;
cpu.exitMode = (u32)((*mem >> 36) & Mask24);
cpu.regA[3] = (u32)((*mem >> 18) & Mask18);
cpu.regB[3] = (u32)((*mem ) & Mask18);
mem += 1;
if ( (features & IsSeries800) != 0
&& (cpu.exitMode & EmFlagExpandedAddress) != 0)
{
cpu.regRaEcs = (u32)((*mem >> 30) & Mask30Ecs);
}
else
{
cpu.regRaEcs = (u32)((*mem >> 36) & Mask24Ecs);
}
cpu.regA[4] = (u32)((*mem >> 18) & Mask18);
cpu.regB[4] = (u32)((*mem ) & Mask18);
mem += 1;
if ( (features & IsSeries800) != 0
&& (cpu.exitMode & EmFlagExpandedAddress) != 0)
{
cpu.regFlEcs = (u32)((*mem >> 30) & Mask30Ecs);
}
else
{
cpu.regFlEcs = (u32)((*mem >> 36) & Mask24Ecs);
}
cpu.regA[5] = (u32)((*mem >> 18) & Mask18);
cpu.regB[5] = (u32)((*mem ) & Mask18);
mem += 1;
cpu.regMa = (u32)((*mem >> 36) & Mask24);
cpu.regA[6] = (u32)((*mem >> 18) & Mask18);
cpu.regB[6] = (u32)((*mem ) & Mask18);
mem += 1;
cpu.regSpare = (u32)((*mem >> 36) & Mask24);
cpu.regA[7] = (u32)((*mem >> 18) & Mask18);
cpu.regB[7] = (u32)((*mem ) & Mask18);
mem += 1;
cpu.regX[0] = *mem++ & Mask60;
cpu.regX[1] = *mem++ & Mask60;
cpu.regX[2] = *mem++ & Mask60;
cpu.regX[3] = *mem++ & Mask60;
cpu.regX[4] = *mem++ & Mask60;
cpu.regX[5] = *mem++ & Mask60;
cpu.regX[6] = *mem++ & Mask60;
cpu.regX[7] = *mem++ & Mask60;
cpu.exitCondition = EcNone;
#if CcDebug == 1
traceExchange(&cpu, addr, "New");
#endif
/*
** Save old context.
*/
mem = cpMem + addr;
*mem++ = ((CpWord)(tmp.regP & Mask18) << 36) | ((CpWord)(tmp.regA[0] & Mask18) << 18);
*mem++ = ((CpWord)(tmp.regRaCm & Mask24) << 36) | ((CpWord)(tmp.regA[1] & Mask18) << 18) | ((CpWord)(tmp.regB[1] & Mask18));
*mem++ = ((CpWord)(tmp.regFlCm & Mask24) << 36) | ((CpWord)(tmp.regA[2] & Mask18) << 18) | ((CpWord)(tmp.regB[2] & Mask18));
*mem++ = ((CpWord)(tmp.exitMode & Mask24) << 36) | ((CpWord)(tmp.regA[3] & Mask18) << 18) | ((CpWord)(tmp.regB[3] & Mask18));
if ( (features & IsSeries800) != 0
&& (tmp.exitMode & EmFlagExpandedAddress) != 0)
{
*mem++ = ((CpWord)(tmp.regRaEcs & Mask30Ecs) << 30) | ((CpWord)(tmp.regA[4] & Mask18) << 18) | ((CpWord)(tmp.regB[4] & Mask18));
}
else
{
*mem++ = ((CpWord)(tmp.regRaEcs & Mask24Ecs) << 36) | ((CpWord)(tmp.regA[4] & Mask18) << 18) | ((CpWord)(tmp.regB[4] & Mask18));
}
if ( (features & IsSeries800) != 0
&& (tmp.exitMode & EmFlagExpandedAddress) != 0)
{
*mem++ = ((CpWord)(tmp.regFlEcs & Mask30Ecs) << 30) | ((CpWord)(tmp.regA[5] & Mask18) << 18) | ((CpWord)(tmp.regB[5] & Mask18));
}
else
{
*mem++ = ((CpWord)(tmp.regFlEcs & Mask24Ecs) << 36) | ((CpWord)(tmp.regA[5] & Mask18) << 18) | ((CpWord)(tmp.regB[5] & Mask18));
}
*mem++ = ((CpWord)(tmp.regMa & Mask24) << 36) | ((CpWord)(tmp.regA[6] & Mask18) << 18) | ((CpWord)(tmp.regB[6] & Mask18));
*mem++ = ((CpWord)(tmp.regSpare & Mask24) << 36) | ((CpWord)(tmp.regA[7] & Mask18) << 18) | ((CpWord)(tmp.regB[7] & Mask18));
*mem++ = tmp.regX[0] & Mask60;
*mem++ = tmp.regX[1] & Mask60;
*mem++ = tmp.regX[2] & Mask60;
*mem++ = tmp.regX[3] & Mask60;
*mem++ = tmp.regX[4] & Mask60;
*mem++ = tmp.regX[5] & Mask60;
*mem++ = tmp.regX[6] & Mask60;
*mem++ = tmp.regX[7] & Mask60;
if ((features & HasInstructionStack) != 0)
{
/*
** Void the instruction stack.
*/
cpuVoidIwStack(~0);
}
/*
** Activate CPU.
*/
cpuStopped = FALSE;
cpuFetchOpWord(cpu.regP, &opWord);
return(TRUE);
}
/*--------------------------------------------------------------------------
** Purpose: Execute next instruction in the CPU.
**
** Parameters: Name Description.
**
** Returns: Nothing.
**
**------------------------------------------------------------------------*/
void cpuStep(void)
{
if (cpuStopped)
{
return;
}
#if CcSMM_EJT
if (skipStep != 0)
{
skipStep -= 1;
return;
}
#endif
/*
** Execute one CM word atomically.
*/
do
{
/*
** Decode based on type.
*/
opFm = (u8)((opWord >> (opOffset - 6)) & Mask6);
opI = (u8)((opWord >> (opOffset - 9)) & Mask3);
opJ = (u8)((opWord >> (opOffset - 12)) & Mask3);
opLength = decodeCpuOpcode[opFm].length;
if (opLength == 0)
{
opLength = cpOp01Length[opI];
}
if (opLength == 15)
{
opK = (u8)((opWord >> (opOffset - 15)) & Mask3);
opAddress = 0;
opOffset -= 15;
}
else
{
if (opOffset == 15)
{
/*
** Invalid packing is handled as illegal instruction.
*/
cpuOpIllegal();
return;
}
opK = 0;
opAddress = (u32)((opWord >> (opOffset - 30)) & Mask18);
opOffset -= 30;
}
oldRegP = cpu.regP;
/*
** Force B0 to 0.
*/
cpu.regB[0] = 0;
/*
** Execute instruction.
*/
decodeCpuOpcode[opFm].execute();
/*
** Force B0 to 0.
*/
cpu.regB[0] = 0;
#if CcDebug == 1
traceCpu(oldRegP, opFm, opI, opJ, opK, opAddress);
#endif
if (cpuStopped)
{
if (opOffset == 0)
{
cpu.regP = (cpu.regP + 1) & Mask18;
}
#if CcDebug == 1
traceCpuPrint("Stopped\n");
#endif
return;
}
/*
** Fetch next instruction word if necessary.
*/
if (opOffset == 0)
{
cpu.regP = (cpu.regP + 1) & Mask18;
cpuFetchOpWord(cpu.regP, &opWord);
}
} while (opOffset != 60);
}
/*--------------------------------------------------------------------------
** Purpose: Perform ECS flag register operation.
**
** Parameters: Name Description.
** ecsAddress ECS address (flag register function and data)
**
** Returns: TRUE if accepted, FALSE otherwise.
**
**------------------------------------------------------------------------*/
bool cpuEcsFlagRegister(u32 ecsAddress)
{
u32 flagFunction = (ecsAddress >> 21) & Mask3;
u32 flagWord = ecsAddress & Mask18;
switch (flagFunction)
{
case 4:
/*
** Ready/Select.
*/
if ((ecsFlagRegister & flagWord ) != 0)
{
/*
** Error exit.
*/
return(FALSE);
}
ecsFlagRegister |= flagWord;
break;
case 5:
/*
** Selective set.
*/
ecsFlagRegister |= flagWord;
break;
case 6:
/*
** Status.
*/
if ((ecsFlagRegister & flagWord ) != 0)
{
/*
** Error exit.
*/
return(FALSE);
}
break;
case 7:
/*
** Selective clear,
*/
ecsFlagRegister = (ecsFlagRegister & ~flagWord) & Mask18;
break;
}
/*
** Normal exit.
*/
return(TRUE);
}
/*--------------------------------------------------------------------------
** Purpose: Transfer on 60 bit word to/from DDP/ECS.
**
** Parameters: Name Description.
** ecsAddress ECS word address
** data Pointer to 60 bit word
** writeToEcs TRUE if this is a write to ECS, FALSE if
** this is a read.
**
** Returns: TRUE if accepted, FALSE otherwise.
**
**------------------------------------------------------------------------*/
bool cpuDdpTransfer(u32 ecsAddress, CpWord *data, bool writeToEcs)
{
/*
** Normal (non flag-register) access must be within ECS boundaries.
*/
if (ecsAddress >= extMaxMemory)
{
/*
** Abort.
*/
return(FALSE);
}
/*
** Perform the transfer.
*/
if (writeToEcs)
{
extMem[ecsAddress] = *data & Mask60;
}
else
{
*data = extMem[ecsAddress] & Mask60;
}
/*
** Normal accept.
*/
return(TRUE);
}
/*
**--------------------------------------------------------------------------
**
** Private Functions
**
**--------------------------------------------------------------------------
*/
/*--------------------------------------------------------------------------
** Purpose: Handle illegal instruction
**
** Parameters: Name Description.
**
** Returns: Nothing
**
**------------------------------------------------------------------------*/
static void cpuOpIllegal(void)
{
cpuStopped = TRUE;
if (cpu.regRaCm < cpuMaxMemory)
{
cpMem[cpu.regRaCm] = ((CpWord)cpu.exitCondition << 48) | ((CpWord)(cpu.regP + 1) << 30);
}
cpu.regP = 0;
if ((features & (HasNoCejMej | IsSeries6x00)) == 0 && !cpu.monitorMode)
{
/*
** Exchange jump to MA.
*/
cpu.monitorMode = TRUE;
cpuExchangeJump(cpu.regMa);
}
}
/*--------------------------------------------------------------------------
** Purpose: Check if CPU instruction word address is within limits.
**
** Parameters: Name Description.
** address RA relative address to read.
** location Pointer to u32 which will contain absolute address.
**
** Returns: TRUE if validation failed, FALSE otherwise;
**
**------------------------------------------------------------------------*/
static bool cpuCheckOpAddress(u32 address, u32 *location)
{
/*
** Calculate absolute address.
*/
*location = cpuAddRa(address);
if (address >= cpu.regFlCm || (*location >= cpuMaxMemory && (features & HasNoCmWrap) != 0))
{
/*
** Exit mode is always selected for RNI or branch.
*/
cpuStopped = TRUE;
cpu.exitCondition |= EcAddressOutOfRange;
if (cpu.regRaCm < cpuMaxMemory)
{
// not need for RNI or branch - how about other uses?
if ((cpu.exitMode & EmAddressOutOfRange) != 0)