how to Connect a JTAG adapter to the NEORV32 jtag_* interface signals. #567
Comments
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Hey @athurwo! Could you provide some code like your pin-mapping and/or your setup's top entity? Do you also use the JTAG reset signal? If not, this signal has to be high. Is the on-chip debugger enabled at all ( |
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hello @stnolting yes, I had enabled ON_CHIP_DEBUGGER_EN generic and assigned jtag reset to high. |
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Maybe it is just a problem with the signal connection... What kind of JTAG adapter are you using? Could you share your top-level design (just the JTAG signals / pin mapping)? |
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hey @stnolting I use jtag usb cable with ftdi ft232h. I assign fpga board gpio to neorv32 cpu jtag pin, and connect gpio to jtag usb cable by DuPont Line. J24, J22, J26, K30 is gpio in fpga board. set_property PACKAGE_PIN J24 [get_ports jtag_tck_i] |
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now the infomation is changed: Open On-Chip Debugger 0.11.0+dev-02556-g78231cda3 (2023-04-03-14:31) |
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Hm ok, all relevant signals are there. I think it might be a wiring problem between the FPGA pins and your JTAG adapter. Do you use a "real" adapter or just a FTDI breakout board? This is the wiring I am using: https://stnolting.github.io/neorv32/ug/#_hardware_requirements |
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Hey I would like to participate in this conversation because I'm strugglung with similar problem. I have Zedboard REV.D development board. It uses ZynQ 7 Series FPGA and has JTAG Connector with Cascaded JTAG. I want to access JTAG in PL (Programming Logic). I already created necessary IPs and connected. I can see a new JTAG connection in Vivado when I programmed the board, but I would like to access that using OpenOCD and debug with GDB. I have followed the tutorial and at the moment am able to see JTAG interfaces in OpenOCD but I'm getting similar error. I'm using Digilent HS1 Rev.A as my JTAG Connector. I already changed
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Looks like you connected your connection or defined pin_layout wrong. This error is raised whenever the pins are not aligned or connected correctly. |
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I don`t know what different between "real" adapter and FTDI breakout board. this jtag adaper is same with digilent usb cable, can program bitstream to fpga board. |
hello, how to change pin_layout in opeocd.cfg? |
This is my
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my ftdi vid_pid is 0x0403 0x6014, I don`t know which is correct: /usr/local/share/openocd/scripts/interface/ftdi/c232hm.cfg:ftdi vid_pid 0x0403 0x6014 |
most likely |
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@stnolting do you have any idea for my problem? I tried lots of different thing but to no avail. |
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i had tried gpio and jtag port in fpga board to connect to jtag cable, but don`t work. |
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hello, @stnolting Could you give some detail step about connect jtag adapter and fpga, like image and infomation? thanks. |
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You can find the wiring (FTDI <-> FPGA) in the openOCD configuration file: neorv32/sw/openocd/openocd_neorv32.cfg Lines 4 to 12 in 3214f30 Could you give some more details regarding your setup? As far as I understand the USB JTAG interface of your board chains the FPGA's configuration port and the FPGA's hard-macro ARM processor port. There is no chance to add another device into this chain - especially not from the FPGA fabric part as this would interrupt the chain when the FPGA itself is not configured. However, there is an option to utilize the FPGA's configuration JTAG TAP for user-logic, but I think this is out of scope here (see this discussion by @NikLeberg: #479 (comment)). So I would suggest to use some IO pins of your board to connect and external JTAG adapter - just like @athurwo did. |
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Hey @stnolting , here is more information about current implementation in IP. IP Block Design
NeoRV32 Settings
Hardware Server
As you can see from the Images that I took, I can generate Bitsream without a problem and all the connections are correct. Hardware Server also works just fine and I am able to see 2 JTAG TAP as well as NeoRV32 JTAG IDCODE which is Thanks |
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Thanks for the additional details! Could you please check the synthesis report of your design? I think the "bscan_jtag_0" module uses at least one From an "electrical" point of view your design is just fine. The problem here is the software part on host side. As I mentioned before, there is no option to add further devices into the FPGA's JTAG chain as this would interrupt the chain when the FPGA is not configured. There are two options here:
The BSCANE primitive allows to "add" (in quotes!) custom JTAG modules to the JTAG chain. But they are not really inserted into the chain. Instead, a tunneling concept is used. And this is where the complicated part begins. This is similar to what @NikLeberg has implemented. OpenOCD does support this tunneling mode and I have seen RISC-V cores being accessed via this approach. Unfortunately, this feature is not very well documented. I have experimented with that some time ago - but I failed 😅 This is by far the best documentation I have found: openhwgroup/core-v-mcu#117 (comment) |
Actually 1 BSCANE2 (its Xilinx 7000 series FPGA) and BSCAN Switch.
Yeah and that's why I do not have any idea what can be the problem. I assume it's a problem with the OpenOCD configuration. Before I forgot I would like to add this new details here as well. So with the same IP Design, I have synthesized and generated bitsream without a problem as always. But this time In OpenOCD side I used
Yeah thats the currunt implemented solution that I'm using to access NeoRV32 JTAG. I'm using PMOD Header that available in PL to access it.
You mean that I should create a VHDL file that uses BSCANE(2) and directly output JTAG connections from it. It makes sense but aren't Debug Bridge and BSCAN to JTAG Converter do that already? I will look into it.
I understand you pain totally. I read 1825 page long Xilinx 7-Series documentation with UG470 beside. It's not a easy thing to achive, there should be a better solution to access over PS -> PL using Cascaded JTAG. Thanks for the help @stnolting |
Right, that is the problem. The tunneling concept only requires single BSCANE primitive - openOCD takes care of the rest (the actual tunneling). But the only real documentation I could find about this was the actual openOCD code itself...
The second option is to use three BSCANE primtives. You can access the "user" registers via openOCD and they can be repurposed to access/implement the RISC-V DTM's All in all a quite complicated situation. I still prefer the first concept (tunneling), but I did not have time to further investigate on that yet. 🙈 |
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I ran into the same problem as @athurwo. The problem is, that i have a Zedboard and a HS3 JTAG. The programming cable of the board and the JTAG have the same vid and pid ,thus openocd tried to connect to both and fails for the programming cable (the autotap), resulting in a similar error message as athurwo had. A solution for this is to specify in the .cfg which adapter should be used, e.g. using: P.S.: Also, i wanted to say at this point that the project is very well documented, so far everything was really easy to setup/understand even as an newb. Thank you for that :) |
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really？thanks，I will try it.
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| From | T.-M. ***@***.***> |
| Date | 07/04/2023 18:52 |
| To | ***@***.***> |
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| Subject | Re: [stnolting/neorv32] how to Connect a JTAG adapter to the NEORV32 jtag_* interface signals. (Issue #567) |
I ran into the same problem as @athurwo. The problem is, that i have a Zedboard and a HS3 JTAG. The programming cable of the board and the JTAG have the same vid and pid ,thus openocd tried to connect to both and fails for the programming cable (the autotap), resulting in a similar error message as athurwo had.
A solution for this is to specify in the .cfg which adapter should be used, e.g. using:
adapter usb location [<bus>-<port>[.<port>]...] see the openocd user documentation
You can get the used bus/port using 'lsusb -t` or using dmesg.
P.S.: Also, i wanted to say at this point that the project is very well documented, so far everything was really easy to setup/understand even as an newb. Thank you for that :)
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I think this can be closed now. Feel free to open a new issue if you still have troubles with the JTAG connection. |
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I constraint NEORV32 jtag_* to FPGA JTAG pin, but opeocd cannot check cpu:
Open On-Chip Debugger 0.11.0+dev-02556-g78231cda3 (2023-04-03-14:31)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : clock speed 2000 kHz
Info : JTAG tap: neorv32.cpu tap/device found: 0x43651093 (mfg: 0x049 (Xilinx), part: 0x3651, ver: 0x4)
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Warn : target neorv32.cpu.0 examination failed
Info : starting gdb server for neorv32.cpu.0 on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet
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