From 6b8a35073815e59deddbdc784a3e78d163de9f61 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 12 Jan 2024 19:17:52 +0100
Subject: [PATCH] testsuite/gna: add a test for #2580

---
 testsuite/gna/issue2580/streamtb.vhdl | 78 +++++++++++++++++++++++++++
 testsuite/gna/issue2580/testsuite.sh  |  5 ++
 2 files changed, 83 insertions(+)
 create mode 100644 testsuite/gna/issue2580/streamtb.vhdl

diff --git a/testsuite/gna/issue2580/streamtb.vhdl b/testsuite/gna/issue2580/streamtb.vhdl
new file mode 100644
index 0000000000..ce4525b8fd
--- /dev/null
+++ b/testsuite/gna/issue2580/streamtb.vhdl
@@ -0,0 +1,78 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package StreamPkg is
+generic(
+   type DAT
+);
+   type streamDataArrayType is array (natural range <>) of DAT;
+end StreamPkg;
+
+package body StreamPkg is
+end package body StreamPkg;
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity StreamRegSlice is
+   generic (
+      type DAT
+   );
+   port (
+      rxcDat_i : in  DAT;
+      txcDat_o : out DAT
+   );
+end StreamRegSlice;
+
+architecture rtl of StreamRegSlice is
+begin
+   txcDat_o <= rxcDat_i;
+end rtl;
+
+
+use std.env.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity StreamTb is
+   generic (
+      WIDTH : positive := 8
+   );
+   package StreamPkgDef is new work.StreamPkg generic map (DAT => std_logic_vector(WIDTH-1 downto 0));
+   use StreamPkgDef.all;
+end StreamTb;
+
+architecture behavior of StreamTb is
+-- subtype DAT is std_logic_vector(WIDTH-1 downto 0);
+   signal txcDat : DAT;
+   signal rxcDat : DAT;
+begin
+
+   -- DUT instance
+   dut : entity work.StreamRegSlice
+   generic map (
+      DAT => DAT
+   )
+   port map (
+      rxcDat_i => txcDat,
+      txcDat_o => rxcDat
+   );
+--   rxcDat <= txcDat;
+
+   p_test : process
+   begin
+      -- end simulation
+      for i in 0 to 8-1 loop
+         txcDat <= std_logic_vector(to_unsigned(i, WIDTH));
+         wait for 10 ns;
+      end loop;
+      report "Simulation end";
+      finish;
+   end process p_test;
+
+end behavior;
diff --git a/testsuite/gna/issue2580/testsuite.sh b/testsuite/gna/issue2580/testsuite.sh
index e98c397f20..790394857f 100755
--- a/testsuite/gna/issue2580/testsuite.sh
+++ b/testsuite/gna/issue2580/testsuite.sh
@@ -10,6 +10,11 @@ elab_simulate test1
 analyze test2.vhdl
 elab_simulate test2
 
+if ghdl_is_preelaboration; then
+    analyze streamtb.vhdl
+    elab_simulate streamtb
+fi
+
 clean
 
 echo "Test successful"