diff --git a/src/simul/simul-vhdl_compile.adb b/src/simul/simul-vhdl_compile.adb index c8aeb85f8d..eff096bd52 100644 --- a/src/simul/simul-vhdl_compile.adb +++ b/src/simul/simul-vhdl_compile.adb @@ -2106,6 +2106,19 @@ package body Simul.Vhdl_Compile is Lunit : constant Node := Elab_Units.Table (I); begin case Iir_Kinds_Library_Unit (Get_Kind (Lunit)) is + when Iir_Kind_Entity_Declaration => + -- Translate a macro-expanded entity which has been + -- instantiated through a component. + declare + Parent : constant Node := Get_Parent (Lunit); + begin + if Get_Kind (Parent) + = Iir_Kind_Component_Instantiation_Statement + and then Is_Component_Instantiation (Parent) + then + Translation.Translate (Lunit, True); + end if; + end; when Iir_Kind_Architecture_Body => Translation.Translate (Lunit, True); when others => diff --git a/src/synth/elab-vhdl_annotations.adb b/src/synth/elab-vhdl_annotations.adb index 0f0b7e63d2..03426d8761 100644 --- a/src/synth/elab-vhdl_annotations.adb +++ b/src/synth/elab-vhdl_annotations.adb @@ -1008,6 +1008,7 @@ package body Elab.Vhdl_Annotations is procedure Annotate_Component_Instantiation_Statement (Block_Info : Sim_Info_Acc; Stmt : Iir) is + Hdr : constant Iir := Get_Instantiated_Header (Stmt); Info: Sim_Info_Acc; begin -- Add a slot just to put the instance. @@ -1018,6 +1019,12 @@ package body Elab.Vhdl_Annotations is Slot => Block_Info.Nbr_Objects, Nbr_Objects => 0); Set_Ann (Stmt, Info); + + if Hdr /= Null_Iir + and then Get_Kind (Hdr) = Iir_Kind_Component_Declaration + then + Instantiate_Annotate (Hdr); + end if; end Annotate_Component_Instantiation_Statement; procedure Annotate_Process_Statement (Block_Info : Sim_Info_Acc; Stmt : Iir) diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index 12566ebffa..ef0b7acf70 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -1080,18 +1080,26 @@ package body Elab.Vhdl_Insts is Stmt : Node; Cfgs : in out Configs_Rec) is - Component : constant Node := - Get_Named_Entity (Get_Instantiated_Unit (Stmt)); + Component : Node; Config : Node; Bind : Node; Aspect : Iir; Comp_Inst : Synth_Instance_Acc; - Ent : Node; - Arch : Node; + Ent, E_Ent : Node; + Arch, E_Arch : Node; Sub_Config : Node; Sub_Inst : Synth_Instance_Acc; begin + -- Get the component (either the macro-expanded one, or the original + -- one). + Component := Get_Instantiated_Header (Stmt); + if Component = Null_Node then + -- Always use the original component. The macro-expanded one is + -- not annotated (and has no parent). + Component := Get_Named_Entity (Get_Instantiated_Unit (Stmt)); + end if; + Get_Next_Component_Configuration (Cfgs, Config); Bind := Get_Binding_Indication (Config); @@ -1165,18 +1173,33 @@ package body Elab.Vhdl_Insts is Elab_Dependencies (Root_Instance, Get_Design_Unit (Ent)); Elab_Dependencies (Root_Instance, Get_Design_Unit (Arch)); - Add_To_Elab_Units (Ent); + if Flag_Macro_Expand_Instance + and then Get_Macro_Expand_Flag (Ent) + then + E_Ent := Vhdl.Sem_Inst.Instantiate_Entity_Declaration (Ent, Bind); + E_Arch := Vhdl.Sem_Inst.Instantiate_Architecture + (Arch, E_Ent, Stmt, Bind); + Elab.Vhdl_Annotations.Instantiate_Annotate (E_Ent); + Elab.Vhdl_Annotations.Instantiate_Annotate (E_Arch); + + Set_Parent (E_Ent, Stmt); + else + E_Ent := Ent; + E_Arch := Arch; + end if; + + Add_To_Elab_Units (E_Ent); -- Elaborate generic + map aspect for the entity instance. - Sub_Inst := Make_Elab_Instance (Comp_Inst, Stmt, Arch, Sub_Config); + Sub_Inst := Make_Elab_Instance (Comp_Inst, Stmt, E_Arch, Sub_Config); Create_Component_Instance (Comp_Inst, Sub_Inst); Elab_Generics_Association (Sub_Inst, Comp_Inst, - Get_Generic_Chain (Ent), + Get_Generic_Chain (E_Ent), Get_Generic_Map_Aspect_Chain (Bind)); Elab_Ports_Association_Type (Sub_Inst, Comp_Inst, - Get_Port_Chain (Ent), + Get_Port_Chain (E_Ent), Get_Port_Map_Aspect_Chain (Bind)); pragma Assert (Is_Expr_Pool_Empty); @@ -1184,7 +1207,7 @@ package body Elab.Vhdl_Insts is Elab_Instance_Body (Sub_Inst); end if; - Add_To_Elab_Units (Arch); + Add_To_Elab_Units (E_Arch); end Elab_Component_Instantiation_Statement; procedure Elab_Design_Instantiation_Statement diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb index 2d963badce..95fecb7f78 100644 --- a/src/vhdl/vhdl-sem_specs.adb +++ b/src/vhdl/vhdl-sem_specs.adb @@ -2079,6 +2079,11 @@ package body Vhdl.Sem_Specs is Set_Actual (Assoc, Name); Found := Found + 1; end if; + if Assoc_Kind = Iir_Kind_Association_Element_Type then + Set_Actual_Type (Assoc, + Get_Associated_Type + (Get_Interface_Type_Definition (Comp_El))); + end if; -- Create the formal name. This is a forward reference as the -- current design unit does not depend on the entity. diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb index e31404d68c..7900cb184b 100644 --- a/src/vhdl/vhdl-sem_stmts.adb +++ b/src/vhdl/vhdl-sem_stmts.adb @@ -2225,6 +2225,7 @@ package body Vhdl.Sem_Stmts is is Decl : Iir; Decl_Inst : Iir; + Hdr : Iir; Entity_Unit : Iir_Design_Unit; Bind : Iir_Binding_Indication; begin @@ -2281,8 +2282,15 @@ package body Vhdl.Sem_Stmts is and then (Flags.Flag_Elaborate_With_Outdated or else Get_Date (Entity_Unit) in Date_Valid) then + -- If the component is macro-expanded, use the macro-expanded + -- component. + Hdr := Get_Instantiated_Header (Stmt); + if Hdr = Null_Iir then + Hdr := Decl; + end if; + Bind := Sem_Create_Default_Binding_Indication - (Decl, Entity_Unit, Stmt, False, True); + (Hdr, Entity_Unit, Stmt, False, True); Set_Default_Binding_Indication (Stmt, Bind); end if; end if;