From 2567addf69b08d2455fe8a691f1b38cf7ed32b48 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 12 Jan 2024 19:19:07 +0100
Subject: [PATCH] testsuite/gna: add a test for #2584

Close #2584
---
 testsuite/gna/issue2584/streamtb.vhdl | 61 +++++++++++++++++++++++++++
 testsuite/gna/issue2584/testsuite.sh  | 14 ++++++
 2 files changed, 75 insertions(+)
 create mode 100644 testsuite/gna/issue2584/streamtb.vhdl
 create mode 100755 testsuite/gna/issue2584/testsuite.sh

diff --git a/testsuite/gna/issue2584/streamtb.vhdl b/testsuite/gna/issue2584/streamtb.vhdl
new file mode 100644
index 0000000000..642b296c4c
--- /dev/null
+++ b/testsuite/gna/issue2584/streamtb.vhdl
@@ -0,0 +1,61 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity StreamRegSlice is
+   generic (
+      type DAT
+   );
+   port (
+      rxcDat_i : in  DAT;
+      txcDat_o : out DAT
+   );
+end StreamRegSlice;
+
+architecture rtl of StreamRegSlice is
+begin
+   txcDat_o <= rxcDat_i;
+end rtl;
+
+
+use std.env.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity StreamTb is
+   generic (
+      WIDTH : positive := 8
+   );
+end StreamTb;
+
+architecture behavior of StreamTb is
+   subtype DAT is std_logic_vector(WIDTH-1 downto 0);
+   signal txcDat : DAT;
+   signal rxcDat : DAT;
+begin
+
+   -- DUT instance
+   dut : entity work.StreamRegSlice
+   generic map (
+      DAT => DAT
+   )
+   port map (
+      rxcDat_i => txcDat,
+      txcDat_o => rxcDat
+   );
+--   rxcDat <= txcDat;
+
+   p_test : process
+   begin
+      -- end simulation
+      for i in 0 to 8-1 loop
+         txcDat <= std_logic_vector(to_unsigned(i, WIDTH));
+         wait for 10 ns;
+      end loop;
+      report "Simulation end";
+      finish;
+   end process p_test;
+
+end behavior;
+
diff --git a/testsuite/gna/issue2584/testsuite.sh b/testsuite/gna/issue2584/testsuite.sh
new file mode 100755
index 0000000000..963768342f
--- /dev/null
+++ b/testsuite/gna/issue2584/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+if ghdl_is_preelaboration; then
+    analyze streamtb.vhdl
+    elab_simulate streamtb
+    clean
+fi
+
+
+echo "Test successful"