From 1bf3814604715d17d7706d6eb9acdfae9e93f91c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 14 Feb 2024 19:36:53 +0100
Subject: [PATCH] testsuite/synth: add more sources for verilog generate

---
 testsuite/synth/generate01/gen1.v | 14 ++++++++++++++
 testsuite/synth/generate01/gen2.v | 12 ++++++++++++
 testsuite/synth/generate01/gen3.v | 12 ++++++++++++
 testsuite/synth/generate01/gen4.v | 19 +++++++++++++++++++
 4 files changed, 57 insertions(+)
 create mode 100644 testsuite/synth/generate01/gen1.v
 create mode 100644 testsuite/synth/generate01/gen2.v
 create mode 100644 testsuite/synth/generate01/gen3.v
 create mode 100644 testsuite/synth/generate01/gen4.v

diff --git a/testsuite/synth/generate01/gen1.v b/testsuite/synth/generate01/gen1.v
new file mode 100644
index 0000000000..8542042d83
--- /dev/null
+++ b/testsuite/synth/generate01/gen1.v
@@ -0,0 +1,14 @@
+module oa8(input [7:0] a,
+	   input [7:0]	b,
+	   input [7:0]	c,
+	   output [7:0]	o);
+
+   genvar i;
+
+   generate
+      for (i = 0; i < 8; i=i+1) begin
+	 wire t = a[i] | b[i];
+	 assign o[i] = t & c[i];
+      end
+   endgenerate
+endmodule
diff --git a/testsuite/synth/generate01/gen2.v b/testsuite/synth/generate01/gen2.v
new file mode 100644
index 0000000000..b41cd08727
--- /dev/null
+++ b/testsuite/synth/generate01/gen2.v
@@ -0,0 +1,12 @@
+module oa8(input [7:0] a,
+	   input [7:0]	b,
+	   input [7:0]	c,
+	   output [7:0]	o);
+
+   genvar i;
+
+   for (i = 0; i < 8; i=i+1) begin
+      wire t = a[i] | b[i];
+      assign o[i] = t & c[i];
+   end
+endmodule
diff --git a/testsuite/synth/generate01/gen3.v b/testsuite/synth/generate01/gen3.v
new file mode 100644
index 0000000000..606f63b716
--- /dev/null
+++ b/testsuite/synth/generate01/gen3.v
@@ -0,0 +1,12 @@
+module oa8(input [7:0] a,
+	   input [7:0]	b,
+	   input [7:0]	c,
+	   output [7:0]	o);
+
+   genvar i;
+
+   for (i = 0; i < 8; i=i+1) begin
+      or a_or_b(t, a[i], b[i]);
+      assign o[i] = t & c[i];
+   end
+endmodule
diff --git a/testsuite/synth/generate01/gen4.v b/testsuite/synth/generate01/gen4.v
new file mode 100644
index 0000000000..9a36681a13
--- /dev/null
+++ b/testsuite/synth/generate01/gen4.v
@@ -0,0 +1,19 @@
+module oa1(input a,
+	   input b,
+	   input c,
+	   output o);
+
+   assign o = (a | b) & c;
+endmodule
+
+module oa8(input [7:0] a,
+	   input [7:0]	b,
+	   input [7:0]	c,
+	   output [7:0]	o);
+
+   genvar i;
+
+   for (i = 0; i < 8; i=i+1) begin
+      oa1 gate(a[i], b[i], c[i], o[i]);
+   end
+endmodule