diff --git a/testsuite/gna/issue2458/test3.vhdl b/testsuite/gna/issue2458/test3.vhdl new file mode 100644 index 0000000000..8e860076b1 --- /dev/null +++ b/testsuite/gna/issue2458/test3.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity e3 is + generic (type data_type); +end entity; + +architecture e of e3 is + signal s : data_type; +begin +end architecture; + +library ieee; +use ieee.std_logic_1164.all; + +entity test3 is +end entity; + +architecture test of test3 is +component e3 is + generic (type data_type); +end component; +begin + inst : e3 generic map(data_type => std_logic); +end architecture; diff --git a/testsuite/gna/issue2458/testsuite.sh b/testsuite/gna/issue2458/testsuite.sh index 43be2c4e9d..efaa56be9a 100755 --- a/testsuite/gna/issue2458/testsuite.sh +++ b/testsuite/gna/issue2458/testsuite.sh @@ -7,6 +7,9 @@ if ghdl_is_preelaboration; then analyze test2.vhdl elab_simulate test2 + analyze test3.vhdl + elab_simulate test3 + clean fi