diff --git a/testfiles/tb/golden_files/buserr_apb.vhdl b/testfiles/tb/golden_files/buserr_apb.vhdl index 49f4063e..d48b8e9e 100644 --- a/testfiles/tb/golden_files/buserr_apb.vhdl +++ b/testfiles/tb/golden_files/buserr_apb.vhdl @@ -6,7 +6,7 @@ entity buserr_apb is port ( pclk : in std_logic; presetn : in std_logic; - paddr : in std_logic_vector(3 downto 2); + paddr : in std_logic_vector(4 downto 2); psel : in std_logic; pwrite : in std_logic; penable : in std_logic; @@ -16,42 +16,53 @@ entity buserr_apb is prdata : out std_logic_vector(31 downto 0); pslverr : out std_logic; - -- REG reg1 - reg1_o : out std_logic_vector(31 downto 0); + -- REG rw0 + rw0_o : out std_logic_vector(31 downto 0); - -- REG reg2 - reg2_o : out std_logic_vector(31 downto 0); + -- REG rw1 + rw1_o : out std_logic_vector(31 downto 0); - -- REG reg3 - reg3_o : out std_logic_vector(31 downto 0) + -- REG rw2 + rw2_o : out std_logic_vector(31 downto 0); + + -- REG ro0 + ro0_i : in std_logic_vector(31 downto 0); + + -- REG wo0 + wo0_o : out std_logic_vector(31 downto 0) ); end buserr_apb; architecture syn of buserr_apb is signal wr_req : std_logic; - signal wr_addr : std_logic_vector(3 downto 2); + signal wr_addr : std_logic_vector(4 downto 2); signal wr_data : std_logic_vector(31 downto 0); + signal wr_req_del : std_logic; signal rd_req : std_logic; - signal rd_addr : std_logic_vector(3 downto 2); + signal rd_addr : std_logic_vector(4 downto 2); signal rd_data : std_logic_vector(31 downto 0); signal wr_err : std_logic; signal wr_ack : std_logic; signal rd_ack : std_logic; signal rd_err : std_logic; - signal reg1_reg : std_logic_vector(31 downto 0); - signal reg1_wreq : std_logic; - signal reg1_wack : std_logic; - signal reg2_reg : std_logic_vector(31 downto 0); - signal reg2_wreq : std_logic; - signal reg2_wack : std_logic; - signal reg3_reg : std_logic_vector(31 downto 0); - signal reg3_wreq : std_logic; - signal reg3_wack : std_logic; + signal rw0_reg : std_logic_vector(31 downto 0); + signal rw0_wreq : std_logic; + signal rw0_wack : std_logic; + signal rw1_reg : std_logic_vector(31 downto 0); + signal rw1_wreq : std_logic; + signal rw1_wack : std_logic; + signal rw2_reg : std_logic_vector(31 downto 0); + signal rw2_wreq : std_logic; + signal rw2_wack : std_logic; + signal wo0_reg : std_logic_vector(31 downto 0); + signal wo0_wreq : std_logic; + signal wo0_wack : std_logic; signal rd_ack_d0 : std_logic; signal rd_err_d0 : std_logic; signal rd_dat_d0 : std_logic_vector(31 downto 0); signal wr_req_d0 : std_logic; - signal wr_adr_d0 : std_logic_vector(3 downto 2); + signal wr_req_del_d0 : std_logic; + signal wr_adr_d0 : std_logic_vector(4 downto 2); signal wr_dat_d0 : std_logic_vector(31 downto 0); begin @@ -59,6 +70,15 @@ begin wr_req <= (psel and pwrite) and not penable; wr_addr <= paddr; wr_data <= pwdata; + process (pclk) begin + if rising_edge(pclk) then + if presetn = '0' then + wr_req_del <= '0'; + else + wr_req_del <= wr_req; + end if; + end if; + end process; -- Read Channel rd_req <= (psel and not pwrite) and not penable; @@ -74,112 +94,151 @@ begin rd_ack <= '0'; rd_err <= '0'; wr_req_d0 <= '0'; + wr_req_del_d0 <= '0'; else rd_ack <= rd_ack_d0; rd_err <= rd_err_d0; rd_data <= rd_dat_d0; wr_req_d0 <= wr_req; + wr_req_del_d0 <= wr_req_del; wr_adr_d0 <= wr_addr; wr_dat_d0 <= wr_data; end if; end if; end process; - -- Register reg1 - reg1_o <= reg1_reg; + -- Register rw0 + rw0_o <= rw0_reg; + process (pclk) begin + if rising_edge(pclk) then + if presetn = '0' then + rw0_reg <= "00010010001101000101011001111000"; + rw0_wack <= '0'; + else + if rw0_wreq = '1' then + rw0_reg <= wr_dat_d0; + end if; + rw0_wack <= rw0_wreq; + end if; + end if; + end process; + + -- Register rw1 + rw1_o <= rw1_reg; process (pclk) begin if rising_edge(pclk) then if presetn = '0' then - reg1_reg <= "00010010001101000101011001111000"; - reg1_wack <= '0'; + rw1_reg <= "00100011010001010110011110001001"; + rw1_wack <= '0'; else - if reg1_wreq = '1' then - reg1_reg <= wr_dat_d0; + if rw1_wreq = '1' then + rw1_reg <= wr_dat_d0; end if; - reg1_wack <= reg1_wreq; + rw1_wack <= rw1_wreq; end if; end if; end process; - -- Register reg2 - reg2_o <= reg2_reg; + -- Register rw2 + rw2_o <= rw2_reg; process (pclk) begin if rising_edge(pclk) then if presetn = '0' then - reg2_reg <= "00010010001101000101011001111000"; - reg2_wack <= '0'; + rw2_reg <= "00110100010101100111100010011010"; + rw2_wack <= '0'; else - if reg2_wreq = '1' then - reg2_reg <= wr_dat_d0; + if rw2_wreq = '1' then + rw2_reg <= wr_dat_d0; end if; - reg2_wack <= reg2_wreq; + rw2_wack <= rw2_wreq; end if; end if; end process; - -- Register reg3 - reg3_o <= reg3_reg; + -- Register ro0 + + -- Register wo0 + wo0_o <= wo0_reg; process (pclk) begin if rising_edge(pclk) then if presetn = '0' then - reg3_reg <= "00010010001101000101011001111000"; - reg3_wack <= '0'; + wo0_reg <= "01010110011110001001101010111100"; + wo0_wack <= '0'; else - if reg3_wreq = '1' then - reg3_reg <= wr_dat_d0; + if wo0_wreq = '1' then + wo0_reg <= wr_dat_d0; end if; - reg3_wack <= reg3_wreq; + wo0_wack <= wo0_wreq; end if; end if; end process; -- Process for write requests. - process (wr_adr_d0, wr_req_d0, reg1_wack, reg2_wack, reg3_wack) begin - reg1_wreq <= '0'; - reg2_wreq <= '0'; - reg3_wreq <= '0'; - case wr_adr_d0(3 downto 2) is - when "00" => - -- Reg reg1 - reg1_wreq <= wr_req_d0; - wr_ack <= reg1_wack; + process (wr_adr_d0, wr_req_d0, rw0_wack, rw1_wack, rw2_wack, wr_req_del_d0, wo0_wack) begin + rw0_wreq <= '0'; + rw1_wreq <= '0'; + rw2_wreq <= '0'; + wo0_wreq <= '0'; + case wr_adr_d0(4 downto 2) is + when "000" => + -- Reg rw0 + rw0_wreq <= wr_req_d0; + wr_ack <= rw0_wack; + wr_err <= '0'; + when "001" => + -- Reg rw1 + rw1_wreq <= wr_req_d0; + wr_ack <= rw1_wack; wr_err <= '0'; - when "01" => - -- Reg reg2 - reg2_wreq <= wr_req_d0; - wr_ack <= reg2_wack; + when "010" => + -- Reg rw2 + rw2_wreq <= wr_req_d0; + wr_ack <= rw2_wack; wr_err <= '0'; - when "10" => - -- Reg reg3 - reg3_wreq <= wr_req_d0; - wr_ack <= reg3_wack; + when "011" => + -- Reg ro0 + wr_ack <= wr_req_del_d0; + wr_err <= wr_req_del_d0; + when "100" => + -- Reg wo0 + wo0_wreq <= wr_req_d0; + wr_ack <= wo0_wack; wr_err <= '0'; when others => - wr_ack <= wr_req_d0; - wr_err <= wr_req_d0; + wr_ack <= wr_req_del_d0; + wr_err <= wr_req_del_d0; end case; end process; -- Process for read requests. - process (rd_addr, rd_req, reg1_reg, reg2_reg, reg3_reg) begin + process (rd_addr, rd_req, rw0_reg, rw1_reg, rw2_reg, ro0_i) begin -- By default ack read requests rd_dat_d0 <= (others => 'X'); - case rd_addr(3 downto 2) is - when "00" => - -- Reg reg1 + case rd_addr(4 downto 2) is + when "000" => + -- Reg rw0 + rd_ack_d0 <= rd_req; + rd_err_d0 <= '0'; + rd_dat_d0 <= rw0_reg; + when "001" => + -- Reg rw1 rd_ack_d0 <= rd_req; rd_err_d0 <= '0'; - rd_dat_d0 <= reg1_reg; - when "01" => - -- Reg reg2 + rd_dat_d0 <= rw1_reg; + when "010" => + -- Reg rw2 rd_ack_d0 <= rd_req; rd_err_d0 <= '0'; - rd_dat_d0 <= reg2_reg; - when "10" => - -- Reg reg3 + rd_dat_d0 <= rw2_reg; + when "011" => + -- Reg ro0 rd_ack_d0 <= rd_req; rd_err_d0 <= '0'; - rd_dat_d0 <= reg3_reg; + rd_dat_d0 <= ro0_i; + when "100" => + -- Reg wo0 + rd_ack_d0 <= rd_req; + rd_err_d0 <= rd_req; when others => rd_ack_d0 <= rd_req; rd_err_d0 <= rd_req; diff --git a/testfiles/tb/golden_files/buserr_axi4.vhdl b/testfiles/tb/golden_files/buserr_axi4.vhdl index 455214ed..1b04d111 100644 --- a/testfiles/tb/golden_files/buserr_axi4.vhdl +++ b/testfiles/tb/golden_files/buserr_axi4.vhdl @@ -8,7 +8,7 @@ entity buserr_axi4 is areset_n : in std_logic; awvalid : in std_logic; awready : out std_logic; - awaddr : in std_logic_vector(3 downto 2); + awaddr : in std_logic_vector(4 downto 2); awprot : in std_logic_vector(2 downto 0); wvalid : in std_logic; wready : out std_logic; @@ -19,21 +19,27 @@ entity buserr_axi4 is bresp : out std_logic_vector(1 downto 0); arvalid : in std_logic; arready : out std_logic; - araddr : in std_logic_vector(3 downto 2); + araddr : in std_logic_vector(4 downto 2); arprot : in std_logic_vector(2 downto 0); rvalid : out std_logic; rready : in std_logic; rdata : out std_logic_vector(31 downto 0); rresp : out std_logic_vector(1 downto 0); - -- REG reg1 - reg1_o : out std_logic_vector(31 downto 0); + -- REG rw0 + rw0_o : out std_logic_vector(31 downto 0); - -- REG reg2 - reg2_o : out std_logic_vector(31 downto 0); + -- REG rw1 + rw1_o : out std_logic_vector(31 downto 0); - -- REG reg3 - reg3_o : out std_logic_vector(31 downto 0) + -- REG rw2 + rw2_o : out std_logic_vector(31 downto 0); + + -- REG ro0 + ro0_i : in std_logic_vector(31 downto 0); + + -- REG wo0 + wo0_o : out std_logic_vector(31 downto 0) ); end buserr_axi4; @@ -41,7 +47,7 @@ architecture syn of buserr_axi4 is signal wr_req : std_logic; signal wr_ack : std_logic; signal wr_err : std_logic; - signal wr_addr : std_logic_vector(3 downto 2); + signal wr_addr : std_logic_vector(4 downto 2); signal wr_data : std_logic_vector(31 downto 0); signal axi_awset : std_logic; signal axi_wset : std_logic; @@ -50,25 +56,28 @@ architecture syn of buserr_axi4 is signal rd_req : std_logic; signal rd_ack : std_logic; signal rd_err : std_logic; - signal rd_addr : std_logic_vector(3 downto 2); + signal rd_addr : std_logic_vector(4 downto 2); signal rd_data : std_logic_vector(31 downto 0); signal axi_arset : std_logic; signal axi_rdone : std_logic; signal axi_rerr : std_logic_vector(1 downto 0); - signal reg1_reg : std_logic_vector(31 downto 0); - signal reg1_wreq : std_logic; - signal reg1_wack : std_logic; - signal reg2_reg : std_logic_vector(31 downto 0); - signal reg2_wreq : std_logic; - signal reg2_wack : std_logic; - signal reg3_reg : std_logic_vector(31 downto 0); - signal reg3_wreq : std_logic; - signal reg3_wack : std_logic; + signal rw0_reg : std_logic_vector(31 downto 0); + signal rw0_wreq : std_logic; + signal rw0_wack : std_logic; + signal rw1_reg : std_logic_vector(31 downto 0); + signal rw1_wreq : std_logic; + signal rw1_wack : std_logic; + signal rw2_reg : std_logic_vector(31 downto 0); + signal rw2_wreq : std_logic; + signal rw2_wack : std_logic; + signal wo0_reg : std_logic_vector(31 downto 0); + signal wo0_wreq : std_logic; + signal wo0_wack : std_logic; signal rd_ack_d0 : std_logic; signal rd_err_d0 : std_logic; signal rd_dat_d0 : std_logic_vector(31 downto 0); signal wr_req_d0 : std_logic; - signal wr_adr_d0 : std_logic_vector(3 downto 2); + signal wr_adr_d0 : std_logic_vector(4 downto 2); signal wr_dat_d0 : std_logic_vector(31 downto 0); begin @@ -172,74 +181,102 @@ begin end if; end process; - -- Register reg1 - reg1_o <= reg1_reg; + -- Register rw0 + rw0_o <= rw0_reg; process (aclk) begin if rising_edge(aclk) then if areset_n = '0' then - reg1_reg <= "00010010001101000101011001111000"; - reg1_wack <= '0'; + rw0_reg <= "00010010001101000101011001111000"; + rw0_wack <= '0'; else - if reg1_wreq = '1' then - reg1_reg <= wr_dat_d0; + if rw0_wreq = '1' then + rw0_reg <= wr_dat_d0; end if; - reg1_wack <= reg1_wreq; + rw0_wack <= rw0_wreq; end if; end if; end process; - -- Register reg2 - reg2_o <= reg2_reg; + -- Register rw1 + rw1_o <= rw1_reg; process (aclk) begin if rising_edge(aclk) then if areset_n = '0' then - reg2_reg <= "00010010001101000101011001111000"; - reg2_wack <= '0'; + rw1_reg <= "00100011010001010110011110001001"; + rw1_wack <= '0'; else - if reg2_wreq = '1' then - reg2_reg <= wr_dat_d0; + if rw1_wreq = '1' then + rw1_reg <= wr_dat_d0; end if; - reg2_wack <= reg2_wreq; + rw1_wack <= rw1_wreq; end if; end if; end process; - -- Register reg3 - reg3_o <= reg3_reg; + -- Register rw2 + rw2_o <= rw2_reg; process (aclk) begin if rising_edge(aclk) then if areset_n = '0' then - reg3_reg <= "00010010001101000101011001111000"; - reg3_wack <= '0'; + rw2_reg <= "00110100010101100111100010011010"; + rw2_wack <= '0'; else - if reg3_wreq = '1' then - reg3_reg <= wr_dat_d0; + if rw2_wreq = '1' then + rw2_reg <= wr_dat_d0; end if; - reg3_wack <= reg3_wreq; + rw2_wack <= rw2_wreq; + end if; + end if; + end process; + + -- Register ro0 + + -- Register wo0 + wo0_o <= wo0_reg; + process (aclk) begin + if rising_edge(aclk) then + if areset_n = '0' then + wo0_reg <= "01010110011110001001101010111100"; + wo0_wack <= '0'; + else + if wo0_wreq = '1' then + wo0_reg <= wr_dat_d0; + end if; + wo0_wack <= wo0_wreq; end if; end if; end process; -- Process for write requests. - process (wr_adr_d0, wr_req_d0, reg1_wack, reg2_wack, reg3_wack) begin - reg1_wreq <= '0'; - reg2_wreq <= '0'; - reg3_wreq <= '0'; - case wr_adr_d0(3 downto 2) is - when "00" => - -- Reg reg1 - reg1_wreq <= wr_req_d0; - wr_ack <= reg1_wack; + process (wr_adr_d0, wr_req_d0, rw0_wack, rw1_wack, rw2_wack, wo0_wack) begin + rw0_wreq <= '0'; + rw1_wreq <= '0'; + rw2_wreq <= '0'; + wo0_wreq <= '0'; + case wr_adr_d0(4 downto 2) is + when "000" => + -- Reg rw0 + rw0_wreq <= wr_req_d0; + wr_ack <= rw0_wack; + wr_err <= '0'; + when "001" => + -- Reg rw1 + rw1_wreq <= wr_req_d0; + wr_ack <= rw1_wack; wr_err <= '0'; - when "01" => - -- Reg reg2 - reg2_wreq <= wr_req_d0; - wr_ack <= reg2_wack; + when "010" => + -- Reg rw2 + rw2_wreq <= wr_req_d0; + wr_ack <= rw2_wack; wr_err <= '0'; - when "10" => - -- Reg reg3 - reg3_wreq <= wr_req_d0; - wr_ack <= reg3_wack; + when "011" => + -- Reg ro0 + wr_ack <= wr_req_d0; + wr_err <= wr_req_d0; + when "100" => + -- Reg wo0 + wo0_wreq <= wr_req_d0; + wr_ack <= wo0_wack; wr_err <= '0'; when others => wr_ack <= wr_req_d0; @@ -248,25 +285,34 @@ begin end process; -- Process for read requests. - process (rd_addr, rd_req, reg1_reg, reg2_reg, reg3_reg) begin + process (rd_addr, rd_req, rw0_reg, rw1_reg, rw2_reg, ro0_i) begin -- By default ack read requests rd_dat_d0 <= (others => 'X'); - case rd_addr(3 downto 2) is - when "00" => - -- Reg reg1 + case rd_addr(4 downto 2) is + when "000" => + -- Reg rw0 rd_ack_d0 <= rd_req; rd_err_d0 <= '0'; - rd_dat_d0 <= reg1_reg; - when "01" => - -- Reg reg2 + rd_dat_d0 <= rw0_reg; + when "001" => + -- Reg rw1 rd_ack_d0 <= rd_req; rd_err_d0 <= '0'; - rd_dat_d0 <= reg2_reg; - when "10" => - -- Reg reg3 + rd_dat_d0 <= rw1_reg; + when "010" => + -- Reg rw2 rd_ack_d0 <= rd_req; rd_err_d0 <= '0'; - rd_dat_d0 <= reg3_reg; + rd_dat_d0 <= rw2_reg; + when "011" => + -- Reg ro0 + rd_ack_d0 <= rd_req; + rd_err_d0 <= '0'; + rd_dat_d0 <= ro0_i; + when "100" => + -- Reg wo0 + rd_ack_d0 <= rd_req; + rd_err_d0 <= rd_req; when others => rd_ack_d0 <= rd_req; rd_err_d0 <= rd_req; diff --git a/testfiles/tb/golden_files/buserr_wb.vhdl b/testfiles/tb/golden_files/buserr_wb.vhdl index 9e0d93ae..b9b53214 100644 --- a/testfiles/tb/golden_files/buserr_wb.vhdl +++ b/testfiles/tb/golden_files/buserr_wb.vhdl @@ -8,7 +8,7 @@ entity buserr_wb is clk_i : in std_logic; wb_cyc_i : in std_logic; wb_stb_i : in std_logic; - wb_adr_i : in std_logic_vector(3 downto 2); + wb_adr_i : in std_logic_vector(4 downto 2); wb_sel_i : in std_logic_vector(3 downto 0); wb_we_i : in std_logic; wb_dat_i : in std_logic_vector(31 downto 0); @@ -18,14 +18,20 @@ entity buserr_wb is wb_stall_o : out std_logic; wb_dat_o : out std_logic_vector(31 downto 0); - -- REG reg1 - reg1_o : out std_logic_vector(31 downto 0); + -- REG rw0 + rw0_o : out std_logic_vector(31 downto 0); - -- REG reg2 - reg2_o : out std_logic_vector(31 downto 0); + -- REG rw1 + rw1_o : out std_logic_vector(31 downto 0); - -- REG reg3 - reg3_o : out std_logic_vector(31 downto 0) + -- REG rw2 + rw2_o : out std_logic_vector(31 downto 0); + + -- REG ro0 + ro0_i : in std_logic_vector(31 downto 0); + + -- REG wo0 + wo0_o : out std_logic_vector(31 downto 0) ); end buserr_wb; @@ -41,20 +47,23 @@ architecture syn of buserr_wb is signal err_int : std_logic; signal wb_rip : std_logic; signal wb_wip : std_logic; - signal reg1_reg : std_logic_vector(31 downto 0); - signal reg1_wreq : std_logic; - signal reg1_wack : std_logic; - signal reg2_reg : std_logic_vector(31 downto 0); - signal reg2_wreq : std_logic; - signal reg2_wack : std_logic; - signal reg3_reg : std_logic_vector(31 downto 0); - signal reg3_wreq : std_logic; - signal reg3_wack : std_logic; + signal rw0_reg : std_logic_vector(31 downto 0); + signal rw0_wreq : std_logic; + signal rw0_wack : std_logic; + signal rw1_reg : std_logic_vector(31 downto 0); + signal rw1_wreq : std_logic; + signal rw1_wack : std_logic; + signal rw2_reg : std_logic_vector(31 downto 0); + signal rw2_wreq : std_logic; + signal rw2_wack : std_logic; + signal wo0_reg : std_logic_vector(31 downto 0); + signal wo0_wreq : std_logic; + signal wo0_wack : std_logic; signal rd_ack_d0 : std_logic; signal rd_err_d0 : std_logic; signal rd_dat_d0 : std_logic_vector(31 downto 0); signal wr_req_d0 : std_logic; - signal wr_adr_d0 : std_logic_vector(3 downto 2); + signal wr_adr_d0 : std_logic_vector(4 downto 2); signal wr_dat_d0 : std_logic_vector(31 downto 0); begin @@ -115,74 +124,102 @@ begin end if; end process; - -- Register reg1 - reg1_o <= reg1_reg; + -- Register rw0 + rw0_o <= rw0_reg; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - reg1_reg <= "00010010001101000101011001111000"; - reg1_wack <= '0'; + rw0_reg <= "00010010001101000101011001111000"; + rw0_wack <= '0'; else - if reg1_wreq = '1' then - reg1_reg <= wr_dat_d0; + if rw0_wreq = '1' then + rw0_reg <= wr_dat_d0; end if; - reg1_wack <= reg1_wreq; + rw0_wack <= rw0_wreq; end if; end if; end process; - -- Register reg2 - reg2_o <= reg2_reg; + -- Register rw1 + rw1_o <= rw1_reg; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - reg2_reg <= "00010010001101000101011001111000"; - reg2_wack <= '0'; + rw1_reg <= "00100011010001010110011110001001"; + rw1_wack <= '0'; else - if reg2_wreq = '1' then - reg2_reg <= wr_dat_d0; + if rw1_wreq = '1' then + rw1_reg <= wr_dat_d0; end if; - reg2_wack <= reg2_wreq; + rw1_wack <= rw1_wreq; end if; end if; end process; - -- Register reg3 - reg3_o <= reg3_reg; + -- Register rw2 + rw2_o <= rw2_reg; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - reg3_reg <= "00010010001101000101011001111000"; - reg3_wack <= '0'; + rw2_reg <= "00110100010101100111100010011010"; + rw2_wack <= '0'; else - if reg3_wreq = '1' then - reg3_reg <= wr_dat_d0; + if rw2_wreq = '1' then + rw2_reg <= wr_dat_d0; end if; - reg3_wack <= reg3_wreq; + rw2_wack <= rw2_wreq; + end if; + end if; + end process; + + -- Register ro0 + + -- Register wo0 + wo0_o <= wo0_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wo0_reg <= "01010110011110001001101010111100"; + wo0_wack <= '0'; + else + if wo0_wreq = '1' then + wo0_reg <= wr_dat_d0; + end if; + wo0_wack <= wo0_wreq; end if; end if; end process; -- Process for write requests. - process (wr_adr_d0, wr_req_d0, reg1_wack, reg2_wack, reg3_wack) begin - reg1_wreq <= '0'; - reg2_wreq <= '0'; - reg3_wreq <= '0'; - case wr_adr_d0(3 downto 2) is - when "00" => - -- Reg reg1 - reg1_wreq <= wr_req_d0; - wr_ack_int <= reg1_wack; + process (wr_adr_d0, wr_req_d0, rw0_wack, rw1_wack, rw2_wack, wo0_wack) begin + rw0_wreq <= '0'; + rw1_wreq <= '0'; + rw2_wreq <= '0'; + wo0_wreq <= '0'; + case wr_adr_d0(4 downto 2) is + when "000" => + -- Reg rw0 + rw0_wreq <= wr_req_d0; + wr_ack_int <= rw0_wack; + wr_err_int <= '0'; + when "001" => + -- Reg rw1 + rw1_wreq <= wr_req_d0; + wr_ack_int <= rw1_wack; wr_err_int <= '0'; - when "01" => - -- Reg reg2 - reg2_wreq <= wr_req_d0; - wr_ack_int <= reg2_wack; + when "010" => + -- Reg rw2 + rw2_wreq <= wr_req_d0; + wr_ack_int <= rw2_wack; wr_err_int <= '0'; - when "10" => - -- Reg reg3 - reg3_wreq <= wr_req_d0; - wr_ack_int <= reg3_wack; + when "011" => + -- Reg ro0 + wr_ack_int <= wr_req_d0; + wr_err_int <= wr_req_d0; + when "100" => + -- Reg wo0 + wo0_wreq <= wr_req_d0; + wr_ack_int <= wo0_wack; wr_err_int <= '0'; when others => wr_ack_int <= wr_req_d0; @@ -191,25 +228,34 @@ begin end process; -- Process for read requests. - process (wb_adr_i, rd_req_int, reg1_reg, reg2_reg, reg3_reg) begin + process (wb_adr_i, rd_req_int, rw0_reg, rw1_reg, rw2_reg, ro0_i) begin -- By default ack read requests rd_dat_d0 <= (others => 'X'); - case wb_adr_i(3 downto 2) is - when "00" => - -- Reg reg1 + case wb_adr_i(4 downto 2) is + when "000" => + -- Reg rw0 rd_ack_d0 <= rd_req_int; rd_err_d0 <= '0'; - rd_dat_d0 <= reg1_reg; - when "01" => - -- Reg reg2 + rd_dat_d0 <= rw0_reg; + when "001" => + -- Reg rw1 rd_ack_d0 <= rd_req_int; rd_err_d0 <= '0'; - rd_dat_d0 <= reg2_reg; - when "10" => - -- Reg reg3 + rd_dat_d0 <= rw1_reg; + when "010" => + -- Reg rw2 rd_ack_d0 <= rd_req_int; rd_err_d0 <= '0'; - rd_dat_d0 <= reg3_reg; + rd_dat_d0 <= rw2_reg; + when "011" => + -- Reg ro0 + rd_ack_d0 <= rd_req_int; + rd_err_d0 <= '0'; + rd_dat_d0 <= ro0_i; + when "100" => + -- Reg wo0 + rd_ack_d0 <= rd_req_int; + rd_err_d0 <= rd_req_int; when others => rd_ack_d0 <= rd_req_int; rd_err_d0 <= rd_req_int;