diff --git a/testfiles/bug-cernbe/repro.sv b/testfiles/bug-cernbe/repro.sv index 14bfd4f7..396af09a 100644 --- a/testfiles/bug-cernbe/repro.sv +++ b/testfiles/bug-cernbe/repro.sv @@ -36,7 +36,7 @@ module example reg [15:0] wr_dat_d0; reg sm_ws; reg sm_wt; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; @@ -84,7 +84,7 @@ module example if (!rst_n) sm_wt <= 1'b0; else - sm_wt <= (sm_wt | sm_ws) & !sm_VMEWrDone_i; + sm_wt <= (sm_wt | sm_ws) & ~sm_VMEWrDone_i; end assign sm_VMEWrMem_o = sm_ws; always @(VMEAddr, wr_adr_d0, sm_wt, sm_ws) diff --git a/testfiles/bug-cernbe/sub_repro.sv b/testfiles/bug-cernbe/sub_repro.sv index 7c3579f2..ca04dfa0 100644 --- a/testfiles/bug-cernbe/sub_repro.sv +++ b/testfiles/bug-cernbe/sub_repro.sv @@ -28,7 +28,7 @@ module sub_repro reg wr_req_d0; reg [1:1] wr_adr_d0; reg [15:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/bug-empty/noinp.sv b/testfiles/bug-empty/noinp.sv index bd877a71..7eb1edfd 100644 --- a/testfiles/bug-empty/noinp.sv +++ b/testfiles/bug-empty/noinp.sv @@ -54,22 +54,22 @@ module noinp if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/bug-empty/noout.sv b/testfiles/bug-empty/noout.sv index c94aa356..6dfa4300 100644 --- a/testfiles/bug-empty/noout.sv +++ b/testfiles/bug-empty/noout.sv @@ -1,8 +1,8 @@ interface t_noout_inter; logic [31:0] reg0; logic [31:0] reg1; - modport master(input reg0, reg1, ); - modport slave(output reg0, reg1, ); + modport master(input reg0, reg1); + modport slave(output reg0, reg1); endinterface @@ -47,22 +47,22 @@ module noout if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/bug-gen_wt/m1.sv b/testfiles/bug-gen_wt/m1.sv index 05e5f0f1..c6991814 100644 --- a/testfiles/bug-gen_wt/m1.sv +++ b/testfiles/bug-gen_wt/m1.sv @@ -34,7 +34,7 @@ module m1 reg [2:2] wr_adr_d0; reg [31:0] wr_dat_d0; reg sm2_ws; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/bug-memory/mem64ro.sv b/testfiles/bug-memory/mem64ro.sv index cf197b9c..8e94b8f9 100644 --- a/testfiles/bug-memory/mem64ro.sv +++ b/testfiles/bug-memory/mem64ro.sv @@ -50,8 +50,8 @@ module mem64ro reg [9:2] wr_adr_d0; reg [31:0] wr_dat_d0; reg [31:0] wr_sel_d0; - reg [3:0] DdrCapturesIndex_sel_int; - reg [3:0] DdrCapturesIndex_sel_int; + reg [3:0] DdrCapturesIndex_0_sel_int; + reg [3:0] DdrCapturesIndex_1_sel_int; // WB decode signals always @(wb_sel_i) @@ -68,22 +68,22 @@ module mem64ro if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -135,7 +135,7 @@ module mem64ro .clk_a_i(clk_i), .clk_b_i(clk_i), .addr_a_i(wb_adr_i[8:3]), - .bwsel_a_i(DdrCapturesIndex_sel_int), + .bwsel_a_i(DdrCapturesIndex_0_sel_int), .data_a_i({32{1'bx}}), .data_a_o(DdrCapturesIndex_DdrCaptures_int_dato0), .rd_a_i(DdrCapturesIndex_DdrCaptures_rreq0), @@ -150,15 +150,15 @@ module mem64ro always @(wr_sel_d0) begin - DdrCapturesIndex_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) - DdrCapturesIndex_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) - DdrCapturesIndex_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) - DdrCapturesIndex_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) - DdrCapturesIndex_sel_int[3] <= 1'b1; + DdrCapturesIndex_0_sel_int <= 4'b0; + if (~(wr_sel_d0[7:0] == 8'b0)) + DdrCapturesIndex_0_sel_int[0] <= 1'b1; + if (~(wr_sel_d0[15:8] == 8'b0)) + DdrCapturesIndex_0_sel_int[1] <= 1'b1; + if (~(wr_sel_d0[23:16] == 8'b0)) + DdrCapturesIndex_0_sel_int[2] <= 1'b1; + if (~(wr_sel_d0[31:24] == 8'b0)) + DdrCapturesIndex_0_sel_int[3] <= 1'b1; end cheby_dpssram #( .g_data_width(32), @@ -171,7 +171,7 @@ module mem64ro .clk_a_i(clk_i), .clk_b_i(clk_i), .addr_a_i(wb_adr_i[8:3]), - .bwsel_a_i(DdrCapturesIndex_sel_int), + .bwsel_a_i(DdrCapturesIndex_1_sel_int), .data_a_i({32{1'bx}}), .data_a_o(DdrCapturesIndex_DdrCaptures_int_dato1), .rd_a_i(DdrCapturesIndex_DdrCaptures_rreq1), @@ -186,15 +186,15 @@ module mem64ro always @(wr_sel_d0) begin - DdrCapturesIndex_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) - DdrCapturesIndex_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) - DdrCapturesIndex_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) - DdrCapturesIndex_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) - DdrCapturesIndex_sel_int[3] <= 1'b1; + DdrCapturesIndex_1_sel_int <= 4'b0; + if (~(wr_sel_d0[7:0] == 8'b0)) + DdrCapturesIndex_1_sel_int[0] <= 1'b1; + if (~(wr_sel_d0[15:8] == 8'b0)) + DdrCapturesIndex_1_sel_int[1] <= 1'b1; + if (~(wr_sel_d0[23:16] == 8'b0)) + DdrCapturesIndex_1_sel_int[2] <= 1'b1; + if (~(wr_sel_d0[31:24] == 8'b0)) + DdrCapturesIndex_1_sel_int[3] <= 1'b1; end always @(posedge(clk_i) or negedge(rst_n_i)) begin diff --git a/testfiles/bug-memory/mem64ro.vhdl b/testfiles/bug-memory/mem64ro.vhdl index 6fe308c1..1d8f568b 100644 --- a/testfiles/bug-memory/mem64ro.vhdl +++ b/testfiles/bug-memory/mem64ro.vhdl @@ -57,8 +57,8 @@ architecture syn of mem64ro is signal wr_adr_d0 : std_logic_vector(9 downto 2); signal wr_dat_d0 : std_logic_vector(31 downto 0); signal wr_sel_d0 : std_logic_vector(31 downto 0); - signal DdrCapturesIndex_sel_int : std_logic_vector(3 downto 0); - signal DdrCapturesIndex_sel_int : std_logic_vector(3 downto 0); + signal DdrCapturesIndex_0_sel_int : std_logic_vector(3 downto 0); + signal DdrCapturesIndex_1_sel_int : std_logic_vector(3 downto 0); begin -- WB decode signals @@ -144,7 +144,7 @@ begin clk_a_i => clk_i, clk_b_i => clk_i, addr_a_i => wb_adr_i(8 downto 3), - bwsel_a_i => DdrCapturesIndex_sel_int, + bwsel_a_i => DdrCapturesIndex_0_sel_int, data_a_i => (others => 'X'), data_a_o => DdrCapturesIndex_DdrCaptures_int_dato0, rd_a_i => DdrCapturesIndex_DdrCaptures_rreq0, @@ -158,18 +158,18 @@ begin ); process (wr_sel_d0) begin - DdrCapturesIndex_sel_int <= (others => '0'); + DdrCapturesIndex_0_sel_int <= (others => '0'); if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(0) <= '1'; + DdrCapturesIndex_0_sel_int(0) <= '1'; end if; if not (wr_sel_d0(15 downto 8) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(1) <= '1'; + DdrCapturesIndex_0_sel_int(1) <= '1'; end if; if not (wr_sel_d0(23 downto 16) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(2) <= '1'; + DdrCapturesIndex_0_sel_int(2) <= '1'; end if; if not (wr_sel_d0(31 downto 24) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(3) <= '1'; + DdrCapturesIndex_0_sel_int(3) <= '1'; end if; end process; DdrCapturesIndex_DdrCaptures_raminst1: cheby_dpssram @@ -184,7 +184,7 @@ begin clk_a_i => clk_i, clk_b_i => clk_i, addr_a_i => wb_adr_i(8 downto 3), - bwsel_a_i => DdrCapturesIndex_sel_int, + bwsel_a_i => DdrCapturesIndex_1_sel_int, data_a_i => (others => 'X'), data_a_o => DdrCapturesIndex_DdrCaptures_int_dato1, rd_a_i => DdrCapturesIndex_DdrCaptures_rreq1, @@ -198,18 +198,18 @@ begin ); process (wr_sel_d0) begin - DdrCapturesIndex_sel_int <= (others => '0'); + DdrCapturesIndex_1_sel_int <= (others => '0'); if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(0) <= '1'; + DdrCapturesIndex_1_sel_int(0) <= '1'; end if; if not (wr_sel_d0(15 downto 8) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(1) <= '1'; + DdrCapturesIndex_1_sel_int(1) <= '1'; end if; if not (wr_sel_d0(23 downto 16) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(2) <= '1'; + DdrCapturesIndex_1_sel_int(2) <= '1'; end if; if not (wr_sel_d0(31 downto 24) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(3) <= '1'; + DdrCapturesIndex_1_sel_int(3) <= '1'; end if; end process; process (clk_i) begin diff --git a/testfiles/bug-repmem/bran.sv b/testfiles/bug-repmem/bran.sv index a83a0c75..0d00f4e7 100644 --- a/testfiles/bug-repmem/bran.sv +++ b/testfiles/bug-repmem/bran.sv @@ -215,22 +215,22 @@ module bran_wb if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0; @@ -503,7 +503,7 @@ module bran_wb if (!wb.rst_n) RawData0_rack <= 1'b0; else - RawData0_rack <= RawData0_re & !RawData0_rack; + RawData0_rack <= RawData0_re & ~RawData0_rack; end assign RawData0_addr_o = adr_int[17:2]; @@ -513,7 +513,7 @@ module bran_wb if (!wb.rst_n) RawData1_rack <= 1'b0; else - RawData1_rack <= RawData1_re & !RawData1_rack; + RawData1_rack <= RawData1_re & ~RawData1_rack; end assign RawData1_addr_o = adr_int[17:2]; @@ -523,7 +523,7 @@ module bran_wb if (!wb.rst_n) RawData2_rack <= 1'b0; else - RawData2_rack <= RawData2_re & !RawData2_rack; + RawData2_rack <= RawData2_re & ~RawData2_rack; end assign RawData2_addr_o = adr_int[17:2]; @@ -533,7 +533,7 @@ module bran_wb if (!wb.rst_n) RawData3_rack <= 1'b0; else - RawData3_rack <= RawData3_re & !RawData3_rack; + RawData3_rack <= RawData3_re & ~RawData3_rack; end assign RawData3_addr_o = adr_int[17:2]; diff --git a/testfiles/crossbar/crossbar.v b/testfiles/crossbar/crossbar.v index 5a217a8a..2adc61b1 100644 --- a/testfiles/crossbar/crossbar.v +++ b/testfiles/crossbar/crossbar.v @@ -66,22 +66,22 @@ module crossbar_wb if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0; @@ -115,8 +115,8 @@ module crossbar_wb end else begin - jesdavalon_rt <= (jesdavalon_rt | jesdavalon_re) & !jesdavalon_rack; - jesdavalon_wt <= (jesdavalon_wt | jesdavalon_we) & !jesdavalon_wack; + jesdavalon_rt <= (jesdavalon_rt | jesdavalon_re) & ~jesdavalon_rack; + jesdavalon_wt <= (jesdavalon_wt | jesdavalon_we) & ~jesdavalon_wack; end end assign jesdavalon.cyc = jesdavalon_tr; @@ -127,13 +127,13 @@ module crossbar_wb always @(wr_sel_d0) begin jesdavalon.sel <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) jesdavalon.sel[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) jesdavalon.sel[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) jesdavalon.sel[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) jesdavalon.sel[3] <= 1'b1; end assign jesdavalon.we = jesdavalon_wt; @@ -150,8 +150,8 @@ module crossbar_wb end else begin - i2ctowb_rt <= (i2ctowb_rt | i2ctowb_re) & !i2ctowb_rack; - i2ctowb_wt <= (i2ctowb_wt | i2ctowb_we) & !i2ctowb_wack; + i2ctowb_rt <= (i2ctowb_rt | i2ctowb_re) & ~i2ctowb_rack; + i2ctowb_wt <= (i2ctowb_wt | i2ctowb_we) & ~i2ctowb_wack; end end assign i2ctowb.cyc = i2ctowb_tr; @@ -162,13 +162,13 @@ module crossbar_wb always @(wr_sel_d0) begin i2ctowb.sel <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) i2ctowb.sel[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) i2ctowb.sel[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) i2ctowb.sel[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) i2ctowb.sel[3] <= 1'b1; end assign i2ctowb.we = i2ctowb_wt; @@ -185,8 +185,8 @@ module crossbar_wb end else begin - bran_rt <= (bran_rt | bran_re) & !bran_rack; - bran_wt <= (bran_wt | bran_we) & !bran_wack; + bran_rt <= (bran_rt | bran_re) & ~bran_rack; + bran_wt <= (bran_wt | bran_we) & ~bran_wack; end end assign bran.cyc = bran_tr; @@ -197,13 +197,13 @@ module crossbar_wb always @(wr_sel_d0) begin bran.sel <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) bran.sel[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) bran.sel[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) bran.sel[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) bran.sel[3] <= 1'b1; end assign bran.we = bran_wt; diff --git a/testfiles/features/axi4_byte.sv b/testfiles/features/axi4_byte.sv index 0e6798a4..a71a087d 100644 --- a/testfiles/features/axi4_byte.sv +++ b/testfiles/features/axi4_byte.sv @@ -55,8 +55,8 @@ module sreg reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -95,7 +95,7 @@ module sreg assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -104,7 +104,7 @@ module sreg rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 1'b0; + rdata <= 32'b0; end else begin diff --git a/testfiles/features/axi4_submap_wb.sv b/testfiles/features/axi4_submap_wb.sv index 7d177fc8..c9f05617 100644 --- a/testfiles/features/axi4_submap_wb.sv +++ b/testfiles/features/axi4_submap_wb.sv @@ -72,22 +72,22 @@ module axi4_submap_wb if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -119,13 +119,13 @@ module axi4_submap_wb always @(wr_sel_d0) begin blk_wstrb_o <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) blk_wstrb_o[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) blk_wstrb_o[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) blk_wstrb_o[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) blk_wstrb_o[3] <= 1'b1; end assign blk_bready_o = 1'b1; @@ -143,9 +143,9 @@ module axi4_submap_wb end else begin - blk_aw_val <= blk_wr | (blk_aw_val & !blk_awready_i); - blk_w_val <= blk_wr | (blk_w_val & !blk_wready_i); - blk_ar_val <= blk_rd | (blk_ar_val & !blk_arready_i); + blk_aw_val <= blk_wr | (blk_aw_val & ~blk_awready_i); + blk_w_val <= blk_wr | (blk_w_val & ~blk_wready_i); + blk_ar_val <= blk_rd | (blk_ar_val & ~blk_arready_i); end end diff --git a/testfiles/features/axi4_word.sv b/testfiles/features/axi4_word.sv index e3cf1836..8218370f 100644 --- a/testfiles/features/axi4_word.sv +++ b/testfiles/features/axi4_word.sv @@ -55,8 +55,8 @@ module sreg reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -95,7 +95,7 @@ module sreg assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -104,7 +104,7 @@ module sreg rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 1'b0; + rdata <= 32'b0; end else begin diff --git a/testfiles/features/blkprefix1.sv b/testfiles/features/blkprefix1.sv index bb5d8002..283da050 100644 --- a/testfiles/features/blkprefix1.sv +++ b/testfiles/features/blkprefix1.sv @@ -53,22 +53,22 @@ module blkprefix1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/blkprefix2.sv b/testfiles/features/blkprefix2.sv index 4c2164b9..9e4488ac 100644 --- a/testfiles/features/blkprefix2.sv +++ b/testfiles/features/blkprefix2.sv @@ -53,22 +53,22 @@ module blkprefix2 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/blkprefix3.sv b/testfiles/features/blkprefix3.sv index ecc7041a..db67f194 100644 --- a/testfiles/features/blkprefix3.sv +++ b/testfiles/features/blkprefix3.sv @@ -61,22 +61,22 @@ module blkprefix3 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/blkprefix4.sv b/testfiles/features/blkprefix4.sv index 288f612f..032d6dda 100644 --- a/testfiles/features/blkprefix4.sv +++ b/testfiles/features/blkprefix4.sv @@ -81,22 +81,22 @@ module blkprefix4 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/enums1.sv b/testfiles/features/enums1.sv index b6881d1f..497dae50 100644 --- a/testfiles/features/enums1.sv +++ b/testfiles/features/enums1.sv @@ -43,22 +43,22 @@ module enums1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/enums2.sv b/testfiles/features/enums2.sv index 52bcd9e0..95571338 100644 --- a/testfiles/features/enums2.sv +++ b/testfiles/features/enums2.sv @@ -43,22 +43,22 @@ module enums2 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/iogroup1.sv b/testfiles/features/iogroup1.sv index 63371df2..07485b7b 100644 --- a/testfiles/features/iogroup1.sv +++ b/testfiles/features/iogroup1.sv @@ -63,22 +63,22 @@ module iogroup1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/iogroup2.sv b/testfiles/features/iogroup2.sv index dd820363..d7bbca46 100644 --- a/testfiles/features/iogroup2.sv +++ b/testfiles/features/iogroup2.sv @@ -55,22 +55,22 @@ module igroup2 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/mapinfo2.sv b/testfiles/features/mapinfo2.sv index d521df22..d8db206c 100644 --- a/testfiles/features/mapinfo2.sv +++ b/testfiles/features/mapinfo2.sv @@ -27,7 +27,7 @@ module mapinfo2 reg wr_req_d0; reg [19:2] wr_adr_d0; reg [31:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/features/mem64ro.sv b/testfiles/features/mem64ro.sv index cf197b9c..8e94b8f9 100644 --- a/testfiles/features/mem64ro.sv +++ b/testfiles/features/mem64ro.sv @@ -50,8 +50,8 @@ module mem64ro reg [9:2] wr_adr_d0; reg [31:0] wr_dat_d0; reg [31:0] wr_sel_d0; - reg [3:0] DdrCapturesIndex_sel_int; - reg [3:0] DdrCapturesIndex_sel_int; + reg [3:0] DdrCapturesIndex_0_sel_int; + reg [3:0] DdrCapturesIndex_1_sel_int; // WB decode signals always @(wb_sel_i) @@ -68,22 +68,22 @@ module mem64ro if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -135,7 +135,7 @@ module mem64ro .clk_a_i(clk_i), .clk_b_i(clk_i), .addr_a_i(wb_adr_i[8:3]), - .bwsel_a_i(DdrCapturesIndex_sel_int), + .bwsel_a_i(DdrCapturesIndex_0_sel_int), .data_a_i({32{1'bx}}), .data_a_o(DdrCapturesIndex_DdrCaptures_int_dato0), .rd_a_i(DdrCapturesIndex_DdrCaptures_rreq0), @@ -150,15 +150,15 @@ module mem64ro always @(wr_sel_d0) begin - DdrCapturesIndex_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) - DdrCapturesIndex_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) - DdrCapturesIndex_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) - DdrCapturesIndex_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) - DdrCapturesIndex_sel_int[3] <= 1'b1; + DdrCapturesIndex_0_sel_int <= 4'b0; + if (~(wr_sel_d0[7:0] == 8'b0)) + DdrCapturesIndex_0_sel_int[0] <= 1'b1; + if (~(wr_sel_d0[15:8] == 8'b0)) + DdrCapturesIndex_0_sel_int[1] <= 1'b1; + if (~(wr_sel_d0[23:16] == 8'b0)) + DdrCapturesIndex_0_sel_int[2] <= 1'b1; + if (~(wr_sel_d0[31:24] == 8'b0)) + DdrCapturesIndex_0_sel_int[3] <= 1'b1; end cheby_dpssram #( .g_data_width(32), @@ -171,7 +171,7 @@ module mem64ro .clk_a_i(clk_i), .clk_b_i(clk_i), .addr_a_i(wb_adr_i[8:3]), - .bwsel_a_i(DdrCapturesIndex_sel_int), + .bwsel_a_i(DdrCapturesIndex_1_sel_int), .data_a_i({32{1'bx}}), .data_a_o(DdrCapturesIndex_DdrCaptures_int_dato1), .rd_a_i(DdrCapturesIndex_DdrCaptures_rreq1), @@ -186,15 +186,15 @@ module mem64ro always @(wr_sel_d0) begin - DdrCapturesIndex_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) - DdrCapturesIndex_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) - DdrCapturesIndex_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) - DdrCapturesIndex_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) - DdrCapturesIndex_sel_int[3] <= 1'b1; + DdrCapturesIndex_1_sel_int <= 4'b0; + if (~(wr_sel_d0[7:0] == 8'b0)) + DdrCapturesIndex_1_sel_int[0] <= 1'b1; + if (~(wr_sel_d0[15:8] == 8'b0)) + DdrCapturesIndex_1_sel_int[1] <= 1'b1; + if (~(wr_sel_d0[23:16] == 8'b0)) + DdrCapturesIndex_1_sel_int[2] <= 1'b1; + if (~(wr_sel_d0[31:24] == 8'b0)) + DdrCapturesIndex_1_sel_int[3] <= 1'b1; end always @(posedge(clk_i) or negedge(rst_n_i)) begin diff --git a/testfiles/features/mem64ro.vhdl b/testfiles/features/mem64ro.vhdl index 6fe308c1..1d8f568b 100644 --- a/testfiles/features/mem64ro.vhdl +++ b/testfiles/features/mem64ro.vhdl @@ -57,8 +57,8 @@ architecture syn of mem64ro is signal wr_adr_d0 : std_logic_vector(9 downto 2); signal wr_dat_d0 : std_logic_vector(31 downto 0); signal wr_sel_d0 : std_logic_vector(31 downto 0); - signal DdrCapturesIndex_sel_int : std_logic_vector(3 downto 0); - signal DdrCapturesIndex_sel_int : std_logic_vector(3 downto 0); + signal DdrCapturesIndex_0_sel_int : std_logic_vector(3 downto 0); + signal DdrCapturesIndex_1_sel_int : std_logic_vector(3 downto 0); begin -- WB decode signals @@ -144,7 +144,7 @@ begin clk_a_i => clk_i, clk_b_i => clk_i, addr_a_i => wb_adr_i(8 downto 3), - bwsel_a_i => DdrCapturesIndex_sel_int, + bwsel_a_i => DdrCapturesIndex_0_sel_int, data_a_i => (others => 'X'), data_a_o => DdrCapturesIndex_DdrCaptures_int_dato0, rd_a_i => DdrCapturesIndex_DdrCaptures_rreq0, @@ -158,18 +158,18 @@ begin ); process (wr_sel_d0) begin - DdrCapturesIndex_sel_int <= (others => '0'); + DdrCapturesIndex_0_sel_int <= (others => '0'); if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(0) <= '1'; + DdrCapturesIndex_0_sel_int(0) <= '1'; end if; if not (wr_sel_d0(15 downto 8) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(1) <= '1'; + DdrCapturesIndex_0_sel_int(1) <= '1'; end if; if not (wr_sel_d0(23 downto 16) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(2) <= '1'; + DdrCapturesIndex_0_sel_int(2) <= '1'; end if; if not (wr_sel_d0(31 downto 24) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(3) <= '1'; + DdrCapturesIndex_0_sel_int(3) <= '1'; end if; end process; DdrCapturesIndex_DdrCaptures_raminst1: cheby_dpssram @@ -184,7 +184,7 @@ begin clk_a_i => clk_i, clk_b_i => clk_i, addr_a_i => wb_adr_i(8 downto 3), - bwsel_a_i => DdrCapturesIndex_sel_int, + bwsel_a_i => DdrCapturesIndex_1_sel_int, data_a_i => (others => 'X'), data_a_o => DdrCapturesIndex_DdrCaptures_int_dato1, rd_a_i => DdrCapturesIndex_DdrCaptures_rreq1, @@ -198,18 +198,18 @@ begin ); process (wr_sel_d0) begin - DdrCapturesIndex_sel_int <= (others => '0'); + DdrCapturesIndex_1_sel_int <= (others => '0'); if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(0) <= '1'; + DdrCapturesIndex_1_sel_int(0) <= '1'; end if; if not (wr_sel_d0(15 downto 8) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(1) <= '1'; + DdrCapturesIndex_1_sel_int(1) <= '1'; end if; if not (wr_sel_d0(23 downto 16) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(2) <= '1'; + DdrCapturesIndex_1_sel_int(2) <= '1'; end if; if not (wr_sel_d0(31 downto 24) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(3) <= '1'; + DdrCapturesIndex_1_sel_int(3) <= '1'; end if; end process; process (clk_i) begin diff --git a/testfiles/features/mem64rodual.sv b/testfiles/features/mem64rodual.sv index 47fab8cb..5cd64fdb 100644 --- a/testfiles/features/mem64rodual.sv +++ b/testfiles/features/mem64rodual.sv @@ -42,8 +42,8 @@ module mem64rodual reg [31:0] rd_dat_d0; reg wr_req_d0; reg [31:0] wr_sel_d0; - reg [3:0] DdrCapturesIndex_sel_int; - reg [3:0] DdrCapturesIndex_sel_int; + reg [3:0] DdrCapturesIndex_0_sel_int; + reg [3:0] DdrCapturesIndex_1_sel_int; // WB decode signals always @(wb_sel_i) @@ -60,22 +60,22 @@ module mem64rodual if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -108,7 +108,7 @@ module mem64rodual .clk_a_i(clk_i), .clk_b_i(DdrCapturesIndex_clk_i), .addr_a_i(wb_adr_i[8:3]), - .bwsel_a_i(DdrCapturesIndex_sel_int), + .bwsel_a_i(DdrCapturesIndex_0_sel_int), .data_a_i({32{1'bx}}), .data_a_o(DdrCapturesIndex_DdrCaptures_int_dato0), .rd_a_i(DdrCapturesIndex_DdrCaptures_rreq0), @@ -123,15 +123,15 @@ module mem64rodual always @(wr_sel_d0) begin - DdrCapturesIndex_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) - DdrCapturesIndex_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) - DdrCapturesIndex_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) - DdrCapturesIndex_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) - DdrCapturesIndex_sel_int[3] <= 1'b1; + DdrCapturesIndex_0_sel_int <= 4'b0; + if (~(wr_sel_d0[7:0] == 8'b0)) + DdrCapturesIndex_0_sel_int[0] <= 1'b1; + if (~(wr_sel_d0[15:8] == 8'b0)) + DdrCapturesIndex_0_sel_int[1] <= 1'b1; + if (~(wr_sel_d0[23:16] == 8'b0)) + DdrCapturesIndex_0_sel_int[2] <= 1'b1; + if (~(wr_sel_d0[31:24] == 8'b0)) + DdrCapturesIndex_0_sel_int[3] <= 1'b1; end cheby_dpssram #( .g_data_width(32), @@ -144,7 +144,7 @@ module mem64rodual .clk_a_i(clk_i), .clk_b_i(DdrCapturesIndex_clk_i), .addr_a_i(wb_adr_i[8:3]), - .bwsel_a_i(DdrCapturesIndex_sel_int), + .bwsel_a_i(DdrCapturesIndex_1_sel_int), .data_a_i({32{1'bx}}), .data_a_o(DdrCapturesIndex_DdrCaptures_int_dato1), .rd_a_i(DdrCapturesIndex_DdrCaptures_rreq1), @@ -159,15 +159,15 @@ module mem64rodual always @(wr_sel_d0) begin - DdrCapturesIndex_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) - DdrCapturesIndex_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) - DdrCapturesIndex_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) - DdrCapturesIndex_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) - DdrCapturesIndex_sel_int[3] <= 1'b1; + DdrCapturesIndex_1_sel_int <= 4'b0; + if (~(wr_sel_d0[7:0] == 8'b0)) + DdrCapturesIndex_1_sel_int[0] <= 1'b1; + if (~(wr_sel_d0[15:8] == 8'b0)) + DdrCapturesIndex_1_sel_int[1] <= 1'b1; + if (~(wr_sel_d0[23:16] == 8'b0)) + DdrCapturesIndex_1_sel_int[2] <= 1'b1; + if (~(wr_sel_d0[31:24] == 8'b0)) + DdrCapturesIndex_1_sel_int[3] <= 1'b1; end always @(posedge(clk_i) or negedge(rst_n_i)) begin diff --git a/testfiles/features/mem64rodual.vhdl b/testfiles/features/mem64rodual.vhdl index 7d8c7d88..13b0c630 100644 --- a/testfiles/features/mem64rodual.vhdl +++ b/testfiles/features/mem64rodual.vhdl @@ -49,8 +49,8 @@ architecture syn of mem64rodual is signal rd_dat_d0 : std_logic_vector(31 downto 0); signal wr_req_d0 : std_logic; signal wr_sel_d0 : std_logic_vector(31 downto 0); - signal DdrCapturesIndex_sel_int : std_logic_vector(3 downto 0); - signal DdrCapturesIndex_sel_int : std_logic_vector(3 downto 0); + signal DdrCapturesIndex_0_sel_int : std_logic_vector(3 downto 0); + signal DdrCapturesIndex_1_sel_int : std_logic_vector(3 downto 0); begin -- WB decode signals @@ -118,7 +118,7 @@ begin clk_a_i => clk_i, clk_b_i => DdrCapturesIndex_clk_i, addr_a_i => wb_adr_i(8 downto 3), - bwsel_a_i => DdrCapturesIndex_sel_int, + bwsel_a_i => DdrCapturesIndex_0_sel_int, data_a_i => (others => 'X'), data_a_o => DdrCapturesIndex_DdrCaptures_int_dato0, rd_a_i => DdrCapturesIndex_DdrCaptures_rreq0, @@ -132,18 +132,18 @@ begin ); process (wr_sel_d0) begin - DdrCapturesIndex_sel_int <= (others => '0'); + DdrCapturesIndex_0_sel_int <= (others => '0'); if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(0) <= '1'; + DdrCapturesIndex_0_sel_int(0) <= '1'; end if; if not (wr_sel_d0(15 downto 8) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(1) <= '1'; + DdrCapturesIndex_0_sel_int(1) <= '1'; end if; if not (wr_sel_d0(23 downto 16) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(2) <= '1'; + DdrCapturesIndex_0_sel_int(2) <= '1'; end if; if not (wr_sel_d0(31 downto 24) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(3) <= '1'; + DdrCapturesIndex_0_sel_int(3) <= '1'; end if; end process; DdrCapturesIndex_DdrCaptures_raminst1: cheby_dpssram @@ -158,7 +158,7 @@ begin clk_a_i => clk_i, clk_b_i => DdrCapturesIndex_clk_i, addr_a_i => wb_adr_i(8 downto 3), - bwsel_a_i => DdrCapturesIndex_sel_int, + bwsel_a_i => DdrCapturesIndex_1_sel_int, data_a_i => (others => 'X'), data_a_o => DdrCapturesIndex_DdrCaptures_int_dato1, rd_a_i => DdrCapturesIndex_DdrCaptures_rreq1, @@ -172,18 +172,18 @@ begin ); process (wr_sel_d0) begin - DdrCapturesIndex_sel_int <= (others => '0'); + DdrCapturesIndex_1_sel_int <= (others => '0'); if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(0) <= '1'; + DdrCapturesIndex_1_sel_int(0) <= '1'; end if; if not (wr_sel_d0(15 downto 8) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(1) <= '1'; + DdrCapturesIndex_1_sel_int(1) <= '1'; end if; if not (wr_sel_d0(23 downto 16) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(2) <= '1'; + DdrCapturesIndex_1_sel_int(2) <= '1'; end if; if not (wr_sel_d0(31 downto 24) = (7 downto 0 => '0')) then - DdrCapturesIndex_sel_int(3) <= '1'; + DdrCapturesIndex_1_sel_int(3) <= '1'; end if; end process; process (clk_i) begin diff --git a/testfiles/features/no_port.sv b/testfiles/features/no_port.sv index 6190f1e7..0e560bbc 100644 --- a/testfiles/features/no_port.sv +++ b/testfiles/features/no_port.sv @@ -37,14 +37,14 @@ module no_port reg [31:0] wr_dat_d0; // Write Channel - assign wr_req = (psel & pwrite) & !penable; + assign wr_req = (psel & pwrite) & ~penable; assign wr_addr = paddr; assign wr_data = pwdata; always @(pstrb) ; // Read Channel - assign rd_req = (psel & !pwrite) & !penable; + assign rd_req = (psel & ~pwrite) & ~penable; assign rd_addr = paddr; assign prdata = rd_data; assign pready = wr_ack | rd_ack; diff --git a/testfiles/features/orclrout_rw.sv b/testfiles/features/orclrout_rw.sv index 7a846758..4fe17b1c 100644 --- a/testfiles/features/orclrout_rw.sv +++ b/testfiles/features/orclrout_rw.sv @@ -44,22 +44,22 @@ module orclrout if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -92,7 +92,7 @@ module orclrout else begin if (breg_wreq == 1'b1) - breg_reg <= breg_i | (breg_reg & !wr_dat_d0); + breg_reg <= breg_i | (breg_reg & ~wr_dat_d0); else breg_reg <= breg_i | breg_reg; breg_wack <= breg_wreq; diff --git a/testfiles/features/reg-strobe.sv b/testfiles/features/reg-strobe.sv index c3f5c78a..299280db 100644 --- a/testfiles/features/reg-strobe.sv +++ b/testfiles/features/reg-strobe.sv @@ -45,22 +45,22 @@ module reg_strobe if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/reg128.sv b/testfiles/features/reg128.sv index 06fcc411..980a9d54 100644 --- a/testfiles/features/reg128.sv +++ b/testfiles/features/reg128.sv @@ -45,22 +45,22 @@ module reg128 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/regprefix1.sv b/testfiles/features/regprefix1.sv index 92851aab..a4054063 100644 --- a/testfiles/features/regprefix1.sv +++ b/testfiles/features/regprefix1.sv @@ -61,22 +61,22 @@ module regprefix1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/regprefix2.sv b/testfiles/features/regprefix2.sv index 35aa947a..9eeef0c0 100644 --- a/testfiles/features/regprefix2.sv +++ b/testfiles/features/regprefix2.sv @@ -61,22 +61,22 @@ module regprefix2 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/regprefix3.sv b/testfiles/features/regprefix3.sv index 07762faf..f5040476 100644 --- a/testfiles/features/regprefix3.sv +++ b/testfiles/features/regprefix3.sv @@ -57,22 +57,22 @@ module regprefix3 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/repeat-iogroup1.sv b/testfiles/features/repeat-iogroup1.sv index 72b75a35..701cf430 100644 --- a/testfiles/features/repeat-iogroup1.sv +++ b/testfiles/features/repeat-iogroup1.sv @@ -54,22 +54,22 @@ module repeat_iogroup1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/repeat-iogroup2.sv b/testfiles/features/repeat-iogroup2.sv index 35f4bd66..fe9ae4bd 100644 --- a/testfiles/features/repeat-iogroup2.sv +++ b/testfiles/features/repeat-iogroup2.sv @@ -49,22 +49,22 @@ module repeat_iogroup1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/repeat-iogroup3.sv b/testfiles/features/repeat-iogroup3.sv index d28263e2..6b9ed658 100644 --- a/testfiles/features/repeat-iogroup3.sv +++ b/testfiles/features/repeat-iogroup3.sv @@ -49,22 +49,22 @@ module repeat_iogroup3 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/repeat-iogroup4.sv b/testfiles/features/repeat-iogroup4.sv index d8da68a1..64bc5511 100644 --- a/testfiles/features/repeat-iogroup4.sv +++ b/testfiles/features/repeat-iogroup4.sv @@ -53,22 +53,22 @@ module repeat_iogroup4 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/semver1.sv b/testfiles/features/semver1.sv index a07798ea..81a83ad0 100644 --- a/testfiles/features/semver1.sv +++ b/testfiles/features/semver1.sv @@ -43,22 +43,22 @@ module semver1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/semver2.sv b/testfiles/features/semver2.sv index 45ae3f99..d14e6ace 100644 --- a/testfiles/features/semver2.sv +++ b/testfiles/features/semver2.sv @@ -45,22 +45,22 @@ module semver2 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/wires1.sv b/testfiles/features/wires1.sv index 20b964f9..8341bd50 100644 --- a/testfiles/features/wires1.sv +++ b/testfiles/features/wires1.sv @@ -61,22 +61,22 @@ module wires1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/features/xilinx_attrs.sv b/testfiles/features/xilinx_attrs.sv index f5197f74..c63310f9 100644 --- a/testfiles/features/xilinx_attrs.sv +++ b/testfiles/features/xilinx_attrs.sv @@ -71,8 +71,8 @@ module xilinx_attrs reg [31:0] wr_sel_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -115,7 +115,7 @@ module xilinx_attrs assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -124,7 +124,7 @@ module xilinx_attrs rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 1'b0; + rdata <= 32'b0; end else begin @@ -177,13 +177,13 @@ module xilinx_attrs always @(wr_sel_d0) begin subm_wstrb_o <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) subm_wstrb_o[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) subm_wstrb_o[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) subm_wstrb_o[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) subm_wstrb_o[3] <= 1'b1; end assign subm_bready_o = 1'b1; @@ -201,9 +201,9 @@ module xilinx_attrs end else begin - subm_aw_val <= subm_wr | (subm_aw_val & !subm_awready_i); - subm_w_val <= subm_wr | (subm_w_val & !subm_wready_i); - subm_ar_val <= subm_rd | (subm_ar_val & !subm_arready_i); + subm_aw_val <= subm_wr | (subm_aw_val & ~subm_awready_i); + subm_w_val <= subm_wr | (subm_w_val & ~subm_wready_i); + subm_ar_val <= subm_rd | (subm_ar_val & ~subm_arready_i); end end diff --git a/testfiles/features/xilinx_attrs_cern.sv b/testfiles/features/xilinx_attrs_cern.sv index 79e52cbe..f0a580c3 100644 --- a/testfiles/features/xilinx_attrs_cern.sv +++ b/testfiles/features/xilinx_attrs_cern.sv @@ -30,7 +30,7 @@ module xilinx_attrs reg [31:0] wr_dat_d0; reg subm_ws; reg subm_wt; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; @@ -59,7 +59,7 @@ module xilinx_attrs if (!rst_n) subm_wt <= 1'b0; else - subm_wt <= (subm_wt | subm_ws) & !subm_VMEWrDone_i; + subm_wt <= (subm_wt | subm_ws) & ~subm_VMEWrDone_i; end assign subm_VMEWrMem_o = subm_ws; always @(VMEAddr, wr_adr_d0, subm_wt, subm_ws) diff --git a/testfiles/fmc-adc01/fmc_adc_alt_trigin.sv b/testfiles/fmc-adc01/fmc_adc_alt_trigin.sv index c264ee88..b6100afb 100644 --- a/testfiles/fmc-adc01/fmc_adc_alt_trigin.sv +++ b/testfiles/fmc-adc01/fmc_adc_alt_trigin.sv @@ -42,22 +42,22 @@ module alt_trigin if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0; diff --git a/testfiles/fmc-adc01/fmc_adc_alt_trigout.sv b/testfiles/fmc-adc01/fmc_adc_alt_trigout.sv index 342c16ec..6c84f2f7 100644 --- a/testfiles/fmc-adc01/fmc_adc_alt_trigout.sv +++ b/testfiles/fmc-adc01/fmc_adc_alt_trigout.sv @@ -77,22 +77,22 @@ module alt_trigout if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0; diff --git a/testfiles/issue10/test.sv b/testfiles/issue10/test.sv index 322d44be..d32325be 100644 --- a/testfiles/issue10/test.sv +++ b/testfiles/issue10/test.sv @@ -67,8 +67,8 @@ module test reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -107,7 +107,7 @@ module test assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -116,7 +116,7 @@ module test rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 3'b0; + rdata <= 32'b0; end else begin diff --git a/testfiles/issue11/test_port1.sv b/testfiles/issue11/test_port1.sv index 0fdd4c67..bf5dde47 100644 --- a/testfiles/issue11/test_port1.sv +++ b/testfiles/issue11/test_port1.sv @@ -45,22 +45,22 @@ module sreg if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/issue11/test_port1_field.sv b/testfiles/issue11/test_port1_field.sv index 0fdd4c67..bf5dde47 100644 --- a/testfiles/issue11/test_port1_field.sv +++ b/testfiles/issue11/test_port1_field.sv @@ -45,22 +45,22 @@ module sreg if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/issue11/test_port1_reg.sv b/testfiles/issue11/test_port1_reg.sv index 40644018..cb39cca5 100644 --- a/testfiles/issue11/test_port1_reg.sv +++ b/testfiles/issue11/test_port1_reg.sv @@ -44,22 +44,22 @@ module sreg if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/issue11/test_port2_reg.sv b/testfiles/issue11/test_port2_reg.sv index 30226a5d..68a9d694 100644 --- a/testfiles/issue11/test_port2_reg.sv +++ b/testfiles/issue11/test_port2_reg.sv @@ -39,22 +39,22 @@ module sreg if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/issue11/test_port2_wire.sv b/testfiles/issue11/test_port2_wire.sv index 3cb12cb7..db768c97 100644 --- a/testfiles/issue11/test_port2_wire.sv +++ b/testfiles/issue11/test_port2_wire.sv @@ -44,22 +44,22 @@ module sreg if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/issue13/mainMap2.sv b/testfiles/issue13/mainMap2.sv index ce1b1d9b..6ad07ce9 100644 --- a/testfiles/issue13/mainMap2.sv +++ b/testfiles/issue13/mainMap2.sv @@ -47,7 +47,7 @@ module mainMap2 reg subMap1_wt; reg subMap2_ws; reg subMap2_wt; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; @@ -76,7 +76,7 @@ module mainMap2 if (!rst_n) subMap1_wt <= 1'b0; else - subMap1_wt <= (subMap1_wt | subMap1_ws) & !subMap1_VMEWrDone_i; + subMap1_wt <= (subMap1_wt | subMap1_ws) & ~subMap1_VMEWrDone_i; end assign subMap1_VMEWrMem_o = subMap1_ws; always @(VMEAddr, wr_adr_d0, subMap1_wt, subMap1_ws) @@ -92,7 +92,7 @@ module mainMap2 if (!rst_n) subMap2_wt <= 1'b0; else - subMap2_wt <= (subMap2_wt | subMap2_ws) & !subMap2_VMEWrDone_i; + subMap2_wt <= (subMap2_wt | subMap2_ws) & ~subMap2_VMEWrDone_i; end assign subMap2_VMEWrMem_o = subMap2_ws; always @(VMEAddr, wr_adr_d0, subMap2_wt, subMap2_ws) diff --git a/testfiles/issue14/test-axi.sv b/testfiles/issue14/test-axi.sv index b0482f44..3ae3a5c9 100644 --- a/testfiles/issue14/test-axi.sv +++ b/testfiles/issue14/test-axi.sv @@ -49,8 +49,8 @@ module test_axi4 reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -89,7 +89,7 @@ module test_axi4 assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -98,7 +98,7 @@ module test_axi4 rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 1'b0; + rdata <= 32'b0; end else begin diff --git a/testfiles/issue14/test-be.sv b/testfiles/issue14/test-be.sv index 6fcd1764..8658ffaa 100644 --- a/testfiles/issue14/test-be.sv +++ b/testfiles/issue14/test-be.sv @@ -49,8 +49,8 @@ module test_axi4 reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -89,7 +89,7 @@ module test_axi4 assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -98,7 +98,7 @@ module test_axi4 rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 1'b0; + rdata <= 32'b0; end else begin diff --git a/testfiles/issue14/test-le.sv b/testfiles/issue14/test-le.sv index b0482f44..3ae3a5c9 100644 --- a/testfiles/issue14/test-le.sv +++ b/testfiles/issue14/test-le.sv @@ -49,8 +49,8 @@ module test_axi4 reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -89,7 +89,7 @@ module test_axi4 assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -98,7 +98,7 @@ module test_axi4 rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 1'b0; + rdata <= 32'b0; end else begin diff --git a/testfiles/issue39/addressingMemory.sv b/testfiles/issue39/addressingMemory.sv index ce5d39e5..ad7fc434 100644 --- a/testfiles/issue39/addressingMemory.sv +++ b/testfiles/issue39/addressingMemory.sv @@ -36,7 +36,7 @@ module eda02175v2 reg [15:0] wr_dat_d0; reg acqVP_ws; reg acqVP_wt; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; @@ -65,7 +65,7 @@ module eda02175v2 if (!rst_n) acqVP_wt <= 1'b0; else - acqVP_wt <= (acqVP_wt | acqVP_ws) & !acqVP_VMEWrDone_i; + acqVP_wt <= (acqVP_wt | acqVP_ws) & ~acqVP_VMEWrDone_i; end assign acqVP_VMEWrMem_o = acqVP_ws; always @(VMEAddr, wr_adr_d0, acqVP_wt, acqVP_ws) diff --git a/testfiles/issue40/bugConstraints.sv b/testfiles/issue40/bugConstraints.sv index 88019e83..0a40bc18 100644 --- a/testfiles/issue40/bugConstraints.sv +++ b/testfiles/issue40/bugConstraints.sv @@ -31,7 +31,7 @@ module bugConstraintFields reg wr_req_d0; reg [2:2] wr_adr_d0; reg [31:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue41/bugBlockFields.sv b/testfiles/issue41/bugBlockFields.sv index cf8c7e8a..26d368bb 100644 --- a/testfiles/issue41/bugBlockFields.sv +++ b/testfiles/issue41/bugBlockFields.sv @@ -31,7 +31,7 @@ module bugBlockRegField reg [31:0] rd_dat_d0; reg wr_req_d0; reg [31:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue44/m1.sv b/testfiles/issue44/m1.sv index 55be4ff8..b6d5bf2f 100644 --- a/testfiles/issue44/m1.sv +++ b/testfiles/issue44/m1.sv @@ -72,22 +72,22 @@ module m1 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -116,7 +116,7 @@ module m1 if (!rst_n_i) m0_wt <= 1'b0; else - m0_wt <= (m0_wt | m0_ws) & !m0_VMEWrDone_i; + m0_wt <= (m0_wt | m0_ws) & ~m0_VMEWrDone_i; end assign m0_VMEWrMem_o = m0_ws; always @(wb_adr_i, wr_adr_d0, m0_wt, m0_ws) @@ -132,7 +132,7 @@ module m1 if (!rst_n_i) m1_wt <= 1'b0; else - m1_wt <= (m1_wt | m1_ws) & !m1_VMEWrDone_i; + m1_wt <= (m1_wt | m1_ws) & ~m1_VMEWrDone_i; end assign m1_VMEWrMem_o = m1_ws; always @(wb_adr_i, wr_adr_d0, m1_wt, m1_ws) @@ -148,7 +148,7 @@ module m1 if (!rst_n_i) m2_wt <= 1'b0; else - m2_wt <= (m2_wt | m2_ws) & !m2_VMEWrDone_i; + m2_wt <= (m2_wt | m2_ws) & ~m2_VMEWrDone_i; end assign m2_VMEWrMem_o = m2_ws; always @(wb_adr_i, wr_adr_d0, m2_wt, m2_ws) diff --git a/testfiles/issue45/test16.sv b/testfiles/issue45/test16.sv index 9433fc6b..b7585692 100644 --- a/testfiles/issue45/test16.sv +++ b/testfiles/issue45/test16.sv @@ -23,7 +23,7 @@ module test8 reg [31:0] rd_dat_d0; reg wr_req_d0; reg [31:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue45/test8.sv b/testfiles/issue45/test8.sv index 94fcf77e..c886671e 100644 --- a/testfiles/issue45/test8.sv +++ b/testfiles/issue45/test8.sv @@ -23,7 +23,7 @@ module test8 reg [31:0] rd_dat_d0; reg wr_req_d0; reg [31:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue52/hwInfo.sv b/testfiles/issue52/hwInfo.sv index 13d7a8dd..85516e76 100644 --- a/testfiles/issue52/hwInfo.sv +++ b/testfiles/issue52/hwInfo.sv @@ -39,7 +39,7 @@ module hwInfo reg wr_req_d0; reg [4:1] wr_adr_d0; reg [15:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue59/inherit.sv b/testfiles/issue59/inherit.sv index c75df02e..7374cb43 100644 --- a/testfiles/issue59/inherit.sv +++ b/testfiles/issue59/inherit.sv @@ -51,22 +51,22 @@ module inherit if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/issue64/simple_reg1.sv b/testfiles/issue64/simple_reg1.sv index 44541be1..28c1655e 100644 --- a/testfiles/issue64/simple_reg1.sv +++ b/testfiles/issue64/simple_reg1.sv @@ -43,22 +43,22 @@ module sreg_map if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/issue66/m1.sv b/testfiles/issue66/m1.sv index 94ccd5c1..5a4b57bd 100644 --- a/testfiles/issue66/m1.sv +++ b/testfiles/issue66/m1.sv @@ -33,7 +33,7 @@ module m1 reg wr_req_d0; reg [19:2] wr_adr_d0; reg [31:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue75/m1.sv b/testfiles/issue75/m1.sv index 5bd4a715..3be45c46 100644 --- a/testfiles/issue75/m1.sv +++ b/testfiles/issue75/m1.sv @@ -25,7 +25,7 @@ module m1 reg wr_req_d0; reg [2:2] wr_adr_d0; reg [31:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue77/m1.sv b/testfiles/issue77/m1.sv index 60a8e7c7..09b5205d 100644 --- a/testfiles/issue77/m1.sv +++ b/testfiles/issue77/m1.sv @@ -44,8 +44,8 @@ module m1 reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -83,7 +83,7 @@ module m1 assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -92,7 +92,7 @@ module m1 rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 0'b0; + rdata <= 32'b0; end else begin diff --git a/testfiles/issue77/m2.sv b/testfiles/issue77/m2.sv index 4dc83749..d2fc841a 100644 --- a/testfiles/issue77/m2.sv +++ b/testfiles/issue77/m2.sv @@ -43,22 +43,22 @@ module m2 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; diff --git a/testfiles/issue77/m3.sv b/testfiles/issue77/m3.sv index c7a5b7f7..dc4e53c5 100644 --- a/testfiles/issue77/m3.sv +++ b/testfiles/issue77/m3.sv @@ -23,7 +23,7 @@ module m2 reg [31:0] rd_dat_d0; reg wr_req_d0; reg [31:0] wr_dat_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue77/s1.sv b/testfiles/issue77/s1.sv index 48d46715..dee94054 100644 --- a/testfiles/issue77/s1.sv +++ b/testfiles/issue77/s1.sv @@ -61,8 +61,8 @@ module s1 reg [31:0] wr_sel_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -104,7 +104,7 @@ module s1 assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -113,7 +113,7 @@ module s1 rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 0'b0; + rdata <= 32'b0; end else begin @@ -168,10 +168,10 @@ module s1 end else begin - sub_wr <= (sub_wr | sub_we) & !sub_wack; - sub_wt <= (sub_wt | (sub_wr & !sub_tr)) & !sub_wack; - sub_rr <= (sub_rr | sub_re) & !sub_rack; - sub_rt <= (sub_rt | (sub_rr & !(sub_wr | sub_tr))) & !sub_rack; + sub_wr <= (sub_wr | sub_we) & ~sub_wack; + sub_wt <= (sub_wt | (sub_wr & ~sub_tr)) & ~sub_wack; + sub_rr <= (sub_rr | sub_re) & ~sub_rack; + sub_rt <= (sub_rt | (sub_rr & ~(sub_wr | sub_tr))) & ~sub_rack; end end assign sub_cyc_o = sub_tr; @@ -181,13 +181,13 @@ module s1 always @(wr_sel_d0) begin sub_sel_o <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) sub_sel_o[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) sub_sel_o[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) sub_sel_o[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) sub_sel_o[3] <= 1'b1; end assign sub_we_o = sub_wt; diff --git a/testfiles/issue77/s2.sv b/testfiles/issue77/s2.sv index 2ca1690c..9f5aabb6 100644 --- a/testfiles/issue77/s2.sv +++ b/testfiles/issue77/s2.sv @@ -54,8 +54,8 @@ module s2 reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -93,7 +93,7 @@ module s2 assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -102,7 +102,7 @@ module s2 rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 0'b0; + rdata <= 32'b0; end else begin @@ -156,14 +156,14 @@ module s2 end else begin - sub_wr <= (sub_wr | sub_we) & !sub_VMEWrDone_i; - sub_wt <= (sub_wt | sub_ws) & !sub_VMEWrDone_i; - sub_rr <= (sub_rr | sub_re) & !sub_VMERdDone_i; - sub_rt <= (sub_rt | sub_rs) & !sub_VMERdDone_i; + sub_wr <= (sub_wr | sub_we) & ~sub_VMEWrDone_i; + sub_wt <= (sub_wt | sub_ws) & ~sub_VMEWrDone_i; + sub_rr <= (sub_rr | sub_re) & ~sub_VMERdDone_i; + sub_rt <= (sub_rt | sub_rs) & ~sub_VMERdDone_i; end end - assign sub_rs = sub_rr & !(sub_wr | (sub_rt | sub_wt)); - assign sub_ws = sub_wr & !(sub_rt | sub_wt); + assign sub_rs = sub_rr & ~(sub_wr | (sub_rt | sub_wt)); + assign sub_ws = sub_wr & ~(sub_rt | sub_wt); // Process for write requests. always @(wr_req_d0, sub_ws, sub_VMEWrDone_i) diff --git a/testfiles/issue77/s3.sv b/testfiles/issue77/s3.sv index 537d5a83..e6f5dc01 100644 --- a/testfiles/issue77/s3.sv +++ b/testfiles/issue77/s3.sv @@ -64,8 +64,8 @@ module s3 reg [31:0] wr_sel_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -107,7 +107,7 @@ module s3 assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -116,7 +116,7 @@ module s3 rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 0'b0; + rdata <= 32'b0; end else begin @@ -166,13 +166,13 @@ module s3 always @(wr_sel_d0) begin sub_wstrb_o <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) sub_wstrb_o[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) sub_wstrb_o[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) sub_wstrb_o[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) sub_wstrb_o[3] <= 1'b1; end assign sub_bready_o = 1'b1; @@ -189,9 +189,9 @@ module s3 end else begin - sub_aw_val <= sub_wr | (sub_aw_val & !sub_awready_i); - sub_w_val <= sub_wr | (sub_w_val & !sub_wready_i); - sub_ar_val <= sub_rd | (sub_ar_val & !sub_arready_i); + sub_aw_val <= sub_wr | (sub_aw_val & ~sub_awready_i); + sub_w_val <= sub_wr | (sub_w_val & ~sub_wready_i); + sub_ar_val <= sub_rd | (sub_ar_val & ~sub_arready_i); end end diff --git a/testfiles/issue77/s4.sv b/testfiles/issue77/s4.sv index d2f7d58f..25134126 100644 --- a/testfiles/issue77/s4.sv +++ b/testfiles/issue77/s4.sv @@ -71,22 +71,22 @@ module s4 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -137,8 +137,8 @@ module s4 end else begin - sub_rt <= (sub_rt | sub_re) & !sub_rack; - sub_wt <= (sub_wt | sub_we) & !sub_wack; + sub_rt <= (sub_rt | sub_re) & ~sub_rack; + sub_wt <= (sub_wt | sub_we) & ~sub_wack; end end assign sub_cyc_o = sub_tr; @@ -148,13 +148,13 @@ module s4 always @(wr_sel_d0) begin sub_sel_o <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) sub_sel_o[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) sub_sel_o[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) sub_sel_o[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) sub_sel_o[3] <= 1'b1; end assign sub_we_o = sub_wt; diff --git a/testfiles/issue77/s5.sv b/testfiles/issue77/s5.sv index 423b21bb..f905c5e7 100644 --- a/testfiles/issue77/s5.sv +++ b/testfiles/issue77/s5.sv @@ -62,22 +62,22 @@ module s5 if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -128,25 +128,25 @@ module s5 end else begin - sub_rt <= (sub_rt | sub_re) & !sub_rack; - sub_wt <= (sub_wt | sub_we) & !sub_wack; + sub_rt <= (sub_rt | sub_re) & ~sub_rack; + sub_wt <= (sub_wt | sub_we) & ~sub_wack; end end assign sub.cyc = sub_tr; assign sub.stb = sub_tr; assign sub_wack = sub.ack & sub_wt; assign sub_rack = sub.ack & sub_rt; - assign sub.adr = {30'b0, wb_adr_i[1:2], 2'b0}; + assign sub.adr = {30'b0, 2'b0}; always @(wr_sel_d0) begin sub.sel <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) sub.sel[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) sub.sel[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) sub.sel[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) sub.sel[3] <= 1'b1; end assign sub.we = sub_wt; diff --git a/testfiles/issue77/s5.vhdl b/testfiles/issue77/s5.vhdl index fece151e..616c56fc 100644 --- a/testfiles/issue77/s5.vhdl +++ b/testfiles/issue77/s5.vhdl @@ -143,7 +143,7 @@ begin sub_o.stb <= sub_tr; sub_wack <= sub_i.ack and sub_wt; sub_rack <= sub_i.ack and sub_rt; - sub_o.adr <= ((29 downto 0 => '0') & wb_adr_i(1 downto 2)) & (1 downto 0 => '0'); + sub_o.adr <= (29 downto 0 => '0') & (1 downto 0 => '0'); process (wr_sel_d0) begin sub_o.sel <= (others => '0'); if not (wr_sel_d0(7 downto 0) = (7 downto 0 => '0')) then diff --git a/testfiles/issue77/s6.sv b/testfiles/issue77/s6.sv index 4f41efd2..f6ef58a1 100644 --- a/testfiles/issue77/s6.sv +++ b/testfiles/issue77/s6.sv @@ -32,22 +32,22 @@ module s6 if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0; diff --git a/testfiles/issue79/CSR.sv b/testfiles/issue79/CSR.sv index fa54d86a..5251de55 100644 --- a/testfiles/issue79/CSR.sv +++ b/testfiles/issue79/CSR.sv @@ -99,22 +99,22 @@ module csr if (!rst_n_i) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb_we_i)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb_we_i)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb_we_i) & !wb_rip; + assign rd_req_int = (wb_en & ~wb_we_i) & ~wb_rip; always @(posedge(clk_i) or negedge(rst_n_i)) begin if (!rst_n_i) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb_we_i)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb_we_i)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb_we_i) & !wb_wip; + assign wr_req_int = (wb_en & wb_we_i) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb_ack_o = ack_int; - assign wb_stall_o = !ack_int & wb_en; + assign wb_stall_o = ~ack_int & wb_en; assign wb_rty_o = 1'b0; assign wb_err_o = 1'b0; @@ -169,8 +169,8 @@ module csr end else begin - i2c_master_rt <= (i2c_master_rt | i2c_master_re) & !i2c_master_rack; - i2c_master_wt <= (i2c_master_wt | i2c_master_we) & !i2c_master_wack; + i2c_master_rt <= (i2c_master_rt | i2c_master_re) & ~i2c_master_rack; + i2c_master_wt <= (i2c_master_wt | i2c_master_we) & ~i2c_master_wack; end end assign i2c_master_cyc_o = i2c_master_tr; @@ -181,13 +181,13 @@ module csr always @(wr_sel_d0) begin i2c_master_sel_o <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) i2c_master_sel_o[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) i2c_master_sel_o[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) i2c_master_sel_o[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) i2c_master_sel_o[3] <= 1'b1; end assign i2c_master_we_o = i2c_master_wt; @@ -221,13 +221,13 @@ module csr always @(wr_sel_d0) begin adc_offs_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) adc_offs_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) adc_offs_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) adc_offs_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) adc_offs_sel_int[3] <= 1'b1; end always @(posedge(clk_i) or negedge(rst_n_i)) @@ -266,13 +266,13 @@ module csr always @(wr_sel_d0) begin adc_meas_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) adc_meas_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) adc_meas_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) adc_meas_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) adc_meas_sel_int[3] <= 1'b1; end always @(posedge(clk_i) or negedge(rst_n_i)) diff --git a/testfiles/issue8/simpleMap_bug.sv b/testfiles/issue8/simpleMap_bug.sv index 2ebca3c2..5ad00aeb 100644 --- a/testfiles/issue8/simpleMap_bug.sv +++ b/testfiles/issue8/simpleMap_bug.sv @@ -24,7 +24,7 @@ module exemple reg [15:0] rd_dat_d0; reg wr_req_d0; reg [19:1] wr_adr_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue8/simpleMap_noBug.sv b/testfiles/issue8/simpleMap_noBug.sv index f44c5767..3186fbdc 100644 --- a/testfiles/issue8/simpleMap_noBug.sv +++ b/testfiles/issue8/simpleMap_noBug.sv @@ -24,7 +24,7 @@ module exemple reg [15:0] rd_dat_d0; reg wr_req_d0; reg [19:1] wr_adr_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue84/sps200CavityControl_as.sv b/testfiles/issue84/sps200CavityControl_as.sv index 7c3a3e68..94164407 100644 --- a/testfiles/issue84/sps200CavityControl_as.sv +++ b/testfiles/issue84/sps200CavityControl_as.sv @@ -97,8 +97,8 @@ module sps200CavityControl_regs reg [31:0] wr_sel_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -141,7 +141,7 @@ module sps200CavityControl_regs assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -150,7 +150,7 @@ module sps200CavityControl_regs rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 19'b0; + rdata <= 32'b0; end else begin @@ -203,13 +203,13 @@ module sps200CavityControl_regs always @(wr_sel_d0) begin hwInfo_wstrb_o <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) hwInfo_wstrb_o[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) hwInfo_wstrb_o[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) hwInfo_wstrb_o[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) hwInfo_wstrb_o[3] <= 1'b1; end assign hwInfo_bready_o = 1'b1; @@ -227,9 +227,9 @@ module sps200CavityControl_regs end else begin - hwInfo_aw_val <= hwInfo_wr | (hwInfo_aw_val & !hwInfo_awready_i); - hwInfo_w_val <= hwInfo_wr | (hwInfo_w_val & !hwInfo_wready_i); - hwInfo_ar_val <= hwInfo_rd | (hwInfo_ar_val & !hwInfo_arready_i); + hwInfo_aw_val <= hwInfo_wr | (hwInfo_aw_val & ~hwInfo_awready_i); + hwInfo_w_val <= hwInfo_wr | (hwInfo_w_val & ~hwInfo_wready_i); + hwInfo_ar_val <= hwInfo_rd | (hwInfo_ar_val & ~hwInfo_arready_i); end end @@ -242,13 +242,13 @@ module sps200CavityControl_regs always @(wr_sel_d0) begin app_wstrb_o <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) app_wstrb_o[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) app_wstrb_o[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) app_wstrb_o[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) app_wstrb_o[3] <= 1'b1; end assign app_bready_o = 1'b1; @@ -266,9 +266,9 @@ module sps200CavityControl_regs end else begin - app_aw_val <= app_wr | (app_aw_val & !app_awready_i); - app_w_val <= app_wr | (app_w_val & !app_wready_i); - app_ar_val <= app_rd | (app_ar_val & !app_arready_i); + app_aw_val <= app_wr | (app_aw_val & ~app_awready_i); + app_w_val <= app_wr | (app_w_val & ~app_wready_i); + app_ar_val <= app_rd | (app_ar_val & ~app_arready_i); end end diff --git a/testfiles/issue87/qsm_regs.sv b/testfiles/issue87/qsm_regs.sv index fb0a82a9..e492e013 100644 --- a/testfiles/issue87/qsm_regs.sv +++ b/testfiles/issue87/qsm_regs.sv @@ -103,22 +103,22 @@ module qsm_regs if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0; @@ -222,7 +222,7 @@ module qsm_regs if (!wb.rst_n) memory_0_mem_readout_rack <= 1'b0; else - memory_0_mem_readout_rack <= memory_0_mem_readout_re & !memory_0_mem_readout_rack; + memory_0_mem_readout_rack <= memory_0_mem_readout_re & ~memory_0_mem_readout_rack; end assign memory_0_mem_readout_addr_o = adr_int[8:2]; @@ -232,7 +232,7 @@ module qsm_regs if (!wb.rst_n) memory_1_mem_readout_rack <= 1'b0; else - memory_1_mem_readout_rack <= memory_1_mem_readout_re & !memory_1_mem_readout_rack; + memory_1_mem_readout_rack <= memory_1_mem_readout_re & ~memory_1_mem_readout_rack; end assign memory_1_mem_readout_addr_o = adr_int[8:2]; diff --git a/testfiles/issue89/map.sv b/testfiles/issue89/map.sv index 850f69a8..9e37f989 100644 --- a/testfiles/issue89/map.sv +++ b/testfiles/issue89/map.sv @@ -32,7 +32,7 @@ module map1 wire m1_wr; wire m1_wreq; reg [5:0] m1_adr_int; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/issue9/test.sv b/testfiles/issue9/test.sv index fa42843b..101d2bdf 100644 --- a/testfiles/issue9/test.sv +++ b/testfiles/issue9/test.sv @@ -67,8 +67,8 @@ module test reg [31:0] wr_dat_d0; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -107,7 +107,7 @@ module test assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -116,7 +116,7 @@ module test rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 3'b0; + rdata <= 32'b0; end else begin diff --git a/testfiles/issue90/bugDPSSRAMbwSel.sv b/testfiles/issue90/bugDPSSRAMbwSel.sv index 5f7a9635..98fb51f9 100644 --- a/testfiles/issue90/bugDPSSRAMbwSel.sv +++ b/testfiles/issue90/bugDPSSRAMbwSel.sv @@ -59,8 +59,8 @@ module bugDPSSRAMbwSel reg [3:0] mem_sel_int; // AW, W and B channels - assign awready = !axi_awset; - assign wready = !axi_wset; + assign awready = ~axi_awset; + assign wready = ~axi_wset; assign bvalid = axi_wdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -103,7 +103,7 @@ module bugDPSSRAMbwSel assign bresp = 2'b00; // AR and R channels - assign arready = !axi_arset; + assign arready = ~axi_arset; assign rvalid = axi_rdone; always @(posedge(aclk) or negedge(areset_n)) begin @@ -112,7 +112,7 @@ module bugDPSSRAMbwSel rd_req <= 1'b0; axi_arset <= 1'b0; axi_rdone <= 1'b0; - rdata <= 18'b0; + rdata <= 32'b0; end else begin @@ -191,13 +191,13 @@ module bugDPSSRAMbwSel always @(wr_sel_d0) begin mem_sel_int <= 4'b0; - if (!(wr_sel_d0[7:0] == 8'b0)) + if (~(wr_sel_d0[7:0] == 8'b0)) mem_sel_int[0] <= 1'b1; - if (!(wr_sel_d0[15:8] == 8'b0)) + if (~(wr_sel_d0[15:8] == 8'b0)) mem_sel_int[1] <= 1'b1; - if (!(wr_sel_d0[23:16] == 8'b0)) + if (~(wr_sel_d0[23:16] == 8'b0)) mem_sel_int[2] <= 1'b1; - if (!(wr_sel_d0[31:24] == 8'b0)) + if (~(wr_sel_d0[31:24] == 8'b0)) mem_sel_int[3] <= 1'b1; end always @(posedge(aclk) or negedge(areset_n)) @@ -205,7 +205,7 @@ module bugDPSSRAMbwSel if (!areset_n) mem_r1_rack <= 1'b0; else - mem_r1_rack <= (mem_r1_rreq & !mem_wreq) & !mem_r1_rack; + mem_r1_rack <= (mem_r1_rreq & ~mem_wreq) & ~mem_r1_rack; end // Process for write requests. @@ -225,7 +225,7 @@ module bugDPSSRAMbwSel mem_r1_rreq <= 1'b0; // Memory mem rd_dat_d0 <= {24'b000000000000000000000000, mem_r1_int_dato}; - mem_r1_rreq <= rd_req & !mem_wreq; + mem_r1_rreq <= rd_req & ~mem_wreq; rd_ack_d0 <= mem_r1_rack; end endmodule diff --git a/testfiles/issue92/blockInMap.sv b/testfiles/issue92/blockInMap.sv index cd79f27f..692813e2 100644 --- a/testfiles/issue92/blockInMap.sv +++ b/testfiles/issue92/blockInMap.sv @@ -17,7 +17,7 @@ module blockInMap reg rd_ack_d0; reg [31:0] rd_dat_d0; reg wr_req_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/memory01/mainMap.sv b/testfiles/memory01/mainMap.sv index 33f53544..3b29d872 100644 --- a/testfiles/memory01/mainMap.sv +++ b/testfiles/memory01/mainMap.sv @@ -26,7 +26,7 @@ module mainMap reg rd_ack_d0; reg [31:0] rd_dat_d0; reg wr_req_d0; - assign rst_n = !Rst; + assign rst_n = ~Rst; assign VMERdDone = rd_ack_int; assign VMEWrDone = wr_ack_int; diff --git a/testfiles/memory01/sramro.sv b/testfiles/memory01/sramro.sv index d31f057e..9b57a1ae 100644 --- a/testfiles/memory01/sramro.sv +++ b/testfiles/memory01/sramro.sv @@ -33,22 +33,22 @@ module sramro if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0; @@ -74,7 +74,7 @@ module sramro if (!wb.rst_n) mymem_rack <= 1'b0; else - mymem_rack <= mymem_re & !mymem_rack; + mymem_rack <= mymem_re & ~mymem_rack; end assign mymem_addr_o = adr_int[7:2]; diff --git a/testfiles/memory01/sramrw.sv b/testfiles/memory01/sramrw.sv index a92af35c..a609fdd9 100644 --- a/testfiles/memory01/sramrw.sv +++ b/testfiles/memory01/sramrw.sv @@ -39,22 +39,22 @@ module sramrw if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0; @@ -82,7 +82,7 @@ module sramrw if (!wb.rst_n) mymem_rack <= 1'b0; else - mymem_rack <= mymem_re & !mymem_rack; + mymem_rack <= mymem_re & ~mymem_rack; end assign mymem_data_o = wr_dat_d0; always @(posedge(wb.clk) or negedge(wb.rst_n)) @@ -92,7 +92,7 @@ module sramrw else mymem_wp <= (wr_req_d0 | mymem_wp) & rd_req_int; end - assign mymem_we = (wr_req_d0 | mymem_wp) & !rd_req_int; + assign mymem_we = (wr_req_d0 | mymem_wp) & ~rd_req_int; always @(adr_int, wr_adr_d0, mymem_re) if (mymem_re == 1'b1) mymem_addr_o <= adr_int[7:2]; diff --git a/testfiles/memory01/sramwo.sv b/testfiles/memory01/sramwo.sv index df185010..82b5f2da 100644 --- a/testfiles/memory01/sramwo.sv +++ b/testfiles/memory01/sramwo.sv @@ -34,22 +34,22 @@ module sramwo if (!wb.rst_n) wb_rip <= 1'b0; else - wb_rip <= (wb_rip | (wb_en & !wb.we)) & !rd_ack_int; + wb_rip <= (wb_rip | (wb_en & ~wb.we)) & ~rd_ack_int; end - assign rd_req_int = (wb_en & !wb.we) & !wb_rip; + assign rd_req_int = (wb_en & ~wb.we) & ~wb_rip; always @(posedge(wb.clk) or negedge(wb.rst_n)) begin if (!wb.rst_n) wb_wip <= 1'b0; else - wb_wip <= (wb_wip | (wb_en & wb.we)) & !wr_ack_int; + wb_wip <= (wb_wip | (wb_en & wb.we)) & ~wr_ack_int; end - assign wr_req_int = (wb_en & wb.we) & !wb_wip; + assign wr_req_int = (wb_en & wb.we) & ~wb_wip; assign ack_int = rd_ack_int | wr_ack_int; assign wb.ack = ack_int; - assign wb.stall = !ack_int & wb_en; + assign wb.stall = ~ack_int & wb_en; assign wb.rty = 1'b0; assign wb.err = 1'b0;