From 4a1aba26f510209caa0ed02df7accb7fa60ddba3 Mon Sep 17 00:00:00 2001
From: Stefan Lippuner <3071885+stefanlippuner@users.noreply.github.com>
Date: Sat, 4 Nov 2023 18:14:08 +0100
Subject: [PATCH] Fix RTL generation issues

---
 proto/cheby/hdl/axi4litebus.py |  2 +-
 proto/cheby/hdl/genmemory.py   |  3 ++-
 proto/cheby/hdl/wbbus.py       | 30 +++++++++++++++++++++---------
 proto/cheby/print_verilog.py   | 17 ++++++++++++++---
 4 files changed, 38 insertions(+), 14 deletions(-)

diff --git a/proto/cheby/hdl/axi4litebus.py b/proto/cheby/hdl/axi4litebus.py
index 9109f06a..03ae6cdd 100644
--- a/proto/cheby/hdl/axi4litebus.py
+++ b/proto/cheby/hdl/axi4litebus.py
@@ -218,7 +218,7 @@ def expand_bus_r(self, root, module, ibus, opts):
 
             module.stmts.append(HDLAssign(axi_rerr, RESP_OKAY))
         proc.rst_stmts.append(
-            HDLAssign(root.h_bus['rdata'], HDLReplicate(bit_0, root.c_addr_bits)))
+            HDLAssign(root.h_bus['rdata'], HDLReplicate(bit_0, root.c_word_bits)))
 
         proc.sync_stmts.append(HDLAssign(ibus.rd_req, bit_0))
         if opts.bus_error:
diff --git a/proto/cheby/hdl/genmemory.py b/proto/cheby/hdl/genmemory.py
index 5d9c4d66..0b748709 100644
--- a/proto/cheby/hdl/genmemory.py
+++ b/proto/cheby/hdl/genmemory.py
@@ -138,8 +138,9 @@ def gen_processes_reg(self, ibus, reg):
             if ibus.wr_sel is not None:
                 # Translate bit-wise write mask of internal bus to Byte-wise write mask
                 # of memory
+                mem_name = mem.c_name + '_' + str(i) if multiword else mem.c_name
                 bwselw_int = self.module.new_HDLSignal(
-                    mem.c_name + "_sel_int", self.root.c_word_bits // tree.BYTE_SIZE
+                    mem_name + "_sel_int", self.root.c_word_bits // tree.BYTE_SIZE
                 )
 
                 proc = HDLComb()
diff --git a/proto/cheby/hdl/wbbus.py b/proto/cheby/hdl/wbbus.py
index ff1e392c..fa0500fa 100644
--- a/proto/cheby/hdl/wbbus.py
+++ b/proto/cheby/hdl/wbbus.py
@@ -248,15 +248,27 @@ def gen_bus_slave(self, root, module, prefix, n, opts):
     def slice_addr(self, addr, root, n):
         """Slice the input :param addr: (from the root bus) so that is can be
         assigned to the slave.  Take care of various sizes."""
-        res = HDLSlice(addr, root.c_addr_word_bits, n.c_addr_bits)
-        if not n.h_busgroup:
-            return res
-        if n.c_addr_bits < 32:
-            res = HDLConcat(HDLReplicate(
-                bit_0, 32 - root.c_addr_word_bits - n.c_addr_bits, False), res)
-        if root.c_addr_word_bits > 0:
-            res = HDLConcat(res,
-                            HDLReplicate(bit_0, root.c_addr_word_bits, False))
+        if n.c_addr_bits > 0:
+            res = HDLSlice(addr, root.c_addr_word_bits, n.c_addr_bits)
+        else:
+            res = None
+
+        if n.h_busgroup:
+            if n.c_addr_bits < 32:
+                repl = HDLReplicate(bit_0, 32 - root.c_addr_word_bits - n.c_addr_bits, False)
+                if res is None:
+                    res = repl
+                else:
+                    res = HDLConcat(repl, res)
+            if root.c_addr_word_bits > 0:
+                repl = HDLReplicate(bit_0, root.c_addr_word_bits, False)
+                if res is None:
+                    res = repl
+                else:
+                    res = HDLConcat(res, repl)
+
+        if res is None:
+            raise AssertionError('Sliced address is empty')
         return res
 
     def wire_bus_slave(self, root, module, n, ibus):
diff --git a/proto/cheby/print_verilog.py b/proto/cheby/print_verilog.py
index c8841eb3..fe86de43 100644
--- a/proto/cheby/print_verilog.py
+++ b/proto/cheby/print_verilog.py
@@ -73,6 +73,14 @@ def generate_interface_modport(fd, itf, dirn, dirname):
             w(fd, " {}".format(p.name))
     return not first
 
+# Check if the interface has a port with the given direction dirn
+def generate_interface_has_dir(itf, dirn):
+    for p in itf.ports:
+        if p.dir == dirn:
+            return True
+    return False
+
+
 def generate_interface(fd, itf, indent):
     generate_decl_comment(fd, itf.comment, indent)
     windent(fd, indent)
@@ -81,16 +89,19 @@ def generate_interface(fd, itf, indent):
         windent(fd, indent + 1)
         wln(fd, "logic {}{};".format(generate_verilog_type(p), p.name))
     windent(fd, indent + 1)
+
+    has_in = generate_interface_has_dir(itf, 'IN')
+    has_out = generate_interface_has_dir(itf, 'OUT')
     w(fd, "modport master(")
     p = generate_interface_modport(fd, itf, 'IN', 'input')
-    if p:
+    if has_in and has_out:
         w(fd, ', ')
     generate_interface_modport(fd, itf, 'OUT', 'output')
     wln(fd, ');')
     windent(fd, indent + 1)
     w(fd, "modport slave(")
     p = generate_interface_modport(fd, itf, 'IN', 'output')
-    if p:
+    if has_in and has_out:
         w(fd, ', ')
     generate_interface_modport(fd, itf, 'OUT', 'input')
     wln(fd, ');')
@@ -148,7 +159,7 @@ def generate_decl(fd, d, indent):
 
 operator = {hdltree.HDLAnd: (' & ', 4),
             hdltree.HDLOr:  (' | ', 3),
-            hdltree.HDLNot: ('!', 5),
+            hdltree.HDLNot: ('~', 5),
             hdltree.HDLSub: ('-', 1),
             hdltree.HDLMul: ('*', 2),
             hdltree.HDLEq:  (' == ', 5),