From ce3d362a42ff040c63933a27962eb3f979ecaffd Mon Sep 17 00:00:00 2001 From: Shannon Kinkead Date: Wed, 31 Jul 2024 12:04:50 -0600 Subject: [PATCH] adding statistics and simulation links --- .../vanadis/examples/vanadis_L1_L2_L3.py | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/sst/elements/vanadis/examples/vanadis_L1_L2_L3.py b/src/sst/elements/vanadis/examples/vanadis_L1_L2_L3.py index 8f4d92045d..e98240a010 100644 --- a/src/sst/elements/vanadis/examples/vanadis_L1_L2_L3.py +++ b/src/sst/elements/vanadis/examples/vanadis_L1_L2_L3.py @@ -53,4 +53,19 @@ memory.addParams({ "access_time" : "1000ns", "mem_size" : "512MiB" -}) \ No newline at end of file +}) + + + +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") +for a in componentlist: + sst.enableAllStatisticsForComponentType(a) + + +# Define the simulation links +link_cpu_cache_link = sst.Link("link_cpu_cache_link") +link_cpu_cache_link.connect( (iface, "port", "1000ps"), (l1cache, "high_network_0", "1000ps") ) +link_mem_bus_link = sst.Link("link_mem_bus_link") +link_mem_bus_link.connect( (l1cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") )