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Note that this concerns a src/util file, and therefore may be out of the scope of Sparkfun contributions.
in dmp_set_fifo_rate() (line 648 of src/util/inv_mpu_dmp_motion_driver.c), I had to change the function to reflect that the DMP FIFO rate appeared to be 4x larger than what I expected it to be:
Other relevant configuration is that gyro was set to 1kHz (DLPF_CFG to 0x01) since I read in the datasheet that DMP would not function if there was an 8kHz sampling rate, which is default for gyro. Note that accel sampling rate is 1kHz by default.
However, when I set the SMPLRT_DIV to 0x04 (i.e. 1kHz/(4+1) = 200Hz), I get frequencies that I would expect based on the existing code.
And finally, when I set the SMPLRT_DIV to 0x09 (i.e. 1kHz/(9+1) = 100Hz), I get frequencies that are 2x small than expected.
My point is that the DMP FIFO rate appears dependent on SMPLRT_DIV. That relationship seems to be that the DMP FIFO further subdivides SMPLRT_DIV, but maxes out at 800Hz. Therefore, dmp_set_fifo_rate() assumes SMPLRT_DIV = 0x04 s.t. 1kHz/(4+1) = 200Hz.
The text was updated successfully, but these errors were encountered:
Note that this concerns a src/util file, and therefore may be out of the scope of Sparkfun contributions.
in dmp_set_fifo_rate() (line 648 of src/util/inv_mpu_dmp_motion_driver.c), I had to change the function to reflect that the DMP FIFO rate appeared to be 4x larger than what I expected it to be:
div hz_expected hz_actual
0 200 800
1 100 400
3 50 200
4 40 160
7 25 100
15 12.5 50
Other relevant configuration is that gyro was set to 1kHz (DLPF_CFG to 0x01) since I read in the datasheet that DMP would not function if there was an 8kHz sampling rate, which is default for gyro. Note that accel sampling rate is 1kHz by default.
However, when I set the SMPLRT_DIV to 0x04 (i.e. 1kHz/(4+1) = 200Hz), I get frequencies that I would expect based on the existing code.
And finally, when I set the SMPLRT_DIV to 0x09 (i.e. 1kHz/(9+1) = 100Hz), I get frequencies that are 2x small than expected.
My point is that the DMP FIFO rate appears dependent on SMPLRT_DIV. That relationship seems to be that the DMP FIFO further subdivides SMPLRT_DIV, but maxes out at 800Hz. Therefore, dmp_set_fifo_rate() assumes SMPLRT_DIV = 0x04 s.t. 1kHz/(4+1) = 200Hz.
The text was updated successfully, but these errors were encountered: