diff --git a/src/aarch64.rs b/src/aarch64.rs index d71fcd60..d6869d9a 100644 --- a/src/aarch64.rs +++ b/src/aarch64.rs @@ -1,7 +1,19 @@ -#![allow(clippy::integer_arithmetic)] +#![allow(clippy::arithmetic_side_effects)] #![allow(clippy::upper_case_acronyms)] -#![allow(clippy::needless_update)] -use crate::jit::{emit, JitCompilerCore, OperandSize}; +#![allow(dead_code)] +use crate::{ + jit::{JitCompiler, OperandSize}, + vm::ContextObject, +}; + +macro_rules! exclude_operand_sizes { + ($size:expr, $($to_exclude:path)|+ $(,)?) => { + debug_assert!(match $size { + $($to_exclude)|+ => false, + _ => true, + }); + } +} pub const X0: u8 = 0; pub const X1: u8 = 1; @@ -100,7 +112,7 @@ pub enum ARM64MemoryOperand { } // Instructions are broken up based on the encoding scheme used -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub enum ARM64Instruction { LogicalRegister(ARM64InstructionLogicalShiftedRegister), AddSubRegister(ARM64InstructionLogicalShiftedRegister), @@ -119,7 +131,7 @@ pub enum ARM64Instruction { RET, } -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionLogicalShiftedRegister { pub size: OperandSize, pub opcode: u8, // 2 bits @@ -146,7 +158,7 @@ impl Default for ARM64InstructionLogicalShiftedRegister { } } -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionDataProcessing { pub size: OperandSize, pub opcode: u8, // 6 bits @@ -171,7 +183,7 @@ impl Default for ARM64InstructionDataProcessing { } } -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionAddSubImm { pub size: OperandSize, pub opcode: u8, // 1 bit @@ -196,7 +208,7 @@ impl Default for ARM64InstructionAddSubImm { } } -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionLogicalImm { pub size: OperandSize, pub opcode: u8, // 2 bits @@ -221,7 +233,7 @@ impl Default for ARM64InstructionLogicalImm { } } -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionWideImm { pub size: OperandSize, pub opcode: u8, // 2 bits @@ -242,26 +254,26 @@ impl Default for ARM64InstructionWideImm { } } -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionConditonalBranch { pub cond: u8, // 4 bits pub imm19: i32, // offset from current instruction, divided by 4 } -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionImm26 { pub opcode: u8, // 6 bits pub imm26: i32, // offset from current instruction, divided by 4 } -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionBLR { pub target: u8, // 5 bit target register } // Load -#[derive(PartialEq, Eq, Copy, Clone)] +#[derive(Copy, Clone)] pub struct ARM64InstructionLoadStore { pub size: OperandSize, pub data: u8, // Rt, 5 bits @@ -281,7 +293,7 @@ impl Default for ARM64InstructionLoadStore { } impl ARM64Instruction { - pub fn emit(&self, jit: &mut JitCompilerCore) { + pub fn emit(&self, jit: &mut JitCompiler) { let mut ins: u32 = 0; match self { @@ -484,7 +496,7 @@ impl ARM64Instruction { } } - emit::(jit, ins); + jit.emit::(ins); } /// Move source to destination @@ -564,7 +576,6 @@ impl ARM64Instruction { imms: imm.imms, dest: SP_XZR, // discard result src: source, - ..ARM64InstructionLogicalImm::default() }) } @@ -697,7 +708,6 @@ impl ARM64Instruction { imms: 7, dest: destination, src: source, - ..ARM64InstructionLogicalImm::default() }), // SXTH OperandSize::S16 => Self::BitfieldImm(ARM64InstructionLogicalImm { @@ -708,7 +718,6 @@ impl ARM64Instruction { imms: 15, dest: destination, src: source, - ..ARM64InstructionLogicalImm::default() }), // SXTW OperandSize::S32 => Self::BitfieldImm(ARM64InstructionLogicalImm { @@ -719,7 +728,6 @@ impl ARM64Instruction { imms: 31, dest: destination, src: source, - ..ARM64InstructionLogicalImm::default() }), OperandSize::S0 | OperandSize::S64 => { panic!("zero_extend is only valid on S8, S16, and S32") @@ -738,7 +746,6 @@ impl ARM64Instruction { imms: 63 - shift_imm, dest: destination, src: source, - ..ARM64InstructionLogicalImm::default() }) } @@ -765,7 +772,6 @@ impl ARM64Instruction { imms: 0b111111, dest: destination, src: source, - ..ARM64InstructionLogicalImm::default() }) } @@ -891,8 +897,7 @@ impl ARM64Instruction { /// Load data from [source + offset] #[must_use] pub fn load(size: OperandSize, source: u8, indirect: ARM64MemoryOperand, data: u8) -> Self { - debug_assert_ne!(size, OperandSize::S0); - debug_assert_ne!(size, OperandSize::S0); + exclude_operand_sizes!(size, OperandSize::S0); match indirect { ARM64MemoryOperand::OffsetPreIndex(_) | ARM64MemoryOperand::OffsetPostIndex(_) => { // in arm64, loads with writeback to the base register cannot also use this @@ -911,7 +916,7 @@ impl ARM64Instruction { #[must_use] pub fn store(size: OperandSize, data: u8, source: u8, indirect: ARM64MemoryOperand) -> Self { - debug_assert_ne!(size, OperandSize::S0); + exclude_operand_sizes!(size, OperandSize::S0); match indirect { ARM64MemoryOperand::OffsetPreIndex(_) | ARM64MemoryOperand::OffsetPostIndex(_) => { // in arm64, loads with writeback to the base register cannot also use this @@ -981,7 +986,6 @@ impl ARM64Instruction { src2, src3, o0: 1, - ..ARM64InstructionDataProcessing::default() }) } diff --git a/src/lib.rs b/src/lib.rs index 48ce93a5..7aaa25fe 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -40,7 +40,11 @@ pub mod error; pub mod fuzz; pub mod insn_builder; pub mod interpreter; -#[cfg(all(feature = "jit", not(target_os = "windows"), target_arch = "x86_64"))] +#[cfg(all( + feature = "jit", + not(target_os = "windows"), + any(target_arch = "aarch64", target_arch = "x86_64") +))] mod jit; #[cfg(feature = "jit")] mod memory_management; diff --git a/src/x86.rs b/src/x86.rs index 9d33ba7f..eaaa1384 100644 --- a/src/x86.rs +++ b/src/x86.rs @@ -4,6 +4,15 @@ use crate::{ vm::ContextObject, }; +macro_rules! exclude_operand_sizes { + ($size:expr, $($to_exclude:path)|+ $(,)?) => { + debug_assert!(match $size { + $($to_exclude)|+ => false, + _ => true, + }); + } +} + pub const RAX: u8 = 0; pub const RCX: u8 = 1; pub const RDX: u8 = 2; @@ -27,16 +36,6 @@ pub const ARGUMENT_REGISTERS: [u8; 6] = [RDI, RSI, RDX, RCX, R8, R9]; pub const CALLER_SAVED_REGISTERS: [u8; 9] = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11]; pub const CALLEE_SAVED_REGISTERS: [u8; 6] = [RBP, RBX, R12, R13, R14, R15]; -macro_rules! exclude_operand_sizes { - ($size:expr, $($to_exclude:path)|+ $(,)?) => { - #[cfg(debug_assertions)] - match $size { - $($to_exclude)|+ => return Self::DEFAULT, - _ => {}, - } - } -} - struct X86Rex { w: bool, r: bool,