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Releases: slaclab/surf

v2.3.0

15 Apr 15:24
@ruck314 ruck314
v2.3.0
15c7aa5
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v2.3.0

Pull Requests Since v2.2.0

Bug

  1. #649 - Fix ruckus checkout branch

Enhancement

  1. #645 - Add auto release generation

Unlabeled

  1. #652 - release candidate v2.3.0
  2. #647 - Remove whitespace
  3. #644 - Add analog devices python for LLRF
  4. #646 - Converting BoxcarIntegrator.vhd to signed
  5. #651 - Fix bad baud rate counter
  6. #650 - adding dual AXI stream types
  7. #648 - missing surf library causing VCS error

Pull Request Details

Add analog devices python for LLRF
Author: Larry Ruckman [email protected]
Date: Wed Apr 1 15:45:47 2020 -0700
Pull: #644 (325 additions, 6 deletions, 5 files changed)
Branch: slaclab/llrf-python

Notes:

Description

  • Adding AttHmc624, Ad5541 and Adt7420

Add auto release generation
Author: Larry Ruckman [email protected]
Date: Mon Apr 13 11:57:23 2020 -0700
Pull: #645 (11 additions, 1 deletions, 1 files changed)
Branch: slaclab/release_gen
Labels: enhancement

Notes:

This adds auto release generation. Once a tag is pushed the release and release notes will be auto generated.

Converting BoxcarIntegrator.vhd to signed
Author: Larry Ruckman [email protected]
Date: Tue Apr 14 11:11:20 2020 -0700
Pull: #646 (131 additions, 85 deletions, 4 files changed)
Branch: slaclab/boxcarIntSigned

Notes:

Converting BoxcarIntegrator.vhd to signed

Remove whitespace
Author: Larry Ruckman [email protected]
Date: Mon Apr 13 08:49:28 2020 -0700
Pull: #647 (9719 additions, 9719 deletions, 719 files changed)
Branch: slaclab/remove-whitespace

Notes:

Description

  • removing white space from YAML files
  • removing white space from Verilog files
  • removing white space from VHDL files

missing surf library causing VCS error
Author: Larry Ruckman [email protected]
Date: Fri Apr 10 16:06:55 2020 -0700
Pull: #648 (2 additions, 0 deletions, 1 files changed)
Branch: slaclab/ePix-dev

Notes:

Just added surf library to Gtp7AutoPhaseAligner.vhd to avoid VCS failed compilation.

Fix ruckus checkout branch
Author: Larry Ruckman [email protected]
Date: Mon Apr 13 15:01:38 2020 -0700
Pull: #649 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/release_gen
Labels: bug

Notes:

Checkout master branch for ruckus release scripts.

adding dual AXI stream types
Author: Larry Ruckman [email protected]
Date: Tue Apr 14 10:45:11 2020 -0700
Pull: #650 (6 additions, 0 deletions, 1 files changed)
Branch: slaclab/AxiStreamPkg-update

Notes:

Description

  • Useful types to have pre-defined (similar to QUAD and OCTAL types)

Fix bad baud rate counter
Author: Larry Ruckman [email protected]
Date: Tue Apr 14 08:12:14 2020 -0700
Pull: #651 (10 additions, 9 deletions, 2 files changed)
Branch: slaclab/uart_fix

Notes:

Description

The previous UART implementation did not account for the output and sample clock periods.

release candidate v2.3.0
Author: Larry Ruckman [email protected]
Date: Wed Apr 15 08:21:12 2020 -0700
Pull: #652 (10190 additions, 9816 deletions, 725 files changed)
Branch: slaclab/pre-release
Issues: #644, #648, #647, #651, #650, #646

Notes:

Description

  • Add analog devices python for LLRF #644
  • missing surf library causing VCS error #648
  • Remove whitespace #647
  • Fix bad baud rate counter #651
  • adding dual AXI stream types #650
  • Converting BoxcarIntegrator.vhd to signed #646
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Minor Release

27 Mar 15:18
@ruck314 ruck314
v2.2.0
ae705c7
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Minor Release

Pull Requests

  1. #639 - Add external blowoff input to AxiStreamBatcherEventBuilder
  2. #640 - SURF/ETH/DHCP: reset FSM if MAC address changes
  3. #532 - AxiStreamBytePacker bug fix
  4. #642 - prevent a MAC address = 0x0 doing a DHCP request

Pull Request Details

Add external blowoff input to AxiStreamBatcherEventBuilder
Author: Benjamin Reese [email protected]
Date: Thu Mar 26 15:18:12 2020 -0700
Pull: #639 (26 additions, 6 deletions, 2 files changed)
Branch: slaclab/asbeb-blowoff

Notes:

Description

Details

This adds an external blowoff input to the AxiStreamBatcherEventBuilder and creates a new register for viewing the external input status.

JIRA

Related

SURF/ETH/DHCP: reset FSM if MAC address changes
Author: Larry Ruckman [email protected]
Date: Tue Mar 24 15:06:34 2020 -0700
Pull: #640 (16 additions, 8 deletions, 1 files changed)
Branch: slaclab/ESCORE-547
Jira: https://jira.slac.stanford.edu/issues/ESCORE-547

Notes:

Description

  • Typically this does not in a lot of our FW builds because the MAC is in the eFUSE
  • But I discovered this race condition bug in the ATLAS ATCA Link Agg FW MAC address should potential change at boot up and have to wait > 8 hours until DHCP lease expires before getting the correct IP address.

AxiStreamBytePacker bug fix
Author: Larry Ruckman [email protected]
Date: Thu Mar 26 17:50:28 2020 -0700
Pull: #532 (1 additions, 14 deletions, 1 files changed)
Branch: slaclab/mw-master-AxiStreamBytePacker

Notes:

Description

  • Shift next to current only if nxt is not full

prevent a MAC address = 0x0 doing a DHCP request
Author: Larry Ruckman [email protected]
Date: Thu Mar 26 10:40:46 2020 -0700
Pull: #642 (5 additions, 3 deletions, 1 files changed)
Branch: slaclab/dhcp-patch

Notes:

Description

  • While MAC address = 00:00:00:00:00:00 is technically a valid Ethernet MAC address, we are using MAC = 00:00:00:00:00:00 (0x0) as an invalid MAC address in the SURF FW
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Patch Release

18 Mar 16:39
@ruck314 ruck314
v2.1.3
c4a01ef
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Patch Release

Pull Requests

  1. #638 - v2.1.3 release candidate
  2. #636 - Bug Fix for EM22xx python device
  3. #637 - AxiAds42lb69Pll.vhd: include IBUFGDS when USE_FBCLK_G = false

Pull Request Details

v2.1.3 release candidate
Author: Larry Ruckman [email protected]
Date: Wed Mar 18 09:37:03 2020 -0700
Pull: #638 (253 additions, 177 deletions, 4 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Bug Fix for EM22xx python device #636
  • AxiAds42lb69Pll.vhd: include IBUFGDS when USE_FBCLK_G = false #637

Bug Fix for EM22xx python device
Author: Larry Ruckman [email protected]
Date: Wed Mar 11 13:52:37 2020 -0700
Pull: #636 (194 additions, 132 deletions, 3 files changed)
Branch: slaclab/ESCRYODET-614
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-614

Notes:

Description

  • bug fix for LITERAL v.s. linear data format with respect to PMbus specs
  • adding simpleDisplay arg and auto-poll for status registers to python/surf/protocols/i2c/_PMBus.py

AxiAds42lb69Pll.vhd: include IBUFGDS when USE_FBCLK_G = false
Author: Larry Ruckman [email protected]
Date: Thu Mar 12 17:24:14 2020 -0700
Pull: #637 (59 additions, 45 deletions, 1 files changed)
Branch: slaclab/wave8-ruckman

Notes:

Description

  • Resolves issue of ports being unconnected/unterminated
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Minor Release

28 Feb 00:26
@ruck314 ruck314
v2.1.0
7874053
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Minor Release

Pull Requests

  1. #617 - Flake8
  2. #627 - Refactor RELEASE_DELAY_G Generic in Synchronization Modules
  3. #622 - Clean up SynchronizerOneShot
  4. #623 - SRPv0 Updates
  5. #612 - adding 185.71 MHz refClk support to pgp3/gthUs for 10.3125 Gb/s
  6. #626 - CDC fix. Use synchornized localMac
  7. #621 - CDC patch for SynchronizerOneShotCntVector and IprogUltraScale
  8. #616 - Remove mac os from conda builds
  9. #620 - 1GbE GTP7 Simulation Bug Fix
  10. #591 - bug fix for adc32rf45
  11. #624 - Fix bug in _Xadc.py
  12. #618 - missing surf library
  13. #615 - Added missing surf library
  14. #614 - Change python package name to lower case
  15. #619 - Rename tox.ini to .flake8

Pull Request Details

Flake8
Author: Larry Ruckman [email protected]
Date: Thu Feb 20 21:16:43 2020 -0800
Pull: #617 (7255 additions, 7716 deletions, 118 files changed)
Branch: slaclab/flake8

Notes:

Description

  • Added python linter to travic CI
  • Fixed some bugs in the python code
    • Caught by the linter
  • Some misc. code header clean up
  • Remove name and description args when they don't differ from the default

Refactor RELEASE_DELAY_G Generic in Synchronization Modules
Author: Benjamin Reese [email protected]
Date: Thu Feb 27 15:14:27 2020 -0800
Pull: #627 (219 additions, 231 deletions, 8 files changed)
Branch: slaclab/release-delay-fix

Notes:

Description

The RELEASE_DELAY_G generic was either not used, not necessary, or improperly named in several modules.

Details

The RELEASE_DELAY_G generic has been modified in the following modules:

  • AxiLiteSyncStatusVector - Unused, removed.
  • SyncStatusVector - Renamed to SYNC_STAGES_G
  • SynchronizerOneShotCnt - Unnecessary, removed
  • SynchronizerOneShotCntVector - Unnecessary, removed
  • SynchronizerOneShotVector - Renamed to OUT_DELAY_G

Any modules that instantiate the affected modules above have also been refactors to reflect the changes.

JIRA

Related

Clean up SynchronizerOneShot
Author: Larry Ruckman [email protected]
Date: Thu Feb 27 08:49:13 2020 -0800
Pull: #622 (180 additions, 234 deletions, 7 files changed)
Branch: slaclab/one-shot

Notes:

Description

A code-breaking cleanup of SynchronizerOneShot.

The part that might break existing code is the removal of generics. Simply cutting them from any instantiation should fix it.

Details

  • Fixed rst input and RST_ASYNC_G generic
    • rst was not being driven to the SynchronizerEdge.
    • Pulse stretch logic did not obey RST_ASYC_G.
  • Removed RELEASE_DELAY_G generic
    • Was applied to a RstSync attached to an edge detector.
    • In that setup, the release delay of RstSync doesn't matter, since we're only looking at the edge.
  • Added OUT_DELAY_G generic
    • Allows the output pulse to be delayed by a configurable number of clock cycles.
    • Must be >= 3 because the internal SynchronizerEdge is used to do the delay.
  • Optimized pulse stretch logic
    • No longer driven by combinatorial output.
    • No more state machine. Just looks at the state of r.dataOut to determine if it should be counting.

Misc

  • Changed some SynchronizerOneShot instances to PwrUpRst which is more appropriate to use.
  • Port declaration of SynchronizerOneShotCnt and SynchronizerOneShotCntVector rearranged according to clock domains.

SRPv0 Updates
Author: Larry Ruckman [email protected]
Date: Thu Feb 27 12:14:44 2020 -0800
Pull: #623 (123 additions, 105 deletions, 7 files changed)
Branch: slaclab/SRPv0-dev

Notes:

Description

  • SsiFifo bug fix when GEN_SYNC_FIFO_G=true and SLAVE_AXI_CONFIG_G/=MASTER_AXI_CONFIG_G
  • SrpV0AxiLite code clean up
  • Updating AxiLiteSrpV0Tb.vhd to have a non-32b AXIS interface
  • Updating AxiLiteSrpV0Tb.vhd to 32-bit word addressing
  • AxiStreamMuxTb code clean up
    • Does not use SssiFifo

adding 185.71 MHz refClk support to pgp3/gthUs for 10.3125 Gb/s
Author: Larry Ruckman [email protected]
Date: Wed Feb 26 13:07:10 2020 -0800
Pull: #612 (133 additions, 34 deletions, 3 files changed)
Branch: slaclab/pgp3-gthUs-refclk

Notes:

Description

  • Required for slaclab/l2si-drp
  • Using the same Pgp3GthUsIp10G IP core as the 156.25 MHz but with different QPLL configurations

CDC fix. Use synchornized localMac
Author: Larry Ruckman [email protected]
Date: Thu Feb 27 12:10:33 2020 -0800
Pull: #626 (43 additions, 34 deletions, 6 files changed)
Branch: slaclab/cdc-patch

Notes:

Description

  • CDC fix. Use synchornized localMac

CDC patch for SynchronizerOneShotCntVector and IprogUltraScale
Author: Larry Ruckman [email protected]
Date: Thu Feb 27 08:50:08 2020 -0800
Pull: #621 (72 additions, 5 deletions, 2 files changed)
Branch: slaclab/cdc-patch

Notes:

CDC fix for SynchronizerOneShotCntVector rollOverEn and cntRst.
CDC fix for IprogUltraScale bootAddress.

Description

CDC fix for SynchronizerOneShotCntVector rollOverEn and cntRst.
SynchronizerOneShotCntVector uses SynchronizerOneShotCnt with COMMON_CLK_G => true and synchronizes the status bus outside of SynchronizerOneShotCnt but then rollOverEn and cntRst also need to be sync'd outside.

CDC fix for IprogUltraScale bootAddress
Sync bootAddress to icape2Clk

Details

JIRA

Related

Remove mac os from conda builds
Author: Larry Ruckman [email protected]
Date: Thu Feb 13 10:32:42 2020 -0800
Pull: #616 (8 additions, 8 deletions, 1 files changed)
Branch: slaclab/rem_mac

Notes:

1GbE GTP7 Simulation Bug Fix
Author: Larry Ruckman [email protected]
Date: Wed Feb 26 10:16:53 2020 -0800
Pull: #620 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/gbE-gtp7-sim-bug-fix

Notes:

Description

  • Can't have mix open/assignment bus for VCS simulation

bug fix for adc32rf45
Author: Larry Ruckman [email protected]
Date: Thu Feb 20 14:18:42 2020 -0800
Pull: #591 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/adc32rf45-patch

Notes:

Description

  • Resolves adc32rf45.vhd width mismatch #589
  • This should be tested with hardware before this PR is approved
    • SMURF is the only hardware platform that uses devices/Ti/adc32rf45/rtl/adc32rf45.vhd right now

Fix bug in _Xadc.py
Author: Benjamin Reese [email protected]
Date: Wed Feb 26 11:26:00 2020 -0800
Pull: #624 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/xadc-rogue-fix

Notes:

Add default arg to pollInterval in addPair() so it doesn't need to be specified.

Not sure how this wasn't noticed before.

missing surf library
Author: Larry Ruckman [email protected]
Date: Thu Feb 20 19:31:17 2020 -0800
Pull: #618 (2 additions, 0 deletions, 1 files ...
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Patch Release

09 Mar 19:15
@ruck314 ruck314
v2.1.2
9f3c93f
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Patch Release

Pull Requests

  1. #635 - v2.1.2 release candidate
  2. #632 - Enable flexible baud rate multiplier in UART
  3. #633 - adding devices.nxp.Pca9555.py
  4. #631 - surf.devices.silabs python bug fixes
  5. #634 - GigEthGtp7Wrapper: Resolved namespace conflicts

Pull Request Details

v2.1.2 release candidate
Author: Larry Ruckman [email protected]
Date: Mon Mar 9 12:11:52 2020 -0700
Pull: #635 (178 additions, 112 deletions, 9 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • surf.devices.silabs python bug fixes #631
  • adding devices.nxp.Pca9555.py #633
  • Enable flexible baud rate multiplier in UART #632
  • GigEthGtp7Wrapper: Resolved namespace conflicts #634

Enable flexible baud rate multiplier in UART
Author: Larry Ruckman [email protected]
Date: Sat Mar 7 14:14:26 2020 -0800
Pull: #632 (102 additions, 96 deletions, 4 files changed)
Branch: slaclab/flex_baud

Notes:

This enables the uart to have a flexible baud rate multiplier instead of the default 16x.

adding devices.nxp.Pca9555.py
Author: Larry Ruckman [email protected]
Date: Fri Mar 6 14:43:38 2020 -0800
Pull: #633 (60 additions, 0 deletions, 2 files changed)
Branch: slaclab/nxp-Pca9555

Notes:

Description

  • Used in ATCA Link Agg development

surf.devices.silabs python bug fixes
Author: Larry Ruckman [email protected]
Date: Tue Mar 3 17:31:57 2020 -0800
Pull: #631 (12 additions, 12 deletions, 2 files changed)
Branch: slaclab/ruckman-dev

Notes:

Description

  • Fixed broken python classes

GigEthGtp7Wrapper: Resolved namespace conflicts
Author: Larry Ruckman [email protected]
Date: Mon Mar 9 08:49:13 2020 -0700
Pull: #634 (4 additions, 4 deletions, 1 files changed)
Branch: slaclab/GigEthGtp7Wrapper-update

Notes:

Description

  • There were two refClkOut output ports being mapped
  • Changing the Copy of internal MMCM reference clock and Reset ports' names
    • From refClkOut to mmcmRefClkOut
    • From refRstOut to mmcmRefRstOut
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Patch Release

29 Feb 01:50
@ruck314 ruck314
v2.1.1
ccde696
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Patch Release

Pull Requests

  1. #630 - v2.1.1 release candidate
  2. #629 - fixed bug in PGP2b that caused reset locked up at power up
  3. #628 - fixed the broken clink python modules

Pull Request Details

v2.1.1 release candidate
Author: Larry Ruckman [email protected]
Date: Fri Feb 28 17:46:58 2020 -0800
Pull: #630 (27 additions, 30 deletions, 7 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • fixed the broken clink python modules #628
  • fixed bug in PGP2b that caused reset locked up at power up #629

fixed bug in PGP2b that caused reset locked up at power up
Author: Larry Ruckman [email protected]
Date: Fri Feb 28 14:06:51 2020 -0800
Pull: #629 (17 additions, 19 deletions, 3 files changed)
Branch: slaclab/pgp-bug-fix

Notes:

Description

  • Bug created in PR #622
  • Fixes GTP7, GTH Ultrascale and GTH Ultrascale+
    • No bug in other fabric fabrics

fixed the broken clink python modules
Author: Larry Ruckman [email protected]
Date: Fri Feb 28 13:57:04 2020 -0800
Pull: #628 (10 additions, 11 deletions, 4 files changed)
Branch: slaclab/clink-dev

Notes:

Description

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Patch Release v2.0.7

11 Feb 22:51
@bengineerd bengineerd
v2.0.7
2020d6f
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Patch Release v2.0.7

Pull Requests

  1. #608 - removing #!/usr/bin/env python & misc code header clean up
  2. #611 - Add anaconda release of Surf
  3. #609 - Modify ClinkSerial to show string in sendString and response
  4. #610 - mapping JESD CmdClearErrors() to countReset()

Pull Request Details

Release Candidate - Patch Release v2.0.7

removing #!/usr/bin/env python & misc code header clean up
Author: Larry Ruckman [email protected]
Date: Fri Feb 7 12:35:57 2020 -0800
Pull: #608 (11 additions, 263 deletions, 130 files changed)
Branch: slaclab/py-patch

Notes:

Description

  • removing #!/usr/bin/env python for all non-executable python scripts
  • misc code header clean up

Add anaconda release of Surf
Author: Ryan Herbst [email protected]
Date: Tue Feb 11 11:52:06 2020 -0800
Pull: #611 (161 additions, 0 deletions, 6 files changed)
Branch: slaclab/conda_release

Notes:

This PR add an anaconda release of the surf library

Modify ClinkSerial to show string in sendString and response
Author: Larry Ruckman [email protected]
Date: Fri Feb 7 15:50:01 2020 -0800
Pull: #609 (14 additions, 5 deletions, 3 files changed)
Branch: bhill-slac/serial-diags

Notes:

Camera testing and support is easier if we can see the string being sent and the response.

Description

Adds a print statement in ClinkSerialTx::sendString() to show the msg being sent.
Also adds support for printing the response after the ACK so we can see response
to queries such as serialNumber, camera model ID, etc.

Example output:
sendString: @id?
Got ACK Response
recvString: @"OPAL-1000m/CL S/N:135043

mapping JESD CmdClearErrors() to countReset()
Author: Benjamin Reese [email protected]
Date: Tue Feb 11 14:19:38 2020 -0800
Pull: #610 (7 additions, 0 deletions, 2 files changed)
Branch: slaclab/jesd-cnt-rst

Notes:

Description

  • Adds support to clear all the JESD status error counters using the GUI "CountReset" button
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Patch Release

06 Feb 23:08
@ruck314 ruck314
v2.0.6
45e4f00
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Patch Release

Pull Requests

  1. #607 - v2.0.6 release candidate
  2. #603 - Ethernet RAM optimizations
  3. #604 - Adding no clock feedback mode to the Ads42lb69 core
  4. #605 - AxiAds42lb69DeserBit.vhd: bug fix when XIL_DEVICE_G=7SERIES
  5. #606 - SynchronizerOneShotCntVector: Bug fix for freq(wrClk) > freq(rdClk)

Pull Request Details

v2.0.6 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Feb 6 15:05:47 2020 -0800
Pull: #607 (453 additions, 204 deletions, 26 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Adding no clock feedback mode to the Ads42lb69 core #604
  • AxiAds42lb69DeserBit.vhd: bug fix when XIL_DEVICE_G=7SERIES #605
  • SynchronizerOneShotCntVector: Bug fix for freq(wrClk) > freq(rdClk) #606
  • Ethernet RAM optimizations #603

Ethernet RAM optimizations
Author: Larry Ruckman [email protected]
Date: Thu Feb 6 13:46:26 2020 -0800
Pull: #603 (337 additions, 161 deletions, 21 files changed)
Branch: slaclab/eth-dev

Notes:

Description

  • TDEST not used internally of EthMacTop.vhd
    • Doing this logic optimization to fit into two 72-bit width RAMs but also maintaining EMAC_AXIS_CONFIG_C with external application to prevent possible TDEST issues
  • add support for (MEMORY_TYPE_G=ultra) and (GEN_SYNC_FIFO_G=false) in SsiFifo
  • updating the Ultscale+ ETH module to use URAMs for ETH RX FIFO
    • 2 URAMs per ETH RX channel

Adding no clock feedback mode to the Ads42lb69 core
Author: Larry Ruckman [email protected]
Date: Tue Feb 4 11:48:50 2020 -0800
Pull: #604 (49 additions, 39 deletions, 4 files changed)
Branch: slaclab/wave8_dev

Notes:

Added no clock feedback mode. Fixed some DRC errors related to IDELAYCTRL in 7 series.

AxiAds42lb69DeserBit.vhd: bug fix when XIL_DEVICE_G=7SERIES
Author: Larry Ruckman [email protected]
Date: Tue Feb 4 12:51:38 2020 -0800
Pull: #605 (62 additions, 3 deletions, 1 files changed)
Branch: slaclab/AxiAds42lb69DeserBit

Notes:

Description

  • resolves issue where a 7-series build does NOT find the Ultrascale source code

SynchronizerOneShotCntVector: Bug fix for freq(wrClk) > freq(rdClk)
Author: Larry Ruckman [email protected]
Date: Wed Feb 5 11:32:24 2020 -0800
Pull: #606 (5 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCORE-532
Jira: https://jira.slac.stanford.edu/issues/ESCORE-532

Notes:

Description

  • SynchronizerOneShotCntVector would previusly freeze if freq(wrClk) > freq(rdClk)
  • Gating the FIFO write with not(AFULL) to prevent this latching state
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Patch Release

30 Jan 22:33
@ruck314 ruck314
v2.0.5
5cb8fd2
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Patch Release

Pull Requests

  1. #601 - v2.0.5 release candidate
  2. #596 - overhauled SsiFifo.vhd and some misc. ETH updates
  3. #593 - Updates to Inferred/XPM wr/rd count reporting
  4. #600 - optmized SynchronizerOneShotCntVector for logic resources
  5. #594 - adding AXIL_PROXY_G to AxiI2cEeprom.vhd & AxiI2cRegMaster.vhd
  6. #597 - AxiStreamFifoV2: resolved bug in mTLastTUser
  7. #602 - Clink Framer Bug Fix
  8. #598 - exposing Si5345's booting status to top-level
  9. #595 - changed MEMORY_TYPE_G from block to distributed
  10. #592 - Adding SYNTH_MODE_G to Pgp3GthUs.vhd

Pull Request Details

v2.0.5 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Jan 30 14:31:01 2020 -0800
Pull: #601 (2260 additions, 1045 deletions, 35 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Updates to Inferred/XPM wr/rd count reporting #593
  • changed MEMORY_TYPE_G from block to distributed #595
  • Adding SYNTH_MODE_G to Pgp3GthUs.vhd #592
  • AxiStreamFifoV2: resolved bug in mTLastTUser #597
  • exposing Si5345's booting status to top-level #598
  • adding AXIL_PROXY_G to AxiI2cEeprom.vhd & AxiI2cRegMaster.vhd #594
  • overhauled SsiFifo.vhd and some misc. ETH updates #596
  • optmized SynchronizerOneShotCntVector for logic resources #600
  • Clink Framer Bug Fix #602

overhauled SsiFifo.vhd and some misc. ETH updates
Author: Larry Ruckman [email protected]
Date: Wed Jan 29 10:26:13 2020 -0800
Pull: #596 (1398 additions, 876 deletions, 19 files changed)
Branch: slaclab/SsiFifo-patch

Notes:

Description

  • overhauled the buggy SsiFifo.vhd
    • depreciated the SsiFifo.EN_FRAME_FILTER_G
  • placeholder for future TDEST_INTERLEAVE_C in AxiStreamPkg.vhd
  • exposing EthMacRxFifo.vhd's SYNTH_MODE_G&MEMORY_TYPE_G
  • fixed typo in AxiStreamFifoV2.vhd
  • bug fix for EthMacTxPause.vhd
    • remPauseCnt = pauseTime/2 when pause frame sent
  • bug fix for DspComparator.vhd
  • updating the default pauseThresh for JUMBO frame in cache
  • adding EthMacPauseTb.vhd

Updates to Inferred/XPM wr/rd count reporting
Author: Larry Ruckman [email protected]
Date: Thu Jan 23 14:03:18 2020 -0800
Pull: #593 (474 additions, 59 deletions, 4 files changed)
Branch: slaclab/ESCORE-521
Jira: https://jira.slac.stanford.edu/issues/ESCORE-521

Notes:

Description

  • adding FwftCntTb.vhd simulation testbed
  • bug fix for FifoXpm read/write count behavior
    • Also added TPD_G to the FifoXpm outputs
  • bug fix in inferred FIFO wr/rd count reporting

optmized SynchronizerOneShotCntVector for logic resources
Author: Larry Ruckman [email protected]
Date: Thu Jan 30 14:26:18 2020 -0800
Pull: #600 (168 additions, 37 deletions, 2 files changed)
Branch: slaclab/SynchronizerOneShotCntVector

Notes:

Description

  • based on my thought process from PR #599
  • Using a single FIFO instead of 1 FIFO per status counter bus

Resource Usage

Using the Default generics:

      TPD_G           : time     := 1 ns;  -- Simulation FF output delay
      RST_POLARITY_G  : sl       := \'1\';  -- \'1\' for active HIGH reset, \'0\' for active LOW reset
      RST_ASYNC_G     : boolean  := false;  -- true if reset is asynchronous, false if reset is synchronous
      COMMON_CLK_G    : boolean  := false;  -- True if wrClk and rdClk are the same clock
      RELEASE_DELAY_G : positive := 3;  -- Delay between deassertion of async and sync resets
      IN_POLARITY_G   : slv      := "1";  -- 0 for active LOW, 1 for active HIGH (for statusIn port)
      USE_DSP_G       : string   := "no";  -- "no" for no DSP implementation, "yes" to use DSP slices
      SYNTH_CNT_G     : slv      := "1";  -- Set to 1 for synthesizing counter RTL, \'0\' to not synthesis the counter
      CNT_RST_EDGE_G  : boolean  := true;  -- true if counter reset should be edge detected, else level detected
      CNT_WIDTH_G     : positive := 32;   -- Counters\' width
      WIDTH_G         : positive := 16);  -- Status vector width

Old Usage:
SyncStatusVector

New Usage:
SynchronizerOneShotCntVector

adding AXIL_PROXY_G to AxiI2cEeprom.vhd & AxiI2cRegMaster.vhd
Author: Larry Ruckman [email protected]
Date: Wed Jan 29 09:18:55 2020 -0800
Pull: #594 (104 additions, 36 deletions, 3 files changed)
Branch: slaclab/AXIL_PROXY_G

Notes:

Description

  • Adding this AxiLite Proxy shim layer to our common AXI-Lite to I2C wrappers
  • Lots of other changes in the code due to emacs vhdl beautify

JIRA

ESROGUE-424

AxiStreamFifoV2: resolved bug in mTLastTUser
Author: Larry Ruckman [email protected]
Date: Tue Jan 28 10:12:47 2020 -0800
Pull: #597 (62 additions, 26 deletions, 3 files changed)
Branch: slaclab/ESCORE-525
Jira: https://jira.slac.stanford.edu/issues/ESCORE-525

Notes:

Description

  • mTLastTUser can be out of phase of mAxisMaster when (VALID_THOLD_G/=1) and ( (FIFO_CONFIG_C.TDATA_BYTES_C /= MASTER_AXI_CONFIG_G.TDATA_BYTES_C) or (PIPE_STAGES_G/=0) )
    • mapping mTLastTUser through the AxiStreamResize/AxiStreamPipeline sideband to resovle this issue
  • adding AxiStreamPipeline sideband feature
  • adding AxiStreamResize sideband feature

Clink Framer Bug Fix
Author: Larry Ruckman [email protected]
Date: Thu Jan 30 14:26:11 2020 -0800
Pull: #602 (48 additions, 6 deletions, 2 files changed)
Branch: slaclab/clink-patch

Notes:

Description

  • bug fix when tlast set but r.byteData.lv = '0'
  • fixed code comment typos for AxiStreamBytePacker.vhd

JIRA

ESCORE-528

exposing Si5345's booting status to top-level
Author: Larry Ruckman [email protected]
Date: Wed Jan 29 09:08:39 2020 -0800
Pull: #598 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/Si5345-update

Notes:

Description

  • Useful to have during the power-up and init processes when the Si5345's Loss of Lock (LOL) port is not connected to the FPGA

changed MEMORY_TYPE_G from block to distributed
Author: Larry Ruckman [email protected]
Date: Fri Jan 24 11:43:23 2020 -0800
Pull: #595 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/SsiCmdMaster-update

Notes:

Description

  • updating default FIFO_ADDR_WIDTH_G=5
    • compensate for RD/WR latency when GEN_SYNC_FIFO_G=false
  • optimized for LUTRAM (instead of BRAM) since the default FIFO_ADDR_WIDTH_G=5

Adding SYNTH_MODE_G to Pgp3GthUs.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jan 24 11:48:36 2020 -0800
Pull: #592 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/Pgp3GthUs-patch

Notes:

Description

  • Adding SYNTH_MODE_G to Pgp3GthUs.vhd
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Patch Release

21 Jan 19:42
@ruck314 ruck314
v2.0.4
ea9d8a2
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Patch Release

Pull Requests

  1. #585 - v2.0.4 release candidate
  2. #567 - Add SlvDelayFifo Module
  3. #580 - Add meta data location to write dma
  4. #587 - exposing the GigE MMCM's clk/rst
  5. #584 - Fix generic name when used, MAXIS_CONFIG_G -> MASTER_AXI_CONFIG_G
  6. #586 - Move scripts to proper directory
  7. #588 - Exposing SYNTH_MODE_G in FifoMux.vhd

Pull Request Details

v2.0.4 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Jan 21 11:39:41 2020 -0800
Pull: #585 (287 additions, 40 deletions, 19 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Add SlvDelayRam and SlvDelayFifo Modules #567
  • Add meta data location to write dma #580
  • Fix generic name when used, MAXIS_CONFIG_G -> MASTER_AXI_CONFIG_G #584
  • Move scripts to proper directory #586
  • Exposing SYNTH_MODE_G in FifoMux.vhd #588
  • exposing the GigE MMCM's clk/rst #587

Add SlvDelayFifo Module
Author: Benjamin Reese [email protected]
Date: Tue Jan 21 11:30:15 2020 -0800
Pull: #567 (160 additions, 9 deletions, 3 files changed)
Branch: slaclab/timestamp-dev

Notes:

Description

This PR adds a new module:

  • SlvDelayFifo
    • Delay an SLV by a specified number of clock cycles by writing entries into a FIFO and waiting N cycles before popping them out.

There is also some minor code cleanup. In AxiStreamFifoV2, the sAxisCtrl output has been given a default value. In the case where FIFO_FIXED_THRESH_G=false, it was not being assigned a value until the first clock cycle. Giving it a default value allows it to be "paused" until the first clock cycles instead of "unknown".

Add meta data location to write dma
Author: Ryan Herbst [email protected]
Date: Wed Jan 15 15:44:12 2020 -0800
Pull: #580 (71 additions, 13 deletions, 2 files changed)
Branch: slaclab/gpu_meta

Notes:

This PR adds support for writing dma meta data to a particular location after a dma write transaction.

exposing the GigE MMCM's clk/rst
Author: Larry Ruckman [email protected]
Date: Tue Jan 21 11:35:13 2020 -0800
Pull: #587 (42 additions, 6 deletions, 6 files changed)
Branch: slaclab/GigEth-wrap

Notes:

Description

  • Useful to get access to this clk/rst in some applications
    • Instead of dropping down another MMCM (or PLL) to generate the same clk/rst

Fix generic name when used, MAXIS_CONFIG_G -> MASTER_AXI_CONFIG_G
Author: Larry Ruckman [email protected]
Date: Wed Jan 15 17:36:03 2020 -0800
Pull: #584 (6 additions, 6 deletions, 1 files changed)
Branch: slaclab/jmdewart-patch1

Notes:

Description

  • Generic map definition defines MASTER_AXI_CONFIG_G, code in module used MAXIS_CONFIG_G, fix to be consistent.

Move scripts to proper directory
Author: Larry Ruckman [email protected]
Date: Thu Jan 16 16:45:17 2020 -0800
Pull: #586 (5 additions, 5 deletions, 6 files changed)
Branch: slaclab/move_scripts

Notes:

This PR moves scripts from the python/tools directory to the scripts directory. Having tools under python violates our firmware repository convention and could results in namespace conflicts when the contents of python are installed with a release.

I also have moved the other top level test and documentation scripts in the scripts directory.

Exposing SYNTH_MODE_G in FifoMux.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jan 17 14:54:26 2020 -0800
Pull: #588 (3 additions, 1 deletions, 1 files changed)
Branch: slaclab/FifoMux-patch

Notes:

Description

  • Allows the user to build the FifoMux with XPM
Assets 2
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