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I am trying to upload hello.c to Xilinx Artix7 ARTYA7-100T. It is true that I can successfully debug hello and sifive-welcome in freedomstudio. Freedomstudio requires programing FPGA image into target before debug new programs on it. The latest FPGA image is design-arty.mcs, must register a account in Sifive to download the E31 file. Software is built upon this target too, it works fine in FreedomStudio.
In Ubuntu terminal
However, I debug gets error when I do it in ubuntu20.04 terminal. I have exported RISCV_PATH and RISCV_OPENOCD_PATH, and properly connected all wires. In another freedom-e-sdk path, I set the target as design-arty instead of freedom-e310-arty, it is still getting error.
Conclusion
Apparently, this guide written in github is outdated for Xilinx FPGA board. I am not sure what problem is here in Ubuntu terminal, any suggestion is helpful.
$ make PROGRAM=hello BSP=metal TARGET=freedom-e310-arty CONFIGURATION=debug upload
scripts/upload --elf /opt/Riscv/freedom-e-sdk/software/hello/debug/hello.elf --openocd /opt/Riscv/riscv-openocd-0.10.0-2020.04.6-x86_64-linux-ubuntu14/bin/openocd --gdb /opt/Riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gdb --openocd-config bsp/freedom-e310-arty/openocd.cfg
Open On-Chip Debugger 0.10.0+dev (SiFive OpenOCD 0.10.0-2020.04.6)
Licensed under GNU GPL v2
For bug reports:
https://github.com/sifive/freedom-tools/issues
Using JTAG
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x20000913 (mfg: 0x489 (SiFive Inc), part: 0x0000, ver: 0x2)
Info : datacount=1 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, misa=0x40901105
Info : Listening on port 3333 for gdb connections
Error: fespi_write_reg() error writing 0x1 to 0x10014050
Error: auto_probe failed
localhost:3333: Connection timed out.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
"monitor" command not supported by this target.
"monitor" command not supported by this target.
$ make PROGRAM=hello TARGET=design-arty CONFIGURATION=debug upload
mkdir -p /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/
make -C /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello hello \
PORT_DIR= \
PROGRAM=hello \
AR=/opt/Riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-ar \
CC=/opt/Riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc \
CXX=/opt/Riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-g++ \
ASFLAGS="-march=rv32imac -mabi=ilp32 -mcmodel=medlow --specs=nano.specs -O0 -g" \
CCASFLAGS="-march=rv32imac -mabi=ilp32 -mcmodel=medlow -I/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/bsp/design-arty/install/include --specs=nano.specs" \
CFLAGS="-march=rv32imac -mabi=ilp32 -mcmodel=medlow -ffunction-sections -fdata-sections -I/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/bsp/design-arty/install/include --specs=nano.specs -DMTIME_RATE_HZ_DEF=32768 -O0 -g" \
CXXFLAGS="-march=rv32imac -mabi=ilp32 -mcmodel=medlow -ffunction-sections -fdata-sections -I/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/bsp/design-arty/install/include --specs=nano.specs -DMTIME_RATE_HZ_DEF=32768 -O0 -g" \
XCFLAGS="-DMETAL_WAIT_CYCLE=0" \
LDFLAGS="-Wl,--gc-sections -Wl,-Map,hello.map -nostartfiles -nostdlib -L/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/bsp/design-arty/install/lib/debug/ -T/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/bsp/design-arty/metal.default.lds" \
LDLIBS="-Wl,--start-group -lc -lgcc -lm -lmetal -lmetal-gloss -Wl,--end-group" \
FREERTOS_METAL_VENV_PATH="/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/venv"
make[1]: Entering directory '/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello'
/opt/Riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -march=rv32imac -mabi=ilp32 -mcmodel=medlow -ffunction-sections -fdata-sections -I/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/bsp/design-arty/install/include --specs=nano.specs -DMTIME_RATE_HZ_DEF=32768 -O0 -g -Wl,--gc-sections -Wl,-Map,hello.map -nostartfiles -nostdlib -L/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/bsp/design-arty/install/lib/debug/ -T/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/bsp/design-arty/metal.default.lds hello.c -Wl,--start-group -lc -lgcc -lm -lmetal -lmetal-gloss -Wl,--end-group -o hello
make[1]: Leaving directory '/opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello'
mv /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/hello /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/hello.elf
mv /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/hello.map /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/
touch -c /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/hello.elf
/opt/Riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-objdump --source --all-headers --demangle --line-numbers --wide /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/hello.elf > /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/hello.lst
/opt/Riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-size /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/hello.elf
text data bss dec hex filename
18896 2052 3236 24184 5e78 /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/hello.elf
scripts/upload --elf /opt/Riscv/sifive_e31_rtl_eval_21G1.01.00/freedom-e-sdk/software/hello/debug/hello.elf --openocd /opt/Riscv/riscv-openocd-0.10.0-2020.04.6-x86_64-linux-ubuntu14/bin/openocd --gdb /opt/Riscv/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gdb --openocd-config bsp/design-arty/openocd.cfg
Open On-Chip Debugger 0.10.0+dev (SiFive OpenOCD 0.10.0-2020.04.6)
Licensed under GNU GPL v2
For bug reports:
https://github.com/sifive/freedom-tools/issues
adapter
adapter usb
adapter usb location [<bus>-port[.port]...]
adapter_khz [khz]
adapter_name
adapter_nsrst_assert_width [milliseconds]
adapter_nsrst_delay [milliseconds]
interface driver_name
interface_list
reset_config [none|trst_only|srst_only|trst_and_srst]
[srst_pulls_trst|trst_pulls_srst|combined|separate]
[srst_gates_jtag|srst_nogate] [trst_push_pull|trst_open_drain]
[srst_push_pull|srst_open_drain]
[connect_deassert_srst|connect_assert_srst]
Error: invalid subcommand "speed 10000"
bsp/design-arty/openocd.cfg:2: Error:
in procedure 'script'
at file "embedded:startup.tcl", line 26
at file "bsp/design-arty/openocd.cfg", line 2
localhost:3333: Connection timed out.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
"monitor" command not supported by this target.
"monitor" command not supported by this target.
The text was updated successfully, but these errors were encountered:
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In FreedomStudio
I am trying to upload
hello.c
to Xilinx Artix7 ARTYA7-100T. It is true that I can successfully debughello
andsifive-welcome
in freedomstudio. Freedomstudio requires programing FPGA image into target before debug new programs on it. The latest FPGA image isdesign-arty.mcs
, must register a account in Sifive to download the E31 file. Software is built upon this target too, it works fine in FreedomStudio.In Ubuntu terminal
However, I debug gets error when I do it in ubuntu20.04 terminal. I have exported
RISCV_PATH
andRISCV_OPENOCD_PATH
, and properly connected all wires. In another freedom-e-sdk path, I set the target asdesign-arty
instead offreedom-e310-arty
, it is still getting error.Conclusion
Apparently, this guide written in github is outdated for Xilinx FPGA board. I am not sure what problem is here in Ubuntu terminal, any suggestion is helpful.
The text was updated successfully, but these errors were encountered: