From 27a8a46b932b6ed245ab26fb4100d45dc97598e3 Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Thu, 16 Jan 2020 13:49:42 -0800 Subject: [PATCH] v0.1.1 --- .gitignore | 1 + setup.cfg | 3 +++ setup.py | 19 +++++++++++++++---- 3 files changed, 19 insertions(+), 4 deletions(-) create mode 100644 setup.cfg diff --git a/.gitignore b/.gitignore index 2744817..5572210 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ +.DS_Store .idea *.log *.egg-info diff --git a/setup.cfg b/setup.cfg new file mode 100644 index 0000000..3287428 --- /dev/null +++ b/setup.cfg @@ -0,0 +1,3 @@ +# Inside of setup.cfg +[metadata] +description-file = README.md diff --git a/setup.py b/setup.py index 366407a..8296476 100644 --- a/setup.py +++ b/setup.py @@ -2,14 +2,25 @@ setup( name='svreal', - version='0.0.1', + version='0.1', + license='MIT', description='Library for working with fixed-point numbers in SystemVerilog', - url='https://github.com/sgherbst/svreal', author='Steven Herbst', - author_email='sherbst@stanford.edu', + author_email='sgherbst@gmail.com', + url='https://github.com/sgherbst/svreal', + download_url = 'https://github.com/sgherbst/svreal/archive/v0.1.1.tar.gz', + keywords = ['fixed-point', 'fixed point', 'verilog', 'system-verilog', 'system verilog', 'synthesizable', 'fpga'] packages=['svreal'], install_requires=[ ], + classifiers=[ + 'Development Status :: 3 - Alpha', + 'Intended Audience :: Developers', + 'Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)', + 'License :: OSI Approved :: MIT License', + 'Programming Language :: Python :: 3', + 'Programming Language :: Python :: 3.7' + ], include_package_data=True, - zip_safe=False, + zip_safe=False )