From 707000bbe3a927cbd84b6b33a98419c09e68d801 Mon Sep 17 00:00:00 2001 From: Curtis Millar <2741168+xurtis@users.noreply.github.com> Date: Tue, 7 Sep 2021 16:15:24 +1000 Subject: [PATCH] Do not disable counters when reading on aarch64 (#32) If the cycle counter is disabled during a read, the operation can be preempted and lose the count of cycles for the duration of the preemption. Signed-off-by: Curtis Millar --- .../arch_include/arm/armv/armv8-a/sel4bench/armv/sel4bench.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/libsel4bench/arch_include/arm/armv/armv8-a/sel4bench/armv/sel4bench.h b/libsel4bench/arch_include/arm/armv/armv8-a/sel4bench/armv/sel4bench.h index 4d1d65125..f438b9afe 100644 --- a/libsel4bench/arch_include/arm/armv/armv8-a/sel4bench/armv/sel4bench.h +++ b/libsel4bench/arch_include/arm/armv/armv8-a/sel4bench/armv/sel4bench.h @@ -77,12 +77,7 @@ static FASTFN seL4_Word sel4bench_get_num_counters() static FASTFN ccnt_t sel4bench_get_cycle_count() { ccnt_t val; - uint32_t enable_word = sel4bench_private_read_cntens(); //store running state - - sel4bench_private_write_cntenc(BIT(SEL4BENCH_ARMV8A_COUNTER_CCNT)); //stop CCNT SEL4BENCH_READ_CCNT(val); //read its value - sel4bench_private_write_cntens(enable_word); //start it again if it was running - return val; }