Update test programs vs platform config

[naure]

For example, those two definition are different:

ceno/ceno_rt/memory.x

Line 3 in cec7b82

RAM : ORIGIN = 0x80000000, LENGTH = 1024M

ceno/ceno_emul/src/platform.rs

Line 23 in cec7b82

ram: 0x8000_0000..0xFFFF_0000,

And other differences following recent changes in Platform.

(cc @lightsing)

[matthiasgoergens]

Some extra context: the upper limit of 0xFFFF_0000 for ram in

ceno/ceno_emul/src/platform.rs

Line 23 in cec7b82

ram: 0x8000_0000..0xFFFF_0000,

is chosen to avoid having to deal with wraparound-overflow from the memory address offset specified in the immediate operand of memory operations.

From the spec page 19:

Load and store instructions transfer a value between the registers and memory. Loads are encoded in the I-type format and stores are S-type. The effective byte address is obtained by adding register rs1 to the sign-extended 12-bit offset. Loads copy a value from memory to register rd. Stores copy the value in register rs2 to memory.

We reserve a whole 16 bit at the end (0xFFFF), instead of just 12 bits (0x0FFF), though. I don't know why we reserve an extra 4 bits. Might be just for simplicity?

Whoever takes this issue: please verify the reasoning above, and mention it somewhere discoverable eg in a doc comment or so. (Or if the reasoning above is wrong, obviously you should correct it, and put the real reason in the doc comment. ;)