diff --git a/config/Config-images.in b/config/Config-images.in index 6f2f92643234d6..47f3dfc0d9603f 100644 --- a/config/Config-images.in +++ b/config/Config-images.in @@ -204,13 +204,14 @@ menu "Target Images" default y config GRUB_EFI_IMAGES - bool "Build GRUB EFI images (Linux x86 or x86_64 host only)" - depends on TARGET_x86 || TARGET_armsr + bool "Build GRUB EFI images" + depends on TARGET_x86 || TARGET_armsr || TARGET_loongarch64 depends on TARGET_ROOTFS_EXT4FS || TARGET_ROOTFS_JFFS2 || TARGET_ROOTFS_SQUASHFS select PACKAGE_grub2 if TARGET_x86 select PACKAGE_grub2-efi if TARGET_x86 select PACKAGE_grub2-bios-setup if TARGET_x86 select PACKAGE_grub2-efi-arm if TARGET_armsr + select PACKAGE_grub2-efi-loongarch64 if TARGET_loongarch64 select PACKAGE_kmod-fs-vfat default y @@ -276,12 +277,12 @@ menu "Target Images" config TARGET_SERIAL string "Serial port device" - depends on TARGET_x86 || TARGET_armsr + depends on TARGET_x86 || TARGET_armsr || TARGET_loongarch64 default "ttyS0" config TARGET_IMAGES_GZIP bool "GZip images" - depends on TARGET_ROOTFS_EXT4FS || TARGET_x86 || TARGET_armsr || TARGET_malta + depends on TARGET_ROOTFS_EXT4FS || TARGET_x86 || TARGET_armsr || TARGET_malta || TARGET_loongarch64 default y comment "Image Options" @@ -300,6 +301,8 @@ menu "Target Images" config TARGET_ROOTFS_PARTSIZE int "Root filesystem partition size (in MiB)" depends on USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS + default 232 if TARGET_loongarch64 + default 448 if TARGET_mediatek default 104 help Select the root filesystem partition size. diff --git a/feeds.conf.default b/feeds.conf.default index 68c55d271c0819..5e40f047d6b5f4 100644 --- a/feeds.conf.default +++ b/feeds.conf.default @@ -2,7 +2,7 @@ src-git packages https://git.openwrt.org/feed/packages.git src-git luci https://git.openwrt.org/project/luci.git src-git routing https://git.openwrt.org/feed/routing.git src-git telephony https://git.openwrt.org/feed/telephony.git -src-git nss_packages https://github.com/qosmio/nss-packages.git;NSS-12.4-K6.x +src-git nss_packages https://github.com/qosmio/nss-packages.git;NSS-12.5-K6.x src-git sqm_scripts_nss https://github.com/qosmio/sqm-scripts-nss.git #src-git video https://github.com/openwrt/video.git #src-git targets https://github.com/openwrt/targets.git diff --git a/include/bpf.mk b/include/bpf.mk index a3357f0e297f08..9abc6601232c0f 100644 --- a/include/bpf.mk +++ b/include/bpf.mk @@ -33,7 +33,7 @@ BPF_TARGET:=bpf$(if $(CONFIG_BIG_ENDIAN),eb,el) BPF_HEADERS_DIR:=$(STAGING_DIR)/bpf-headers BPF_KERNEL_INCLUDE := \ - -nostdinc -isystem $(TOOLCHAIN_INC_DIRS) \ + -nostdinc $(patsubst %,-isystem %,$(TOOLCHAIN_INC_DIRS)) \ -I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include \ -I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include/asm/mach-generic \ -I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include/generated \ diff --git a/include/kernel-6.1 b/include/kernel-6.1 index 7760c440affcc1..6717917ac1edc4 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .86 -LINUX_KERNEL_HASH-6.1.86 = d3d3c8c44f0f0a870a95bd2823f9d91979d1aa6f266da5d8cccd0c4b15e3115b +LINUX_VERSION-6.1 = .89 +LINUX_KERNEL_HASH-6.1.89 = 12bab8e092618d1d4eeaf4201e6e70054c94896198956bd84ff0e908b0264719 diff --git a/include/kernel.mk b/include/kernel.mk index 479c586ea2d8fe..6ef766388a960c 100644 --- a/include/kernel.mk +++ b/include/kernel.mk @@ -86,6 +86,8 @@ else ifneq (,$(findstring $(ARCH) , arceb )) LINUX_KARCH := arc else ifneq (,$(findstring $(ARCH) , armeb )) LINUX_KARCH := arm +else ifneq (,$(findstring $(ARCH) , loongarch64 )) + LINUX_KARCH := loongarch else ifneq (,$(findstring $(ARCH) , mipsel mips64 mips64el )) LINUX_KARCH := mips else ifneq (,$(findstring $(ARCH) , powerpc64 )) diff --git a/include/site/loongarch64 b/include/site/loongarch64 new file mode 100644 index 00000000000000..b8d581d448edc9 --- /dev/null +++ b/include/site/loongarch64 @@ -0,0 +1,30 @@ +#!/bin/sh +. $TOPDIR/include/site/linux +ac_cv_c_littleendian=${ac_cv_c_littleendian=yes} +ac_cv_c_bigendian=${ac_cv_c_bigendian=no} + +ac_cv_sizeof___int64=0 +ac_cv_sizeof_char=1 +ac_cv_sizeof_int=4 +ac_cv_sizeof_int16_t=2 +ac_cv_sizeof_int32_t=4 +ac_cv_sizeof_int64_t=8 +ac_cv_sizeof_long_int=8 +ac_cv_sizeof_long_long=8 +ac_cv_sizeof_long=8 +ac_cv_sizeof_off_t=8 +ac_cv_sizeof_short_int=2 +ac_cv_sizeof_short=2 +ac_cv_sizeof_size_t=8 +ac_cv_sizeof_ssize_t=8 +ac_cv_sizeof_u_int16_t=2 +ac_cv_sizeof_u_int32_t=4 +ac_cv_sizeof_u_int64_t=8 +ac_cv_sizeof_uint16_t=2 +ac_cv_sizeof_uint32_t=4 +ac_cv_sizeof_uint64_t=8 +ac_cv_sizeof_unsigned_int=4 +ac_cv_sizeof_unsigned_long=8 +ac_cv_sizeof_unsigned_long_long=8 +ac_cv_sizeof_unsigned_short=2 +ac_cv_sizeof_void_p=8 diff --git a/include/target.mk b/include/target.mk index b5e3e7ff6fdeca..68558601f33c4f 100644 --- a/include/target.mk +++ b/include/target.mk @@ -264,6 +264,11 @@ ifeq ($(DUMP),1) CPU_TYPE ?= riscv64 CPU_CFLAGS_riscv64:=-mabi=lp64d -march=rv64imafdc endif + ifeq ($(ARCH),loongarch64) + CPU_TYPE ?= generic + CPU_CFLAGS := -O2 -pipe + CPU_CFLAGS_generic:=-march=loongarch64 + endif ifneq ($(CPU_TYPE),) ifndef CPU_CFLAGS_$(CPU_TYPE) $(warning CPU_TYPE "$(CPU_TYPE)" doesn't correspond to a known type) diff --git a/package/boot/grub2/Makefile b/package/boot/grub2/Makefile index 279f2bd3c688ba..14933e80ce52f5 100644 --- a/package/boot/grub2/Makefile +++ b/package/boot/grub2/Makefile @@ -42,6 +42,7 @@ endef Package/grub2=$(call Package/grub2/Default,x86,pc) Package/grub2-efi=$(call Package/grub2/Default,x86,efi) Package/grub2-efi-arm=$(call Package/grub2/Default,armsr,efi) +Package/grub2-efi-loongarch64=$(call Package/grub2/Default,loongarch64,efi) define Package/grub2-editenv CATEGORY:=Utilities @@ -191,6 +192,19 @@ define Package/grub2-efi-arm/install reboot serial test efi_gop endef +define Package/grub2-efi-loongarch64/install + $(INSTALL_DIR) $(STAGING_DIR_IMAGE)/grub2 + cp ./files/grub-early-gpt.cfg $(PKG_BUILD_DIR)/grub-early.cfg + $(STAGING_DIR_HOST)/bin/grub-mkimage \ + -d $(PKG_BUILD_DIR)/grub-core \ + -p /boot/grub \ + -O loongarch64-efi \ + -c $(PKG_BUILD_DIR)/grub-early.cfg \ + -o $(STAGING_DIR_IMAGE)/grub2/bootloongarch64.efi \ + boot chain configfile fat linux ls lsefi minicmd part_gpt part_msdos reboot search \ + search_fs_uuid search_label serial efi_gop all_video gfxterm ext2 +endef + define Package/grub2-editenv/install $(INSTALL_DIR) $(1)/usr/sbin @@ -206,5 +220,6 @@ $(eval $(call HostBuild)) $(eval $(call BuildPackage,grub2)) $(eval $(call BuildPackage,grub2-efi)) $(eval $(call BuildPackage,grub2-efi-arm)) +$(eval $(call BuildPackage,grub2-efi-loongarch64)) $(eval $(call BuildPackage,grub2-editenv)) $(eval $(call BuildPackage,grub2-bios-setup)) diff --git a/package/boot/opensbi/Makefile b/package/boot/opensbi/Makefile index 99a463163063cd..b2ef27dd71cd50 100644 --- a/package/boot/opensbi/Makefile +++ b/package/boot/opensbi/Makefile @@ -6,13 +6,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=opensbi -PKG_RELEASE:=1.2 +PKG_RELEASE:=1.4 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=https://github.com/riscv/opensbi -PKG_SOURCE_DATE:=2022-12-24 -PKG_SOURCE_VERSION:=6b5188ca14e59ce7bf71afe4e7d3d557c3d31bf8 -PKG_MIRROR_HASH:=5939a3225cb37c1dde0b5b9f28f9980c0712533676774ae244d6d84bb09a1439 +PKG_SOURCE_DATE:=2023-12-24 +PKG_SOURCE_VERSION:=a2b255b88918715173942f2c5e1f97ac9e90c877 +PKG_MIRROR_HASH:=a81d7b3622feba80b2a45fe0d38600be73cfbee64a0426be82a71545c10c54d3 PKG_BUILD_DIR=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION) diff --git a/package/boot/uboot-bmips/Makefile b/package/boot/uboot-bmips/Makefile new file mode 100644 index 00000000000000..5581a6fbfc9b19 --- /dev/null +++ b/package/boot/uboot-bmips/Makefile @@ -0,0 +1,32 @@ +include $(TOPDIR)/rules.mk + +PKG_VERSION:=2024.04 +PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a +PKG_RELEASE:=$(AUTORELEASE) + +include $(INCLUDE_DIR)/u-boot.mk +include $(INCLUDE_DIR)/package.mk + +define U-Boot/Default + BUILD_TARGET:=bmips + BUILD_SUBTARGET:=bcm6328 + UBOOT_CONFIG:=inteno_xg6846_ram + UBOOT_BOARD:=$(1) +endef + +define U-Boot/xg6846 + NAME:=Inteno XG6846 + BUILD_DEVICES:=inteno_xg6846 +endef + +UBOOT_TARGETS := xg6846 + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot.bin +endef + +define Package/u-boot/install/default +endef + +$(eval $(call BuildPackage/U-Boot)) diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index 02f43ebc7fb6ea..7d46e73dbe166a 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -38,7 +38,8 @@ asus,rt-ax59u) ;; bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ -bananapi,bpi-r4) +bananapi,bpi-r4|\ +jdcloud,re-cp-03) . /lib/upgrade/common.sh bootdev="$(fitblk_get_bootdev)" @@ -98,11 +99,6 @@ glinet,gl-mt6000) glinet,gl-mt3000) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000" ;; -jdcloud,re-cp-03) - local envdev=$(find_mmc_part "ubootenv" "mmcblk0") - ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1" - ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1" - ;; mercusys,mr90x-v1|\ routerich,ax3000) local envdev=/dev/mtd$(find_mtd_index "u-boot-env") diff --git a/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch b/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch index e0f3a6e2354d9d..dc8dfe01400f51 100644 --- a/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch +++ b/package/boot/uboot-mediatek/patches/441-add-jdcloud_re-cp-03.patch @@ -271,7 +271,7 @@ +serverip=192.168.1.254 +loadaddr=0x46000000 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 -+bootargs=root=/dev/mmcblk0p65 ++bootargs=root=/dev/fit0 rootwait +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi +bootconf=config-1 +bootdelay=0 diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 863d0157f42002..844f59e9f6ba9e 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -151,6 +151,13 @@ define U-Boot/rk3568/Default TPL:=rk3568_ddr_1560MHz_v1.21.bin endef +define U-Boot/bpi-r2-pro-rk3568 + $(U-Boot/rk3568/Default) + NAME:=Bananapi-R2 Pro + BUILD_DEVICES:= \ + sinovoip_bpi-r2-pro +endef + define U-Boot/nanopi-r5c-rk3568 $(U-Boot/rk3568/Default) NAME:=NanoPi R5C @@ -186,6 +193,7 @@ UBOOT_TARGETS := \ rock64-rk3328 \ rock-pi-e-rk3328 \ radxa-cm3-io-rk3566 \ + bpi-r2-pro-rk3568 \ nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 \ radxa-e25-rk3568 diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index 112ea47d21d762..c6f98a0db44a5e 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -140,6 +140,12 @@ define U-Boot/Linksprite_pcDuino BUILD_DEVICES:=linksprite_a10-pcduino endef +define U-Boot/LicheePi_Zero + BUILD_SUBTARGET:=cortexa7 + NAME:=Lichee Pi Zero V3s + BUILD_DEVICES:=licheepi_licheepi-zero-dock +endef + define U-Boot/Linksprite_pcDuino3 BUILD_SUBTARGET:=cortexa7 NAME:=Linksprite pcDuino3 @@ -389,6 +395,7 @@ UBOOT_TARGETS := \ Marsboard_A10 \ Mele_M9 \ OLIMEX_A13_SOM \ + LicheePi_Zero \ Linksprite_pcDuino \ Linksprite_pcDuino3 \ Linksprite_pcDuino3_Nano \ diff --git a/package/kernel/bpf-headers/patches/101-linux-netlink-drop-NL_SET_ERR_MSG-for-kernel-modules.patch b/package/kernel/bpf-headers/patches/101-linux-netlink-drop-NL_SET_ERR_MSG-for-kernel-modules.patch new file mode 100644 index 00000000000000..5771b329540d44 --- /dev/null +++ b/package/kernel/bpf-headers/patches/101-linux-netlink-drop-NL_SET_ERR_MSG-for-kernel-modules.patch @@ -0,0 +1,30 @@ +From 7ed95633bff19950069c348b94c9c13164a57a2a Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 18 Jan 2023 20:20:39 +0100 +Subject: [PATCH] linux/netlink: drop NL_SET_ERR_MSG for kernel modules + +We don't need NL_SET_ERR_MSG_MOD for bpf modules and we can drop it to +solve missing KBUILD_MODNAME define. + +Signed-off-by: Christian Marangi +--- + include/linux/netlink.h | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/include/linux/netlink.h b/include/linux/netlink.h +index 61b1c7f..93561fb 100644 +--- a/include/linux/netlink.h ++++ b/include/linux/netlink.h +@@ -98,9 +98,6 @@ struct netlink_ext_ack { + __extack->_msg = __msg; \ + } while (0) + +-#define NL_SET_ERR_MSG_MOD(extack, msg) \ +- NL_SET_ERR_MSG((extack), KBUILD_MODNAME ": " msg) +- + #define NL_SET_BAD_ATTR_POLICY(extack, attr, pol) do { \ + if ((extack)) { \ + (extack)->bad_attr = (attr); \ +-- +2.38.1 + diff --git a/package/kernel/bpf-headers/patches/102-net-flow_offload-use-NL_SET_ERR_MSG-instead-of-NL_SE.patch b/package/kernel/bpf-headers/patches/102-net-flow_offload-use-NL_SET_ERR_MSG-instead-of-NL_SE.patch new file mode 100644 index 00000000000000..4dec16874ef19c --- /dev/null +++ b/package/kernel/bpf-headers/patches/102-net-flow_offload-use-NL_SET_ERR_MSG-instead-of-NL_SE.patch @@ -0,0 +1,44 @@ +From 6e7cd9c0abffea55e39a4160949bc6fba972d161 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 19 Jan 2023 13:37:46 +0100 +Subject: [PATCH] net/flow_offload: use NL_SET_ERR_MSG instead of + NL_SET_ERR_MSG_MOD + +Use NL_SET_ERR_MSG instead of NL_SET_ERR_MSG_MOD for bpf modules as +kernel modules are not supported. + +Signed-off-by: Christian Marangi +--- + include/net/flow_offload.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h +index 7a2b022..f17c485 100644 +--- a/include/net/flow_offload.h ++++ b/include/net/flow_offload.h +@@ -321,7 +321,7 @@ flow_action_mixed_hw_stats_check(const struct flow_action *action, + + flow_action_for_each(i, action_entry, action) { + if (i && action_entry->hw_stats != last_hw_stats) { +- NL_SET_ERR_MSG_MOD(extack, "Mixing HW stats types for actions is not supported"); ++ NL_SET_ERR_MSG(extack, "Mixing HW stats types for actions is not supported"); + return false; + } + last_hw_stats = action_entry->hw_stats; +@@ -356,11 +356,11 @@ __flow_action_hw_stats_check(const struct flow_action *action, + + if (!check_allow_bit && + ~action_entry->hw_stats & FLOW_ACTION_HW_STATS_ANY) { +- NL_SET_ERR_MSG_MOD(extack, "Driver supports only default HW stats type \"any\""); ++ NL_SET_ERR_MSG(extack, "Driver supports only default HW stats type \"any\""); + return false; + } else if (check_allow_bit && + !(action_entry->hw_stats & BIT(allow_bit))) { +- NL_SET_ERR_MSG_MOD(extack, "Driver does not support selected HW stats type"); ++ NL_SET_ERR_MSG(extack, "Driver does not support selected HW stats type"); + return false; + } + return true; +-- +2.38.1 + diff --git a/package/kernel/linux/modules/block.mk b/package/kernel/linux/modules/block.mk index 4f3a6e085ffb22..3dbeca9f9f282d 100644 --- a/package/kernel/linux/modules/block.mk +++ b/package/kernel/linux/modules/block.mk @@ -89,6 +89,18 @@ endef $(eval $(call KernelPackage,ata-artop)) +define KernelPackage/ata-ahci-dwc + TITLE:=Synopsys DWC AHCI SATA + KCONFIG:= \ + CONFIG_AHCI_DWC \ + CONFIG_SATA_HOST=y + FILES:=$(LINUX_DIR)/drivers/ata/ahci_dwc.ko + DEPENDS:=+kmod-ata-ahci-platform + AUTOLOAD:=$(call AutoLoad,41,ahci_dwc,1) + $(call AddDepends/ata,@TARGET_rockchip) +endef + +$(eval $(call KernelPackage,ata-ahci-dwc)) define KernelPackage/ata-nvidia-sata TITLE:=Nvidia Serial ATA support diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk index e0110764c2eda5..cf253ff9e05e13 100644 --- a/package/kernel/linux/modules/netdevices.mk +++ b/package/kernel/linux/modules/netdevices.mk @@ -142,7 +142,7 @@ $(eval $(call KernelPackage,mii)) define KernelPackage/mdio-devres SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:=Supports MDIO device registration - DEPENDS:=+kmod-libphy +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_malta||TARGET_tegra):kmod-of-mdio + DEPENDS:=+kmod-libphy +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_loongarch64||TARGET_malta||TARGET_tegra):kmod-of-mdio KCONFIG:=CONFIG_MDIO_DEVRES HIDDEN:=1 FILES:=$(LINUX_DIR)/drivers/net/phy/mdio_devres.ko @@ -159,7 +159,7 @@ $(eval $(call KernelPackage,mdio-devres)) define KernelPackage/mdio-gpio SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:= Supports GPIO lib-based MDIO busses - DEPENDS:=+kmod-libphy @GPIO_SUPPORT +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_malta||TARGET_tegra):kmod-of-mdio + DEPENDS:=+kmod-libphy @GPIO_SUPPORT +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_loongarch64||TARGET_malta||TARGET_tegra):kmod-of-mdio KCONFIG:= \ CONFIG_MDIO_BITBANG \ CONFIG_MDIO_GPIO @@ -523,7 +523,7 @@ $(eval $(call KernelPackage,switch-rtl8306)) define KernelPackage/switch-rtl8366-smi SUBMENU:=$(NETWORK_DEVICES_MENU) TITLE:=Realtek RTL8366 SMI switch interface support - DEPENDS:=@GPIO_SUPPORT +kmod-swconfig +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_malta||TARGET_tegra):kmod-of-mdio + DEPENDS:=@GPIO_SUPPORT +kmod-swconfig +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_loongarch64||TARGET_malta||TARGET_tegra):kmod-of-mdio KCONFIG:=CONFIG_RTL8366_SMI FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8366_smi.ko AUTOLOAD:=$(call AutoLoad,42,rtl8366_smi,1) diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk index b282d7695c92ee..dc1953279e434b 100644 --- a/package/kernel/linux/modules/video.mk +++ b/package/kernel/linux/modules/video.mk @@ -19,19 +19,23 @@ V4L2_MEM2MEM_DIR=platform define KernelPackage/acpi-video SUBMENU:=$(VIDEO_MENU) TITLE:=ACPI Extensions For Display Adapters - DEPENDS:=@TARGET_x86 +kmod-backlight + DEPENDS:=@TARGET_x86||TARGET_loongarch64 +kmod-backlight HIDDEN:=1 - KCONFIG:=CONFIG_ACPI_VIDEO \ - CONFIG_ACPI_WMI - FILES:=$(LINUX_DIR)/drivers/acpi/video.ko \ - $(LINUX_DIR)/drivers/platform/x86/wmi.ko - AUTOLOAD:=$(call AutoProbe,wmi video) + KCONFIG:=CONFIG_ACPI_VIDEO + FILES:=$(LINUX_DIR)/drivers/acpi/video.ko + AUTOLOAD:=$(call AutoProbe,video) endef define KernelPackage/acpi-video/description Kernel support for integrated graphics devices. endef +define KernelPackage/acpi-video/x86 + KCONFIG+=CONFIG_ACPI_WMI + FILES+=$(LINUX_DIR)/drivers/platform/x86/wmi.ko + AUTOLOAD:=$(call AutoProbe,wmi video) +endef + $(eval $(call KernelPackage,acpi-video)) define KernelPackage/backlight @@ -372,7 +376,7 @@ $(eval $(call KernelPackage,drm-suballoc-helper)) define KernelPackage/drm-amdgpu SUBMENU:=$(VIDEO_MENU) TITLE:=AMDGPU DRM support - DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-ttm \ + DEPENDS:=@TARGET_x86||TARGET_loongarch64 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-ttm \ +kmod-drm-ttm-helper +kmod-drm-kms-helper +kmod-i2c-algo-bit +amdgpu-firmware \ +kmod-drm-display-helper +kmod-drm-buddy +kmod-acpi-video \ +LINUX_6_6:kmod-drm-exec +LINUX_6_6:kmod-drm-suballoc-helper @@ -391,6 +395,13 @@ define KernelPackage/drm-amdgpu/description Direct Rendering Manager (DRM) support for AMDGPU Cards endef +define KernelPackage/drm-amdgpu/loongarch64 + KCONFIG+=CONFIG_DRM_AMDGPU_USERPTR=y \ + CONFIG_DRM_AMD_DC=y \ + CONFIG_DRM_AMD_DC_FP=y \ + CONFIG_DRM_AMD_DC_SI=y +endef + $(eval $(call KernelPackage,drm-amdgpu)) diff --git a/package/kernel/mac80211/patches/nss/ath11k/909-wifi-ath11k-fix-invalid-access-to-memory.patch b/package/kernel/mac80211/patches/nss/ath11k/909-wifi-ath11k-fix-invalid-access-to-memory.patch new file mode 100644 index 00000000000000..b62f0761358db2 --- /dev/null +++ b/package/kernel/mac80211/patches/nss/ath11k/909-wifi-ath11k-fix-invalid-access-to-memory.patch @@ -0,0 +1,52 @@ +From cea94c73e068ce4e015327bf251f782545d8e365 Mon Sep 17 00:00:00 2001 +From: Sarika Sharma +Date: Mon, 29 Jan 2024 16:01:23 +0530 +Subject: [PATCH] wifi: ath11k: fix invalid access to memory + +In ath11k_dp_rx_msdu_coalesce(), rxcb is fetched from skb and bool +is_continuation is part of rxcb. +Currently, after freeing the skb, the rxcb->is_continuation accessed +again which is wrong since the memory is already freed. + +Hence fix the issue by locally defining bool is_continuation from rxcb, +so that after freeing skb also we can use is_continuation. + +Signed-off-by: Sarika Sharma +--- + drivers/net/wireless/ath/ath11k/dp_rx.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/wireless/ath/ath11k/dp_rx.c b/drivers/net/wireless/ath/ath11k/dp_rx.c +index de71bc7..2c88986 100644 +--- a/drivers/net/wireless/ath/ath11k/dp_rx.c ++++ b/drivers/net/wireless/ath/ath11k/dp_rx.c +@@ -2278,6 +2278,7 @@ static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, + struct hal_rx_desc *ldesc; + int space_extra, rem_len, buf_len; + u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; ++ bool is_continuation; + + /* As the msdu is spread across multiple rx buffers, + * find the offset to the start of msdu for computing +@@ -2326,7 +2327,8 @@ static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, + rem_len = msdu_len - buf_first_len; + while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { + rxcb = ATH11K_SKB_RXCB(skb); +- if (rxcb->is_continuation) ++ is_continuation = rxcb->is_continuation; ++ if (is_continuation) + buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; + else + buf_len = rem_len; +@@ -2344,7 +2346,7 @@ static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, + dev_kfree_skb_any(skb); + + rem_len -= buf_len; +- if (!rxcb->is_continuation) ++ if (!is_continuation) + break; + } + +-- +2.34.1 + diff --git a/package/kernel/qca-ssdk/Makefile b/package/kernel/qca-ssdk/Makefile index bbe9f120514627..ed18f17504dbef 100644 --- a/package/kernel/qca-ssdk/Makefile +++ b/package/kernel/qca-ssdk/Makefile @@ -1,13 +1,13 @@ include $(TOPDIR)/rules.mk PKG_NAME:=qca-ssdk -PKG_RELEASE:=6 +PKG_RELEASE:=1 PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git PKG_SOURCE_PROTO:=git -PKG_SOURCE_DATE:=2023-10-04 -PKG_SOURCE_VERSION:=23a5aa4a4d5834da7a07efb58baebfbee91786b0 -PKG_MIRROR_HASH:=53fb201053b3aca004c4da07b06a0608b0b3322a2062b1f7ab3b3a7871ddabcb +PKG_SOURCE_DATE:=2024-04-17 +PKG_SOURCE_VERSION:=3d060f7ad70d087f6b0452abe79ab6d042e8cd53 +PKG_MIRROR_HASH:=6f5e390b294e699491584094f5d7eb941de6237ad8c5320191e9e306fbcd8eb5 PKG_FLAGS:=nonshared PKG_BUILD_PARALLEL:=1 diff --git a/package/kernel/qca-ssdk/patches/0001-config-identify-kernel-6.6.patch b/package/kernel/qca-ssdk/patches/0001-config-identify-kernel-6.6.patch deleted file mode 100644 index 2dc092326306b3..00000000000000 --- a/package/kernel/qca-ssdk/patches/0001-config-identify-kernel-6.6.patch +++ /dev/null @@ -1,47 +0,0 @@ -From f6c0115daaac586740e873a3b8145c5370a73dce Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 17 Feb 2024 13:02:31 +0100 -Subject: [PATCH] config: identify kernel 6.6 - -Identify kernel 6.6 so it can be compiled against. - -Signed-off-by: Robert Marko ---- - config | 5 +++++ - make/linux_opt.mk | 4 ++-- - 2 files changed, 7 insertions(+), 2 deletions(-) - ---- a/config -+++ b/config -@@ -27,6 +27,11 @@ endif - ifeq ($(KVER),$(filter 6.1%,$(KVER))) - OS_VER=6_1 - endif -+ -+ifeq ($(KVER),$(filter 6.6%,$(KVER))) -+ OS_VER=6_6 -+endif -+ - ifeq ($(KVER), 3.4.0) - OS_VER=3_4 - endif ---- a/make/linux_opt.mk -+++ b/make/linux_opt.mk -@@ -450,7 +450,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - KASAN_SHADOW_SCALE_SHIFT := 3 - endif - -- ifeq ($(OS_VER),$(filter 5_4 6_1, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 5_4 6_1 6_6, $(OS_VER))) - ifeq ($(ARCH), arm64) - KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) - endif -@@ -481,7 +481,7 @@ ifeq (KSLIB, $(MODULE_TYPE)) - - endif - -- ifeq ($(OS_VER),$(filter 4_4 5_4 6_1, $(OS_VER))) -+ ifeq ($(OS_VER),$(filter 4_4 5_4 6_1 6_6, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 diff --git a/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch b/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch index 5e390d8ee339c0..db84ea1422f1b8 100644 --- a/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch +++ b/package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch @@ -24,15 +24,15 @@ Signed-off-by: Mantas Pucka --- a/include/init/ssdk_dts.h +++ b/include/init/ssdk_dts.h -@@ -101,6 +101,7 @@ typedef struct +@@ -99,6 +99,7 @@ typedef struct a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/ a_uint32_t clk_mode; a_uint32_t pcie_hw_base; + a_uint32_t port3_pcs_channel; + led_ctrl_pattern_t source_pattern[SSDK_MAX_PORT_NUM][PORT_LED_SOURCE_MAX]; } ssdk_dt_cfg; - #define SSDK_MAX_NR_ETH 6 -@@ -162,6 +163,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t +@@ -161,6 +162,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t struct device_node *ssdk_dts_node_get(a_uint32_t dev_id); struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id); struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id); @@ -62,7 +62,7 @@ Signed-off-by: Mantas Pucka cppe_port_mux_ctrl.bf.port4_pcs_sel = --- a/src/adpt/hppe/adpt_hppe_uniphy.c +++ b/src/adpt/hppe/adpt_hppe_uniphy.c -@@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin +@@ -1160,9 +1160,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin { a_uint32_t i; sw_error_t rv = SW_OK; @@ -72,7 +72,7 @@ Signed-off-by: Mantas Pucka union uniphy_mode_ctrl_u uniphy_mode_ctrl; -@@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin +@@ -1172,9 +1169,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index); #if defined(CPPE) if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) { @@ -92,14 +92,14 @@ Signed-off-by: Mantas Pucka +a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id) +{ + ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; -+ ++ + return cfg->port3_pcs_channel; +} + - #ifndef BOARD_AR71XX #if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id, -@@ -306,6 +313,25 @@ static void ssdk_dt_parse_mac_mode(a_uin + struct device_node *switch_node, ssdk_init_cfg *cfg) +@@ -305,6 +312,25 @@ static void ssdk_dt_parse_mac_mode(a_uin return; } @@ -109,7 +109,7 @@ Signed-off-by: Mantas Pucka +{ + const __be32 *port3_pcs_channel; + a_uint32_t len = 0; -+ ++ + port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len); + if (!port3_pcs_channel) { + ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2; @@ -125,7 +125,7 @@ Signed-off-by: Mantas Pucka #ifdef IN_UNIPHY static void ssdk_dt_parse_uniphy(a_uint32_t dev_id) { -@@ -1292,6 +1318,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg * +@@ -1347,6 +1373,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg * rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv); SW_RTN_ON_ERROR(rv); ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg); diff --git a/package/kernel/qca-ssdk/patches/103-mdio-adapt-to-C22-and-C45-read-write-split.patch b/package/kernel/qca-ssdk/patches/103-mdio-adapt-to-C22-and-C45-read-write-split.patch deleted file mode 100644 index 7ddca554ecbd50..00000000000000 --- a/package/kernel/qca-ssdk/patches/103-mdio-adapt-to-C22-and-C45-read-write-split.patch +++ /dev/null @@ -1,98 +0,0 @@ -From bdae481e89cbe551068a99028bb57119b59f5ff4 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Tue, 26 Mar 2024 12:19:49 +0100 -Subject: [PATCH] mdio: adapt to C22 and C45 read/write split - -Kernel 6.3 has introduced separate C45 read/write operations, and thus -split them out of the C22 operations completely so the old way of marking -C45 reads and writes via the register value does not work anymore. - -This is causing SSDK to fail and find C45 only PHY-s such as Aquantia ones: -[ 22.187877] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 8, phy_id = 0x0 phytype doesn't match -[ 22.209924] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 0, phy_id = 0x0 phytype doesn't match - -This in turn causes USXGMII MAC autoneg bit to not get set and then UNIPHY -autoneg will time out, causing the 10G ports not to work: -[ 37.292784] uniphy autoneg time out! - -So, lets detect C45 reads and writes by the magic BIT(30) in the register -argument and if so call separate C45 mdiobus read/write functions. - -Signed-off-by: Robert Marko ---- - include/init/ssdk_plat.h | 7 +++++++ - src/init/ssdk_plat.c | 30 ++++++++++++++++++++++++++++++ - 2 files changed, 37 insertions(+) - ---- a/include/init/ssdk_plat.h -+++ b/include/init/ssdk_plat.h -@@ -505,3 +505,10 @@ void ssdk_plat_exit(a_uint32_t dev_id); - - #endif - /*qca808x_end*/ -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)) -+#define MII_ADDR_C45 (1<<30) -+#define MII_DEVADDR_C45_SHIFT 16 -+#define MII_DEVADDR_C45_MASK GENMASK(20, 16) -+#define MII_REGADDR_C45_MASK GENMASK(15, 0) -+#endif ---- a/src/init/ssdk_plat.c -+++ b/src/init/ssdk_plat.c -@@ -356,6 +356,18 @@ phy_addr_validation_check(a_uint32_t phy - return A_TRUE; - } - -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)) -+static inline u16 mdiobus_c45_regad(u32 regnum) -+{ -+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum); -+} -+ -+static inline u16 mdiobus_c45_devad(u32 regnum) -+{ -+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); -+} -+#endif -+ - sw_error_t - qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t* data) -@@ -371,9 +383,18 @@ qca_ar8327_phy_read(a_uint32_t dev_id, a - if (!bus) - return SW_NOT_SUPPORTED; - phy_addr = TO_PHY_ADDR(phy_addr); -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)) -+ mutex_lock(&bus->mdio_lock); -+ if (reg & MII_ADDR_C45) -+ *data = __mdiobus_c45_read(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg)); -+ else -+ *data = __mdiobus_read(bus, phy_addr, reg); -+ mutex_unlock(&bus->mdio_lock); -+#else - mutex_lock(&bus->mdio_lock); - *data = __mdiobus_read(bus, phy_addr, reg); - mutex_unlock(&bus->mdio_lock); -+#endif - - return 0; - } -@@ -393,9 +414,18 @@ qca_ar8327_phy_write(a_uint32_t dev_id, - if (!bus) - return SW_NOT_SUPPORTED; - phy_addr = TO_PHY_ADDR(phy_addr); -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)) -+ mutex_lock(&bus->mdio_lock); -+ if (reg & MII_ADDR_C45) -+ __mdiobus_c45_write(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg), data); -+ else -+ __mdiobus_write(bus, phy_addr, reg, data); -+ mutex_unlock(&bus->mdio_lock); -+#else - mutex_lock(&bus->mdio_lock); - __mdiobus_write(bus, phy_addr, reg, data); - mutex_unlock(&bus->mdio_lock); -+#endif - - return 0; - } diff --git a/package/libs/libunwind/Makefile b/package/libs/libunwind/Makefile index 7a82d76663e22e..7bd3c5ac176a84 100644 --- a/package/libs/libunwind/Makefile +++ b/package/libs/libunwind/Makefile @@ -32,7 +32,7 @@ define Package/libunwind CATEGORY:=Libraries TITLE:=The libunwind project URL:=http://www.nongnu.org/libunwind/ - DEPENDS:=@((mips||mipsel||mips64||powerpc64||x86_64||arm||aarch64)||(USE_GLIBC&&(powerpc||i386))) +zlib + DEPENDS:=@((mips||mipsel||mips64||powerpc64||x86_64||arm||aarch64||loongarch64)||(USE_GLIBC&&(powerpc||i386))) +zlib ABI_VERSION:=8 endef diff --git a/package/libs/libunwind/patches/005-loongarch64-musl.pattch b/package/libs/libunwind/patches/005-loongarch64-musl.pattch new file mode 100644 index 00000000000000..bb961bdfad23cf --- /dev/null +++ b/package/libs/libunwind/patches/005-loongarch64-musl.pattch @@ -0,0 +1,12 @@ +--- a/src/loongarch64/getcontext.S ++++ b/src/loongarch64/getcontext.S +@@ -25,7 +25,9 @@ OF CONTRACT, TORT OR OTHERWISE, ARISING + WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + #include "offsets.h" ++#ifdef __GLIBC__ + #include ++#endif + .text + + #define SREG(X) st.d $r##X, $r4, (LINUX_UC_MCONTEXT_GREGS + 8 * X) diff --git a/package/libs/openssl/patches/110-openwrt_targets.patch b/package/libs/openssl/patches/110-openwrt_targets.patch index a97c603fa7c224..d02bc03fb89f78 100644 --- a/package/libs/openssl/patches/110-openwrt_targets.patch +++ b/package/libs/openssl/patches/110-openwrt_targets.patch @@ -9,7 +9,7 @@ Signed-off-by: Eneas U de Queiroz --- /dev/null +++ b/Configurations/25-openwrt.conf -@@ -0,0 +1,56 @@ +@@ -0,0 +1,59 @@ +## Openwrt "CONFIG_ARCH" matching targets. + +# The targets need to end in '-openwrt' for the AFALG patch to work @@ -34,6 +34,9 @@ Signed-off-by: Eneas U de Queiroz + "linux-i386-openwrt" => { + inherit_from => [ "linux-x86", "openwrt" ], + }, ++ "linux-loongarch64-openwrt" => { ++ inherit_from => [ "linux64-loongarch64", "openwrt" ], ++ }, + "linux-mips-openwrt" => { + inherit_from => [ "linux-mips32", "openwrt" ], + }, diff --git a/package/libs/toolchain/Makefile b/package/libs/toolchain/Makefile index 285fbcfa98938f..3dd844d65b6558 100644 --- a/package/libs/toolchain/Makefile +++ b/package/libs/toolchain/Makefile @@ -144,7 +144,7 @@ define Package/libtsan $(call Package/gcc/Default) NAME:=libtsan TITLE:=Runtime library for ThreadSanitizer in GCC - DEPENDS:=@USE_GLIBC +librt +libstdcpp @!mips @!mipsel @!mips64 @!mips64el @!arc + DEPENDS:=@USE_GLIBC +librt +libstdcpp @!loongarch64 @!mips @!mipsel @!mips64 @!mips64el @!arc ABI_VERSION:=0 endef @@ -173,7 +173,7 @@ define Package/liblsan $(call Package/gcc/Default) NAME:=liblsan TITLE:=Runtime library for LeakSanitizer in GCC - DEPENDS:=@USE_GLIBC +librt +libstdcpp @!mips @!mipsel @!mips64 @!mips64el @!arc + DEPENDS:=@USE_GLIBC +librt +libstdcpp @!loongarch64 @!mips @!mipsel @!mips64 @!mips64el @!arc ABI_VERSION:=0 endef diff --git a/package/network/services/hostapd/patches/052-AP-add-missing-null-pointer-check-in-hostapd_free_ha.patch b/package/network/services/hostapd/patches/052-AP-add-missing-null-pointer-check-in-hostapd_free_ha.patch new file mode 100644 index 00000000000000..85d5127f600d2d --- /dev/null +++ b/package/network/services/hostapd/patches/052-AP-add-missing-null-pointer-check-in-hostapd_free_ha.patch @@ -0,0 +1,20 @@ +From: Felix Fietkau +Date: Wed, 1 May 2024 18:55:24 +0200 +Subject: [PATCH] AP: add missing null pointer check in hostapd_free_hapd_data + +When called from wpa_supplicant, iface->interfaces can be NULL + +Signed-off-by: Felix Fietkau +--- + +--- a/src/ap/hostapd.c ++++ b/src/ap/hostapd.c +@@ -502,7 +502,7 @@ void hostapd_free_hapd_data(struct hosta + struct hapd_interfaces *ifaces = hapd->iface->interfaces; + size_t i; + +- for (i = 0; i < ifaces->count; i++) { ++ for (i = 0; ifaces && i < ifaces->count; i++) { + struct hostapd_iface *iface = ifaces->iface[i]; + size_t j; + diff --git a/package/network/utils/xdp-tools/Makefile b/package/network/utils/xdp-tools/Makefile index dba775e4ea1420..8a839954e9b73c 100644 --- a/package/network/utils/xdp-tools/Makefile +++ b/package/network/utils/xdp-tools/Makefile @@ -85,8 +85,13 @@ CONFIGURE_VARS += \ CFLAGS="$(TARGET_CFLAGS)" \ LDFLAGS="$(TARGET_LDFLAGS)" \ CLANG="$(CLANG)" \ - BPF_TARGET="$(BPF_TARGET)" \ - LLC="$(LLVM_LLC)" + BPF_TARGET="$(BPF_ARCH)-linux-gnu" \ + LLC="$(LLVM_LLC)" \ + BPF_LDFLAGS="-march=$(BPF_TARGET) -mcpu=v3" + +ifneq ($(findstring s,$(OPENWRT_VERBOSE)),) + MAKE_FLAGS+=V=1 +endif MAKE_VARS += \ PREFIX=/usr \ @@ -94,7 +99,7 @@ MAKE_VARS += \ define Build/Configure $(call Build/Configure/Default) - echo "BPF_CFLAGS += -I$(BPF_HEADERS_DIR)/tools/lib -fno-stack-protector" >> $(PKG_BUILD_DIR)/config.mk + echo "BPF_CFLAGS += $(BPF_CFLAGS) -Wno-error -fno-stack-protector" >> $(PKG_BUILD_DIR)/config.mk endef define Build/InstallDev diff --git a/package/network/utils/xdp-tools/patches/020-libxdp-Use-__noinline__-reserved-attribute-for-XDP-d.patch b/package/network/utils/xdp-tools/patches/020-libxdp-Use-__noinline__-reserved-attribute-for-XDP-d.patch new file mode 100644 index 00000000000000..1a157df32c6308 --- /dev/null +++ b/package/network/utils/xdp-tools/patches/020-libxdp-Use-__noinline__-reserved-attribute-for-XDP-d.patch @@ -0,0 +1,49 @@ +From 1f160c287c14b4300c4248752e20da5981c9763e Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 18 Jan 2023 19:00:54 +0100 +Subject: [PATCH] libxdp: Use __noinline__ reserved attribute for XDP + dispatcher + +The use of noinline is wrong as noline is not a reserved attribute and +with gcc12 this became an error. Use the reserved __noinline__ attribute +to fix compilation error. + +Signed-off-by: Christian Marangi +[a.heider: adapt lib/libxdp/protocol.org too] +Signed-off-by: Andre Heider +--- + lib/libxdp/protocol.org | 2 +- + lib/libxdp/xdp-dispatcher.c.in | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/lib/libxdp/protocol.org ++++ b/lib/libxdp/protocol.org +@@ -54,7 +54,7 @@ static volatile const struct xdp_dispatc + /* The volatile return value prevents the compiler from assuming it knows the + * return value and optimising based on that. + */ +-__attribute__ ((noinline)) ++__attribute__ ((__noinline__)) + int prog0(struct xdp_md *ctx) { + volatile int ret = XDP_DISPATCHER_RETVAL; + +--- a/lib/libxdp/xdp-dispatcher.c.in ++++ b/lib/libxdp/xdp-dispatcher.c.in +@@ -30,7 +30,7 @@ static volatile const struct xdp_dispatc + * return value and optimising based on that. + */ + forloop(`i', `0', NUM_PROGS, +-`__attribute__ ((noinline)) ++`__attribute__ ((__noinline__)) + int format(`prog%d', i)(struct xdp_md *ctx) { + volatile int ret = XDP_DISPATCHER_RETVAL; + +@@ -40,7 +40,7 @@ int format(`prog%d', i)(struct xdp_md *c + } + ') + +-__attribute__ ((noinline)) ++__attribute__ ((__noinline__)) + int compat_test(struct xdp_md *ctx) { + volatile int ret = XDP_DISPATCHER_RETVAL; + diff --git a/package/network/utils/xdp-tools/patches/021-headers-xdp-drop-vlan_hdr-as-already-defined.patch b/package/network/utils/xdp-tools/patches/021-headers-xdp-drop-vlan_hdr-as-already-defined.patch new file mode 100644 index 00000000000000..d508e489ea3986 --- /dev/null +++ b/package/network/utils/xdp-tools/patches/021-headers-xdp-drop-vlan_hdr-as-already-defined.patch @@ -0,0 +1,31 @@ +From bc2a11227b5bed29d33926d5ff7e707228db9e87 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 18 Jan 2023 20:07:58 +0100 +Subject: [PATCH] headers: xdp: drop vlan_hdr as already defined + +Drop vlan_hdr as already defined by bpf headers. + +Signed-off-by: Christian Marangi +--- + headers/xdp/parsing_helpers.h | 10 ---------- + 1 file changed, 10 deletions(-) + +--- a/headers/xdp/parsing_helpers.h ++++ b/headers/xdp/parsing_helpers.h +@@ -33,16 +33,6 @@ struct hdr_cursor { + }; + + /* +- * struct vlan_hdr - vlan header +- * @h_vlan_TCI: priority and VLAN ID +- * @h_vlan_encapsulated_proto: packet type ID or len +- */ +-struct vlan_hdr { +- __be16 h_vlan_TCI; +- __be16 h_vlan_encapsulated_proto; +-}; +- +-/* + * Struct icmphdr_common represents the common part of the icmphdr and icmp6hdr + * structures. + */ diff --git a/package/network/utils/xdp-tools/patches/022-xdp-dump-add-missing-perf_event-include-for-bpf-and-.patch b/package/network/utils/xdp-tools/patches/022-xdp-dump-add-missing-perf_event-include-for-bpf-and-.patch new file mode 100644 index 00000000000000..edeb403281e89f --- /dev/null +++ b/package/network/utils/xdp-tools/patches/022-xdp-dump-add-missing-perf_event-include-for-bpf-and-.patch @@ -0,0 +1,34 @@ +From 0388d7447de027e0d2369d6b8a9c58ea0f8f027c Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Wed, 18 Jan 2023 20:37:12 +0100 +Subject: [PATCH] xdp-dump: add missing perf_event include for bpf and xdp + +Add missing perf_event include needed for struct perf_event_header for +bpf and xdp. + +Signed-off-by: Christian Marangi +--- + xdp-dump/xdpdump_bpf.c | 1 + + xdp-dump/xdpdump_xdp.c | 1 + + 2 files changed, 2 insertions(+) + +--- a/xdp-dump/xdpdump_bpf.c ++++ b/xdp-dump/xdpdump_bpf.c +@@ -4,6 +4,7 @@ + * Include files + *****************************************************************************/ + #include ++#include + #include + #include + #include +--- a/xdp-dump/xdpdump_xdp.c ++++ b/xdp-dump/xdpdump_xdp.c +@@ -4,6 +4,7 @@ + * Include files + *****************************************************************************/ + #include ++#include + #include + #include + #include diff --git a/package/network/utils/xdp-tools/patches/023-libxdp-fix-compilation-on-multiarch-systems.patch b/package/network/utils/xdp-tools/patches/023-libxdp-fix-compilation-on-multiarch-systems.patch new file mode 100644 index 00000000000000..cc60ebf61165f0 --- /dev/null +++ b/package/network/utils/xdp-tools/patches/023-libxdp-fix-compilation-on-multiarch-systems.patch @@ -0,0 +1,30 @@ +From cb1ef3322671a67e2050a3eee18b49cdb4ed4bed Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 18 Jan 2023 20:54:41 +0100 +Subject: [PATCH] libxdp: fix compilation on multiarch systems + +Multiarch systems require an additional include path, which is covered +by ARCH_INCLUDES here. Just as lib/util, add it to BPF_CFLAGS. + +Fixes compilation on debian: + +In file included from xdp-dispatcher.c:3: +In file included from ../../headers/linux/bpf.h:11: +/usr/include/linux/types.h:5:10: fatal error: 'asm/types.h' file not found + +Signed-off-by: Andre Heider +--- + lib/libxdp/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/lib/libxdp/Makefile ++++ b/lib/libxdp/Makefile +@@ -30,7 +30,7 @@ PC_FILE := $(OBJDIR)/libxdp.pc + TEMPLATED_SOURCES := xdp-dispatcher.c + + CFLAGS += -I$(HEADER_DIR) +-BPF_CFLAGS += -I$(HEADER_DIR) ++BPF_CFLAGS += -I$(HEADER_DIR) $(ARCH_INCLUDES) + + + ifndef BUILD_STATIC_ONLY diff --git a/package/network/utils/xdp-tools/patches/024-lib-allow-overwriting-W-flags-via-BPF_CFLAGS.patch b/package/network/utils/xdp-tools/patches/024-lib-allow-overwriting-W-flags-via-BPF_CFLAGS.patch new file mode 100644 index 00000000000000..16835eae375837 --- /dev/null +++ b/package/network/utils/xdp-tools/patches/024-lib-allow-overwriting-W-flags-via-BPF_CFLAGS.patch @@ -0,0 +1,49 @@ +From e2d8eae9477f6ba41ab75ad77202f235e34c04f7 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 18 Jan 2023 22:30:23 +0100 +Subject: [PATCH] lib: allow overwriting -W* flags via BPF_CFLAGS + +The bpf header file situation is a mess, and the default warning +compiler flags may not be suitable everywhere, especially with -Werror +in the mix. + +Move BPF_CFLAGS further down, so these can be overwritten by builders. + +Signed-off-by: Andre Heider +--- + lib/common.mk | 2 +- + lib/libxdp/Makefile | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/lib/common.mk ++++ b/lib/common.mk +@@ -108,12 +108,12 @@ $(XDP_OBJ): %.o: %.c $(KERN_USER_H) $(EX + $(QUIET_CLANG)$(CLANG) -S \ + -target $(BPF_TARGET) \ + -D __BPF_TRACING__ \ +- $(BPF_CFLAGS) \ + -Wall \ + -Wno-unused-value \ + -Wno-pointer-sign \ + -Wno-compare-distinct-pointer-types \ + -Werror \ ++ $(BPF_CFLAGS) \ + -O2 -emit-llvm -c -g -o ${@:.o=.ll} $< + $(QUIET_LLC)$(LLC) -march=$(BPF_TARGET) -filetype=obj -o $@ ${@:.o=.ll} + +--- a/lib/libxdp/Makefile ++++ b/lib/libxdp/Makefile +@@ -139,12 +139,12 @@ $(XDP_OBJS): %.o: %.c $(BPF_HEADERS) $(L + $(QUIET_CLANG)$(CLANG) -S \ + -target $(BPF_TARGET) \ + -D __BPF_TRACING__ \ +- $(BPF_CFLAGS) \ + -Wall \ + -Wno-unused-value \ + -Wno-pointer-sign \ + -Wno-compare-distinct-pointer-types \ + -Werror \ ++ $(BPF_CFLAGS) \ + -O2 -emit-llvm -c -g -o ${@:.o=.ll} $< + $(QUIET_LLC)$(LLC) -march=$(BPF_TARGET) -filetype=obj -o $@ ${@:.o=.ll} + diff --git a/package/network/utils/xdp-tools/patches/025-Add-BPF_LDFLAGS-to-allow-overwriting-llc-s-march-arg.patch b/package/network/utils/xdp-tools/patches/025-Add-BPF_LDFLAGS-to-allow-overwriting-llc-s-march-arg.patch new file mode 100644 index 00000000000000..d375e1db0cc53d --- /dev/null +++ b/package/network/utils/xdp-tools/patches/025-Add-BPF_LDFLAGS-to-allow-overwriting-llc-s-march-arg.patch @@ -0,0 +1,55 @@ +From 7b00d4a90af1d7bff50833ffe1216cf59592353a Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Wed, 18 Jan 2023 22:42:28 +0100 +Subject: [PATCH] Add BPF_LDFLAGS to allow overwriting llc's -march argument + +The argument to clang's -target isn't necessarily the same as to +llc's -march. + +Analogue to BPF_CFLAGS, introduce BPF_LDFLAGS to allow e.g.: +BPF_TARGET="mipsel-linux-gnu" BPF_LDFLAGS="-march=bpfel -mcpu=v3" + +Signed-off-by: Andre Heider +--- + configure | 2 ++ + lib/common.mk | 2 +- + lib/libxdp/Makefile | 2 +- + 3 files changed, 4 insertions(+), 2 deletions(-) + +--- a/configure ++++ b/configure +@@ -17,10 +17,12 @@ check_opts() + : ${DYNAMIC_LIBXDP:=0} + : ${MAX_DISPATCHER_ACTIONS:=10} + : ${BPF_TARGET:=bpf} ++ : ${BPF_LDFLAGS:=-march=$(BPF_TARGET)} + echo "PRODUCTION:=${PRODUCTION}" >>$CONFIG + echo "DYNAMIC_LIBXDP:=${DYNAMIC_LIBXDP}" >>$CONFIG + echo "MAX_DISPATCHER_ACTIONS:=${MAX_DISPATCHER_ACTIONS}" >>$CONFIG + echo "BPF_TARGET:=${BPF_TARGET}" >>$CONFIG ++ echo "BPF_LDFLAGS:=${BPF_LDFLAGS}" >>$CONFIG + } + + find_tool() +--- a/lib/common.mk ++++ b/lib/common.mk +@@ -115,7 +115,7 @@ $(XDP_OBJ): %.o: %.c $(KERN_USER_H) $(EX + -Werror \ + $(BPF_CFLAGS) \ + -O2 -emit-llvm -c -g -o ${@:.o=.ll} $< +- $(QUIET_LLC)$(LLC) -march=$(BPF_TARGET) -filetype=obj -o $@ ${@:.o=.ll} ++ $(QUIET_LLC)$(LLC) $(BPF_LDFLAGS) -filetype=obj -o $@ ${@:.o=.ll} + + .PHONY: man + ifeq ($(EMACS),) +--- a/lib/libxdp/Makefile ++++ b/lib/libxdp/Makefile +@@ -146,7 +146,7 @@ $(XDP_OBJS): %.o: %.c $(BPF_HEADERS) $(L + -Werror \ + $(BPF_CFLAGS) \ + -O2 -emit-llvm -c -g -o ${@:.o=.ll} $< +- $(QUIET_LLC)$(LLC) -march=$(BPF_TARGET) -filetype=obj -o $@ ${@:.o=.ll} ++ $(QUIET_LLC)$(LLC) $(BPF_LDFLAGS) -filetype=obj -o $@ ${@:.o=.ll} + + .PHONY: man + ifeq ($(EMACS),) diff --git a/package/utils/ucode/patches/100-ubus-fix-uc_ubus_have_uloop-for-eloop-uloop-combinat.patch b/package/utils/ucode/patches/100-ubus-fix-uc_ubus_have_uloop-for-eloop-uloop-combinat.patch new file mode 100644 index 00000000000000..a1659be3c89fd1 --- /dev/null +++ b/package/utils/ucode/patches/100-ubus-fix-uc_ubus_have_uloop-for-eloop-uloop-combinat.patch @@ -0,0 +1,26 @@ +From: Felix Fietkau +Date: Wed, 1 May 2024 18:40:19 +0200 +Subject: [PATCH] ubus: fix uc_ubus_have_uloop for eloop+uloop combination + +When uloop has been integrated with eloop (in hostapd/wpa_supplicant), +uloop_cancelling will return false, since uloop_run is not being called. +This leads to ubus.defer() calling uloop_run in a context where it can +prevent the other event loop from running. + +Fix this by detecting event loop integration via uloop_fd_set_cb being set + +Signed-off-by: Felix Fietkau +--- + +--- a/lib/ubus.c ++++ b/lib/ubus.c +@@ -665,6 +665,9 @@ uc_ubus_have_uloop(void) + bool prev = uloop_cancelled; + bool active; + ++ if (uloop_fd_set_cb) ++ return true; ++ + uloop_cancelled = true; + active = uloop_cancelling(); + uloop_cancelled = prev; diff --git a/target/Config.in b/target/Config.in index ac0f1f9826bf9d..c2395923d4d361 100644 --- a/target/Config.in +++ b/target/Config.in @@ -156,6 +156,10 @@ config i386 config i686 bool +config loongarch64 + select ARCH_64BIT + bool + config m68k bool @@ -220,6 +224,7 @@ config ARCH default "armeb" if armeb default "i386" if i386 default "i686" if i686 + default "loongarch64" if loongarch64 default "m68k" if m68k default "mips" if mips default "mipsel" if mipsel diff --git a/target/linux/bcm27xx/image/cmdline.txt b/target/linux/bcm27xx/image/cmdline.txt index 41f76f10af078a..bdd1e59a093627 100644 --- a/target/linux/bcm27xx/image/cmdline.txt +++ b/target/linux/bcm27xx/image/cmdline.txt @@ -1 +1 @@ -console=serial0,115200 console=tty1 root=@ROOT@ rootfstype=squashfs,ext4 rootwait +console=tty1 console=serial0,115200 root=@ROOT@ rootfstype=squashfs,ext4 rootwait diff --git a/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch b/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch index ab145eb66f734b..600fe08126ddd2 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0106-Add-dwc_otg-driver.patch @@ -1185,7 +1185,7 @@ Signed-off-by: Jonathan Bell } --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c -@@ -5686,7 +5686,7 @@ static void port_event(struct usb_hub *h +@@ -5697,7 +5697,7 @@ static void port_event(struct usb_hub *h port_dev->over_current_count++; port_over_current_notify(port_dev); diff --git a/target/linux/bcm27xx/patches-6.1/950-0181-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch b/target/linux/bcm27xx/patches-6.1/950-0181-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch index 34b923fb235ca5..3feabeaf9dea88 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0181-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0181-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch @@ -90,10 +90,10 @@ Signed-off-by: Jonathan Bell + */ + void (*fixup_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, + struct usb_host_endpoint *ep, int interval); - /* Returns the hardware-chosen device address */ - int (*address_device)(struct usb_hcd *, struct usb_device *udev); - /* prepares the hardware to send commands to the device */ -@@ -435,6 +440,8 @@ extern void usb_hcd_unmap_urb_setup_for_ + /* Set the hardware-chosen device address */ + int (*address_device)(struct usb_hcd *, struct usb_device *udev, + unsigned int timeout_ms); +@@ -436,6 +441,8 @@ extern void usb_hcd_unmap_urb_setup_for_ extern void usb_hcd_unmap_urb_for_dma(struct usb_hcd *, struct urb *); extern void usb_hcd_flush_endpoint(struct usb_device *udev, struct usb_host_endpoint *ep); diff --git a/target/linux/bcm27xx/patches-6.1/950-0182-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch b/target/linux/bcm27xx/patches-6.1/950-0182-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch index 3c1e41ba0afcac..a5e08d4cca92d6 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0182-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0182-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch @@ -125,7 +125,7 @@ Signed-off-by: Jonathan Bell * non-error returns are a promise to giveback() the urb later * we drop ownership so next owner (or urb unlink) can get it */ -@@ -5471,6 +5574,7 @@ static const struct hc_driver xhci_hc_dr +@@ -5480,6 +5583,7 @@ static const struct hc_driver xhci_hc_dr .endpoint_reset = xhci_endpoint_reset, .check_bandwidth = xhci_check_bandwidth, .reset_bandwidth = xhci_reset_bandwidth, diff --git a/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch b/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch index 93f7ffde9c20d2..1188b4dbe4f187 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0190-xhci-Use-more-event-ring-segment-table-entries.patch @@ -22,7 +22,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c -@@ -2522,9 +2522,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, +@@ -2524,9 +2524,11 @@ int xhci_mem_init(struct xhci_hcd *xhci, * Event ring setup: Allocate a normal ring, but also setup * the event ring segment table (ERST). Section 4.9.3. */ @@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell if (!xhci->event_ring) goto fail; if (xhci_check_trb_in_td_math(xhci) < 0) -@@ -2537,7 +2539,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, +@@ -2539,7 +2541,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, /* set ERST count with the number of entries in the segment table */ val = readl(&xhci->ir_set->erst_size); val &= ERST_SIZE_MASK; @@ -47,7 +47,7 @@ Signed-off-by: Jonathan Bell val); --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1672,8 +1672,8 @@ struct urb_priv { +@@ -1677,8 +1677,8 @@ struct urb_priv { * Each segment table entry is 4*32bits long. 1K seems like an ok size: * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, * meaning 64 ring segments. diff --git a/target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch b/target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch index db15c65809ff32..ed242cbbe4ffc0 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch @@ -26,7 +26,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c -@@ -674,9 +674,9 @@ deq_found: +@@ -675,9 +675,9 @@ deq_found: } if ((ep->ep_state & SET_DEQ_PENDING)) { diff --git a/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch b/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch index 073bb8be79c828..0725689bf8a7d4 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch @@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c -@@ -664,6 +664,15 @@ static int xhci_move_dequeue_past_td(str +@@ -665,6 +665,15 @@ static int xhci_move_dequeue_past_td(str } while (!cycle_found || !td_last_trb_found); deq_found: @@ -54,7 +54,7 @@ Signed-off-by: Jonathan Bell addr = xhci_trb_virt_to_dma(new_seg, new_deq); --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1902,6 +1902,7 @@ struct xhci_hcd { +@@ -1907,6 +1907,7 @@ struct xhci_hcd { #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) #define XHCI_ZHAOXIN_HOST BIT_ULL(46) diff --git a/target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch b/target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch index ab76ad76cd17ae..414716760031f1 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch @@ -144,7 +144,7 @@ Signed-off-by: Jonathan Bell if (ret) return -ENOMEM; -@@ -1811,7 +1815,7 @@ int xhci_alloc_erst(struct xhci_hcd *xhc +@@ -1813,7 +1817,7 @@ int xhci_alloc_erst(struct xhci_hcd *xhc for (val = 0; val < evt_ring->num_segs; val++) { entry = &erst->entries[val]; entry->seg_addr = cpu_to_le64(seg->dma); @@ -204,7 +204,7 @@ Signed-off-by: Jonathan Bell xhci_err(xhci, "Tried to move enqueue past ring segment\n"); return; } -@@ -3150,7 +3153,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd +@@ -3151,7 +3154,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd * that clears the EHB. */ while (xhci_handle_event(xhci) > 0) { @@ -213,7 +213,7 @@ Signed-off-by: Jonathan Bell continue; xhci_update_erst_dequeue(xhci, event_ring_deq); event_ring_deq = xhci->event_ring->dequeue; -@@ -3292,7 +3295,8 @@ static int prepare_ring(struct xhci_hcd +@@ -3293,7 +3296,8 @@ static int prepare_ring(struct xhci_hcd } } @@ -247,7 +247,7 @@ Signed-off-by: Jonathan Bell * when the cycle bit is set to 1. --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1634,6 +1634,7 @@ struct xhci_ring { +@@ -1639,6 +1639,7 @@ struct xhci_ring { unsigned int num_trbs_free; unsigned int num_trbs_free_temp; unsigned int bounce_buf_len; diff --git a/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch b/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch index 041f98a97d52be..da0d7cd969d1d5 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch @@ -63,7 +63,7 @@ Signed-off-by: Jonathan Bell if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1904,6 +1904,7 @@ struct xhci_hcd { +@@ -1909,6 +1909,7 @@ struct xhci_hcd { #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) #define XHCI_ZHAOXIN_HOST BIT_ULL(46) #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47) diff --git a/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch b/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch index 0dd7b78b30d68a..df13f539bd8867 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch @@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c -@@ -3605,14 +3605,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3606,14 +3606,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd * unsigned int num_trbs; unsigned int start_cycle, num_sgs = 0; unsigned int enqd_len, block_len, trb_buff_len, full_len; @@ -54,7 +54,7 @@ Signed-off-by: Jonathan Bell full_len = urb->transfer_buffer_length; /* If we have scatter/gather list, we use it. */ if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) { -@@ -3649,6 +3650,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3650,6 +3651,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd * start_cycle = ring->cycle_state; send_addr = addr; @@ -72,7 +72,7 @@ Signed-off-by: Jonathan Bell /* Queue the TRBs, even if they are zero-length */ for (enqd_len = 0; first_trb || enqd_len < full_len; enqd_len += trb_buff_len) { -@@ -3661,6 +3673,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3662,6 +3674,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd * if (enqd_len + trb_buff_len > full_len) trb_buff_len = full_len - enqd_len; @@ -86,7 +86,7 @@ Signed-off-by: Jonathan Bell first_trb = false; --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1905,6 +1905,7 @@ struct xhci_hcd { +@@ -1910,6 +1910,7 @@ struct xhci_hcd { #define XHCI_ZHAOXIN_HOST BIT_ULL(46) #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47) #define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48) diff --git a/target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch b/target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch index e3f1848ad539e7..fecee7d9528a46 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch @@ -13,7 +13,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c -@@ -3605,7 +3605,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3606,7 +3606,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * unsigned int num_trbs; unsigned int start_cycle, num_sgs = 0; unsigned int enqd_len, block_len, trb_buff_len, full_len; @@ -22,7 +22,7 @@ Signed-off-by: Jonathan Bell u32 field, length_field, remainder, maxpacket; u64 addr, send_addr; -@@ -3651,14 +3651,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3652,14 +3652,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd * send_addr = addr; if (xhci->quirks & XHCI_VLI_SS_BULK_OUT_BUG && @@ -40,7 +40,7 @@ Signed-off-by: Jonathan Bell } /* Queue the TRBs, even if they are zero-length */ -@@ -3673,7 +3668,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3674,7 +3669,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * if (enqd_len + trb_buff_len > full_len) trb_buff_len = full_len - enqd_len; diff --git a/target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch b/target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch index f604759c2ff29e..1afe830091fddf 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch @@ -31,7 +31,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c -@@ -1012,11 +1012,13 @@ static int xhci_invalidate_cancelled_tds +@@ -1013,11 +1013,13 @@ static int xhci_invalidate_cancelled_tds td->urb->stream_id, td->urb, cached_td->urb->stream_id, cached_td->urb); cached_td = td; @@ -45,7 +45,7 @@ Signed-off-by: Jonathan Bell } } -@@ -1264,10 +1266,7 @@ static void update_ring_for_set_deq_comp +@@ -1265,10 +1267,7 @@ static void update_ring_for_set_deq_comp unsigned int ep_index) { union xhci_trb *dequeue_temp; @@ -56,7 +56,7 @@ Signed-off-by: Jonathan Bell dequeue_temp = ep_ring->dequeue; /* If we get two back-to-back stalls, and the first stalled transfer -@@ -1282,8 +1281,6 @@ static void update_ring_for_set_deq_comp +@@ -1283,8 +1282,6 @@ static void update_ring_for_set_deq_comp } while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { @@ -65,7 +65,7 @@ Signed-off-by: Jonathan Bell ep_ring->dequeue++; if (trb_is_link(ep_ring->dequeue)) { if (ep_ring->dequeue == -@@ -1293,15 +1290,10 @@ static void update_ring_for_set_deq_comp +@@ -1294,15 +1291,10 @@ static void update_ring_for_set_deq_comp ep_ring->dequeue = ep_ring->deq_seg->trbs; } if (ep_ring->dequeue == dequeue_temp) { diff --git a/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch b/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch index ade55cf33703c6..ab0bae587b6af0 100644 --- a/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch +++ b/target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch @@ -40,7 +40,7 @@ Signed-off-by: Jonathan Bell if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c -@@ -3582,6 +3582,48 @@ static int xhci_align_td(struct xhci_hcd +@@ -3583,6 +3583,48 @@ static int xhci_align_td(struct xhci_hcd return 1; } @@ -89,7 +89,7 @@ Signed-off-by: Jonathan Bell /* This is very similar to what ehci-q.c qtd_fill() does */ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, int slot_id, unsigned int ep_index) -@@ -3750,6 +3792,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd * +@@ -3751,6 +3793,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd * } check_trb_math(urb, enqd_len); @@ -98,7 +98,7 @@ Signed-off-by: Jonathan Bell giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, start_cycle, start_trb); return 0; -@@ -3885,6 +3929,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * +@@ -3886,6 +3930,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * /* Event on completion */ field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); @@ -109,7 +109,7 @@ Signed-off-by: Jonathan Bell return 0; --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1906,6 +1906,7 @@ struct xhci_hcd { +@@ -1911,6 +1911,7 @@ struct xhci_hcd { #define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47) #define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48) #define XHCI_VLI_SS_BULK_OUT_BUG BIT_ULL(49) diff --git a/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch index edae77ccd1374b..9c769880a0cbdd 100644 --- a/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch +++ b/target/linux/bcm53xx/patches-6.1/180-usb-xhci-add-support-for-performing-fake-doorbell.patch @@ -108,7 +108,7 @@ it on BCM4708 family. if (xhci->quirks & XHCI_NEC_HOST) --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1902,6 +1902,7 @@ struct xhci_hcd { +@@ -1907,6 +1907,7 @@ struct xhci_hcd { #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) #define XHCI_ZHAOXIN_HOST BIT_ULL(46) diff --git a/target/linux/bmips/bcm6328/base-files/etc/board.d/02_network b/target/linux/bmips/bcm6328/base-files/etc/board.d/02_network index 104f20ef0e2383..78c0794f231138 100644 --- a/target/linux/bmips/bcm6328/base-files/etc/board.d/02_network +++ b/target/linux/bmips/bcm6328/base-files/etc/board.d/02_network @@ -9,6 +9,9 @@ arcadyan,ar7516) ucidef_set_bridge_device switch ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan" ;; +inteno,xg6846) + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan ext1" + ;; comtrend,ar-5381u |\ comtrend,ar-5387un |\ innacomm,w3400v6 |\ diff --git a/target/linux/bmips/bcm6328/config-6.1 b/target/linux/bmips/bcm6328/config-6.1 index 5b33e932360fec..de7784e80ab15f 100644 --- a/target/linux/bmips/bcm6328/config-6.1 +++ b/target/linux/bmips/bcm6328/config-6.1 @@ -170,6 +170,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPLIT_BCM63XX_FW=y CONFIG_MTD_SPLIT_BCM_WFI_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_BLOCK=y diff --git a/target/linux/bmips/dts/bcm6328-inteno-xg6846.dts b/target/linux/bmips/dts/bcm6328-inteno-xg6846.dts new file mode 100644 index 00000000000000..72f85a53ca7c74 --- /dev/null +++ b/target/linux/bmips/dts/bcm6328-inteno-xg6846.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/* + * Devicetree for the Inteno XG6846 router, mostly used as a + * media converter from fiber to twisted pair ethernet + * "fiber modem" in many households in Sweden. The Marvell + * switch has one of its ports connected to an SFP (Small Form + * Factor pluggable) optical fiber receiver, which is bridged + * to the twisted pair connector LAN1. + * + * This device tree is inspired by research from the OpenWrt + * and Sweclockers forums, including contributions from + * NPeca75, mrhaav and csom. + * + * Some devices have a USB type A host receptacle mounted, + * some do not. + */ +#include "bcm6328.dtsi" +#include +#include + +/ { + model = "Inteno XG6846"; + compatible = "inteno,xg6846", "brcm,bcm6328"; + + /* OpenWrt-specific aliases */ + aliases { + led-boot = &led_pwr_red; + led-failsafe = &led_pwr_red; + led-running = &led_pwr_green; + led-upgrade = &led_pwr_red; + led-usb = &led_usb_green; + }; + + chosen { + bootargs = "rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; + }; + + /* + * This I2C port is connected to the SFP and reflects the EEPROM etc + * inside the SFP module. If the module is not plugged in, consequently + * nothing will be found on the bus. + */ + i2c0: i2c-sfp { + compatible = "i2c-gpio"; + sda-gpios = <&gpio 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* This I2C bus is used for the external CATV connector (usually unused) */ + i2c1: i2c-catv { + compatible = "i2c-gpio"; + sda-gpios = <&gpio 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c0>; + los-gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + }; + }; +}; + +&hsspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + /* + * HW 1.0-1.1: Spansion S25FL128S1 + * HW 1.3: Winbond W25Q128 + * + * Fast Read Data max speed is 50MHz, see the Winbond W25Q128 + * datasheet table 9.5 "AC Electrical Characteristics", we can + * use this speed because the chip supports fast reads. Older + * HW has different NOR chips, I assume they can all do fast + * reads. + */ + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + m25p,fast-read; + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + cfe: partition@0 { + label = "cfe"; + reg = <0x0000000 0x0010000>; + read-only; + }; + + partition@10000 { + compatible = "openwrt,uimage", "denx,uimage"; + reg = <0x010000 0xfe0000>; + label = "firmware"; + openwrt,offset = <0x30000>; + }; + + partition@ff0000 { + reg = <0xff0000 0x010000>; + label = "nvram"; + }; + }; + }; +}; + +&cfe { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_cfe_6a0: macaddr@6a0 { + reg = <0x6a0 0x6>; + }; +}; + +ðernet { + status = "okay"; + + nvmem-cells = <&macaddr_cfe_6a0>; + nvmem-cell-names = "mac-address"; +}; + +&switch0 { + dsa,member = <0 0>; + + ports { + switch0port4: port@4 { + reg = <4>; + label = "extsw"; + + phy-mode = "rgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&mdio_ext { + switch1: switch@0 { + /* The switch is not using any external IRQ, sadly */ + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + phy-handle = <&lan1phy>; + }; + + port@1 { + reg = <1>; + label = "lan2"; + phy-handle = <&lan2phy>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-handle = <&lan3phy>; + }; + + port@3 { + reg = <3>; + label = "lan4"; + phy-handle = <&lan4phy>; + }; + + port@4 { + reg = <4>; + label = "ext1"; + phy-handle = <&ext1phy>; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + label = "wan"; + sfp = <&sfp0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + phy-mode = "rgmii-id"; + label = "cpu"; + ethernet = <&switch0port4>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + lan1phy: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&switch1>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + }; + lan2phy: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&switch1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + lan3phy: ethernet-phy@2 { + reg = <2>; + interrupt-parent = <&switch1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + lan4phy: ethernet-phy@3 { + reg = <3>; + interrupt-parent = <&switch1>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + ext1phy: ethernet-phy@4 { + reg = <4>; + interrupt-parent = <&switch1>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&pinctrl { + pinctrl_xg6846_usb_spd_led: xg6846_usb_spd_led-pins { + function = "led"; + pins = "gpio17"; + }; +}; + +&leds { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xg6846_usb_spd_led>, /* GPIO16 LED USB */ + <&pinctrl_ephy1_spd_led>, /* GPIO18 LED PWR red */ + <&pinctrl_ephy3_spd_led>; /* GPIO20 LED PWR green */ + + /* On board variants without USB this LED is not mounted */ + led_usb_green: led@16 { + reg = <16>; + active-low; + label = "green:usb"; + default-state = "off"; + }; + + /* + * LED 18 and 20 drive the same physical LED, the PWR + * LED that can be both red and green. + */ + led_pwr_red: led@18 { + reg = <18>; + active-low; + label = "red:pwr"; + default-state = "off"; + }; + + led_pwr_green: led@20 { + reg = <20>; + active-low; + label = "green:pwr"; + default-state = "off"; + }; + +}; diff --git a/target/linux/bmips/image/Makefile b/target/linux/bmips/image/Makefile index 9311e2df096fc0..b79974931d48ce 100644 --- a/target/linux/bmips/image/Makefile +++ b/target/linux/bmips/image/Makefile @@ -4,6 +4,7 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/image.mk KERNEL_LOADADDR := 0x80010000 # RAM start + 64K +UBOOT_ENTRY := 0x81c00000 LOADER_ENTRY := 0x81000000 # RAM start + 16M, for relocate LZMA_TEXT_START := 0x82000000 # RAM start + 32M @@ -94,6 +95,21 @@ define Build/cfe-bin $(CFE_EXTRAS) $(1) endef +# Build a CFE image with just U-Boot +define Build/cfe-bin-uboot + cp $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.bin $@ + $(call Build/lzma) + mv $@ $@.uboot.lzma + echo "dummy" > $@.dummyfs + $(STAGING_DIR_HOST)/bin/imagetag -i $@.uboot.lzma -f $@.dummyfs \ + --output $@ --boardid $(CFE_BOARD_ID) --chipid $(CHIP_ID) \ + --entry $(UBOOT_ENTRY) --load-addr $(UBOOT_ENTRY) \ + --info1 "$(call ModelNameLimit16,$(DEVICE_NAME))" \ + $(CFE_EXTRAS) $(1) + rm $@.uboot.lzma + rm $@.dummyfs +endef + define Build/cfe-jffs2 $(STAGING_DIR_HOST)/bin/mkfs.jffs2 \ --big-endian \ @@ -284,6 +300,21 @@ define Device/bcm63xx-cfe-legacy KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma-cfe endef +# CFE images with U-Boot in front of the kernel, these will execute +# U-Boot instead of the kernel and U-Boot will then proceed to load +# the kernel. The reason to do this is that CFE is sometimes unable to +# load big kernels even with the lzma loader tricks. +define Device/bcm63xx-cfe-uboot + $(Device/bcm63xx-cfe) + KERNEL := kernel-bin | append-dtb | lzma | uImage lzma + IMAGE/cfe.bin := cfe-bin-uboot | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \ + append-kernel | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \ + append-rootfs $$$$(if $$$$(FLASH_MB),--pad $$$$(shell expr $$$$(FLASH_MB) / 2)) + IMAGE/sysupgrade.bin := cfe-bin-uboot | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \ + append-kernel | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \ + append-rootfs | append-metadata +endef + # CFE expects a single JFFS2 partition with cferam and kernel. However, # it's possible to fool CFE into properly loading both cferam and kernel # from two different JFFS2 partitions by adding dummy files (see diff --git a/target/linux/bmips/image/bcm6328.mk b/target/linux/bmips/image/bcm6328.mk index b28926b1e71506..b85b6ac7a88f62 100644 --- a/target/linux/bmips/image/bcm6328.mk +++ b/target/linux/bmips/image/bcm6328.mk @@ -51,6 +51,20 @@ define Device/innacomm_w3400v6 endef TARGET_DEVICES += innacomm_w3400v6 +define Device/inteno_xg6846 + $(Device/bcm63xx-cfe-uboot) + DEVICE_VENDOR := Inteno + DEVICE_MODEL := XG6846 + CHIP_ID := 6328 + CFE_BOARD_ID := 96328avng + FLASH_MB := 16 + DEVICE_PACKAGES := $(USB2_PACKAGES) \ + kmod-i2c-core kmod-i2c-gpio \ + kmod-leds-bcm6328 kmod-dsa-mv88e6xxx \ + kmod-sfp +endef +TARGET_DEVICES += inteno_xg6846 + define Device/nucom_r5010unv2 $(Device/bcm63xx-cfe) DEVICE_VENDOR := NuCom diff --git a/target/linux/generic/backport-6.1/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch b/target/linux/generic/backport-6.1/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch new file mode 100644 index 00000000000000..6dbec3c75244c0 --- /dev/null +++ b/target/linux/generic/backport-6.1/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch @@ -0,0 +1,107 @@ +From: Richard Gobert +Date: Wed, 3 Jan 2024 15:44:21 +0100 +Subject: [PATCH] net: gro: parse ipv6 ext headers without frag0 invalidation + +The existing code always pulls the IPv6 header and sets the transport +offset initially. Then optionally again pulls any extension headers in +ipv6_gso_pull_exthdrs and sets the transport offset again on return from +that call. skb->data is set at the start of the first extension header +before calling ipv6_gso_pull_exthdrs, and must disable the frag0 +optimization because that function uses pskb_may_pull/pskb_pull instead of +skb_gro_ helpers. It sets the GRO offset to the TCP header with +skb_gro_pull and sets the transport header. Then returns skb->data to its +position before this block. + +This commit introduces a new helper function - ipv6_gro_pull_exthdrs - +which is used in ipv6_gro_receive to pull ipv6 ext headers instead of +ipv6_gso_pull_exthdrs. Thus, there is no modification of skb->data, all +operations use skb_gro_* helpers, and the frag0 fast path can be taken for +IPv6 packets with ext headers. + +Signed-off-by: Richard Gobert +Reviewed-by: Willem de Bruijn +Reviewed-by: David Ahern +Reviewed-by: Eric Dumazet +Link: https://lore.kernel.org/r/504130f6-b56c-4dcc-882c-97942c59f5b7@gmail.com +Signed-off-by: Jakub Kicinski +--- + +--- a/net/ipv6/ip6_offload.c ++++ b/net/ipv6/ip6_offload.c +@@ -36,6 +36,40 @@ + INDIRECT_CALL_L4(cb, f2, f1, head, skb); \ + }) + ++static int ipv6_gro_pull_exthdrs(struct sk_buff *skb, int off, int proto) ++{ ++ const struct net_offload *ops = NULL; ++ struct ipv6_opt_hdr *opth; ++ ++ for (;;) { ++ int len; ++ ++ ops = rcu_dereference(inet6_offloads[proto]); ++ ++ if (unlikely(!ops)) ++ break; ++ ++ if (!(ops->flags & INET6_PROTO_GSO_EXTHDR)) ++ break; ++ ++ opth = skb_gro_header(skb, off + sizeof(*opth), off); ++ if (unlikely(!opth)) ++ break; ++ ++ len = ipv6_optlen(opth); ++ ++ opth = skb_gro_header(skb, off + len, off); ++ if (unlikely(!opth)) ++ break; ++ proto = opth->nexthdr; ++ ++ off += len; ++ } ++ ++ skb_gro_pull(skb, off - skb_network_offset(skb)); ++ return proto; ++} ++ + static int ipv6_gso_pull_exthdrs(struct sk_buff *skb, int proto) + { + const struct net_offload *ops = NULL; +@@ -224,28 +258,25 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff * + goto out; + + skb_set_network_header(skb, off); +- skb_gro_pull(skb, sizeof(*iph)); +- skb_set_transport_header(skb, skb_gro_offset(skb)); + +- flush += ntohs(iph->payload_len) != skb_gro_len(skb); ++ flush += ntohs(iph->payload_len) != skb->len - hlen; + + proto = iph->nexthdr; + ops = rcu_dereference(inet6_offloads[proto]); + if (!ops || !ops->callbacks.gro_receive) { +- pskb_pull(skb, skb_gro_offset(skb)); +- skb_gro_frag0_invalidate(skb); +- proto = ipv6_gso_pull_exthdrs(skb, proto); +- skb_gro_pull(skb, -skb_transport_offset(skb)); +- skb_reset_transport_header(skb); +- __skb_push(skb, skb_gro_offset(skb)); ++ proto = ipv6_gro_pull_exthdrs(skb, hlen, proto); + + ops = rcu_dereference(inet6_offloads[proto]); + if (!ops || !ops->callbacks.gro_receive) + goto out; + +- iph = ipv6_hdr(skb); ++ iph = skb_gro_network_header(skb); ++ } else { ++ skb_gro_pull(skb, sizeof(*iph)); + } + ++ skb_set_transport_header(skb, skb_gro_offset(skb)); ++ + NAPI_GRO_CB(skb)->proto = proto; + + flush--; diff --git a/target/linux/generic/backport-6.1/600-v6.9-03-net-gro-add-flush-check-in-udp_gro_receive_segment.patch b/target/linux/generic/backport-6.1/600-v6.9-03-net-gro-add-flush-check-in-udp_gro_receive_segment.patch new file mode 100644 index 00000000000000..55dac85df897df --- /dev/null +++ b/target/linux/generic/backport-6.1/600-v6.9-03-net-gro-add-flush-check-in-udp_gro_receive_segment.patch @@ -0,0 +1,48 @@ +From: Richard Gobert +Date: Tue, 30 Apr 2024 16:35:55 +0200 +Subject: [PATCH] net: gro: add flush check in udp_gro_receive_segment + +GRO-GSO path is supposed to be transparent and as such L3 flush checks are +relevant to all UDP flows merging in GRO. This patch uses the same logic +and code from tcp_gro_receive, terminating merge if flush is non zero. + +Fixes: e20cf8d3f1f7 ("udp: implement GRO for plain UDP sockets.") +Signed-off-by: Richard Gobert +Reviewed-by: Willem de Bruijn +Signed-off-by: Paolo Abeni +--- + +--- a/net/ipv4/udp_offload.c ++++ b/net/ipv4/udp_offload.c +@@ -463,6 +463,7 @@ static struct sk_buff *udp_gro_receive_s + struct sk_buff *p; + unsigned int ulen; + int ret = 0; ++ int flush; + + /* requires non zero csum, for symmetry with GSO */ + if (!uh->check) { +@@ -496,13 +497,22 @@ static struct sk_buff *udp_gro_receive_s + return p; + } + ++ flush = NAPI_GRO_CB(p)->flush; ++ ++ if (NAPI_GRO_CB(p)->flush_id != 1 || ++ NAPI_GRO_CB(p)->count != 1 || ++ !NAPI_GRO_CB(p)->is_atomic) ++ flush |= NAPI_GRO_CB(p)->flush_id; ++ else ++ NAPI_GRO_CB(p)->is_atomic = false; ++ + /* Terminate the flow on len mismatch or if it grow "too much". + * Under small packet flood GRO count could elsewhere grow a lot + * leading to excessive truesize values. + * On len mismatch merge the first packet shorter than gso_size, + * otherwise complete the GRO packet. + */ +- if (ulen > ntohs(uh2->len)) { ++ if (ulen > ntohs(uh2->len) || flush) { + pp = p; + } else { + if (NAPI_GRO_CB(skb)->is_flist) { diff --git a/target/linux/generic/backport-6.1/740-v6.9-01-netfilter-flowtable-validate-pppoe-header.patch b/target/linux/generic/backport-6.1/740-v6.9-01-netfilter-flowtable-validate-pppoe-header.patch deleted file mode 100644 index 29f211e8a5023d..00000000000000 --- a/target/linux/generic/backport-6.1/740-v6.9-01-netfilter-flowtable-validate-pppoe-header.patch +++ /dev/null @@ -1,87 +0,0 @@ -From: Pablo Neira Ayuso -Date: Thu, 11 Apr 2024 13:28:59 +0200 -Subject: [PATCH] netfilter: flowtable: validate pppoe header - -Ensure there is sufficient room to access the protocol field of the -PPPoe header. Validate it once before the flowtable lookup, then use a -helper function to access protocol field. - -Reported-by: syzbot+b6f07e1c07ef40199081@syzkaller.appspotmail.com -Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support") -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -335,7 +335,7 @@ int nf_flow_rule_route_ipv6(struct net * - int nf_flow_table_offload_init(void); - void nf_flow_table_offload_exit(void); - --static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb) -+static inline __be16 __nf_flow_pppoe_proto(const struct sk_buff *skb) - { - __be16 proto; - -@@ -351,6 +351,16 @@ static inline __be16 nf_flow_pppoe_proto - return 0; - } - -+static inline bool nf_flow_pppoe_proto(struct sk_buff *skb, __be16 *inner_proto) -+{ -+ if (!pskb_may_pull(skb, PPPOE_SES_HLEN)) -+ return false; -+ -+ *inner_proto = __nf_flow_pppoe_proto(skb); -+ -+ return true; -+} -+ - #define NF_FLOW_TABLE_STAT_INC(net, count) __this_cpu_inc((net)->ft.stat->count) - #define NF_FLOW_TABLE_STAT_DEC(net, count) __this_cpu_dec((net)->ft.stat->count) - #define NF_FLOW_TABLE_STAT_INC_ATOMIC(net, count) \ ---- a/net/netfilter/nf_flow_table_inet.c -+++ b/net/netfilter/nf_flow_table_inet.c -@@ -21,7 +21,8 @@ nf_flow_offload_inet_hook(void *priv, st - proto = veth->h_vlan_encapsulated_proto; - break; - case htons(ETH_P_PPP_SES): -- proto = nf_flow_pppoe_proto(skb); -+ if (!nf_flow_pppoe_proto(skb, &proto)) -+ return NF_ACCEPT; - break; - default: - proto = skb->protocol; ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -267,10 +267,11 @@ static unsigned int nf_flow_xmit_xfrm(st - return NF_STOLEN; - } - --static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto, -+static bool nf_flow_skb_encap_protocol(struct sk_buff *skb, __be16 proto, - u32 *offset) - { - struct vlan_ethhdr *veth; -+ __be16 inner_proto; - - switch (skb->protocol) { - case htons(ETH_P_8021Q): -@@ -281,7 +282,8 @@ static bool nf_flow_skb_encap_protocol(c - } - break; - case htons(ETH_P_PPP_SES): -- if (nf_flow_pppoe_proto(skb) == proto) { -+ if (nf_flow_pppoe_proto(skb, &inner_proto) && -+ inner_proto == proto) { - *offset += PPPOE_SES_HLEN; - return true; - } -@@ -310,7 +312,7 @@ static void nf_flow_encap_pop(struct sk_ - skb_reset_network_header(skb); - break; - case htons(ETH_P_PPP_SES): -- skb->protocol = nf_flow_pppoe_proto(skb); -+ skb->protocol = __nf_flow_pppoe_proto(skb); - skb_pull(skb, PPPOE_SES_HLEN); - skb_reset_network_header(skb); - break; diff --git a/target/linux/generic/backport-6.1/740-v6.9-02-netfilter-flowtable-incorrect-pppoe-tuple.patch b/target/linux/generic/backport-6.1/740-v6.9-02-netfilter-flowtable-incorrect-pppoe-tuple.patch deleted file mode 100644 index 3b822b169d24bb..00000000000000 --- a/target/linux/generic/backport-6.1/740-v6.9-02-netfilter-flowtable-incorrect-pppoe-tuple.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Pablo Neira Ayuso -Date: Thu, 11 Apr 2024 13:29:00 +0200 -Subject: [PATCH] netfilter: flowtable: incorrect pppoe tuple - -pppoe traffic reaching ingress path does not match the flowtable entry -because the pppoe header is expected to be at the network header offset. -This bug causes a mismatch in the flow table lookup, so pppoe packets -enter the classical forwarding path. - -Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support") -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -156,7 +156,7 @@ static void nf_flow_tuple_encap(struct s - tuple->encap[i].proto = skb->protocol; - break; - case htons(ETH_P_PPP_SES): -- phdr = (struct pppoe_hdr *)skb_mac_header(skb); -+ phdr = (struct pppoe_hdr *)skb_network_header(skb); - tuple->encap[i].id = ntohs(phdr->sid); - tuple->encap[i].proto = skb->protocol; - break; diff --git a/target/linux/generic/backport-6.1/766-v6.10-net-dsa-allow-DSA-switch-drivers-to-provide-their-ow.patch b/target/linux/generic/backport-6.1/766-v6.10-net-dsa-allow-DSA-switch-drivers-to-provide-their-ow.patch index 51250ac97a45dc..0119925ab03795 100644 --- a/target/linux/generic/backport-6.1/766-v6.10-net-dsa-allow-DSA-switch-drivers-to-provide-their-ow.patch +++ b/target/linux/generic/backport-6.1/766-v6.10-net-dsa-allow-DSA-switch-drivers-to-provide-their-ow.patch @@ -99,7 +99,7 @@ Signed-off-by: Jakub Kicinski } --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c -@@ -1736,6 +1736,15 @@ static int dsa_switch_probe(struct dsa_s +@@ -1758,6 +1758,15 @@ static int dsa_switch_probe(struct dsa_s if (!ds->num_ports) return -EINVAL; diff --git a/target/linux/generic/backport-6.1/790-01-v6.2-net-dsa-mt7530-remove-redundant-assignment.patch b/target/linux/generic/backport-6.1/790-01-v6.2-net-dsa-mt7530-remove-redundant-assignment.patch index f662a7636862b3..e0319fd355a5d1 100644 --- a/target/linux/generic/backport-6.1/790-01-v6.2-net-dsa-mt7530-remove-redundant-assignment.patch +++ b/target/linux/generic/backport-6.1/790-01-v6.2-net-dsa-mt7530-remove-redundant-assignment.patch @@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3010,9 +3010,6 @@ static void mt753x_phylink_get_caps(stru +@@ -3198,9 +3198,6 @@ static void mt753x_phylink_get_caps(stru config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; diff --git a/target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch b/target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch index 36ff3549e9d0bb..2697f2e563244b 100644 --- a/target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch +++ b/target/linux/generic/backport-6.1/790-02-v6.4-net-dsa-mt7530-use-external-PCS-driver.patch @@ -44,7 +44,7 @@ Signed-off-by: Jakub Kicinski #include #include #include -@@ -2651,128 +2652,11 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2839,128 +2840,11 @@ static int mt7531_rgmii_setup(struct mt7 return 0; } @@ -173,7 +173,7 @@ Signed-off-by: Jakub Kicinski static int mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) -@@ -2795,11 +2679,11 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2983,11 +2867,11 @@ mt7531_mac_config(struct dsa_switch *ds, phydev = dp->slave->phydev; return mt7531_rgmii_setup(priv, port, interface, phydev); case PHY_INTERFACE_MODE_SGMII: @@ -187,7 +187,7 @@ Signed-off-by: Jakub Kicinski default: return -EINVAL; } -@@ -2824,11 +2708,11 @@ mt753x_phylink_mac_select_pcs(struct dsa +@@ -3012,11 +2896,11 @@ mt753x_phylink_mac_select_pcs(struct dsa switch (interface) { case PHY_INTERFACE_MODE_TRGMII: @@ -201,7 +201,7 @@ Signed-off-by: Jakub Kicinski default: return NULL; } -@@ -3066,86 +2950,6 @@ static void mt7530_pcs_get_state(struct +@@ -3254,86 +3138,6 @@ static void mt7530_pcs_get_state(struct state->pause |= MLO_PAUSE_TX; } @@ -288,7 +288,7 @@ Signed-off-by: Jakub Kicinski static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, phy_interface_t interface, const unsigned long *advertising, -@@ -3165,18 +2969,57 @@ static const struct phylink_pcs_ops mt75 +@@ -3353,18 +3157,57 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -352,7 +352,7 @@ Signed-off-by: Jakub Kicinski int i, ret; /* Initialise the PCS devices */ -@@ -3184,8 +3027,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3372,8 +3215,6 @@ mt753x_setup(struct dsa_switch *ds) priv->pcs[i].pcs.ops = priv->info->pcs_ops; priv->pcs[i].priv = priv; priv->pcs[i].port = i; @@ -361,7 +361,7 @@ Signed-off-by: Jakub Kicinski } ret = priv->info->sw_setup(ds); -@@ -3200,6 +3041,16 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3388,6 +3229,16 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -378,7 +378,7 @@ Signed-off-by: Jakub Kicinski return ret; } -@@ -3291,7 +3142,7 @@ static const struct mt753x_info mt753x_t +@@ -3480,7 +3331,7 @@ static const struct mt753x_info mt753x_t }, [ID_MT7531] = { .id = ID_MT7531, @@ -387,7 +387,7 @@ Signed-off-by: Jakub Kicinski .sw_setup = mt7531_setup, .phy_read = mt7531_ind_phy_read, .phy_write = mt7531_ind_phy_write, -@@ -3399,7 +3250,7 @@ static void +@@ -3588,7 +3439,7 @@ static void mt7530_remove(struct mdio_device *mdiodev) { struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); @@ -396,7 +396,7 @@ Signed-off-by: Jakub Kicinski if (!priv) return; -@@ -3418,6 +3269,10 @@ mt7530_remove(struct mdio_device *mdiode +@@ -3607,6 +3458,10 @@ mt7530_remove(struct mdio_device *mdiode mt7530_free_irq(priv); dsa_unregister_switch(priv->ds); @@ -409,7 +409,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -391,47 +391,8 @@ enum mt7530_vlan_port_acc_frm { +@@ -401,47 +401,8 @@ enum mt7530_vlan_port_acc_frm { CCR_TX_OCT_CNT_BAD) /* MT7531 SGMII register group */ @@ -459,7 +459,7 @@ Signed-off-by: Jakub Kicinski /* Register for system reset */ #define MT7530_SYS_CTRL 0x7000 -@@ -730,13 +691,13 @@ struct mt7530_fdb { +@@ -741,13 +702,13 @@ struct mt7530_fdb { * @pm: The matrix used to show all connections with the port. * @pvid: The VLAN specified is to be considered a PVID at ingress. Any * untagged frames will be assigned to the related VLAN. diff --git a/target/linux/generic/backport-6.1/790-04-v6.4-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch b/target/linux/generic/backport-6.1/790-04-v6.4-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch index ed24c452e2b52f..1bf19a813e6e33 100644 --- a/target/linux/generic/backport-6.1/790-04-v6.4-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch +++ b/target/linux/generic/backport-6.1/790-04-v6.4-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3001,26 +3001,56 @@ static const struct regmap_bus mt7531_re +@@ -3189,26 +3189,56 @@ static const struct regmap_bus mt7531_re .reg_update_bits = mt7530_regmap_update_bits, }; @@ -88,7 +88,7 @@ Signed-off-by: David S. Miller int i, ret; /* Initialise the PCS devices */ -@@ -3042,15 +3072,11 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3230,15 +3260,11 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-6.1/790-05-v6.4-net-dsa-mt7530-use-unlocked-regmap-accessors.patch b/target/linux/generic/backport-6.1/790-05-v6.4-net-dsa-mt7530-use-unlocked-regmap-accessors.patch index 0298ebd2740632..bd28b4be76ab73 100644 --- a/target/linux/generic/backport-6.1/790-05-v6.4-net-dsa-mt7530-use-unlocked-regmap-accessors.patch +++ b/target/linux/generic/backport-6.1/790-05-v6.4-net-dsa-mt7530-use-unlocked-regmap-accessors.patch @@ -19,7 +19,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2974,7 +2974,7 @@ static int mt7530_regmap_read(void *cont +@@ -3162,7 +3162,7 @@ static int mt7530_regmap_read(void *cont { struct mt7530_priv *priv = context; @@ -28,7 +28,7 @@ Signed-off-by: David S. Miller return 0; }; -@@ -2982,23 +2982,25 @@ static int mt7530_regmap_write(void *con +@@ -3170,23 +3170,25 @@ static int mt7530_regmap_write(void *con { struct mt7530_priv *priv = context; @@ -62,7 +62,7 @@ Signed-off-by: David S. Miller }; static int -@@ -3024,6 +3026,9 @@ mt7531_create_sgmii(struct mt7530_priv * +@@ -3212,6 +3214,9 @@ mt7531_create_sgmii(struct mt7530_priv * mt7531_pcs_config[i]->reg_stride = 4; mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i); mt7531_pcs_config[i]->max_register = 0x17c; diff --git a/target/linux/generic/backport-6.1/790-06-v6.4-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch b/target/linux/generic/backport-6.1/790-06-v6.4-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch index e5625f67de0649..42c225d91cb1ec 100644 --- a/target/linux/generic/backport-6.1/790-06-v6.4-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch +++ b/target/linux/generic/backport-6.1/790-06-v6.4-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch @@ -133,7 +133,7 @@ Signed-off-by: David S. Miller } static void -@@ -2970,22 +2991,6 @@ static const struct phylink_pcs_ops mt75 +@@ -3158,22 +3179,6 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -156,7 +156,7 @@ Signed-off-by: David S. Miller static void mt7530_mdio_regmap_lock(void *mdio_lock) { -@@ -2998,7 +3003,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc +@@ -3186,7 +3191,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc mutex_unlock(mdio_lock); } @@ -165,7 +165,7 @@ Signed-off-by: David S. Miller .reg_write = mt7530_regmap_write, .reg_read = mt7530_regmap_read, }; -@@ -3031,7 +3036,7 @@ mt7531_create_sgmii(struct mt7530_priv * +@@ -3219,7 +3224,7 @@ mt7531_create_sgmii(struct mt7530_priv * mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock; regmap = devm_regmap_init(priv->dev, @@ -174,7 +174,7 @@ Signed-off-by: David S. Miller mt7531_pcs_config[i]); if (IS_ERR(regmap)) { ret = PTR_ERR(regmap); -@@ -3196,6 +3201,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) +@@ -3385,6 +3390,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) static int mt7530_probe(struct mdio_device *mdiodev) { @@ -182,7 +182,7 @@ Signed-off-by: David S. Miller struct mt7530_priv *priv; struct device_node *dn; -@@ -3275,6 +3281,21 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3464,6 +3470,21 @@ mt7530_probe(struct mdio_device *mdiodev mutex_init(&priv->reg_mutex); dev_set_drvdata(&mdiodev->dev, priv); @@ -206,7 +206,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -774,6 +774,7 @@ struct mt753x_info { +@@ -785,6 +785,7 @@ struct mt753x_info { * @dev: The device pointer * @ds: The pointer to the dsa core structure * @bus: The bus used for the device and built-in PHY @@ -214,7 +214,7 @@ Signed-off-by: David S. Miller * @rstc: The pointer to reset control used by MCM * @core_pwr: The power supplied into the core * @io_pwr: The power supplied into the I/O -@@ -794,6 +795,7 @@ struct mt7530_priv { +@@ -805,6 +806,7 @@ struct mt7530_priv { struct device *dev; struct dsa_switch *ds; struct mii_bus *bus; diff --git a/target/linux/generic/backport-6.1/790-07-v6.4-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch b/target/linux/generic/backport-6.1/790-07-v6.4-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch index ca1f38f9c23844..9cd817c05680be 100644 --- a/target/linux/generic/backport-6.1/790-07-v6.4-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch +++ b/target/linux/generic/backport-6.1/790-07-v6.4-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3082,12 +3082,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3270,12 +3270,6 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -31,7 +31,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -3204,6 +3198,7 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3393,6 +3387,7 @@ mt7530_probe(struct mdio_device *mdiodev static struct regmap_config *regmap_config; struct mt7530_priv *priv; struct device_node *dn; @@ -39,7 +39,7 @@ Signed-off-by: David S. Miller dn = mdiodev->dev.of_node; -@@ -3296,6 +3291,12 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3485,6 +3480,12 @@ mt7530_probe(struct mdio_device *mdiodev if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); diff --git a/target/linux/generic/backport-6.1/790-08-v6.4-net-dsa-mt7530-introduce-mutex-helpers.patch b/target/linux/generic/backport-6.1/790-08-v6.4-net-dsa-mt7530-introduce-mutex-helpers.patch index 813e976810525c..4f77078eef9673 100644 --- a/target/linux/generic/backport-6.1/790-08-v6.4-net-dsa-mt7530-introduce-mutex-helpers.patch +++ b/target/linux/generic/backport-6.1/790-08-v6.4-net-dsa-mt7530-introduce-mutex-helpers.patch @@ -114,7 +114,7 @@ Signed-off-by: David S. Miller } static void -@@ -645,14 +649,13 @@ static int +@@ -659,14 +663,13 @@ static int mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, int regnum) { @@ -130,7 +130,7 @@ Signed-off-by: David S. Miller ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, !(val & MT7531_PHY_ACS_ST), 20, 100000); -@@ -685,7 +688,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr +@@ -699,7 +702,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr ret = val & MT7531_MDIO_RW_DATA_MASK; out: @@ -139,7 +139,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -694,14 +697,13 @@ static int +@@ -708,14 +711,13 @@ static int mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, int regnum, u32 data) { @@ -155,7 +155,7 @@ Signed-off-by: David S. Miller ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, !(val & MT7531_PHY_ACS_ST), 20, 100000); -@@ -733,7 +735,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p +@@ -747,7 +749,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p } out: @@ -164,7 +164,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -741,14 +743,13 @@ out: +@@ -755,14 +757,13 @@ out: static int mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) { @@ -180,7 +180,7 @@ Signed-off-by: David S. Miller ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, !(val & MT7531_PHY_ACS_ST), 20, 100000); -@@ -771,7 +772,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr +@@ -785,7 +786,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr ret = val & MT7531_MDIO_RW_DATA_MASK; out: @@ -189,7 +189,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -780,14 +781,13 @@ static int +@@ -794,14 +795,13 @@ static int mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, u16 data) { @@ -205,7 +205,7 @@ Signed-off-by: David S. Miller ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, !(reg & MT7531_PHY_ACS_ST), 20, 100000); -@@ -809,7 +809,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p +@@ -823,7 +823,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p } out: @@ -214,7 +214,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -1161,7 +1161,6 @@ static int +@@ -1343,7 +1343,6 @@ static int mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct mt7530_priv *priv = ds->priv; @@ -222,7 +222,7 @@ Signed-off-by: David S. Miller int length; u32 val; -@@ -1172,7 +1171,7 @@ mt7530_port_change_mtu(struct dsa_switch +@@ -1354,7 +1353,7 @@ mt7530_port_change_mtu(struct dsa_switch if (!dsa_is_cpu_port(ds, port)) return 0; @@ -231,7 +231,7 @@ Signed-off-by: David S. Miller val = mt7530_mii_read(priv, MT7530_GMACCR); val &= ~MAX_RX_PKT_LEN_MASK; -@@ -1193,7 +1192,7 @@ mt7530_port_change_mtu(struct dsa_switch +@@ -1375,7 +1374,7 @@ mt7530_port_change_mtu(struct dsa_switch mt7530_mii_write(priv, MT7530_GMACCR, val); @@ -240,7 +240,7 @@ Signed-off-by: David S. Miller return 0; } -@@ -1994,10 +1993,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ +@@ -2176,10 +2175,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ u32 val; int p; @@ -253,7 +253,7 @@ Signed-off-by: David S. Miller for (p = 0; p < MT7530_NUM_PHYS; p++) { if (BIT(p) & val) { -@@ -2033,7 +2032,7 @@ mt7530_irq_bus_lock(struct irq_data *d) +@@ -2215,7 +2214,7 @@ mt7530_irq_bus_lock(struct irq_data *d) { struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); @@ -262,7 +262,7 @@ Signed-off-by: David S. Miller } static void -@@ -2042,7 +2041,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da +@@ -2224,7 +2223,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); diff --git a/target/linux/generic/backport-6.1/790-09-v6.4-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch b/target/linux/generic/backport-6.1/790-09-v6.4-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch index 177f6af78084c6..9cb0b2dd61e16c 100644 --- a/target/linux/generic/backport-6.1/790-09-v6.4-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch +++ b/target/linux/generic/backport-6.1/790-09-v6.4-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch @@ -21,7 +21,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -950,6 +950,24 @@ mt7530_set_ageing_time(struct dsa_switch +@@ -964,6 +964,24 @@ mt7530_set_ageing_time(struct dsa_switch return 0; } @@ -48,7 +48,7 @@ Signed-off-by: David S. Miller struct mt7530_priv *priv = ds->priv; --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -709,24 +709,6 @@ enum p5_interface_select { +@@ -720,24 +720,6 @@ enum p5_interface_select { P5_INTF_SEL_GMAC5_SGMII, }; diff --git a/target/linux/generic/backport-6.1/790-10-v6.4-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch b/target/linux/generic/backport-6.1/790-10-v6.4-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch index 8950caaaeff268..a6af6828264e30 100644 --- a/target/linux/generic/backport-6.1/790-10-v6.4-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch +++ b/target/linux/generic/backport-6.1/790-10-v6.4-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3210,44 +3210,21 @@ static const struct of_device_id mt7530_ +@@ -3399,44 +3399,21 @@ static const struct of_device_id mt7530_ MODULE_DEVICE_TABLE(of, mt7530_of_match); static int @@ -67,7 +67,7 @@ Signed-off-by: David S. Miller if (!priv->info) return -EINVAL; -@@ -3261,23 +3238,53 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3450,23 +3427,53 @@ mt7530_probe(struct mdio_device *mdiodev return -EINVAL; priv->id = priv->info->id; @@ -131,7 +131,7 @@ Signed-off-by: David S. Miller priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(priv->reset)) { -@@ -3286,12 +3293,15 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3475,12 +3482,15 @@ mt7530_probe(struct mdio_device *mdiodev } } diff --git a/target/linux/generic/backport-6.1/790-11-v6.4-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch b/target/linux/generic/backport-6.1/790-11-v6.4-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch index 24eadb589e6c7f..4192753e89b30c 100644 --- a/target/linux/generic/backport-6.1/790-11-v6.4-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch +++ b/target/linux/generic/backport-6.1/790-11-v6.4-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3328,6 +3328,17 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3517,6 +3517,17 @@ mt7530_probe(struct mdio_device *mdiodev } static void @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller mt7530_remove(struct mdio_device *mdiodev) { struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); -@@ -3346,15 +3357,10 @@ mt7530_remove(struct mdio_device *mdiode +@@ -3535,15 +3546,10 @@ mt7530_remove(struct mdio_device *mdiode dev_err(priv->dev, "Failed to disable io pwr: %d\n", ret); diff --git a/target/linux/generic/backport-6.1/790-12-v6.4-net-dsa-mt7530-introduce-separate-MDIO-driver.patch b/target/linux/generic/backport-6.1/790-12-v6.4-net-dsa-mt7530-introduce-separate-MDIO-driver.patch index a6bb7d9e7b1bba..72a499381f404f 100644 --- a/target/linux/generic/backport-6.1/790-12-v6.4-net-dsa-mt7530-introduce-separate-MDIO-driver.patch +++ b/target/linux/generic/backport-6.1/790-12-v6.4-net-dsa-mt7530-introduce-separate-MDIO-driver.patch @@ -420,7 +420,7 @@ Signed-off-by: David S. Miller static u32 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) { -@@ -3008,72 +2959,6 @@ static const struct phylink_pcs_ops mt75 +@@ -3196,72 +3147,6 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -493,7 +493,7 @@ Signed-off-by: David S. Miller static int mt753x_setup(struct dsa_switch *ds) { -@@ -3132,7 +3017,7 @@ static int mt753x_set_mac_eee(struct dsa +@@ -3320,7 +3205,7 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -501,8 +501,8 @@ Signed-off-by: David S. Miller +const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, - .get_strings = mt7530_get_strings, -@@ -3166,8 +3051,9 @@ static const struct dsa_switch_ops mt753 + .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, +@@ -3355,8 +3240,9 @@ static const struct dsa_switch_ops mt753 .get_mac_eee = mt753x_get_mac_eee, .set_mac_eee = mt753x_set_mac_eee, }; @@ -513,7 +513,7 @@ Signed-off-by: David S. Miller [ID_MT7621] = { .id = ID_MT7621, .pcs_ops = &mt7530_pcs_ops, -@@ -3200,16 +3086,9 @@ static const struct mt753x_info mt753x_t +@@ -3389,16 +3275,9 @@ static const struct mt753x_info mt753x_t .mac_port_config = mt7531_mac_config, }, }; @@ -532,7 +532,7 @@ Signed-off-by: David S. Miller mt7530_probe_common(struct mt7530_priv *priv) { struct device *dev = priv->dev; -@@ -3246,88 +3125,9 @@ mt7530_probe_common(struct mt7530_priv * +@@ -3435,88 +3314,9 @@ mt7530_probe_common(struct mt7530_priv * return 0; } @@ -623,7 +623,7 @@ Signed-off-by: David S. Miller mt7530_remove_common(struct mt7530_priv *priv) { if (priv->irq) -@@ -3337,55 +3137,7 @@ mt7530_remove_common(struct mt7530_priv +@@ -3526,55 +3326,7 @@ mt7530_remove_common(struct mt7530_priv mutex_destroy(&priv->reg_mutex); } @@ -682,7 +682,7 @@ Signed-off-by: David S. Miller MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -834,4 +834,10 @@ static inline void INIT_MT7530_DUMMY_POL +@@ -845,4 +845,10 @@ static inline void INIT_MT7530_DUMMY_POL p->reg = reg; } diff --git a/target/linux/generic/backport-6.1/790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-6.1/790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch index 9bc3f54c235663..f5573fc6c458d9 100644 --- a/target/linux/generic/backport-6.1/790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch +++ b/target/linux/generic/backport-6.1/790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch @@ -184,7 +184,7 @@ Signed-off-by: David S. Miller +MODULE_LICENSE("GPL"); --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2041,6 +2041,47 @@ static const struct irq_domain_ops mt753 +@@ -2223,6 +2223,47 @@ static const struct irq_domain_ops mt753 }; static void @@ -232,7 +232,7 @@ Signed-off-by: David S. Miller mt7530_setup_mdio_irq(struct mt7530_priv *priv) { struct dsa_switch *ds = priv->ds; -@@ -2074,8 +2115,15 @@ mt7530_setup_irq(struct mt7530_priv *pri +@@ -2256,8 +2297,15 @@ mt7530_setup_irq(struct mt7530_priv *pri return priv->irq ? : -EINVAL; } @@ -250,7 +250,7 @@ Signed-off-by: David S. Miller if (!priv->irq_domain) { dev_err(dev, "failed to create IRQ domain\n"); return -ENOMEM; -@@ -2574,6 +2622,25 @@ static void mt7531_mac_port_get_caps(str +@@ -2762,6 +2810,25 @@ static void mt7531_mac_port_get_caps(str } } @@ -276,7 +276,7 @@ Signed-off-by: David S. Miller static int mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) { -@@ -2650,6 +2717,17 @@ static bool mt753x_is_mac_port(u32 port) +@@ -2838,6 +2905,17 @@ static bool mt753x_is_mac_port(u32 port) } static int @@ -294,7 +294,7 @@ Signed-off-by: David S. Miller mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { -@@ -2719,7 +2797,8 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2907,7 +2985,8 @@ mt753x_phylink_mac_config(struct dsa_swi switch (port) { case 0 ... 4: /* Internal phy */ @@ -304,7 +304,7 @@ Signed-off-by: David S. Miller goto unsupported; break; case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ -@@ -2797,7 +2876,8 @@ static void mt753x_phylink_mac_link_up(s +@@ -2985,7 +3064,8 @@ static void mt753x_phylink_mac_link_up(s /* MT753x MAC works in 1G full duplex mode for all up-clocked * variants. */ @@ -314,7 +314,7 @@ Signed-off-by: David S. Miller (phy_interface_mode_is_8023z(interface))) { speed = SPEED_1000; duplex = DUPLEX_FULL; -@@ -2877,6 +2957,21 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -3065,6 +3145,21 @@ mt7531_cpu_port_config(struct dsa_switch return 0; } @@ -336,7 +336,7 @@ Signed-off-by: David S. Miller static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { -@@ -3019,6 +3114,27 @@ static int mt753x_set_mac_eee(struct dsa +@@ -3207,6 +3302,27 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -364,7 +364,7 @@ Signed-off-by: David S. Miller const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, -@@ -3087,6 +3203,17 @@ const struct mt753x_info mt753x_table[] +@@ -3276,6 +3392,17 @@ const struct mt753x_info mt753x_table[] .mac_port_get_caps = mt7531_mac_port_get_caps, .mac_port_config = mt7531_mac_config, }, @@ -392,9 +392,9 @@ Signed-off-by: David S. Miller }; #define NUM_TRGMII_CTRL 5 -@@ -54,11 +55,11 @@ enum mt753x_id { - #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) +@@ -59,11 +60,11 @@ enum mt753x_id { #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) + #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) -#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \ +#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ @@ -407,7 +407,7 @@ Signed-off-by: David S. Miller MT7531_MIRROR_MASK : MIRROR_MASK) /* Registers for BPDU and PAE frame control*/ -@@ -322,9 +323,8 @@ enum mt7530_vlan_port_acc_frm { +@@ -332,9 +333,8 @@ enum mt7530_vlan_port_acc_frm { MT7531_FORCE_DPX | \ MT7531_FORCE_RX_FC | \ MT7531_FORCE_TX_FC) diff --git a/target/linux/generic/backport-6.1/790-15-v6.4-net-dsa-mt7530-fix-support-for-MT7531BE.patch b/target/linux/generic/backport-6.1/790-15-v6.4-net-dsa-mt7530-fix-support-for-MT7531BE.patch index ef2d07ab79910e..40209b030583b8 100644 --- a/target/linux/generic/backport-6.1/790-15-v6.4-net-dsa-mt7530-fix-support-for-MT7531BE.patch +++ b/target/linux/generic/backport-6.1/790-15-v6.4-net-dsa-mt7530-fix-support-for-MT7531BE.patch @@ -73,7 +73,7 @@ Signed-off-by: Jakub Kicinski } --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3081,6 +3081,12 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3269,6 +3269,12 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -88,7 +88,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -768,10 +768,10 @@ struct mt753x_info { +@@ -779,10 +779,10 @@ struct mt753x_info { * registers * @p6_interface Holding the current port 6 interface * @p5_intf_sel: Holding the current port 5 interface select @@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski */ struct mt7530_priv { struct device *dev; -@@ -790,7 +790,6 @@ struct mt7530_priv { +@@ -801,7 +801,6 @@ struct mt7530_priv { unsigned int p5_intf_sel; u8 mirror_rx; u8 mirror_tx; @@ -108,7 +108,7 @@ Signed-off-by: Jakub Kicinski struct mt7530_port ports[MT7530_NUM_PORTS]; struct mt753x_pcs pcs[MT7530_NUM_PORTS]; /* protect among processes for registers access*/ -@@ -798,6 +797,7 @@ struct mt7530_priv { +@@ -809,6 +808,7 @@ struct mt7530_priv { int irq; struct irq_domain *irq_domain; u32 irq_enable; diff --git a/target/linux/generic/backport-6.1/790-16-v6.4-net-dsa-mt7530-set-all-CPU-ports-in-MT7531_CPU_PMAP.patch b/target/linux/generic/backport-6.1/790-16-v6.4-net-dsa-mt7530-set-all-CPU-ports-in-MT7531_CPU_PMAP.patch deleted file mode 100644 index 068fb38a4ee110..00000000000000 --- a/target/linux/generic/backport-6.1/790-16-v6.4-net-dsa-mt7530-set-all-CPU-ports-in-MT7531_CPU_PMAP.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 4b11e3eb0eb7245a0d22a5dc4161c54eea42910c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Sat, 17 Jun 2023 09:26:44 +0300 -Subject: [PATCH 16/48] net: dsa: mt7530: set all CPU ports in MT7531_CPU_PMAP -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MT7531_CPU_PMAP represents the destination port mask for trapped-to-CPU -frames (further restricted by PCR_MATRIX). - -Currently the driver sets the first CPU port as the single port in this bit -mask, which works fine regardless of whether the device tree defines port -5, 6 or 5+6 as CPU ports. This is because the logic coincides with DSA's -logic of picking the first CPU port as the CPU port that all user ports are -affine to, by default. - -An upcoming change would like to influence DSA's selection of the default -CPU port to no longer be the first one, and in that case, this logic needs -adaptation. - -Since there is no observed leakage or duplication of frames if all CPU -ports are defined in this bit mask, simply include them all. - -Suggested-by: Russell King (Oracle) -Suggested-by: Vladimir Oltean -Signed-off-by: Arınç ÜNAL -Reviewed-by: Vladimir Oltean -Reviewed-by: Russell King (Oracle) -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/mt7530.c | 15 +++++++-------- - drivers/net/dsa/mt7530.h | 1 + - 2 files changed, 8 insertions(+), 8 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1069,6 +1069,13 @@ mt753x_cpu_port_enable(struct dsa_switch - if (priv->id == ID_MT7530 || priv->id == ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - -+ /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on -+ * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that -+ * is affine to the inbound user port. -+ */ -+ if (priv->id == ID_MT7531 || priv->id == ID_MT7988) -+ mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); -+ - /* CPU port gets connected to all user ports of - * the switch. - */ -@@ -2411,16 +2418,8 @@ static int - mt7531_setup_common(struct dsa_switch *ds) - { - struct mt7530_priv *priv = ds->priv; -- struct dsa_port *cpu_dp; - int ret, i; - -- /* BPDU to CPU port */ -- dsa_switch_for_each_cpu_port(cpu_dp, ds) { -- mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, -- BIT(cpu_dp->index)); -- break; -- } -- - mt753x_trap_frames(priv); - - /* Enable and reset MIB counters */ ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -54,6 +54,7 @@ enum mt753x_id { - #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) - #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) - #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) -+#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) - - #define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ - MT7531_CFC : MT7530_MFC) diff --git a/target/linux/generic/backport-6.1/790-17-v6.5-net-dsa-mt7530-update-PCS-driver-to-use-neg_mode.patch b/target/linux/generic/backport-6.1/790-17-v6.5-net-dsa-mt7530-update-PCS-driver-to-use-neg_mode.patch index bbf6d9b16ff9a8..78e332b1c2ae51 100644 --- a/target/linux/generic/backport-6.1/790-17-v6.5-net-dsa-mt7530-update-PCS-driver-to-use-neg_mode.patch +++ b/target/linux/generic/backport-6.1/790-17-v6.5-net-dsa-mt7530-update-PCS-driver-to-use-neg_mode.patch @@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3036,7 +3036,7 @@ static void mt7530_pcs_get_state(struct +@@ -3225,7 +3225,7 @@ static void mt7530_pcs_get_state(struct state->pause |= MLO_PAUSE_TX; } @@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski phy_interface_t interface, const unsigned long *advertising, bool permit_pause_to_mac) -@@ -3064,6 +3064,7 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3253,6 +3253,7 @@ mt753x_setup(struct dsa_switch *ds) /* Initialise the PCS devices */ for (i = 0; i < priv->ds->num_ports; i++) { priv->pcs[i].pcs.ops = priv->info->pcs_ops; diff --git a/target/linux/generic/backport-6.1/790-19-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch b/target/linux/generic/backport-6.1/790-19-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch index e9a36eea41ac95..d69ee7f104d11d 100644 --- a/target/linux/generic/backport-6.1/790-19-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch +++ b/target/linux/generic/backport-6.1/790-19-v6.7-net-dsa-mt753x-remove-mt753x_phylink_pcs_link_up.patch @@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2851,15 +2851,6 @@ static void mt753x_phylink_mac_link_down +@@ -3040,15 +3040,6 @@ static void mt753x_phylink_mac_link_down mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); } @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface, -@@ -2948,8 +2939,6 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -3137,8 +3128,6 @@ mt7531_cpu_port_config(struct dsa_switch return ret; mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPU_PORT_SETTING(priv->id)); diff --git a/target/linux/generic/backport-6.1/790-20-v6.7-net-dsa-mt7530-replace-deprecated-strncpy-with-ethto.patch b/target/linux/generic/backport-6.1/790-20-v6.7-net-dsa-mt7530-replace-deprecated-strncpy-with-ethto.patch index e8fec3f6a1a45c..8af6820270c5c3 100644 --- a/target/linux/generic/backport-6.1/790-20-v6.7-net-dsa-mt7530-replace-deprecated-strncpy-with-ethto.patch +++ b/target/linux/generic/backport-6.1/790-20-v6.7-net-dsa-mt7530-replace-deprecated-strncpy-with-ethto.patch @@ -28,7 +28,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -829,8 +829,7 @@ mt7530_get_strings(struct dsa_switch *ds +@@ -843,8 +843,7 @@ mt7530_get_strings(struct dsa_switch *ds return; for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) diff --git a/target/linux/generic/backport-6.1/790-21-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch b/target/linux/generic/backport-6.1/790-21-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch index 8b374679cadc0a..4c6c0577391ee7 100644 --- a/target/linux/generic/backport-6.1/790-21-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch +++ b/target/linux/generic/backport-6.1/790-21-v6.9-net-dsa-mt7530-support-OF-based-registration-of-swit.patch @@ -46,7 +46,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2175,24 +2175,40 @@ mt7530_free_irq_common(struct mt7530_pri +@@ -2350,24 +2350,40 @@ mt7530_free_irq_common(struct mt7530_pri static void mt7530_free_irq(struct mt7530_priv *priv) { @@ -92,7 +92,7 @@ Signed-off-by: Paolo Abeni bus->priv = priv; bus->name = KBUILD_MODNAME "-mii"; snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); -@@ -2201,16 +2217,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2376,16 +2392,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr bus->parent = dev; bus->phy_mask = ~ds->phys_mii_mask; diff --git a/target/linux/generic/backport-6.1/790-22-v6.8-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/backport-6.1/790-22-v6.8-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch index 381902472c8ab3..0b141b4a3f09b0 100644 --- a/target/linux/generic/backport-6.1/790-22-v6.8-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch +++ b/target/linux/generic/backport-6.1/790-22-v6.8-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch @@ -22,7 +22,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2883,8 +2883,7 @@ static void mt753x_phylink_mac_link_up(s +@@ -3072,8 +3072,7 @@ static void mt753x_phylink_mac_link_up(s /* MT753x MAC works in 1G full duplex mode for all up-clocked * variants. */ diff --git a/target/linux/generic/backport-6.1/790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch b/target/linux/generic/backport-6.1/790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch index c3f55f8106d181..44d8e07c12eea1 100644 --- a/target/linux/generic/backport-6.1/790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch +++ b/target/linux/generic/backport-6.1/790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch @@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1064,10 +1064,6 @@ mt753x_cpu_port_enable(struct dsa_switch +@@ -1239,10 +1239,6 @@ mt753x_cpu_port_enable(struct dsa_switch mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); @@ -46,10 +46,10 @@ Signed-off-by: Jakub Kicinski - if (priv->id == ID_MT7530 || priv->id == ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on - * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that - * is affine to the inbound user port. -@@ -3125,6 +3121,36 @@ static int mt753x_set_mac_eee(struct dsa + /* Add the CPU port to the CPU port bitmap for MT7531. Trapped frames + * will be forwarded to the CPU port that is affine to the inbound user + * port. +@@ -3314,6 +3310,36 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { return 0; -@@ -3179,6 +3205,7 @@ const struct dsa_switch_ops mt7530_switc +@@ -3369,6 +3395,7 @@ const struct dsa_switch_ops mt7530_switc .phylink_mac_link_up = mt753x_phylink_mac_link_up, .get_mac_eee = mt753x_get_mac_eee, .set_mac_eee = mt753x_set_mac_eee, @@ -96,7 +96,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -41,8 +41,8 @@ enum mt753x_id { +@@ -45,8 +45,8 @@ enum mt753x_id { #define UNU_FFP(x) (((x) & 0xff) << 8) #define UNU_FFP_MASK UNU_FFP(~0) #define CPU_EN BIT(7) @@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski #define MIRROR_EN BIT(3) #define MIRROR_PORT(x) ((x) & 0x7) #define MIRROR_MASK 0x7 -@@ -773,6 +773,7 @@ struct mt753x_info { +@@ -783,6 +783,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) @@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski */ struct mt7530_priv { struct device *dev; -@@ -799,6 +800,7 @@ struct mt7530_priv { +@@ -809,6 +810,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); diff --git a/target/linux/generic/backport-6.1/790-24-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch b/target/linux/generic/backport-6.1/790-24-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch index 35abed6b037bd0..3454948b865113 100644 --- a/target/linux/generic/backport-6.1/790-24-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch +++ b/target/linux/generic/backport-6.1/790-24-v6.9-net-dsa-mt7530-use-p5_interface_select-as-data-type-.patch @@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -703,7 +703,7 @@ struct mt7530_port { +@@ -713,7 +713,7 @@ struct mt7530_port { /* Port 5 interface select definitions */ enum p5_interface_select { @@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, -@@ -789,7 +789,7 @@ struct mt7530_priv { +@@ -799,7 +799,7 @@ struct mt7530_priv { bool mcm; phy_interface_t p6_interface; phy_interface_t p5_interface; diff --git a/target/linux/generic/backport-6.1/790-25-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch b/target/linux/generic/backport-6.1/790-25-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch index 03329f8ba88008..357579e2bdf1b3 100644 --- a/target/linux/generic/backport-6.1/790-25-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch +++ b/target/linux/generic/backport-6.1/790-25-v6.9-net-dsa-mt7530-store-port-5-SGMII-capability-of-MT75.patch @@ -65,7 +65,7 @@ Signed-off-by: Jakub Kicinski GFP_KERNEL); --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -473,15 +473,6 @@ mt7530_pad_clk_setup(struct dsa_switch * +@@ -487,15 +487,6 @@ mt7530_pad_clk_setup(struct dsa_switch * return 0; } @@ -81,7 +81,7 @@ Signed-off-by: Jakub Kicinski static int mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { -@@ -496,9 +487,6 @@ mt7531_pll_setup(struct mt7530_priv *pri +@@ -510,9 +501,6 @@ mt7531_pll_setup(struct mt7530_priv *pri u32 xtal; u32 val; @@ -91,7 +91,7 @@ Signed-off-by: Jakub Kicinski val = mt7530_read(priv, MT7531_CREV); top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); hwstrap = mt7530_read(priv, MT7531_HWTRAP); -@@ -913,8 +901,6 @@ static const char *p5_intf_modes(unsigne +@@ -927,8 +915,6 @@ static const char *p5_intf_modes(unsigne return "PHY P4"; case P5_INTF_SEL_GMAC5: return "GMAC5"; @@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski default: return "unknown"; } -@@ -2515,6 +2501,12 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2697,6 +2683,12 @@ mt7531_setup(struct dsa_switch *ds) return -ENODEV; } @@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski /* all MACs must be forced link-down before sw reset */ for (i = 0; i < MT7530_NUM_PORTS; i++) mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); -@@ -2524,21 +2516,18 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2706,21 +2698,18 @@ mt7531_setup(struct dsa_switch *ds) SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); @@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); -@@ -2598,11 +2587,6 @@ static void mt7530_mac_port_get_caps(str +@@ -2787,11 +2776,6 @@ static void mt7530_mac_port_get_caps(str } } @@ -153,7 +153,7 @@ Signed-off-by: Jakub Kicinski static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { -@@ -2615,7 +2599,7 @@ static void mt7531_mac_port_get_caps(str +@@ -2804,7 +2788,7 @@ static void mt7531_mac_port_get_caps(str break; case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ @@ -162,7 +162,7 @@ Signed-off-by: Jakub Kicinski phy_interface_set_rgmii(config->supported_interfaces); break; } -@@ -2682,7 +2666,7 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2871,7 +2855,7 @@ static int mt7531_rgmii_setup(struct mt7 { u32 val; @@ -171,7 +171,7 @@ Signed-off-by: Jakub Kicinski dev_err(priv->dev, "RGMII mode is not available for port %d\n", port); return -EINVAL; -@@ -2925,7 +2909,7 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -3114,7 +3098,7 @@ mt7531_cpu_port_config(struct dsa_switch switch (port) { case 5: @@ -180,7 +180,7 @@ Signed-off-by: Jakub Kicinski interface = PHY_INTERFACE_MODE_RGMII; else interface = PHY_INTERFACE_MODE_2500BASEX; -@@ -3083,7 +3067,7 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3272,7 +3256,7 @@ mt753x_setup(struct dsa_switch *ds) mt7530_free_irq_common(priv); if (priv->create_sgmii) { @@ -191,7 +191,7 @@ Signed-off-by: Jakub Kicinski } --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -707,7 +707,6 @@ enum p5_interface_select { +@@ -717,7 +717,6 @@ enum p5_interface_select { P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, @@ -199,7 +199,7 @@ Signed-off-by: Jakub Kicinski }; struct mt7530_priv; -@@ -769,6 +768,8 @@ struct mt753x_info { +@@ -779,6 +778,8 @@ struct mt753x_info { * registers * @p6_interface Holding the current port 6 interface * @p5_intf_sel: Holding the current port 5 interface select @@ -208,7 +208,7 @@ Signed-off-by: Jakub Kicinski * @irq: IRQ number of the switch * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN -@@ -790,6 +791,7 @@ struct mt7530_priv { +@@ -800,6 +801,7 @@ struct mt7530_priv { phy_interface_t p6_interface; phy_interface_t p5_interface; enum p5_interface_select p5_intf_sel; @@ -216,7 +216,7 @@ Signed-off-by: Jakub Kicinski u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; -@@ -799,7 +801,7 @@ struct mt7530_priv { +@@ -809,7 +811,7 @@ struct mt7530_priv { int irq; struct irq_domain *irq_domain; u32 irq_enable; diff --git a/target/linux/generic/backport-6.1/790-26-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch b/target/linux/generic/backport-6.1/790-26-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch index 1489c4f2f3ba29..46dbd53ede48db 100644 --- a/target/linux/generic/backport-6.1/790-26-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch +++ b/target/linux/generic/backport-6.1/790-26-v6.9-net-dsa-mt7530-improve-comments-regarding-switch-por.patch @@ -37,7 +37,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2565,12 +2565,14 @@ static void mt7530_mac_port_get_caps(str +@@ -2754,12 +2754,14 @@ static void mt7530_mac_port_get_caps(str struct phylink_config *config) { switch (port) { @@ -54,7 +54,7 @@ Signed-off-by: Jakub Kicinski phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); -@@ -2578,7 +2580,8 @@ static void mt7530_mac_port_get_caps(str +@@ -2767,7 +2769,8 @@ static void mt7530_mac_port_get_caps(str config->supported_interfaces); break; @@ -64,7 +64,7 @@ Signed-off-by: Jakub Kicinski __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, -@@ -2593,19 +2596,24 @@ static void mt7531_mac_port_get_caps(str +@@ -2782,19 +2785,24 @@ static void mt7531_mac_port_get_caps(str struct mt7530_priv *priv = ds->priv; switch (port) { @@ -92,7 +92,7 @@ Signed-off-by: Jakub Kicinski __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, -@@ -2624,11 +2632,13 @@ static void mt7988_mac_port_get_caps(str +@@ -2813,11 +2821,13 @@ static void mt7988_mac_port_get_caps(str phy_interface_zero(config->supported_interfaces); switch (port) { @@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski case 6: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); -@@ -2792,12 +2802,12 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2981,12 +2991,12 @@ mt753x_phylink_mac_config(struct dsa_swi u32 mcr_cur, mcr_new; switch (port) { @@ -122,7 +122,7 @@ Signed-off-by: Jakub Kicinski if (priv->p5_interface == state->interface) break; -@@ -2807,7 +2817,7 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2996,7 +3006,7 @@ mt753x_phylink_mac_config(struct dsa_swi if (priv->p5_intf_sel != P5_DISABLED) priv->p5_interface = state->interface; break; diff --git a/target/linux/generic/backport-6.1/790-27-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch b/target/linux/generic/backport-6.1/790-27-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch index 6fbf259735dd0a..43f629b2431d1c 100644 --- a/target/linux/generic/backport-6.1/790-27-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch +++ b/target/linux/generic/backport-6.1/790-27-v6.9-net-dsa-mt7530-improve-code-path-for-setting-up-port.patch @@ -52,7 +52,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2353,16 +2353,15 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2532,16 +2532,15 @@ mt7530_setup(struct dsa_switch *ds) return ret; /* Setup port 5 */ @@ -75,7 +75,7 @@ Signed-off-by: Jakub Kicinski for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) -@@ -2393,6 +2392,8 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2572,6 +2571,8 @@ mt7530_setup(struct dsa_switch *ds) of_node_put(phy_node); break; } @@ -84,7 +84,7 @@ Signed-off-by: Jakub Kicinski } #ifdef CONFIG_GPIOLIB -@@ -2403,8 +2404,6 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2582,8 +2583,6 @@ mt7530_setup(struct dsa_switch *ds) } #endif /* CONFIG_GPIOLIB */ diff --git a/target/linux/generic/backport-6.1/790-28-v6.9-net-dsa-mt7530-do-not-set-priv-p5_interface-on-mt753.patch b/target/linux/generic/backport-6.1/790-28-v6.9-net-dsa-mt7530-do-not-set-priv-p5_interface-on-mt753.patch index 94692d948ffbf1..385d587729ee02 100644 --- a/target/linux/generic/backport-6.1/790-28-v6.9-net-dsa-mt7530-do-not-set-priv-p5_interface-on-mt753.patch +++ b/target/linux/generic/backport-6.1/790-28-v6.9-net-dsa-mt7530-do-not-set-priv-p5_interface-on-mt753.patch @@ -31,7 +31,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -971,8 +971,6 @@ static void mt7530_setup_port5(struct ds +@@ -985,8 +985,6 @@ static void mt7530_setup_port5(struct ds dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); diff --git a/target/linux/generic/backport-6.1/790-29-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch b/target/linux/generic/backport-6.1/790-29-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch index c121eb4a358598..b4c0b75c49c7f0 100644 --- a/target/linux/generic/backport-6.1/790-29-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch +++ b/target/linux/generic/backport-6.1/790-29-v6.9-net-dsa-mt7530-do-not-run-mt7530_setup_port5-if-port.patch @@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -935,9 +935,6 @@ static void mt7530_setup_port5(struct ds +@@ -949,9 +949,6 @@ static void mt7530_setup_port5(struct ds /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ val &= ~MHWTRAP_P5_DIS; break; @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski default: dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", priv->p5_intf_sel); -@@ -2358,8 +2355,6 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2537,8 +2534,6 @@ mt7530_setup(struct dsa_switch *ds) * Set priv->p5_intf_sel to the appropriate value if PHY muxing * is detected. */ @@ -49,7 +49,7 @@ Signed-off-by: Jakub Kicinski for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) -@@ -2391,7 +2386,9 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2570,7 +2565,9 @@ mt7530_setup(struct dsa_switch *ds) break; } diff --git a/target/linux/generic/backport-6.1/790-30-v6.9-net-dsa-mt7530-empty-default-case-on-mt7530_setup_po.patch b/target/linux/generic/backport-6.1/790-30-v6.9-net-dsa-mt7530-empty-default-case-on-mt7530_setup_po.patch index 9b610e0bdb09b5..89527e2b39a3b2 100644 --- a/target/linux/generic/backport-6.1/790-30-v6.9-net-dsa-mt7530-empty-default-case-on-mt7530_setup_po.patch +++ b/target/linux/generic/backport-6.1/790-30-v6.9-net-dsa-mt7530-empty-default-case-on-mt7530_setup_po.patch @@ -37,7 +37,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -936,9 +936,7 @@ static void mt7530_setup_port5(struct ds +@@ -950,9 +950,7 @@ static void mt7530_setup_port5(struct ds val &= ~MHWTRAP_P5_DIS; break; default: @@ -48,7 +48,7 @@ Signed-off-by: Jakub Kicinski } /* Setup RGMII settings */ -@@ -968,7 +966,6 @@ static void mt7530_setup_port5(struct ds +@@ -982,7 +980,6 @@ static void mt7530_setup_port5(struct ds dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); diff --git a/target/linux/generic/backport-6.1/790-31-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch b/target/linux/generic/backport-6.1/790-31-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch index dba1cb734e8dd2..0dc4baf0c76af4 100644 --- a/target/linux/generic/backport-6.1/790-31-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch +++ b/target/linux/generic/backport-6.1/790-31-v6.9-net-dsa-mt7530-move-XTAL-check-to-mt7530_setup.patch @@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -408,13 +408,6 @@ mt7530_pad_clk_setup(struct dsa_switch * +@@ -422,13 +422,6 @@ mt7530_pad_clk_setup(struct dsa_switch * xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; @@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski switch (interface) { case PHY_INTERFACE_MODE_RGMII: trgint = 0; -@@ -2286,6 +2279,12 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2461,6 +2454,12 @@ mt7530_setup(struct dsa_switch *ds) return -ENODEV; } diff --git a/target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch b/target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch index 90f8e095ef0cbd..46e1b50f246e6c 100644 --- a/target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch +++ b/target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch @@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -404,65 +404,54 @@ static int +@@ -418,65 +418,54 @@ static int mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; diff --git a/target/linux/generic/backport-6.1/790-33-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch b/target/linux/generic/backport-6.1/790-33-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch index 93eccc8637b7db..7d78b7df70ec52 100644 --- a/target/linux/generic/backport-6.1/790-33-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch +++ b/target/linux/generic/backport-6.1/790-33-v6.9-net-dsa-mt7530-call-port-6-setup-from-mt7530_mac_con.patch @@ -47,7 +47,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -400,8 +400,8 @@ static void mt7530_pll_setup(struct mt75 +@@ -414,8 +414,8 @@ mt753x_preferred_default_local_cpu_port( } /* Setup port 6 interface mode and TRGMII TX circuit */ @@ -58,7 +58,7 @@ Signed-off-by: Jakub Kicinski { struct mt7530_priv *priv = ds->priv; u32 ncpo1, ssc_delta, xtal; -@@ -412,7 +412,7 @@ mt7530_pad_clk_setup(struct dsa_switch * +@@ -426,7 +426,7 @@ mt7530_pad_clk_setup(struct dsa_switch * if (interface == PHY_INTERFACE_MODE_RGMII) { mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(0)); @@ -67,7 +67,7 @@ Signed-off-by: Jakub Kicinski } mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); -@@ -451,7 +451,11 @@ mt7530_pad_clk_setup(struct dsa_switch * +@@ -465,7 +465,11 @@ mt7530_pad_clk_setup(struct dsa_switch * /* Enable the MT7530 TRGMII clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); @@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski return 0; } -@@ -2640,11 +2644,10 @@ mt7530_mac_config(struct dsa_switch *ds, +@@ -2829,11 +2833,10 @@ mt7530_mac_config(struct dsa_switch *ds, { struct mt7530_priv *priv = ds->priv; diff --git a/target/linux/generic/backport-6.1/790-34-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch b/target/linux/generic/backport-6.1/790-34-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch index a423c0899c805d..725830e769d61a 100644 --- a/target/linux/generic/backport-6.1/790-34-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch +++ b/target/linux/generic/backport-6.1/790-34-v6.9-net-dsa-mt7530-remove-pad_setup-function-pointer.patch @@ -28,7 +28,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -453,18 +453,6 @@ mt7530_setup_port6(struct dsa_switch *ds +@@ -467,18 +467,6 @@ mt7530_setup_port6(struct dsa_switch *ds core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); } @@ -47,7 +47,7 @@ Signed-off-by: Jakub Kicinski static void mt7531_pll_setup(struct mt7530_priv *priv) { -@@ -2631,14 +2619,6 @@ static void mt7988_mac_port_get_caps(str +@@ -2820,14 +2808,6 @@ static void mt7988_mac_port_get_caps(str } static int @@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { -@@ -2803,8 +2783,6 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2992,8 +2972,6 @@ mt753x_phylink_mac_config(struct dsa_swi if (priv->p6_interface == state->interface) break; @@ -71,7 +71,7 @@ Signed-off-by: Jakub Kicinski if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; -@@ -3127,11 +3105,6 @@ mt753x_conduit_state_change(struct dsa_s +@@ -3316,11 +3294,6 @@ mt753x_conduit_state_change(struct dsa_s mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val); } @@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski static int mt7988_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; -@@ -3192,7 +3165,6 @@ const struct mt753x_info mt753x_table[] +@@ -3382,7 +3355,6 @@ const struct mt753x_info mt753x_table[] .sw_setup = mt7530_setup, .phy_read = mt7530_phy_read, .phy_write = mt7530_phy_write, @@ -91,7 +91,7 @@ Signed-off-by: Jakub Kicinski .mac_port_get_caps = mt7530_mac_port_get_caps, .mac_port_config = mt7530_mac_config, }, -@@ -3202,7 +3174,6 @@ const struct mt753x_info mt753x_table[] +@@ -3392,7 +3364,6 @@ const struct mt753x_info mt753x_table[] .sw_setup = mt7530_setup, .phy_read = mt7530_phy_read, .phy_write = mt7530_phy_write, @@ -99,7 +99,7 @@ Signed-off-by: Jakub Kicinski .mac_port_get_caps = mt7530_mac_port_get_caps, .mac_port_config = mt7530_mac_config, }, -@@ -3212,7 +3183,6 @@ const struct mt753x_info mt753x_table[] +@@ -3402,7 +3373,6 @@ const struct mt753x_info mt753x_table[] .sw_setup = mt7531_setup, .phy_read = mt7531_ind_phy_read, .phy_write = mt7531_ind_phy_write, @@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski .cpu_port_config = mt7531_cpu_port_config, .mac_port_get_caps = mt7531_mac_port_get_caps, .mac_port_config = mt7531_mac_config, -@@ -3223,7 +3193,6 @@ const struct mt753x_info mt753x_table[] +@@ -3413,7 +3383,6 @@ const struct mt753x_info mt753x_table[] .sw_setup = mt7988_setup, .phy_read = mt7531_ind_phy_read, .phy_write = mt7531_ind_phy_write, @@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski .cpu_port_config = mt7988_cpu_port_config, .mac_port_get_caps = mt7988_mac_port_get_caps, .mac_port_config = mt7988_mac_config, -@@ -3253,9 +3222,8 @@ mt7530_probe_common(struct mt7530_priv * +@@ -3443,9 +3412,8 @@ mt7530_probe_common(struct mt7530_priv * /* Sanity check if these required device operations are filled * properly. */ @@ -129,7 +129,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -722,8 +722,6 @@ struct mt753x_pcs { +@@ -732,8 +732,6 @@ struct mt753x_pcs { * @sw_setup: Holding the handler to a device initialization * @phy_read: Holding the way reading PHY port * @phy_write: Holding the way writing PHY port @@ -138,7 +138,7 @@ Signed-off-by: Jakub Kicinski * @phy_mode_supported: Check if the PHY type is being supported on a certain * port * @mac_port_validate: Holding the way to set addition validate type for a -@@ -739,7 +737,6 @@ struct mt753x_info { +@@ -749,7 +747,6 @@ struct mt753x_info { int (*sw_setup)(struct dsa_switch *ds); int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); diff --git a/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch b/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch index 3667dbf54a4d37..606c48234c18bc 100644 --- a/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch +++ b/target/linux/generic/backport-6.1/790-35-v6.9-net-dsa-mt7530-correct-port-capabilities-of-MT7988.patch @@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2604,7 +2604,7 @@ static void mt7988_mac_port_get_caps(str +@@ -2793,7 +2793,7 @@ static void mt7988_mac_port_get_caps(str switch (port) { /* Ports which are connected to switch PHYs. There is no MII pinout. */ diff --git a/target/linux/generic/backport-6.1/790-36-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch b/target/linux/generic/backport-6.1/790-36-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch index 48433705f62504..e2f1f23435cca9 100644 --- a/target/linux/generic/backport-6.1/790-36-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch +++ b/target/linux/generic/backport-6.1/790-36-v6.9-net-dsa-mt7530-do-not-clear-config-supported_interfa.patch @@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2600,8 +2600,6 @@ static void mt7531_mac_port_get_caps(str +@@ -2789,8 +2789,6 @@ static void mt7531_mac_port_get_caps(str static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { diff --git a/target/linux/generic/backport-6.1/790-37-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch b/target/linux/generic/backport-6.1/790-37-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch index b707de87ed2677..be6fe39f38ff63 100644 --- a/target/linux/generic/backport-6.1/790-37-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch +++ b/target/linux/generic/backport-6.1/790-37-v6.9-net-dsa-mt7530-remove-.mac_port_config-for-MT7988-an.patch @@ -33,7 +33,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2683,17 +2683,6 @@ static bool mt753x_is_mac_port(u32 port) +@@ -2872,17 +2872,6 @@ static bool mt753x_is_mac_port(u32 port) } static int @@ -51,7 +51,7 @@ Signed-off-by: Paolo Abeni mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { -@@ -2733,6 +2722,9 @@ mt753x_mac_config(struct dsa_switch *ds, +@@ -2922,6 +2911,9 @@ mt753x_mac_config(struct dsa_switch *ds, { struct mt7530_priv *priv = ds->priv; @@ -61,7 +61,7 @@ Signed-off-by: Paolo Abeni return priv->info->mac_port_config(ds, port, mode, state->interface); } -@@ -3193,7 +3185,6 @@ const struct mt753x_info mt753x_table[] +@@ -3383,7 +3375,6 @@ const struct mt753x_info mt753x_table[] .phy_write = mt7531_ind_phy_write, .cpu_port_config = mt7988_cpu_port_config, .mac_port_get_caps = mt7988_mac_port_get_caps, @@ -69,7 +69,7 @@ Signed-off-by: Paolo Abeni }, }; EXPORT_SYMBOL_GPL(mt753x_table); -@@ -3221,8 +3212,7 @@ mt7530_probe_common(struct mt7530_priv * +@@ -3411,8 +3402,7 @@ mt7530_probe_common(struct mt7530_priv * * properly. */ if (!priv->info->sw_setup || !priv->info->phy_read || diff --git a/target/linux/generic/backport-6.1/790-38-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch b/target/linux/generic/backport-6.1/790-38-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch index 5dfb8bddbbef45..b8473ed1285e8b 100644 --- a/target/linux/generic/backport-6.1/790-38-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch +++ b/target/linux/generic/backport-6.1/790-38-v6.9-net-dsa-mt7530-set-interrupt-register-only-for-MT753.patch @@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2084,7 +2084,7 @@ mt7530_setup_irq(struct mt7530_priv *pri +@@ -2259,7 +2259,7 @@ mt7530_setup_irq(struct mt7530_priv *pri } /* This register must be set for MT7530 to properly fire interrupts */ diff --git a/target/linux/generic/backport-6.1/790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch b/target/linux/generic/backport-6.1/790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch index 565f16a47f134e..216a781087ddba 100644 --- a/target/linux/generic/backport-6.1/790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch +++ b/target/linux/generic/backport-6.1/790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch @@ -22,7 +22,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2478,14 +2478,12 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2660,14 +2660,12 @@ mt7531_setup(struct dsa_switch *ds) val = mt7530_read(priv, MT7531_TOP_SIG_SR); priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); diff --git a/target/linux/generic/backport-6.1/790-40-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch b/target/linux/generic/backport-6.1/790-40-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch index d636e2d56440c4..f920a6604d5ab7 100644 --- a/target/linux/generic/backport-6.1/790-40-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch +++ b/target/linux/generic/backport-6.1/790-40-v6.9-net-dsa-mt7530-get-rid-of-useless-error-returns-on-p.patch @@ -36,7 +36,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2614,7 +2614,7 @@ static void mt7988_mac_port_get_caps(str +@@ -2803,7 +2803,7 @@ static void mt7988_mac_port_get_caps(str } } @@ -45,7 +45,7 @@ Signed-off-by: Paolo Abeni mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { -@@ -2624,22 +2624,14 @@ mt7530_mac_config(struct dsa_switch *ds, +@@ -2813,22 +2813,14 @@ mt7530_mac_config(struct dsa_switch *ds, mt7530_setup_port5(priv->ds, interface); else if (port == 6) mt7530_setup_port6(priv->ds, interface); @@ -71,7 +71,7 @@ Signed-off-by: Paolo Abeni val = mt7530_read(priv, MT7531_CLKGEN_CTRL); val |= GP_CLK_EN; val &= ~GP_MODE_MASK; -@@ -2667,20 +2659,14 @@ static int mt7531_rgmii_setup(struct mt7 +@@ -2856,20 +2848,14 @@ static int mt7531_rgmii_setup(struct mt7 case PHY_INTERFACE_MODE_RGMII_ID: break; default: @@ -95,7 +95,7 @@ Signed-off-by: Paolo Abeni mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { -@@ -2688,42 +2674,21 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2877,42 +2863,21 @@ mt7531_mac_config(struct dsa_switch *ds, struct phy_device *phydev; struct dsa_port *dp; @@ -143,7 +143,7 @@ Signed-off-by: Paolo Abeni } static struct phylink_pcs * -@@ -2752,17 +2717,11 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2941,17 +2906,11 @@ mt753x_phylink_mac_config(struct dsa_swi u32 mcr_cur, mcr_new; switch (port) { @@ -162,7 +162,7 @@ Signed-off-by: Paolo Abeni if (priv->p5_intf_sel != P5_DISABLED) priv->p5_interface = state->interface; -@@ -2771,16 +2730,10 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2960,16 +2919,10 @@ mt753x_phylink_mac_config(struct dsa_swi if (priv->p6_interface == state->interface) break; @@ -180,7 +180,7 @@ Signed-off-by: Paolo Abeni } mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); -@@ -2863,7 +2816,6 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -3052,7 +3005,6 @@ mt7531_cpu_port_config(struct dsa_switch struct mt7530_priv *priv = ds->priv; phy_interface_t interface; int speed; @@ -188,7 +188,7 @@ Signed-off-by: Paolo Abeni switch (port) { case 5: -@@ -2888,9 +2840,8 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -3077,9 +3029,8 @@ mt7531_cpu_port_config(struct dsa_switch else speed = SPEED_1000; @@ -202,7 +202,7 @@ Signed-off-by: Paolo Abeni mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -743,9 +743,9 @@ struct mt753x_info { +@@ -753,9 +753,9 @@ struct mt753x_info { void (*mac_port_validate)(struct dsa_switch *ds, int port, phy_interface_t interface, unsigned long *supported); diff --git a/target/linux/generic/backport-6.1/790-41-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch b/target/linux/generic/backport-6.1/790-41-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch index 60b369c8f8122f..eb0a5706ecab17 100644 --- a/target/linux/generic/backport-6.1/790-41-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch +++ b/target/linux/generic/backport-6.1/790-41-v6.9-net-dsa-mt7530-get-rid-of-priv-info-cpu_port_config.patch @@ -57,8 +57,8 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -995,18 +995,10 @@ mt753x_trap_frames(struct mt7530_priv *p - MT753X_BPDU_CPU_ONLY); +@@ -1170,18 +1170,10 @@ mt753x_trap_frames(struct mt7530_priv *p + MT753X_BPDU_CPU_ONLY); } -static int @@ -77,7 +77,7 @@ Signed-off-by: Paolo Abeni /* Enable Mediatek header mode on the cpu port */ mt7530_write(priv, MT7530_PVC_P(port), -@@ -1032,8 +1024,6 @@ mt753x_cpu_port_enable(struct dsa_switch +@@ -1207,8 +1199,6 @@ mt753x_cpu_port_enable(struct dsa_switch /* Set to fallback mode for independent VLAN learning */ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE); @@ -86,16 +86,16 @@ Signed-off-by: Paolo Abeni } static int -@@ -2288,8 +2278,6 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2461,8 +2451,6 @@ mt7530_setup(struct dsa_switch *ds) val |= MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); - priv->p6_interface = PHY_INTERFACE_MODE_NA; - - mt753x_trap_frames(priv); + if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) + mt7530_pll_setup(priv); - /* Enable and reset MIB counters */ -@@ -2304,9 +2292,7 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2480,9 +2468,7 @@ mt7530_setup(struct dsa_switch *ds) mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); if (dsa_is_cpu_port(ds, i)) { @@ -106,7 +106,7 @@ Signed-off-by: Paolo Abeni } else { mt7530_port_disable(ds, i); -@@ -2410,9 +2396,7 @@ mt7531_setup_common(struct dsa_switch *d +@@ -2589,9 +2575,7 @@ mt7531_setup_common(struct dsa_switch *d mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); if (dsa_is_cpu_port(ds, i)) { @@ -117,7 +117,7 @@ Signed-off-by: Paolo Abeni } else { mt7530_port_disable(ds, i); -@@ -2501,10 +2485,6 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2683,10 +2667,6 @@ mt7531_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); @@ -125,10 +125,10 @@ Signed-off-by: Paolo Abeni - priv->p5_interface = PHY_INTERFACE_MODE_NA; - priv->p6_interface = PHY_INTERFACE_MODE_NA; - - /* Enable PHY core PLL, since phy_device has not yet been created - * provided for phy_[read,write]_mmd_indirect is called, we provide - * our own mt7531_ind_mmd_phy_[read,write] to complete this -@@ -2716,26 +2696,9 @@ mt753x_phylink_mac_config(struct dsa_swi + /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since + * phy_device has not yet been created provided for + * phy_[read,write]_mmd_indirect is called, we provide our own +@@ -2905,26 +2885,9 @@ mt753x_phylink_mac_config(struct dsa_swi struct mt7530_priv *priv = ds->priv; u32 mcr_cur, mcr_new; @@ -156,7 +156,7 @@ Signed-off-by: Paolo Abeni mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); mcr_new = mcr_cur; mcr_new &= ~PMCR_LINK_SETTINGS_MASK; -@@ -2771,17 +2734,10 @@ static void mt753x_phylink_mac_link_up(s +@@ -2960,17 +2923,10 @@ static void mt753x_phylink_mac_link_up(s mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; @@ -176,7 +176,7 @@ Signed-off-by: Paolo Abeni mcr |= PMCR_FORCE_SPEED_1000; break; case SPEED_100: -@@ -2799,6 +2755,7 @@ static void mt753x_phylink_mac_link_up(s +@@ -2988,6 +2944,7 @@ static void mt753x_phylink_mac_link_up(s if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { switch (speed) { case SPEED_1000: @@ -184,7 +184,7 @@ Signed-off-by: Paolo Abeni mcr |= PMCR_FORCE_EEE1G; break; case SPEED_100: -@@ -2810,61 +2767,6 @@ static void mt753x_phylink_mac_link_up(s +@@ -2999,61 +2956,6 @@ static void mt753x_phylink_mac_link_up(s mt7530_set(priv, MT7530_PMCR_P(port), mcr); } @@ -246,7 +246,7 @@ Signed-off-by: Paolo Abeni static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { -@@ -3122,7 +3024,6 @@ const struct mt753x_info mt753x_table[] +@@ -3312,7 +3214,6 @@ const struct mt753x_info mt753x_table[] .sw_setup = mt7531_setup, .phy_read = mt7531_ind_phy_read, .phy_write = mt7531_ind_phy_write, @@ -254,7 +254,7 @@ Signed-off-by: Paolo Abeni .mac_port_get_caps = mt7531_mac_port_get_caps, .mac_port_config = mt7531_mac_config, }, -@@ -3132,7 +3033,6 @@ const struct mt753x_info mt753x_table[] +@@ -3322,7 +3223,6 @@ const struct mt753x_info mt753x_table[] .sw_setup = mt7988_setup, .phy_read = mt7531_ind_phy_read, .phy_write = mt7531_ind_phy_write, @@ -264,7 +264,7 @@ Signed-off-by: Paolo Abeni }; --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -331,13 +331,6 @@ enum mt7530_vlan_port_acc_frm { +@@ -340,13 +340,6 @@ enum mt7530_vlan_port_acc_frm { PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) @@ -278,7 +278,7 @@ Signed-off-by: Paolo Abeni #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) -@@ -737,7 +730,6 @@ struct mt753x_info { +@@ -747,7 +740,6 @@ struct mt753x_info { int (*sw_setup)(struct dsa_switch *ds); int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); @@ -286,7 +286,7 @@ Signed-off-by: Paolo Abeni void (*mac_port_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); void (*mac_port_validate)(struct dsa_switch *ds, int port, -@@ -763,7 +755,6 @@ struct mt753x_info { +@@ -773,7 +765,6 @@ struct mt753x_info { * @ports: Holding the state among ports * @reg_mutex: The lock for protecting among process accessing * registers @@ -294,7 +294,7 @@ Signed-off-by: Paolo Abeni * @p5_intf_sel: Holding the current port 5 interface select * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch * has got SGMII -@@ -785,8 +776,6 @@ struct mt7530_priv { +@@ -795,8 +786,6 @@ struct mt7530_priv { const struct mt753x_info *info; unsigned int id; bool mcm; diff --git a/target/linux/generic/backport-6.1/790-42-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch b/target/linux/generic/backport-6.1/790-42-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch index f14634c17a1ae6..c83a6278089476 100644 --- a/target/linux/generic/backport-6.1/790-42-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch +++ b/target/linux/generic/backport-6.1/790-42-v6.9-net-dsa-mt7530-get-rid-of-mt753x_mac_config.patch @@ -18,7 +18,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2661,16 +2661,6 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2850,16 +2850,6 @@ mt7531_mac_config(struct dsa_switch *ds, } } @@ -35,7 +35,7 @@ Signed-off-by: Paolo Abeni static struct phylink_pcs * mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, phy_interface_t interface) -@@ -2696,8 +2686,8 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2885,8 +2875,8 @@ mt753x_phylink_mac_config(struct dsa_swi struct mt7530_priv *priv = ds->priv; u32 mcr_cur, mcr_new; diff --git a/target/linux/generic/backport-6.1/790-43-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch b/target/linux/generic/backport-6.1/790-43-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch index 2fa17d45582217..84ee7416bff4e1 100644 --- a/target/linux/generic/backport-6.1/790-43-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch +++ b/target/linux/generic/backport-6.1/790-43-v6.9-net-dsa-mt7530-put-initialising-PCS-devices-code-bac.patch @@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2845,17 +2845,9 @@ static int +@@ -3034,17 +3034,9 @@ static int mt753x_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; @@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni if (ret) return ret; -@@ -2867,6 +2859,14 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3056,6 +3048,14 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-6.1/790-44-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch b/target/linux/generic/backport-6.1/790-44-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch index d7c8180c8a0006..814a9d06e70213 100644 --- a/target/linux/generic/backport-6.1/790-44-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch +++ b/target/linux/generic/backport-6.1/790-44-v6.9-net-dsa-mt7530-sort-link-settings-ops-and-force-link.patch @@ -24,7 +24,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1047,7 +1047,6 @@ mt7530_port_enable(struct dsa_switch *ds +@@ -1222,7 +1222,6 @@ mt7530_port_enable(struct dsa_switch *ds priv->ports[port].enable = true; mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, priv->ports[port].pm); @@ -32,7 +32,7 @@ Signed-off-by: Paolo Abeni mutex_unlock(&priv->reg_mutex); -@@ -1067,7 +1066,6 @@ mt7530_port_disable(struct dsa_switch *d +@@ -1242,7 +1241,6 @@ mt7530_port_disable(struct dsa_switch *d priv->ports[port].enable = false; mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, PCR_MATRIX_CLR); @@ -40,7 +40,7 @@ Signed-off-by: Paolo Abeni mutex_unlock(&priv->reg_mutex); } -@@ -2284,6 +2282,12 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2460,6 +2458,12 @@ mt7530_setup(struct dsa_switch *ds) mt7530_mib_reset(ds); for (i = 0; i < MT7530_NUM_PORTS; i++) { @@ -53,7 +53,7 @@ Signed-off-by: Paolo Abeni /* Disable forwarding by default on all ports */ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, PCR_MATRIX_CLR); -@@ -2386,6 +2390,12 @@ mt7531_setup_common(struct dsa_switch *d +@@ -2565,6 +2569,12 @@ mt7531_setup_common(struct dsa_switch *d UNU_FFP_MASK); for (i = 0; i < MT7530_NUM_PORTS; i++) { diff --git a/target/linux/generic/backport-6.1/790-45-v6.9-net-dsa-mt7530-simplify-link-operations.patch b/target/linux/generic/backport-6.1/790-45-v6.9-net-dsa-mt7530-simplify-link-operations.patch index d29b183be1f447..d9f91a932ad1db 100644 --- a/target/linux/generic/backport-6.1/790-45-v6.9-net-dsa-mt7530-simplify-link-operations.patch +++ b/target/linux/generic/backport-6.1/790-45-v6.9-net-dsa-mt7530-simplify-link-operations.patch @@ -45,7 +45,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2694,23 +2694,13 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2883,23 +2883,13 @@ mt753x_phylink_mac_config(struct dsa_swi const struct phylink_link_state *state) { struct mt7530_priv *priv = ds->priv; @@ -72,7 +72,7 @@ Signed-off-by: Paolo Abeni static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h -@@ -324,8 +324,6 @@ enum mt7530_vlan_port_acc_frm { +@@ -333,8 +333,6 @@ enum mt7530_vlan_port_acc_frm { MT7531_FORCE_DPX | \ MT7531_FORCE_RX_FC | \ MT7531_FORCE_TX_FC) diff --git a/target/linux/generic/backport-6.1/790-46-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch b/target/linux/generic/backport-6.1/790-46-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch deleted file mode 100644 index e00615d5401833..00000000000000 --- a/target/linux/generic/backport-6.1/790-46-v6.9-net-dsa-mt7530-fix-improper-frames-on-all-25MHz-and-.patch +++ /dev/null @@ -1,74 +0,0 @@ -From cfa7c85f92cd3814ad9748eb1ab25658c7f7cc67 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Wed, 20 Mar 2024 23:45:30 +0300 -Subject: [PATCH 48/48] net: dsa: mt7530: fix improper frames on all 25MHz and - 40MHz XTAL MT7530 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The MT7530 switch after reset initialises with a core clock frequency that -works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock -frequency must be set to 500MHz. - -The mt7530_pll_setup() function is responsible of setting the core clock -frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This -causes MT7530 switch with 25MHz XTAL to egress and ingress frames -improperly. - -Introduce a check to run it only on MT7530 with 40MHz XTAL. - -The core clock frequency is set by writing to a switch PHY's register. -Access to the PHY's register is done via the MDIO bus the switch is also -on. Therefore, it works only when the switch makes switch PHYs listen on -the MDIO bus the switch is on. This is controlled either by the state of -the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the -modifiable trap register. - -When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means -accessing PHY registers via the PHY indirect access control register of the -switch. - -When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means -accessing PHY registers via the MDIO bus the switch is on. - -For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high, -the core clock frequency won't be set to 500MHz, causing the switch to -egress and ingress frames improperly. - -Run mt7530_pll_setup() after PHY direct access is set on the modifiable -trap register. - -With these two changes, all MT7530 switches with 25MHz and 40MHz, and -P1_LED_1 pulled high or low, will egress and ingress frames properly. - -Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039 -Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") -Signed-off-by: Arınç ÜNAL -Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com -Signed-off-by: Paolo Abeni ---- - drivers/net/dsa/mt7530.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2259,8 +2259,6 @@ mt7530_setup(struct dsa_switch *ds) - SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | - SYS_CTRL_REG_RST); - -- mt7530_pll_setup(priv); -- - /* Lower Tx driving for TRGMII path */ - for (i = 0; i < NUM_TRGMII_CTRL; i++) - mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), -@@ -2276,6 +2274,9 @@ mt7530_setup(struct dsa_switch *ds) - val |= MHWTRAP_MANUAL; - mt7530_write(priv, MT7530_MHWTRAP, val); - -+ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) -+ mt7530_pll_setup(priv); -+ - mt753x_trap_frames(priv); - - /* Enable and reset MIB counters */ diff --git a/target/linux/generic/backport-6.1/790-47-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch b/target/linux/generic/backport-6.1/790-47-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch deleted file mode 100644 index dc202a55e69df4..00000000000000 --- a/target/linux/generic/backport-6.1/790-47-v6.10-net-dsa-mt7530-fix-enabling-EEE-on-MT7531-switch-on-.patch +++ /dev/null @@ -1,92 +0,0 @@ -From ef972fc9f5743da589ce9546dd565d6c56e679b8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Mon, 8 Apr 2024 10:08:53 +0300 -Subject: [PATCH 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on - all boards -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") -brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is -enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board -(bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting -the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to -SkyLake Huang (黃啟澤) from MediaTek for providing information on the -internal EEE switch bit. - -There are existing boards that were not designed to pull the pin low. -Because of that, the EEE status currently depends on the board design. - -The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually -used to control an LED. Once the bit is unset, the pin will be low. That -will make the active low LED turn on. The pin is controlled by the switch -PHY. It seems that the PHY controls the pin in the way that it inverts the -pin state. That means depending on the wiring of the LED connected to -LAN2LED0 on the board, the LED may be on without an active link. - -To not cause this unwanted behaviour whilst enabling EEE on all boards, set -the internal EEE switch bit on the CORE_PLL_GROUP4 register. - -My testing on MT7531 shows a certain amount of traffic loss when EEE is -enabled. That said, I haven't come across a board that enables EEE. So -enable EEE on the switch MACs but disable EEE advertisement on the switch -PHYs. This way, we don't change the behaviour of the majority of the boards -that have this switch. The mediatek-ge PHY driver already disables EEE -advertisement on the switch PHYs but my testing shows that it is somehow -enabled afterwards. Disabling EEE advertisement before the PHY driver -initialises keeps it off. - -With this change, EEE can now be enabled using ethtool. - -Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") -Reviewed-by: Florian Fainelli -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 17 ++++++++++++----- - drivers/net/dsa/mt7530.h | 1 + - 2 files changed, 13 insertions(+), 5 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2496,18 +2496,25 @@ mt7531_setup(struct dsa_switch *ds) - mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, - MT7531_GPIO0_INTERRUPT); - -- /* Enable PHY core PLL, since phy_device has not yet been created -- * provided for phy_[read,write]_mmd_indirect is called, we provide -- * our own mt7531_ind_mmd_phy_[read,write] to complete this -- * function. -+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since -+ * phy_device has not yet been created provided for -+ * phy_[read,write]_mmd_indirect is called, we provide our own -+ * mt7531_ind_mmd_phy_[read,write] to complete this function. - */ - val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, - MDIO_MMD_VEND2, CORE_PLL_GROUP4); -- val |= MT7531_PHY_PLL_BYPASS_MODE; -+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; - val &= ~MT7531_PHY_PLL_OFF; - mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, - CORE_PLL_GROUP4, val); - -+ /* Disable EEE advertisement on the switch PHYs. */ -+ for (i = MT753X_CTRL_PHY_ADDR; -+ i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) { -+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, -+ 0); -+ } -+ - mt7531_setup_common(ds); - - /* Setup VLAN ID 0 for VLAN-unaware bridges */ ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -616,6 +616,7 @@ enum mt7531_clk_skew { - #define RG_SYSPLL_DDSFBK_EN BIT(12) - #define RG_SYSPLL_BIAS_EN BIT(11) - #define RG_SYSPLL_BIAS_LPF_EN BIT(10) -+#define MT7531_RG_SYSPLL_DMY2 BIT(6) - #define MT7531_PHY_PLL_OFF BIT(5) - #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) - diff --git a/target/linux/generic/backport-6.1/790-48-STABLE-net-dsa-mt7530-trap-link-local-frames-regardless-of-.patch b/target/linux/generic/backport-6.1/790-48-STABLE-net-dsa-mt7530-trap-link-local-frames-regardless-of-.patch deleted file mode 100644 index 4d70e774a4d510..00000000000000 --- a/target/linux/generic/backport-6.1/790-48-STABLE-net-dsa-mt7530-trap-link-local-frames-regardless-of-.patch +++ /dev/null @@ -1,483 +0,0 @@ -From b7427d66cb3d6dca5165de5f7d80d59f08c2795b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Tue, 9 Apr 2024 18:01:14 +0300 -Subject: [PATCH 2/2] net: dsa: mt7530: trap link-local frames regardless of ST - Port State -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer -(DLL) of the Open Systems Interconnection basic reference model (OSI/RM) -are described; the medium access control (MAC) and logical link control -(LLC) sublayers. The MAC sublayer is the one facing the physical layer. - -In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A -Bridge component comprises a MAC Relay Entity for interconnecting the Ports -of the Bridge, at least two Ports, and higher layer entities with at least -a Spanning Tree Protocol Entity included. - -Each Bridge Port also functions as an end station and shall provide the MAC -Service to an LLC Entity. Each instance of the MAC Service is provided to a -distinct LLC Entity that supports protocol identification, multiplexing, -and demultiplexing, for protocol data unit (PDU) transmission and reception -by one or more higher layer entities. - -It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC -Entity associated with each Bridge Port is modeled as being directly -connected to the attached Local Area Network (LAN). - -On the switch with CPU port architecture, CPU port functions as Management -Port, and the Management Port functionality is provided by software which -functions as an end station. Software is connected to an IEEE 802 LAN that -is wholly contained within the system that incorporates the Bridge. -Software provides access to the LLC Entity associated with each Bridge Port -by the value of the source port field on the special tag on the frame -received by software. - -We call frames that carry control information to determine the active -topology and current extent of each Virtual Local Area Network (VLAN), -i.e., spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN -Registration Protocol Data Units (MVRPDUs), and frames from other link -constrained protocols, such as Extensible Authentication Protocol over LAN -(EAPOL) and Link Layer Discovery Protocol (LLDP), link-local frames. They -are not forwarded by a Bridge. Permanently configured entries in the -filtering database (FDB) ensure that such frames are discarded by the -Forwarding Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in -detail: - -Each of the reserved MAC addresses specified in Table 8-1 -(01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be -permanently configured in the FDB in C-VLAN components and ERs. - -Each of the reserved MAC addresses specified in Table 8-2 -(01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently -configured in the FDB in S-VLAN components. - -Each of the reserved MAC addresses specified in Table 8-3 -(01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB -in TPMR components. - -The FDB entries for reserved MAC addresses shall specify filtering for all -Bridge Ports and all VIDs. Management shall not provide the capability to -modify or remove entries for reserved MAC addresses. - -The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of -propagation of PDUs within a Bridged Network, as follows: - - The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that - no conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) - component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. - PDUs transmitted using this destination address, or any other addresses - that appear in Table 8-1, Table 8-2, and Table 8-3 - (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can - therefore travel no further than those stations that can be reached via a - single individual LAN from the originating station. - - The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an - address that no conformant S-VLAN component, C-VLAN component, or MAC - Bridge can forward; however, this address is relayed by a TPMR component. - PDUs using this destination address, or any of the other addresses that - appear in both Table 8-1 and Table 8-2 but not in Table 8-3 - (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed - by any TPMRs but will propagate no further than the nearest S-VLAN - component, C-VLAN component, or MAC Bridge. - - The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an - address that no conformant C-VLAN component, MAC Bridge can forward; - however, it is relayed by TPMR components and S-VLAN components. PDUs - using this destination address, or any of the other addresses that appear - in Table 8-1 but not in either Table 8-2 or Table 8-3 - (01-80-C2-00-00-[00,0B,0C,0D,0F]), will be relayed by TPMR components and - S-VLAN components but will propagate no further than the nearest C-VLAN - component or MAC Bridge. - -Because the LLC Entity associated with each Bridge Port is provided via CPU -port, we must not filter these frames but forward them to CPU port. - -In a Bridge, the transmission Port is majorly decided by ingress and egress -rules, FDB, and spanning tree Port State functions of the Forwarding -Process. For link-local frames, only CPU port should be designated as -destination port in the FDB, and the other functions of the Forwarding -Process must not interfere with the decision of the transmission Port. We -call this process trapping frames to CPU port. - -Therefore, on the switch with CPU port architecture, link-local frames must -be trapped to CPU port, and certain link-local frames received by a Port of -a Bridge comprising a TPMR component or an S-VLAN component must be -excluded from it. - -A Bridge of the switch with CPU port architecture cannot comprise a -Two-Port MAC Relay (TPMR) component as a TPMR component supports only a -subset of the functionality of a MAC Bridge. A Bridge comprising two Ports -(Management Port doesn't count) of this architecture will either function -as a standard MAC Bridge or a standard VLAN Bridge. - -Therefore, a Bridge of this architecture can only comprise S-VLAN -components, C-VLAN components, or MAC Bridge components. Since there's no -TPMR component, we don't need to relay PDUs using the destination addresses -specified on the Nearest non-TPMR section, and the proportion of the -Nearest Customer Bridge section where they must be relayed by TPMR -components. - -One option to trap link-local frames to CPU port is to add static FDB -entries with CPU port designated as destination port. However, because that -Independent VLAN Learning (IVL) is being used on every VID, each entry only -applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC -Bridge component or a C-VLAN component, there would have to be 16 times -4096 entries. This switch intellectual property can only hold a maximum of -2048 entries. Using this option, there also isn't a mechanism to prevent -link-local frames from being discarded when the spanning tree Port State of -the reception Port is discarding. - -The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 -registers. Whilst this applies to every VID, it doesn't contain all of the -reserved MAC addresses without affecting the remaining Standard Group MAC -Addresses. The REV_UN frame tag utilised using the RGAC4 register covers -the remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination -addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF -destination addresses which may be relayed by MAC Bridges or VLAN Bridges. -The latter option provides better but not complete conformance. - -This switch intellectual property also does not provide a mechanism to trap -link-local frames with specific destination addresses to CPU port by -Bridge, to conform to the filtering rules for the distinct Bridge -components. - -Therefore, regardless of the type of the Bridge component, link-local -frames with these destination addresses will be trapped to CPU port: - -01-80-C2-00-00-[00,01,02,03,0E] - -In a Bridge comprising a MAC Bridge component or a C-VLAN component: - - Link-local frames with these destination addresses won't be trapped to - CPU port which won't conform to IEEE Std 802.1Q-2022: - - 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] - -In a Bridge comprising an S-VLAN component: - - Link-local frames with these destination addresses will be trapped to CPU - port which won't conform to IEEE Std 802.1Q-2022: - - 01-80-C2-00-00-00 - - Link-local frames with these destination addresses won't be trapped to - CPU port which won't conform to IEEE Std 802.1Q-2022: - - 01-80-C2-00-00-[04,05,06,07,08,09,0A] - -Currently on this switch intellectual property, if the spanning tree Port -State of the reception Port is discarding, link-local frames will be -discarded. - -To trap link-local frames regardless of the spanning tree Port State, make -the switch regard them as Bridge Protocol Data Units (BPDUs). This switch -intellectual property only lets the frames regarded as BPDUs bypass the -spanning tree Port State function of the Forwarding Process. - -With this change, the only remaining interference is the ingress rules. -When the reception Port has no PVID assigned on software, VLAN-untagged -frames won't be allowed in. There doesn't seem to be a mechanism on the -switch intellectual property to have link-local frames bypass this function -of the Forwarding Process. - -Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") -Reviewed-by: Daniel Golle -Signed-off-by: Arınç ÜNAL ---- - drivers/net/dsa/mt7530.c | 229 +++++++++++++++++++++++++++++++++------ - drivers/net/dsa/mt7530.h | 5 + - 2 files changed, 200 insertions(+), 34 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -943,20 +943,173 @@ static void mt7530_setup_port5(struct ds - mutex_unlock(&priv->reg_mutex); - } - --/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std -- * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA -- * must only be propagated to C-VLAN and MAC Bridge components. That means -- * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports, -- * these frames are supposed to be processed by the CPU (software). So we make -- * the switch only forward them to the CPU port. And if received from a CPU -- * port, forward to a single port. The software is responsible of making the -- * switch conform to the latter by setting a single port as destination port on -- * the special tag. -- * -- * This switch intellectual property cannot conform to this part of the standard -- * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC -- * DAs, it also includes :22-FF which the scope of propagation is not supposed -- * to be restricted for these MAC DAs. -+/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) -+ * of the Open Systems Interconnection basic reference model (OSI/RM) are -+ * described; the medium access control (MAC) and logical link control (LLC) -+ * sublayers. The MAC sublayer is the one facing the physical layer. -+ * -+ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A -+ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports -+ * of the Bridge, at least two Ports, and higher layer entities with at least a -+ * Spanning Tree Protocol Entity included. -+ * -+ * Each Bridge Port also functions as an end station and shall provide the MAC -+ * Service to an LLC Entity. Each instance of the MAC Service is provided to a -+ * distinct LLC Entity that supports protocol identification, multiplexing, and -+ * demultiplexing, for protocol data unit (PDU) transmission and reception by -+ * one or more higher layer entities. -+ * -+ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC -+ * Entity associated with each Bridge Port is modeled as being directly -+ * connected to the attached Local Area Network (LAN). -+ * -+ * On the switch with CPU port architecture, CPU port functions as Management -+ * Port, and the Management Port functionality is provided by software which -+ * functions as an end station. Software is connected to an IEEE 802 LAN that is -+ * wholly contained within the system that incorporates the Bridge. Software -+ * provides access to the LLC Entity associated with each Bridge Port by the -+ * value of the source port field on the special tag on the frame received by -+ * software. -+ * -+ * We call frames that carry control information to determine the active -+ * topology and current extent of each Virtual Local Area Network (VLAN), i.e., -+ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration -+ * Protocol Data Units (MVRPDUs), and frames from other link constrained -+ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and -+ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not -+ * forwarded by a Bridge. Permanently configured entries in the filtering -+ * database (FDB) ensure that such frames are discarded by the Forwarding -+ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: -+ * -+ * Each of the reserved MAC addresses specified in Table 8-1 -+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be -+ * permanently configured in the FDB in C-VLAN components and ERs. -+ * -+ * Each of the reserved MAC addresses specified in Table 8-2 -+ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently -+ * configured in the FDB in S-VLAN components. -+ * -+ * Each of the reserved MAC addresses specified in Table 8-3 -+ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in -+ * TPMR components. -+ * -+ * The FDB entries for reserved MAC addresses shall specify filtering for all -+ * Bridge Ports and all VIDs. Management shall not provide the capability to -+ * modify or remove entries for reserved MAC addresses. -+ * -+ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of -+ * propagation of PDUs within a Bridged Network, as follows: -+ * -+ * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no -+ * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) -+ * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. -+ * PDUs transmitted using this destination address, or any other addresses -+ * that appear in Table 8-1, Table 8-2, and Table 8-3 -+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can -+ * therefore travel no further than those stations that can be reached via a -+ * single individual LAN from the originating station. -+ * -+ * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an -+ * address that no conformant S-VLAN component, C-VLAN component, or MAC -+ * Bridge can forward; however, this address is relayed by a TPMR component. -+ * PDUs using this destination address, or any of the other addresses that -+ * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 -+ * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by -+ * any TPMRs but will propagate no further than the nearest S-VLAN component, -+ * C-VLAN component, or MAC Bridge. -+ * -+ * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address -+ * that no conformant C-VLAN component, MAC Bridge can forward; however, it is -+ * relayed by TPMR components and S-VLAN components. PDUs using this -+ * destination address, or any of the other addresses that appear in Table 8-1 -+ * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), -+ * will be relayed by TPMR components and S-VLAN components but will propagate -+ * no further than the nearest C-VLAN component or MAC Bridge. -+ * -+ * Because the LLC Entity associated with each Bridge Port is provided via CPU -+ * port, we must not filter these frames but forward them to CPU port. -+ * -+ * In a Bridge, the transmission Port is majorly decided by ingress and egress -+ * rules, FDB, and spanning tree Port State functions of the Forwarding Process. -+ * For link-local frames, only CPU port should be designated as destination port -+ * in the FDB, and the other functions of the Forwarding Process must not -+ * interfere with the decision of the transmission Port. We call this process -+ * trapping frames to CPU port. -+ * -+ * Therefore, on the switch with CPU port architecture, link-local frames must -+ * be trapped to CPU port, and certain link-local frames received by a Port of a -+ * Bridge comprising a TPMR component or an S-VLAN component must be excluded -+ * from it. -+ * -+ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port -+ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the -+ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port -+ * doesn't count) of this architecture will either function as a standard MAC -+ * Bridge or a standard VLAN Bridge. -+ * -+ * Therefore, a Bridge of this architecture can only comprise S-VLAN components, -+ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, -+ * we don't need to relay PDUs using the destination addresses specified on the -+ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge -+ * section where they must be relayed by TPMR components. -+ * -+ * One option to trap link-local frames to CPU port is to add static FDB entries -+ * with CPU port designated as destination port. However, because that -+ * Independent VLAN Learning (IVL) is being used on every VID, each entry only -+ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC -+ * Bridge component or a C-VLAN component, there would have to be 16 times 4096 -+ * entries. This switch intellectual property can only hold a maximum of 2048 -+ * entries. Using this option, there also isn't a mechanism to prevent -+ * link-local frames from being discarded when the spanning tree Port State of -+ * the reception Port is discarding. -+ * -+ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 -+ * registers. Whilst this applies to every VID, it doesn't contain all of the -+ * reserved MAC addresses without affecting the remaining Standard Group MAC -+ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the -+ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination -+ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF -+ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. -+ * The latter option provides better but not complete conformance. -+ * -+ * This switch intellectual property also does not provide a mechanism to trap -+ * link-local frames with specific destination addresses to CPU port by Bridge, -+ * to conform to the filtering rules for the distinct Bridge components. -+ * -+ * Therefore, regardless of the type of the Bridge component, link-local frames -+ * with these destination addresses will be trapped to CPU port: -+ * -+ * 01-80-C2-00-00-[00,01,02,03,0E] -+ * -+ * In a Bridge comprising a MAC Bridge component or a C-VLAN component: -+ * -+ * Link-local frames with these destination addresses won't be trapped to CPU -+ * port which won't conform to IEEE Std 802.1Q-2022: -+ * -+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] -+ * -+ * In a Bridge comprising an S-VLAN component: -+ * -+ * Link-local frames with these destination addresses will be trapped to CPU -+ * port which won't conform to IEEE Std 802.1Q-2022: -+ * -+ * 01-80-C2-00-00-00 -+ * -+ * Link-local frames with these destination addresses won't be trapped to CPU -+ * port which won't conform to IEEE Std 802.1Q-2022: -+ * -+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A] -+ * -+ * To trap link-local frames to CPU port as conformant as this switch -+ * intellectual property can allow, link-local frames are made to be regarded as -+ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual -+ * property only lets the frames regarded as BPDUs bypass the spanning tree Port -+ * State function of the Forwarding Process. -+ * -+ * The only remaining interference is the ingress rules. When the reception Port -+ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. -+ * There doesn't seem to be a mechanism on the switch intellectual property to -+ * have link-local frames bypass this function of the Forwarding Process. - */ - static void - mt753x_trap_frames(struct mt7530_priv *priv) -@@ -964,35 +1117,43 @@ mt753x_trap_frames(struct mt7530_priv *p - /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them - * VLAN-untagged. - */ -- mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK | -- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | -- MT753X_BPDU_PORT_FW_MASK, -- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ mt7530_rmw(priv, MT753X_BPC, -+ MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK | -+ MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK | -+ MT753X_BPDU_PORT_FW_MASK, -+ MT753X_PAE_BPDU_FR | -+ MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) | -+ MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ MT753X_BPDU_CPU_ONLY); - - /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ -- mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK | -- MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK | -- MT753X_R01_PORT_FW_MASK, -- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ mt7530_rmw(priv, MT753X_RGAC1, -+ MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK | -+ MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR | -+ MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK, -+ MT753X_R02_BPDU_FR | -+ MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) | -+ MT753X_R01_BPDU_FR | -+ MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ MT753X_BPDU_CPU_ONLY); - - /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress - * them VLAN-untagged. - */ -- mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK | -- MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK | -- MT753X_R03_PORT_FW_MASK, -- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | -- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -- MT753X_BPDU_CPU_ONLY); -+ mt7530_rmw(priv, MT753X_RGAC2, -+ MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK | -+ MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR | -+ MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK, -+ MT753X_R0E_BPDU_FR | -+ MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) | -+ MT753X_R03_BPDU_FR | -+ MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | -+ MT753X_BPDU_CPU_ONLY); - } - - static void ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -65,6 +65,7 @@ enum mt753x_id { - - /* Registers for BPDU and PAE frame control*/ - #define MT753X_BPC 0x24 -+#define MT753X_PAE_BPDU_FR BIT(25) - #define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22) - #define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x) - #define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16) -@@ -75,20 +76,24 @@ enum mt753x_id { - - /* Register for :01 and :02 MAC DA frame control */ - #define MT753X_RGAC1 0x28 -+#define MT753X_R02_BPDU_FR BIT(25) - #define MT753X_R02_EG_TAG_MASK GENMASK(24, 22) - #define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x) - #define MT753X_R02_PORT_FW_MASK GENMASK(18, 16) - #define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x) -+#define MT753X_R01_BPDU_FR BIT(9) - #define MT753X_R01_EG_TAG_MASK GENMASK(8, 6) - #define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x) - #define MT753X_R01_PORT_FW_MASK GENMASK(2, 0) - - /* Register for :03 and :0E MAC DA frame control */ - #define MT753X_RGAC2 0x2c -+#define MT753X_R0E_BPDU_FR BIT(25) - #define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22) - #define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x) - #define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) - #define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) -+#define MT753X_R03_BPDU_FR BIT(9) - #define MT753X_R03_EG_TAG_MASK GENMASK(8, 6) - #define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x) - #define MT753X_R03_PORT_FW_MASK GENMASK(2, 0) diff --git a/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch b/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch index ca2657d57d5f18..8962e560f71ca8 100644 --- a/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch +++ b/target/linux/generic/backport-6.1/790-49-v6.10-net-dsa-mt7530-provide-own-phylink-MAC-operations.patch @@ -19,7 +19,7 @@ Signed-off-by: Paolo Abeni --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2841,28 +2841,34 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2861,28 +2861,34 @@ mt7531_mac_config(struct dsa_switch *ds, } static struct phylink_pcs * @@ -60,7 +60,7 @@ Signed-off-by: Paolo Abeni if ((port == 5 || port == 6) && priv->info->mac_port_config) priv->info->mac_port_config(ds, port, mode, state->interface); -@@ -2872,23 +2878,25 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2892,23 +2898,25 @@ mt753x_phylink_mac_config(struct dsa_swi mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY); } @@ -92,7 +92,7 @@ Signed-off-by: Paolo Abeni u32 mcr; mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; -@@ -2923,7 +2931,7 @@ static void mt753x_phylink_mac_link_up(s +@@ -2943,7 +2951,7 @@ static void mt753x_phylink_mac_link_up(s } } @@ -101,7 +101,7 @@ Signed-off-by: Paolo Abeni } static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, -@@ -3148,16 +3156,19 @@ const struct dsa_switch_ops mt7530_switc +@@ -3169,16 +3177,19 @@ const struct dsa_switch_ops mt7530_switc .port_mirror_add = mt753x_port_mirror_add, .port_mirror_del = mt753x_port_mirror_del, .phylink_get_caps = mt753x_phylink_get_caps, @@ -125,7 +125,7 @@ Signed-off-by: Paolo Abeni const struct mt753x_info mt753x_table[] = { [ID_MT7621] = { .id = ID_MT7621, -@@ -3227,6 +3238,7 @@ mt7530_probe_common(struct mt7530_priv * +@@ -3248,6 +3259,7 @@ mt7530_probe_common(struct mt7530_priv * priv->dev = dev; priv->ds->priv = priv; priv->ds->ops = &mt7530_switch_ops; diff --git a/target/linux/generic/backport-6.1/790-50-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch b/target/linux/generic/backport-6.1/790-50-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch deleted file mode 100644 index 7640a9cb410eaf..00000000000000 --- a/target/linux/generic/backport-6.1/790-50-v6.10-net-dsa-mt7530-fix-mirroring-frames-received-on-loca.patch +++ /dev/null @@ -1,70 +0,0 @@ -From d4097ddef078a113643a6dcde01e99741f852adb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Sat, 13 Apr 2024 16:01:39 +0300 -Subject: [PATCH 2/5] net: dsa: mt7530: fix mirroring frames received on local - port -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This switch intellectual property provides a bit on the ARL global control -register which controls allowing mirroring frames which are received on the -local port (monitor port). This bit is unset after reset. - -This ability must be enabled to fully support the port mirroring feature on -this switch intellectual property. - -Therefore, this patch fixes the traffic not being reflected on a port, -which would be configured like below: - - tc qdisc add dev swp0 clsact - - tc filter add dev swp0 ingress matchall skip_sw \ - action mirred egress mirror dev swp0 - -As a side note, this configuration provides the hairpinning feature for a -single port. - -Fixes: 37feab6076aa ("net: dsa: mt7530: add support for port mirroring") -Signed-off-by: Arınç ÜNAL -Signed-off-by: David S. Miller ---- - drivers/net/dsa/mt7530.c | 6 ++++++ - drivers/net/dsa/mt7530.h | 4 ++++ - 2 files changed, 10 insertions(+) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2471,6 +2471,9 @@ mt7530_setup(struct dsa_switch *ds) - PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); - } - -+ /* Allow mirroring frames received on the local port (monitor port). */ -+ mt7530_set(priv, MT753X_AGC, LOCAL_EN); -+ - /* Setup VLAN ID 0 for VLAN-unaware bridges */ - ret = mt7530_setup_vlan0(priv); - if (ret) -@@ -2582,6 +2585,9 @@ mt7531_setup_common(struct dsa_switch *d - PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); - } - -+ /* Allow mirroring frames received on the local port (monitor port). */ -+ mt7530_set(priv, MT753X_AGC, LOCAL_EN); -+ - /* Flush the FDB table */ - ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); - if (ret < 0) ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -32,6 +32,10 @@ enum mt753x_id { - #define SYSC_REG_RSTCTRL 0x34 - #define RESET_MCM BIT(2) - -+/* Register for ARL global control */ -+#define MT753X_AGC 0xc -+#define LOCAL_EN BIT(7) -+ - /* Registers to mac forward control for unknown frames */ - #define MT7530_MFC 0x10 - #define BC_FFP(x) (((x) & 0xff) << 24) diff --git a/target/linux/generic/backport-6.1/790-51-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch b/target/linux/generic/backport-6.1/790-51-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch index 304ea21adc7740..cd5b7b287d3912 100644 --- a/target/linux/generic/backport-6.1/790-51-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch +++ b/target/linux/generic/backport-6.1/790-51-v6.10-net-dsa-mt7530-fix-port-mirroring-for-MT7988-SoC-swi.patch @@ -26,7 +26,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1876,14 +1876,16 @@ mt7530_port_vlan_del(struct dsa_switch * +@@ -1890,14 +1890,16 @@ mt7530_port_vlan_del(struct dsa_switch * static int mt753x_mirror_port_get(unsigned int id, u32 val) { diff --git a/target/linux/generic/backport-6.1/790-52-v6.10-net-dsa-mt7530-mdio-read-PHY-address-of-switch-from-.patch b/target/linux/generic/backport-6.1/790-52-v6.10-net-dsa-mt7530-mdio-read-PHY-address-of-switch-from-.patch index 6b6a255e26d800..e9c8f955c9fe72 100644 --- a/target/linux/generic/backport-6.1/790-52-v6.10-net-dsa-mt7530-mdio-read-PHY-address-of-switch-from-.patch +++ b/target/linux/generic/backport-6.1/790-52-v6.10-net-dsa-mt7530-mdio-read-PHY-address-of-switch-from-.patch @@ -184,7 +184,7 @@ Signed-off-by: Paolo Abeni err: if (ret < 0) dev_err(&bus->dev, -@@ -2670,16 +2678,19 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2684,16 +2692,19 @@ mt7531_setup(struct dsa_switch *ds) * phy_[read,write]_mmd_indirect is called, we provide our own * mt7531_ind_mmd_phy_[read,write] to complete this function. */ diff --git a/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch b/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch index 3cbd62e9293f9e..158e5f8c00808d 100644 --- a/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch +++ b/target/linux/generic/backport-6.1/790-55-v6.10-net-dsa-mt7530-refactor-MT7530_PMCR_P.patch @@ -33,7 +33,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -889,7 +889,7 @@ static void mt7530_setup_port5(struct ds +@@ -903,7 +903,7 @@ static void mt7530_setup_port5(struct ds val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; /* Setup the MAC by default for the cpu port */ @@ -42,7 +42,7 @@ Signed-off-by: Arınç ÜNAL break; case P5_INTF_SEL_GMAC5: /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ -@@ -2435,8 +2435,8 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2449,8 +2449,8 @@ mt7530_setup(struct dsa_switch *ds) /* Clear link settings and enable force mode to force link down * on all ports until they're enabled later. */ @@ -53,7 +53,7 @@ Signed-off-by: Arınç ÜNAL /* Disable forwarding by default on all ports */ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, -@@ -2546,8 +2546,8 @@ mt7531_setup_common(struct dsa_switch *d +@@ -2560,8 +2560,8 @@ mt7531_setup_common(struct dsa_switch *d /* Clear link settings and enable force mode to force link down * on all ports until they're enabled later. */ @@ -64,7 +64,7 @@ Signed-off-by: Arınç ÜNAL /* Disable forwarding by default on all ports */ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, -@@ -2630,7 +2630,7 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2644,7 +2644,7 @@ mt7531_setup(struct dsa_switch *ds) /* Force link down on all ports before internal reset */ for (i = 0; i < MT7530_NUM_PORTS; i++) @@ -73,7 +73,7 @@ Signed-off-by: Arınç ÜNAL /* Reset the switch through internal reset */ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); -@@ -2872,7 +2872,7 @@ mt753x_phylink_mac_config(struct phylink +@@ -2886,7 +2886,7 @@ mt753x_phylink_mac_config(struct phylink /* Are we connected to external phy */ if (port == 5 && dsa_is_user_port(ds, 5)) @@ -82,7 +82,7 @@ Signed-off-by: Arınç ÜNAL } static void mt753x_phylink_mac_link_down(struct phylink_config *config, -@@ -2882,7 +2882,7 @@ static void mt753x_phylink_mac_link_down +@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_down struct dsa_port *dp = dsa_phylink_to_port(config); struct mt7530_priv *priv = dp->ds->priv; @@ -91,7 +91,7 @@ Signed-off-by: Arınç ÜNAL } static void mt753x_phylink_mac_link_up(struct phylink_config *config, -@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_up(s +@@ -2910,7 +2910,7 @@ static void mt753x_phylink_mac_link_up(s struct mt7530_priv *priv = dp->ds->priv; u32 mcr; @@ -100,7 +100,7 @@ Signed-off-by: Arınç ÜNAL switch (speed) { case SPEED_1000: -@@ -2911,9 +2911,9 @@ static void mt753x_phylink_mac_link_up(s +@@ -2925,9 +2925,9 @@ static void mt753x_phylink_mac_link_up(s if (duplex == DUPLEX_FULL) { mcr |= PMCR_FORCE_FDX; if (tx_pause) @@ -112,7 +112,7 @@ Signed-off-by: Arınç ÜNAL } if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { -@@ -2928,7 +2928,7 @@ static void mt753x_phylink_mac_link_up(s +@@ -2942,7 +2942,7 @@ static void mt753x_phylink_mac_link_up(s } } diff --git a/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch b/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch index 9697e7eb4fbb97..9a0ce7c36c70f3 100644 --- a/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch +++ b/target/linux/generic/backport-6.1/790-56-v6.10-net-dsa-mt7530-rename-p5_intf_sel-and-use-only-for-M.patch @@ -25,7 +25,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -850,19 +850,15 @@ mt7530_set_ageing_time(struct dsa_switch +@@ -864,19 +864,15 @@ mt7530_set_ageing_time(struct dsa_switch return 0; } @@ -52,7 +52,7 @@ Signed-off-by: Arınç ÜNAL } } -@@ -879,23 +875,23 @@ static void mt7530_setup_port5(struct ds +@@ -893,23 +889,23 @@ static void mt7530_setup_port5(struct ds val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; @@ -85,7 +85,7 @@ Signed-off-by: Arınç ÜNAL break; } -@@ -923,8 +919,8 @@ static void mt7530_setup_port5(struct ds +@@ -937,8 +933,8 @@ static void mt7530_setup_port5(struct ds mt7530_write(priv, MT7530_MHWTRAP, val); @@ -96,7 +96,7 @@ Signed-off-by: Arınç ÜNAL mutex_unlock(&priv->reg_mutex); } -@@ -2467,13 +2463,11 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2481,13 +2477,11 @@ mt7530_setup(struct dsa_switch *ds) if (ret) return ret; @@ -114,7 +114,7 @@ Signed-off-by: Arınç ÜNAL */ for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, -@@ -2497,17 +2491,16 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2511,17 +2505,16 @@ mt7530_setup(struct dsa_switch *ds) } id = of_mdio_parse_addr(ds->dev, phy_node); if (id == 0) @@ -135,7 +135,7 @@ Signed-off-by: Arınç ÜNAL mt7530_setup_port5(ds, interface); } -@@ -2645,9 +2638,6 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2659,9 +2652,6 @@ mt7531_setup(struct dsa_switch *ds) MT7531_EXT_P_MDIO_12); } diff --git a/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch b/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch index 77a2df8586323d..c8ffd5f07c2731 100644 --- a/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch +++ b/target/linux/generic/backport-6.1/790-57-v6.10-net-dsa-mt7530-rename-mt753x_bpdu_port_fw-enum-to-mt.patch @@ -21,7 +21,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1100,42 +1100,34 @@ mt753x_trap_frames(struct mt7530_priv *p +@@ -1114,42 +1114,34 @@ mt753x_trap_frames(struct mt7530_priv *p * VLAN-untagged. */ mt7530_rmw(priv, MT753X_BPC, diff --git a/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch b/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch index 95cdfac02e6c74..c977fe46cd91bb 100644 --- a/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch +++ b/target/linux/generic/backport-6.1/790-58-v6.10-net-dsa-mt7530-refactor-MT7530_MFC-and-MT7531_CFC-ad.patch @@ -25,7 +25,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1140,7 +1140,7 @@ mt753x_cpu_port_enable(struct dsa_switch +@@ -1154,7 +1154,7 @@ mt753x_cpu_port_enable(struct dsa_switch PORT_SPEC_TAG); /* Enable flooding on the CPU port */ @@ -33,8 +33,8 @@ Signed-off-by: Arınç ÜNAL + mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on -@@ -1304,15 +1304,15 @@ mt7530_port_bridge_flags(struct dsa_swit + /* Add the CPU port to the CPU port bitmap for MT7531. Trapped frames +@@ -1318,15 +1318,15 @@ mt7530_port_bridge_flags(struct dsa_swit flags.val & BR_LEARNING ? 0 : SA_DIS); if (flags.mask & BR_FLOOD) @@ -53,7 +53,7 @@ Signed-off-by: Arınç ÜNAL flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); return 0; -@@ -1848,20 +1848,6 @@ mt7530_port_vlan_del(struct dsa_switch * +@@ -1862,20 +1862,6 @@ mt7530_port_vlan_del(struct dsa_switch * return 0; } @@ -74,7 +74,7 @@ Signed-off-by: Arınç ÜNAL static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, struct dsa_mall_mirror_tc_entry *mirror, bool ingress, struct netlink_ext_ack *extack) -@@ -1877,14 +1863,14 @@ static int mt753x_port_mirror_add(struct +@@ -1891,14 +1877,14 @@ static int mt753x_port_mirror_add(struct val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); /* MT7530 only supports one monitor port */ @@ -92,7 +92,7 @@ Signed-off-by: Arınç ÜNAL mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); val = mt7530_read(priv, MT7530_PCR_P(port)); -@@ -2524,7 +2510,7 @@ mt7531_setup_common(struct dsa_switch *d +@@ -2538,7 +2524,7 @@ mt7531_setup_common(struct dsa_switch *d mt7530_mib_reset(ds); /* Disable flooding on all ports */ @@ -101,7 +101,7 @@ Signed-off-by: Arınç ÜNAL UNU_FFP_MASK); for (i = 0; i < MT7530_NUM_PORTS; i++) { -@@ -3086,10 +3072,12 @@ mt753x_conduit_state_change(struct dsa_s +@@ -3100,10 +3086,12 @@ mt753x_conduit_state_change(struct dsa_s else priv->active_cpu_ports &= ~mask; diff --git a/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch b/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch index d2497d5c908965..3c487d21f685b4 100644 --- a/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch +++ b/target/linux/generic/backport-6.1/790-59-v6.10-net-dsa-mt7530-refactor-MT7530_HWTRAP-and-MT7530_MHW.patch @@ -30,7 +30,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -403,23 +403,23 @@ mt7530_setup_port6(struct dsa_switch *ds +@@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); @@ -60,7 +60,7 @@ Signed-off-by: Arınç ÜNAL ncpo1 = 0x1400; } -@@ -442,19 +442,20 @@ mt7530_setup_port6(struct dsa_switch *ds +@@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds static void mt7531_pll_setup(struct mt7530_priv *priv) { @@ -86,7 +86,7 @@ Signed-off-by: Arınç ÜNAL /* Step 1 : Disable MT7531 COREPLL */ val = mt7530_read(priv, MT7531_PLLGP_EN); -@@ -483,13 +484,13 @@ mt7531_pll_setup(struct mt7530_priv *pri +@@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri usleep_range(25, 35); switch (xtal) { @@ -102,7 +102,7 @@ Signed-off-by: Arınç ÜNAL val = mt7530_read(priv, MT7531_PLLGP_CR0); val &= ~RG_COREPLL_SDM_PCW_M; val |= 0x190000 << RG_COREPLL_SDM_PCW_S; -@@ -870,20 +871,20 @@ static void mt7530_setup_port5(struct ds +@@ -884,20 +885,20 @@ static void mt7530_setup_port5(struct ds mutex_lock(&priv->reg_mutex); @@ -128,7 +128,7 @@ Signed-off-by: Arınç ÜNAL /* Setup the MAC by default for the cpu port */ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); -@@ -891,13 +892,13 @@ static void mt7530_setup_port5(struct ds +@@ -905,13 +906,13 @@ static void mt7530_setup_port5(struct ds /* GMAC5: P5 -> SoC MAC or external PHY */ default: @@ -144,7 +144,7 @@ Signed-off-by: Arınç ÜNAL /* P5 RGMII RX Clock Control: delay setting for 1000M */ mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); -@@ -917,7 +918,7 @@ static void mt7530_setup_port5(struct ds +@@ -931,7 +932,7 @@ static void mt7530_setup_port5(struct ds P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); } @@ -153,7 +153,7 @@ Signed-off-by: Arınç ÜNAL dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); -@@ -2356,7 +2357,7 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2370,7 +2371,7 @@ mt7530_setup(struct dsa_switch *ds) } /* Waiting for MT7530 got to stable */ @@ -162,7 +162,7 @@ Signed-off-by: Arınç ÜNAL ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 20, 1000000); if (ret < 0) { -@@ -2371,7 +2372,7 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2385,7 +2386,7 @@ mt7530_setup(struct dsa_switch *ds) return -ENODEV; } @@ -171,7 +171,7 @@ Signed-off-by: Arınç ÜNAL dev_err(priv->dev, "MT7530 with a 20MHz XTAL is not supported!\n"); return -EINVAL; -@@ -2392,12 +2393,12 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2406,12 +2407,12 @@ mt7530_setup(struct dsa_switch *ds) RD_TAP_MASK, RD_TAP(16)); /* Enable port 6 */ @@ -189,7 +189,7 @@ Signed-off-by: Arınç ÜNAL mt7530_pll_setup(priv); mt753x_trap_frames(priv); -@@ -2577,7 +2578,7 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2591,7 +2592,7 @@ mt7531_setup(struct dsa_switch *ds) } /* Waiting for MT7530 got to stable */ diff --git a/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch b/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch index e7da939588cc36..cfc38f81d07536 100644 --- a/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch +++ b/target/linux/generic/backport-6.1/790-60-v6.10-net-dsa-mt7530-move-MT753X_MTRAP-operations-for-MT75.patch @@ -28,7 +28,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -873,8 +873,7 @@ static void mt7530_setup_port5(struct ds +@@ -887,8 +887,7 @@ static void mt7530_setup_port5(struct ds val = mt7530_read(priv, MT753X_MTRAP); @@ -38,7 +38,7 @@ Signed-off-by: Arınç ÜNAL switch (priv->p5_mode) { /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ -@@ -884,15 +883,13 @@ static void mt7530_setup_port5(struct ds +@@ -898,15 +897,13 @@ static void mt7530_setup_port5(struct ds /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ case MUX_PHY_P4: @@ -55,7 +55,7 @@ Signed-off-by: Arınç ÜNAL break; } -@@ -1186,6 +1183,14 @@ mt7530_port_enable(struct dsa_switch *ds +@@ -1200,6 +1197,14 @@ mt7530_port_enable(struct dsa_switch *ds mutex_unlock(&priv->reg_mutex); @@ -70,7 +70,7 @@ Signed-off-by: Arınç ÜNAL return 0; } -@@ -1204,6 +1209,14 @@ mt7530_port_disable(struct dsa_switch *d +@@ -1218,6 +1223,14 @@ mt7530_port_disable(struct dsa_switch *d PCR_MATRIX_CLR); mutex_unlock(&priv->reg_mutex); @@ -85,7 +85,7 @@ Signed-off-by: Arınç ÜNAL } static int -@@ -2392,11 +2405,11 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2406,11 +2419,11 @@ mt7530_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_MASK, RD_TAP(16)); @@ -102,7 +102,7 @@ Signed-off-by: Arınç ÜNAL if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) mt7530_pll_setup(priv); -@@ -2479,8 +2492,11 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2493,8 +2506,11 @@ mt7530_setup(struct dsa_switch *ds) break; } diff --git a/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch b/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch index 7cc145327c9c93..178ac8022ffc9d 100644 --- a/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch +++ b/target/linux/generic/backport-6.1/790-61-v6.10-net-dsa-mt7530-return-mt7530_setup_mdio-mt7531_setup.patch @@ -17,7 +17,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2658,7 +2658,9 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2672,7 +2672,9 @@ mt7531_setup(struct dsa_switch *ds) 0); } @@ -28,7 +28,7 @@ Signed-off-by: Arınç ÜNAL /* Setup VLAN ID 0 for VLAN-unaware bridges */ ret = mt7530_setup_vlan0(priv); -@@ -3017,6 +3019,8 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3031,6 +3033,8 @@ mt753x_setup(struct dsa_switch *ds) ret = mt7530_setup_mdio(priv); if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch b/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch index f4d19db2744946..af8edf5a4273d7 100644 --- a/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch +++ b/target/linux/generic/backport-6.1/790-62-v6.10-net-dsa-mt7530-define-MAC-speed-capabilities-per-swi.patch @@ -24,7 +24,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2676,6 +2676,8 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2690,6 +2690,8 @@ mt7531_setup(struct dsa_switch *ds) static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { @@ -33,7 +33,7 @@ Signed-off-by: Arınç ÜNAL switch (port) { /* Ports which are connected to switch PHYs. There is no MII pinout. */ case 0 ... 4: -@@ -2707,6 +2709,8 @@ static void mt7531_mac_port_get_caps(str +@@ -2721,6 +2723,8 @@ static void mt7531_mac_port_get_caps(str { struct mt7530_priv *priv = ds->priv; @@ -42,7 +42,7 @@ Signed-off-by: Arınç ÜNAL switch (port) { /* Ports which are connected to switch PHYs. There is no MII pinout. */ case 0 ... 4: -@@ -2746,14 +2750,17 @@ static void mt7988_mac_port_get_caps(str +@@ -2760,14 +2764,17 @@ static void mt7988_mac_port_get_caps(str case 0 ... 3: __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); @@ -62,7 +62,7 @@ Signed-off-by: Arınç ÜNAL } } -@@ -2923,9 +2930,7 @@ static void mt753x_phylink_get_caps(stru +@@ -2937,9 +2944,7 @@ static void mt753x_phylink_get_caps(stru { struct mt7530_priv *priv = ds->priv; diff --git a/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch b/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch index 5bb7756c51da9e..3825952dc31243 100644 --- a/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch +++ b/target/linux/generic/backport-6.1/790-63-v6.10-net-dsa-mt7530-get-rid-of-function-sanity-check.patch @@ -17,7 +17,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3220,13 +3220,6 @@ mt7530_probe_common(struct mt7530_priv * +@@ -3235,13 +3235,6 @@ mt7530_probe_common(struct mt7530_priv * if (!priv->info) return -EINVAL; diff --git a/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch b/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch index f8147b641262c4..df474580141088 100644 --- a/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch +++ b/target/linux/generic/backport-6.1/790-64-v6.10-net-dsa-mt7530-refactor-MT7530_PMEEECR_P.patch @@ -19,7 +19,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3048,10 +3048,10 @@ static int mt753x_get_mac_eee(struct dsa +@@ -3062,10 +3062,10 @@ static int mt753x_get_mac_eee(struct dsa struct ethtool_eee *e) { struct mt7530_priv *priv = ds->priv; @@ -32,7 +32,7 @@ Signed-off-by: Arınç ÜNAL return 0; } -@@ -3065,11 +3065,11 @@ static int mt753x_set_mac_eee(struct dsa +@@ -3079,11 +3079,11 @@ static int mt753x_set_mac_eee(struct dsa if (e->tx_lpi_timer > 0xFFF) return -EINVAL; diff --git a/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch b/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch index 0037f974991557..e9512421c22275 100644 --- a/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch +++ b/target/linux/generic/backport-6.1/790-66-v6.10-net-dsa-mt7530-use-priv-ds-num_ports-instead-of-MT75.patch @@ -19,7 +19,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1404,7 +1404,7 @@ mt7530_port_set_vlan_unaware(struct dsa_ +@@ -1418,7 +1418,7 @@ mt7530_port_set_vlan_unaware(struct dsa_ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, G0_PORT_VID_DEF); @@ -28,7 +28,7 @@ Signed-off-by: Arınç ÜNAL if (dsa_is_user_port(ds, i) && dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { all_user_ports_removed = false; -@@ -2419,7 +2419,7 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2433,7 +2433,7 @@ mt7530_setup(struct dsa_switch *ds) /* Enable and reset MIB counters */ mt7530_mib_reset(ds); @@ -37,7 +37,7 @@ Signed-off-by: Arınç ÜNAL /* Clear link settings and enable force mode to force link down * on all ports until they're enabled later. */ -@@ -2530,7 +2530,7 @@ mt7531_setup_common(struct dsa_switch *d +@@ -2544,7 +2544,7 @@ mt7531_setup_common(struct dsa_switch *d mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK); @@ -46,7 +46,7 @@ Signed-off-by: Arınç ÜNAL /* Clear link settings and enable force mode to force link down * on all ports until they're enabled later. */ -@@ -2617,7 +2617,7 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2631,7 +2631,7 @@ mt7531_setup(struct dsa_switch *ds) priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); /* Force link down on all ports before internal reset */ diff --git a/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch b/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch index ee8e13ea70eaa9..3b3330bdce8083 100644 --- a/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch +++ b/target/linux/generic/backport-6.1/790-67-v6.10-net-dsa-mt7530-do-not-pass-port-variable-to-mt7531_r.patch @@ -17,7 +17,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2776,7 +2776,7 @@ mt7530_mac_config(struct dsa_switch *ds, +@@ -2790,7 +2790,7 @@ mt7530_mac_config(struct dsa_switch *ds, mt7530_setup_port6(priv->ds, interface); } @@ -26,7 +26,7 @@ Signed-off-by: Arınç ÜNAL phy_interface_t interface, struct phy_device *phydev) { -@@ -2827,7 +2827,7 @@ mt7531_mac_config(struct dsa_switch *ds, +@@ -2841,7 +2841,7 @@ mt7531_mac_config(struct dsa_switch *ds, if (phy_interface_mode_is_rgmii(interface)) { dp = dsa_to_port(ds, port); phydev = dp->slave->phydev; diff --git a/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch b/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch index 666bcb75e8e80b..6d28e5b5f970a9 100644 --- a/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch +++ b/target/linux/generic/backport-6.1/790-68-v6.10-net-dsa-mt7530-explain-exposing-MDIO-bus-of-MT7531AE.patch @@ -19,7 +19,7 @@ Signed-off-by: Arınç ÜNAL --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2626,7 +2626,10 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2640,7 +2640,10 @@ mt7531_setup(struct dsa_switch *ds) if (!priv->p5_sgmii) { mt7531_pll_setup(priv); } else { diff --git a/target/linux/generic/backport-6.6/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch b/target/linux/generic/backport-6.6/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch new file mode 100644 index 00000000000000..d0fed02005c586 --- /dev/null +++ b/target/linux/generic/backport-6.6/600-v6.9-01-net-gro-parse-ipv6-ext-headers-without-frag0-invalid.patch @@ -0,0 +1,107 @@ +From: Richard Gobert +Date: Wed, 3 Jan 2024 15:44:21 +0100 +Subject: [PATCH] net: gro: parse ipv6 ext headers without frag0 invalidation + +The existing code always pulls the IPv6 header and sets the transport +offset initially. Then optionally again pulls any extension headers in +ipv6_gso_pull_exthdrs and sets the transport offset again on return from +that call. skb->data is set at the start of the first extension header +before calling ipv6_gso_pull_exthdrs, and must disable the frag0 +optimization because that function uses pskb_may_pull/pskb_pull instead of +skb_gro_ helpers. It sets the GRO offset to the TCP header with +skb_gro_pull and sets the transport header. Then returns skb->data to its +position before this block. + +This commit introduces a new helper function - ipv6_gro_pull_exthdrs - +which is used in ipv6_gro_receive to pull ipv6 ext headers instead of +ipv6_gso_pull_exthdrs. Thus, there is no modification of skb->data, all +operations use skb_gro_* helpers, and the frag0 fast path can be taken for +IPv6 packets with ext headers. + +Signed-off-by: Richard Gobert +Reviewed-by: Willem de Bruijn +Reviewed-by: David Ahern +Reviewed-by: Eric Dumazet +Link: https://lore.kernel.org/r/504130f6-b56c-4dcc-882c-97942c59f5b7@gmail.com +Signed-off-by: Jakub Kicinski +--- + +--- a/net/ipv6/ip6_offload.c ++++ b/net/ipv6/ip6_offload.c +@@ -37,6 +37,40 @@ + INDIRECT_CALL_L4(cb, f2, f1, head, skb); \ + }) + ++static int ipv6_gro_pull_exthdrs(struct sk_buff *skb, int off, int proto) ++{ ++ const struct net_offload *ops = NULL; ++ struct ipv6_opt_hdr *opth; ++ ++ for (;;) { ++ int len; ++ ++ ops = rcu_dereference(inet6_offloads[proto]); ++ ++ if (unlikely(!ops)) ++ break; ++ ++ if (!(ops->flags & INET6_PROTO_GSO_EXTHDR)) ++ break; ++ ++ opth = skb_gro_header(skb, off + sizeof(*opth), off); ++ if (unlikely(!opth)) ++ break; ++ ++ len = ipv6_optlen(opth); ++ ++ opth = skb_gro_header(skb, off + len, off); ++ if (unlikely(!opth)) ++ break; ++ proto = opth->nexthdr; ++ ++ off += len; ++ } ++ ++ skb_gro_pull(skb, off - skb_network_offset(skb)); ++ return proto; ++} ++ + static int ipv6_gso_pull_exthdrs(struct sk_buff *skb, int proto) + { + const struct net_offload *ops = NULL; +@@ -206,28 +240,25 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff * + goto out; + + skb_set_network_header(skb, off); +- skb_gro_pull(skb, sizeof(*iph)); +- skb_set_transport_header(skb, skb_gro_offset(skb)); + +- flush += ntohs(iph->payload_len) != skb_gro_len(skb); ++ flush += ntohs(iph->payload_len) != skb->len - hlen; + + proto = iph->nexthdr; + ops = rcu_dereference(inet6_offloads[proto]); + if (!ops || !ops->callbacks.gro_receive) { +- pskb_pull(skb, skb_gro_offset(skb)); +- skb_gro_frag0_invalidate(skb); +- proto = ipv6_gso_pull_exthdrs(skb, proto); +- skb_gro_pull(skb, -skb_transport_offset(skb)); +- skb_reset_transport_header(skb); +- __skb_push(skb, skb_gro_offset(skb)); ++ proto = ipv6_gro_pull_exthdrs(skb, hlen, proto); + + ops = rcu_dereference(inet6_offloads[proto]); + if (!ops || !ops->callbacks.gro_receive) + goto out; + +- iph = ipv6_hdr(skb); ++ iph = skb_gro_network_header(skb); ++ } else { ++ skb_gro_pull(skb, sizeof(*iph)); + } + ++ skb_set_transport_header(skb, skb_gro_offset(skb)); ++ + NAPI_GRO_CB(skb)->proto = proto; + + flush--; diff --git a/target/linux/generic/backport-6.6/600-v6.9-02-net-gro-fix-udp-bad-offset-in-socket-lookup-by-addin.patch b/target/linux/generic/backport-6.6/600-v6.9-02-net-gro-fix-udp-bad-offset-in-socket-lookup-by-addin.patch new file mode 100644 index 00000000000000..c5d8497dee626b --- /dev/null +++ b/target/linux/generic/backport-6.6/600-v6.9-02-net-gro-fix-udp-bad-offset-in-socket-lookup-by-addin.patch @@ -0,0 +1,178 @@ +From: Richard Gobert +Date: Tue, 30 Apr 2024 16:35:54 +0200 +Subject: [PATCH] net: gro: fix udp bad offset in socket lookup by adding + {inner_}network_offset to napi_gro_cb + +Commits a602456 ("udp: Add GRO functions to UDP socket") and 57c67ff ("udp: +additional GRO support") introduce incorrect usage of {ip,ipv6}_hdr in the +complete phase of gro. The functions always return skb->network_header, +which in the case of encapsulated packets at the gro complete phase, is +always set to the innermost L3 of the packet. That means that calling +{ip,ipv6}_hdr for skbs which completed the GRO receive phase (both in +gro_list and *_gro_complete) when parsing an encapsulated packet's _outer_ +L3/L4 may return an unexpected value. + +This incorrect usage leads to a bug in GRO's UDP socket lookup. +udp{4,6}_lib_lookup_skb functions use ip_hdr/ipv6_hdr respectively. These +*_hdr functions return network_header which will point to the innermost L3, +resulting in the wrong offset being used in __udp{4,6}_lib_lookup with +encapsulated packets. + +This patch adds network_offset and inner_network_offset to napi_gro_cb, and +makes sure both are set correctly. + +To fix the issue, network_offsets union is used inside napi_gro_cb, in +which both the outer and the inner network offsets are saved. + +Reproduction example: + +Endpoint configuration example (fou + local address bind) + + # ip fou add port 6666 ipproto 4 + # ip link add name tun1 type ipip remote 2.2.2.1 local 2.2.2.2 encap fou encap-dport 5555 encap-sport 6666 mode ipip + # ip link set tun1 up + # ip a add 1.1.1.2/24 dev tun1 + +Netperf TCP_STREAM result on net-next before patch is applied: + +net-next main, GRO enabled: + $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5 + Recv Send Send + Socket Socket Message Elapsed + Size Size Size Time Throughput + bytes bytes bytes secs. 10^6bits/sec + + 131072 16384 16384 5.28 2.37 + +net-next main, GRO disabled: + $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5 + Recv Send Send + Socket Socket Message Elapsed + Size Size Size Time Throughput + bytes bytes bytes secs. 10^6bits/sec + + 131072 16384 16384 5.01 2745.06 + +patch applied, GRO enabled: + $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5 + Recv Send Send + Socket Socket Message Elapsed + Size Size Size Time Throughput + bytes bytes bytes secs. 10^6bits/sec + + 131072 16384 16384 5.01 2877.38 + +Fixes: a6024562ffd7 ("udp: Add GRO functions to UDP socket") +Signed-off-by: Richard Gobert +Reviewed-by: Eric Dumazet +Reviewed-by: Willem de Bruijn +Signed-off-by: Paolo Abeni +--- + +--- a/include/net/gro.h ++++ b/include/net/gro.h +@@ -86,6 +86,15 @@ struct napi_gro_cb { + + /* used to support CHECKSUM_COMPLETE for tunneling protocols */ + __wsum csum; ++ ++ /* L3 offsets */ ++ union { ++ struct { ++ u16 network_offset; ++ u16 inner_network_offset; ++ }; ++ u16 network_offsets[2]; ++ }; + }; + + #define NAPI_GRO_CB(skb) ((struct napi_gro_cb *)(skb)->cb) +--- a/net/8021q/vlan_core.c ++++ b/net/8021q/vlan_core.c +@@ -478,6 +478,8 @@ static struct sk_buff *vlan_gro_receive( + if (unlikely(!vhdr)) + goto out; + ++ NAPI_GRO_CB(skb)->network_offsets[NAPI_GRO_CB(skb)->encap_mark] = hlen; ++ + type = vhdr->h_vlan_encapsulated_proto; + + ptype = gro_find_receive_by_type(type); +--- a/net/core/gro.c ++++ b/net/core/gro.c +@@ -373,6 +373,7 @@ static inline void skb_gro_reset_offset( + const struct skb_shared_info *pinfo = skb_shinfo(skb); + const skb_frag_t *frag0 = &pinfo->frags[0]; + ++ NAPI_GRO_CB(skb)->network_offset = 0; + NAPI_GRO_CB(skb)->data_offset = 0; + NAPI_GRO_CB(skb)->frag0 = NULL; + NAPI_GRO_CB(skb)->frag0_len = 0; +--- a/net/ipv4/af_inet.c ++++ b/net/ipv4/af_inet.c +@@ -1571,6 +1571,7 @@ struct sk_buff *inet_gro_receive(struct + /* The above will be needed by the transport layer if there is one + * immediately following this IP hdr. + */ ++ NAPI_GRO_CB(skb)->inner_network_offset = off; + + /* Note : No need to call skb_gro_postpull_rcsum() here, + * as we already checked checksum over ipv4 header was 0 +--- a/net/ipv4/udp.c ++++ b/net/ipv4/udp.c +@@ -534,7 +534,8 @@ static inline struct sock *__udp4_lib_lo + struct sock *udp4_lib_lookup_skb(const struct sk_buff *skb, + __be16 sport, __be16 dport) + { +- const struct iphdr *iph = ip_hdr(skb); ++ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation]; ++ const struct iphdr *iph = (struct iphdr *)(skb->data + offset); + struct net *net = dev_net(skb->dev); + int iif, sdif; + +--- a/net/ipv4/udp_offload.c ++++ b/net/ipv4/udp_offload.c +@@ -718,7 +718,8 @@ EXPORT_SYMBOL(udp_gro_complete); + + INDIRECT_CALLABLE_SCOPE int udp4_gro_complete(struct sk_buff *skb, int nhoff) + { +- const struct iphdr *iph = ip_hdr(skb); ++ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation]; ++ const struct iphdr *iph = (struct iphdr *)(skb->data + offset); + struct udphdr *uh = (struct udphdr *)(skb->data + nhoff); + + /* do fraglist only if there is no outer UDP encap (or we already processed it) */ +--- a/net/ipv6/ip6_offload.c ++++ b/net/ipv6/ip6_offload.c +@@ -240,6 +240,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff * + goto out; + + skb_set_network_header(skb, off); ++ NAPI_GRO_CB(skb)->inner_network_offset = off; + + flush += ntohs(iph->payload_len) != skb->len - hlen; + +--- a/net/ipv6/udp.c ++++ b/net/ipv6/udp.c +@@ -275,7 +275,8 @@ static struct sock *__udp6_lib_lookup_sk + struct sock *udp6_lib_lookup_skb(const struct sk_buff *skb, + __be16 sport, __be16 dport) + { +- const struct ipv6hdr *iph = ipv6_hdr(skb); ++ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation]; ++ const struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + offset); + struct net *net = dev_net(skb->dev); + int iif, sdif; + +--- a/net/ipv6/udp_offload.c ++++ b/net/ipv6/udp_offload.c +@@ -164,7 +164,8 @@ flush: + + INDIRECT_CALLABLE_SCOPE int udp6_gro_complete(struct sk_buff *skb, int nhoff) + { +- const struct ipv6hdr *ipv6h = ipv6_hdr(skb); ++ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation]; ++ const struct ipv6hdr *ipv6h = (struct ipv6hdr *)(skb->data + offset); + struct udphdr *uh = (struct udphdr *)(skb->data + nhoff); + + /* do fraglist only if there is no outer UDP encap (or we already processed it) */ diff --git a/target/linux/generic/backport-6.6/600-v6.9-03-net-gro-add-flush-check-in-udp_gro_receive_segment.patch b/target/linux/generic/backport-6.6/600-v6.9-03-net-gro-add-flush-check-in-udp_gro_receive_segment.patch new file mode 100644 index 00000000000000..72b76dd938bf83 --- /dev/null +++ b/target/linux/generic/backport-6.6/600-v6.9-03-net-gro-add-flush-check-in-udp_gro_receive_segment.patch @@ -0,0 +1,48 @@ +From: Richard Gobert +Date: Tue, 30 Apr 2024 16:35:55 +0200 +Subject: [PATCH] net: gro: add flush check in udp_gro_receive_segment + +GRO-GSO path is supposed to be transparent and as such L3 flush checks are +relevant to all UDP flows merging in GRO. This patch uses the same logic +and code from tcp_gro_receive, terminating merge if flush is non zero. + +Fixes: e20cf8d3f1f7 ("udp: implement GRO for plain UDP sockets.") +Signed-off-by: Richard Gobert +Reviewed-by: Willem de Bruijn +Signed-off-by: Paolo Abeni +--- + +--- a/net/ipv4/udp_offload.c ++++ b/net/ipv4/udp_offload.c +@@ -471,6 +471,7 @@ static struct sk_buff *udp_gro_receive_s + struct sk_buff *p; + unsigned int ulen; + int ret = 0; ++ int flush; + + /* requires non zero csum, for symmetry with GSO */ + if (!uh->check) { +@@ -504,13 +505,22 @@ static struct sk_buff *udp_gro_receive_s + return p; + } + ++ flush = NAPI_GRO_CB(p)->flush; ++ ++ if (NAPI_GRO_CB(p)->flush_id != 1 || ++ NAPI_GRO_CB(p)->count != 1 || ++ !NAPI_GRO_CB(p)->is_atomic) ++ flush |= NAPI_GRO_CB(p)->flush_id; ++ else ++ NAPI_GRO_CB(p)->is_atomic = false; ++ + /* Terminate the flow on len mismatch or if it grow "too much". + * Under small packet flood GRO count could elsewhere grow a lot + * leading to excessive truesize values. + * On len mismatch merge the first packet shorter than gso_size, + * otherwise complete the GRO packet. + */ +- if (ulen > ntohs(uh2->len)) { ++ if (ulen > ntohs(uh2->len) || flush) { + pp = p; + } else { + if (NAPI_GRO_CB(skb)->is_flist) { diff --git a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch index dfbe88e8e6386a..2729a0ec38ec01 100644 --- a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch @@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1152,6 +1157,11 @@ static const struct usb_device_id option +@@ -1156,6 +1161,11 @@ static const struct usb_device_id option { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */ .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) }, @@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support /* Quectel products using Qualcomm vendor ID */ { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)}, { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20), -@@ -1193,6 +1203,11 @@ static const struct usb_device_id option +@@ -1197,6 +1207,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, diff --git a/target/linux/generic/pending-6.1/150-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/pending-6.1/150-bridge_allow_receiption_on_disabled_port.patch index 93a2d146b5ad84..ac4a3138a55030 100644 --- a/target/linux/generic/pending-6.1/150-bridge_allow_receiption_on_disabled_port.patch +++ b/target/linux/generic/pending-6.1/150-bridge_allow_receiption_on_disabled_port.patch @@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c -@@ -222,6 +222,9 @@ static void __br_handle_local_finish(str +@@ -227,6 +227,9 @@ static void __br_handle_local_finish(str /* note: already called with rcu_read_lock */ static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { @@ -25,7 +25,7 @@ Signed-off-by: Felix Fietkau __br_handle_local_finish(skb); /* return 1 to signal the okfn() was called so it's ok to use the skb */ -@@ -390,6 +393,17 @@ forward: +@@ -397,6 +400,17 @@ forward: goto defer_stp_filtering; switch (p->state) { diff --git a/target/linux/generic/pending-6.1/350-mips-kernel-fix-detect_memory_region-function.patch b/target/linux/generic/pending-6.1/350-mips-kernel-fix-detect_memory_region-function.patch new file mode 100644 index 00000000000000..3bf7ae98bf35f2 --- /dev/null +++ b/target/linux/generic/pending-6.1/350-mips-kernel-fix-detect_memory_region-function.patch @@ -0,0 +1,74 @@ +From: Shiji Yang +Date: Wed, 13 Mar 2024 20:28:37 +0800 +Subject: [PATCH] mips: kernel: fix detect_memory_region() function + +1. Do not use memcmp() on unallocated memory, as the new introduced + fortify dynamic object size check[1] will report unexpected result. +2. Use a fixed pattern instead of a random function pointer as the + magic value. +3. Flip magic value and double check it. +4. Enable this feature only for 32-bit CPUs. Currently, only ath79 and + ralink CPUs are using it. + +[1] 439a1bcac648 ("fortify: Use __builtin_dynamic_object_size() when available") +Signed-off-by: Shiji Yang +--- + arch/mips/include/asm/bootinfo.h | 2 ++ + arch/mips/kernel/setup.c | 17 ++++++++++++----- + 2 files changed, 14 insertions(+), 5 deletions(-) + +--- a/arch/mips/include/asm/bootinfo.h ++++ b/arch/mips/include/asm/bootinfo.h +@@ -93,7 +93,9 @@ const char *get_system_type(void); + + extern unsigned long mips_machtype; + ++#ifndef CONFIG_64BIT + extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max); ++#endif + + extern void prom_init(void); + extern void prom_free_prom_memory(void); +--- a/arch/mips/kernel/setup.c ++++ b/arch/mips/kernel/setup.c +@@ -90,21 +90,27 @@ static struct resource bss_resource = { + unsigned long __kaslr_offset __ro_after_init; + EXPORT_SYMBOL(__kaslr_offset); + +-static void *detect_magic __initdata = detect_memory_region; +- + #ifdef CONFIG_MIPS_AUTO_PFN_OFFSET + unsigned long ARCH_PFN_OFFSET; + EXPORT_SYMBOL(ARCH_PFN_OFFSET); + #endif + ++#ifndef CONFIG_64BIT ++static u32 detect_magic __initdata; ++#define MIPS_MEM_TEST_PATTERN 0xaa5555aa ++ + void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max) + { +- void *dm = &detect_magic; ++ void *dm = (void *)KSEG1ADDR(&detect_magic); + phys_addr_t size; + + for (size = sz_min; size < sz_max; size <<= 1) { +- if (!memcmp(dm, dm + size, sizeof(detect_magic))) +- break; ++ __raw_writel(MIPS_MEM_TEST_PATTERN, dm); ++ if (__raw_readl(dm) == __raw_readl(dm + size)) { ++ __raw_writel(~MIPS_MEM_TEST_PATTERN, dm); ++ if (__raw_readl(dm) == __raw_readl(dm + size)) ++ break; ++ } + } + + pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n", +@@ -115,6 +121,7 @@ void __init detect_memory_region(phys_ad + + memblock_add(start, size); + } ++#endif /* CONFIG_64BIT */ + + /* + * Manage initrd diff --git a/target/linux/generic/pending-6.1/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/pending-6.1/610-netfilter_match_bypass_default_checks.patch index 56d62ab8e2e329..0ab89564eeb1d3 100644 --- a/target/linux/generic/pending-6.1/610-netfilter_match_bypass_default_checks.patch +++ b/target/linux/generic/pending-6.1/610-netfilter_match_bypass_default_checks.patch @@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau for (i = sizeof(struct ipt_entry); i < e->target_offset; i += m->u.match_size) { -@@ -1225,12 +1262,15 @@ compat_copy_entry_to_user(struct ipt_ent +@@ -1227,12 +1264,15 @@ compat_copy_entry_to_user(struct ipt_ent compat_uint_t origsize; const struct xt_entry_match *ematch; int ret = 0; diff --git a/target/linux/generic/pending-6.1/680-net-add-TCP-fraglist-GRO-support.patch b/target/linux/generic/pending-6.1/680-net-add-TCP-fraglist-GRO-support.patch index 841c0de3e1b8a4..f52233fe908efa 100644 --- a/target/linux/generic/pending-6.1/680-net-add-TCP-fraglist-GRO-support.patch +++ b/target/linux/generic/pending-6.1/680-net-add-TCP-fraglist-GRO-support.patch @@ -318,7 +318,7 @@ Signe-off-by: Felix Fietkau flush = NAPI_GRO_CB(p)->flush; flush |= (__force int)(flags & TCP_FLAG_CWR); flush |= (__force int)((flags ^ tcp_flag_word(th2)) & -@@ -268,6 +350,18 @@ found: +@@ -268,6 +350,19 @@ found: flush |= p->decrypted ^ skb->decrypted; #endif @@ -326,6 +326,7 @@ Signe-off-by: Felix Fietkau + flush |= (__force int)(flags ^ tcp_flag_word(th2)); + flush |= skb->ip_summed != p->ip_summed; + flush |= skb->csum_level != p->csum_level; ++ flush |= !pskb_may_pull(skb, skb_gro_offset(skb)); + flush |= NAPI_GRO_CB(p)->count >= 64; + + if (flush || skb_gro_receive_list(p, skb)) @@ -337,7 +338,7 @@ Signe-off-by: Felix Fietkau if (flush || skb_gro_receive(p, skb)) { mss = 1; goto out_check_final; -@@ -289,7 +383,6 @@ out_check_final: +@@ -289,7 +384,6 @@ out_check_final: if (p && (!NAPI_GRO_CB(skb)->same_flow || flush)) pp = p; @@ -345,7 +346,7 @@ Signe-off-by: Felix Fietkau NAPI_GRO_CB(skb)->flush |= (flush != 0); return pp; -@@ -315,18 +408,58 @@ int tcp_gro_complete(struct sk_buff *skb +@@ -315,18 +409,58 @@ int tcp_gro_complete(struct sk_buff *skb } EXPORT_SYMBOL(tcp_gro_complete); @@ -409,7 +410,7 @@ Signe-off-by: Felix Fietkau } INDIRECT_CALLABLE_SCOPE int tcp4_gro_complete(struct sk_buff *skb, int thoff) -@@ -334,6 +467,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com +@@ -334,6 +468,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com const struct iphdr *iph = ip_hdr(skb); struct tcphdr *th = tcp_hdr(skb); diff --git a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch index fb6eb73232d3ce..9f8c3d6ff57bdf 100644 --- a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch +++ b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch @@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c -@@ -7951,7 +7951,7 @@ static int nft_register_flowtable_net_ho +@@ -7959,7 +7959,7 @@ static int nft_register_flowtable_net_ho err = flowtable->data.type->setup(&flowtable->data, hook->ops.dev, FLOW_BLOCK_BIND); diff --git a/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch b/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch index 989aca8f3537bf..20d1c130459d84 100644 --- a/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch +++ b/target/linux/generic/pending-6.1/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch @@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev) --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c -@@ -344,6 +344,8 @@ static rx_handler_result_t br_handle_fra +@@ -349,6 +349,8 @@ static rx_handler_result_t br_handle_fra fwd_mask |= p->group_fwd_mask; switch (dest[5]) { case 0x00: /* Bridge Group Address */ diff --git a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch b/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch index da3fd7cbe1923d..04d8c8760fcc61 100644 --- a/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch +++ b/target/linux/generic/pending-6.1/795-01-net-dsa-mt7530-do-not-set-MT7530_P5_DIS-when-PHY-.patch @@ -68,7 +68,7 @@ Best regards, --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1213,7 +1213,7 @@ mt7530_port_disable(struct dsa_switch *d +@@ -1227,7 +1227,7 @@ mt7530_port_disable(struct dsa_switch *d if (priv->id != ID_MT7530 && priv->id != ID_MT7621) return; diff --git a/target/linux/generic/pending-6.1/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch b/target/linux/generic/pending-6.1/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch new file mode 100644 index 00000000000000..5db834e23f31fd --- /dev/null +++ b/target/linux/generic/pending-6.1/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch @@ -0,0 +1,136 @@ +From patchwork Tue Apr 30 05:01:33 2024 +Content-Type: text/plain; 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+ Tue, 30 Apr 2024 05:01:39 +0000 (UTC) +From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= + +Date: Tue, 30 Apr 2024 08:01:33 +0300 +Subject: [PATCH net-next v2] net: dsa: mt7530: detect PHY muxing when PHY + is defined on switch MDIO bus +Precedence: bulk +X-Mailing-List: netdev@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 +Message-Id: + <20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com> +X-B4-Tracking: v=1; b=H4sIACx7MGYC/6WOSw6DMBBDr1LNulNBIHy66j0qFhAGmAUJSgIFI + e7eNFeovLJsPfsER5bJwfN2gqWNHRsdjLjfQE2tHgm5Dx5EIvIkFzV2OQ7Goiavafc4+1JmCa6 + O0H3Yqwnnng12q4u1ZTpwXnfWI8qqEEWdlamSEgJ+sTTwHqffEHD440ETkomdN/aIn7Y05v/Pb + ykGDWUp6yqjVMpXa1mr+qHMDM11XV8dryM7CwEAAA== +To: Daniel Golle , DENG Qingfang , + Sean Wang , Andrew Lunn , + Florian Fainelli , + Vladimir Oltean , + "David S. Miller" , Eric Dumazet , + Jakub Kicinski , Paolo Abeni , + Matthias Brugger , + AngeloGioacchino Del Regno +Cc: Bartel Eerdekens , + mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org, + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= +X-Mailer: b4 0.13.0 +X-Developer-Signature: v=1; a=ed25519-sha256; t=1714453297; l=1949; + i=arinc.unal@arinc9.com; s=arinc9-PC; h=from:subject:message-id; + bh=c3IRARdnxa6x5otHszH4xrnla2RxJAal1114ej/d2wE=; + b=FL4WEHh4zYu1gBE7wbaN+X2OMCOIMJVsYBkXurHM0IC3CnI6XfpKE1V5QLUSXby75WZfvQ0se + lrMQos/eOAaCNbkyxUkmwb3opbC915iywMECA0lv/g0IAo6snRYzMae +X-Developer-Key: i=arinc.unal@arinc9.com; a=ed25519; + pk=Bd1s2kQtNfZAWyeLHg39jaWBDqt8Ud1WJXLFh7gxl20= +X-Endpoint-Received: by B4 Relay for arinc.unal@arinc9.com/arinc9-PC with + auth_id=158 +X-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= +Reply-To: arinc.unal@arinc9.com +X-Patchwork-Delegate: kuba@kernel.org + +From: Arınç ÜNAL + +Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide +direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO +bus the switch listens on. The PHY muxing feature makes use of this. + +This is problematic as the PHY may be attached before the switch is +initialised, in which case, the PHY will fail to be attached. + +Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration +of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of +the switch on the device tree. Extend the check to detect PHY muxing when +the PHY is defined on the MDIO bus of the switch on the device tree. + +When the PHY is described this way, the switch will be initialised first, +then the switch MDIO bus will be registered. Only after these steps, the +PHY will be attached. + +Signed-off-by: Arınç ÜNAL +--- +Changes in v2: +- Address the terminology on the patch log. +- Link to v1: https://lore.kernel.org/r/20240429-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v1-1-1f775983e155@arinc9.com +--- + drivers/net/dsa/mt7530.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + + +--- +base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c +change-id: 20240429-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-586269371c55 + +Best regards, + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2488,7 +2488,8 @@ mt7530_setup(struct dsa_switch *ds) + if (!phy_node) + continue; + +- if (phy_node->parent == priv->dev->of_node->parent) { ++ if (phy_node->parent == priv->dev->of_node->parent || ++ phy_node->parent->parent == priv->dev->of_node) { + ret = of_get_phy_mode(mac_np, &interface); + if (ret && ret != -ENODEV) { + of_node_put(mac_np); diff --git a/target/linux/generic/pending-6.1/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/pending-6.1/811-pci_disable_usb_common_quirks.patch index 98ea4c06d9f8ce..fcb77e51747003 100644 --- a/target/linux/generic/pending-6.1/811-pci_disable_usb_common_quirks.patch +++ b/target/linux/generic/pending-6.1/811-pci_disable_usb_common_quirks.patch @@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau static struct amd_chipset_info { struct pci_dev *nb_dev; struct pci_dev *smbus_dev; -@@ -633,6 +635,10 @@ bool usb_amd_pt_check_port(struct device +@@ -631,6 +633,10 @@ bool usb_amd_pt_check_port(struct device } EXPORT_SYMBOL_GPL(usb_amd_pt_check_port); @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau /* * Make sure the controller is completely inactive, unable to * generate interrupts or do DMA. -@@ -712,8 +718,17 @@ reset_needed: +@@ -710,8 +716,17 @@ reset_needed: uhci_reset_hc(pdev, base); return 1; } @@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) { u16 cmd; -@@ -1285,3 +1300,4 @@ static void quirk_usb_early_handoff(stru +@@ -1283,3 +1298,4 @@ static void quirk_usb_early_handoff(stru } DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); @@ -98,7 +98,7 @@ Signed-off-by: Felix Fietkau #endif /* __LINUX_USB_PCI_QUIRKS_H */ --- a/include/linux/usb/hcd.h +++ b/include/linux/usb/hcd.h -@@ -483,7 +483,14 @@ extern int usb_hcd_pci_probe(struct pci_ +@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_ extern void usb_hcd_pci_remove(struct pci_dev *dev); extern void usb_hcd_pci_shutdown(struct pci_dev *dev); diff --git a/target/linux/generic/pending-6.1/920-mangle_bootargs.patch b/target/linux/generic/pending-6.1/920-mangle_bootargs.patch index 76e3f2544d5a31..ca36d0ccab8552 100644 --- a/target/linux/generic/pending-6.1/920-mangle_bootargs.patch +++ b/target/linux/generic/pending-6.1/920-mangle_bootargs.patch @@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz /* * We need to store the untouched command line for future reference. * We also need to store the touched command line since the parameter -@@ -959,6 +982,7 @@ asmlinkage __visible void __init __no_sa +@@ -961,6 +984,7 @@ asmlinkage __visible void __init __no_sa pr_notice("%s", linux_banner); early_security_init(); setup_arch(&command_line); diff --git a/target/linux/generic/pending-6.6/195-block-fix-and-simplify-blkdevparts-cmdline-parsing.patch b/target/linux/generic/pending-6.6/195-block-fix-and-simplify-blkdevparts-cmdline-parsing.patch new file mode 100644 index 00000000000000..d504a74fdecd77 --- /dev/null +++ b/target/linux/generic/pending-6.6/195-block-fix-and-simplify-blkdevparts-cmdline-parsing.patch @@ -0,0 +1,217 @@ +From patchwork Sun Apr 21 07:39:52 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: INAGAKI Hiroshi +X-Patchwork-Id: 13637306 +From: INAGAKI Hiroshi +To: axboe@kernel.dk +Cc: yang.yang29@zte.com, + justinstitt@google.com, + xu.panda@zte.com.cn, + linux-block@vger.kernel.org, + linux-kernel@vger.kernel.org, + INAGAKI Hiroshi , + Naohiro Aota +Subject: [PATCH] block: fix and simplify blkdevparts= cmdline parsing +Date: Sun, 21 Apr 2024 16:39:52 +0900 +Message-ID: <20240421074005.565-1-musashino.open@gmail.com> +X-Mailer: git-send-email 2.42.0.windows.2 +Precedence: bulk +X-Mailing-List: linux-block@vger.kernel.org +List-Id: +List-Subscribe: +List-Unsubscribe: +MIME-Version: 1.0 + +Fix the cmdline parsing of the "blkdevparts=" parameter using strsep(), +which makes the code simpler. + +Before commit 146afeb235cc ("block: use strscpy() to instead of +strncpy()"), we used a strncpy() to copy a block device name and partition +names. The commit simply replaced a strncpy() and NULL termination with +a strscpy(). It did not update calculations of length passed to strscpy(). +While the length passed to strncpy() is just a length of valid characters +without NULL termination ('\0'), strscpy() takes it as a length of the +destination buffer, including a NULL termination. + +Since the source buffer is not necessarily NULL terminated, the current +code copies "length - 1" characters and puts a NULL character in the +destination buffer. It replaces the last character with NULL and breaks +the parsing. + +As an example, that buffer will be passed to parse_parts() and breaks +parsing sub-partitions due to the missing ')' at the end, like the +following. + +example (Check Point V-80 & OpenWrt): + +- Linux Kernel 6.6 + + [ 0.000000] Kernel command line: console=ttyS0,115200 earlycon=uart8250,mmio32,0xf0512000 crashkernel=30M mvpp2x.queue_mode=1 blkdevparts=mmcblk1:48M@10M(kernel-1),1M(dtb-1),720M(rootfs-1),48M(kernel-2),1M(dtb-2),720M(rootfs-2),300M(default_sw),650M(logs),1M(preset_cfg),1M(adsl),-(storage) maxcpus=4 + ... + [ 0.884016] mmc1: new HS200 MMC card at address 0001 + [ 0.889951] mmcblk1: mmc1:0001 004GA0 3.69 GiB + [ 0.895043] cmdline partition format is invalid. + [ 0.895704] mmcblk1: p1 + [ 0.903447] mmcblk1boot0: mmc1:0001 004GA0 2.00 MiB + [ 0.908667] mmcblk1boot1: mmc1:0001 004GA0 2.00 MiB + [ 0.913765] mmcblk1rpmb: mmc1:0001 004GA0 512 KiB, chardev (248:0) + + 1. "48M@10M(kernel-1),..." is passed to strscpy() with length=17 + from parse_parts() + 2. strscpy() returns -E2BIG and the destination buffer has + "48M@10M(kernel-1\0" + 3. "48M@10M(kernel-1\0" is passed to parse_subpart() + 4. parse_subpart() fails to find ')' when parsing a partition name, + and returns error + +- Linux Kernel 6.1 + + [ 0.000000] Kernel command line: console=ttyS0,115200 earlycon=uart8250,mmio32,0xf0512000 crashkernel=30M mvpp2x.queue_mode=1 blkdevparts=mmcblk1:48M@10M(kernel-1),1M(dtb-1),720M(rootfs-1),48M(kernel-2),1M(dtb-2),720M(rootfs-2),300M(default_sw),650M(logs),1M(preset_cfg),1M(adsl),-(storage) maxcpus=4 + ... + [ 0.953142] mmc1: new HS200 MMC card at address 0001 + [ 0.959114] mmcblk1: mmc1:0001 004GA0 3.69 GiB + [ 0.964259] mmcblk1: p1(kernel-1) p2(dtb-1) p3(rootfs-1) p4(kernel-2) p5(dtb-2) 6(rootfs-2) p7(default_sw) p8(logs) p9(preset_cfg) p10(adsl) p11(storage) + [ 0.979174] mmcblk1boot0: mmc1:0001 004GA0 2.00 MiB + [ 0.984674] mmcblk1boot1: mmc1:0001 004GA0 2.00 MiB + [ 0.989926] mmcblk1rpmb: mmc1:0001 004GA0 512 KiB, chardev (248:0 + +By the way, strscpy() takes a length of destination buffer and it is +often confusing when copying characters with a specified length. Using +strsep() helps to separate the string by the specified character. Then, +we can use strscpy() naturally with the size of the destination buffer. + +Separating the string on the fly is also useful to omit the redundant +string copy, reducing memory usage and improve the code readability. + +Fixes: 146afeb235cc ("block: use strscpy() to instead of strncpy()") +Suggested-by: Naohiro Aota +Signed-off-by: INAGAKI Hiroshi +Reviewed-by: Daniel Golle +--- + block/partitions/cmdline.c | 49 ++++++++++---------------------------- + 1 file changed, 12 insertions(+), 37 deletions(-) + +--- a/block/partitions/cmdline.c ++++ b/block/partitions/cmdline.c +@@ -70,8 +70,8 @@ static int parse_subpart(struct cmdline_ + } + + if (*partdef == '(') { +- int length; +- char *next = strchr(++partdef, ')'); ++ partdef++; ++ char *next = strsep(&partdef, ")"); + + if (!next) { + pr_warn("cmdline partition format is invalid."); +@@ -79,11 +79,7 @@ static int parse_subpart(struct cmdline_ + goto fail; + } + +- length = min_t(int, next - partdef, +- sizeof(new_subpart->name) - 1); +- strscpy(new_subpart->name, partdef, length); +- +- partdef = ++next; ++ strscpy(new_subpart->name, next, sizeof(new_subpart->name)); + } else + new_subpart->name[0] = '\0'; + +@@ -117,14 +113,12 @@ static void free_subpart(struct cmdline_ + } + } + +-static int parse_parts(struct cmdline_parts **parts, const char *bdevdef) ++static int parse_parts(struct cmdline_parts **parts, char *bdevdef) + { + int ret = -EINVAL; + char *next; +- int length; + struct cmdline_subpart **next_subpart; + struct cmdline_parts *newparts; +- char buf[BDEVNAME_SIZE + 32 + 4]; + + *parts = NULL; + +@@ -132,28 +126,19 @@ static int parse_parts(struct cmdline_pa + if (!newparts) + return -ENOMEM; + +- next = strchr(bdevdef, ':'); ++ next = strsep(&bdevdef, ":"); + if (!next) { + pr_warn("cmdline partition has no block device."); + goto fail; + } + +- length = min_t(int, next - bdevdef, sizeof(newparts->name) - 1); +- strscpy(newparts->name, bdevdef, length); ++ strscpy(newparts->name, next, sizeof(newparts->name)); + newparts->nr_subparts = 0; + + next_subpart = &newparts->subpart; + +- while (next && *(++next)) { +- bdevdef = next; +- next = strchr(bdevdef, ','); +- +- length = (!next) ? (sizeof(buf) - 1) : +- min_t(int, next - bdevdef, sizeof(buf) - 1); +- +- strscpy(buf, bdevdef, length); +- +- ret = parse_subpart(next_subpart, buf); ++ while ((next = strsep(&bdevdef, ","))) { ++ ret = parse_subpart(next_subpart, next); + if (ret) + goto fail; + +@@ -199,24 +184,17 @@ static int cmdline_parts_parse(struct cm + + *parts = NULL; + +- next = pbuf = buf = kstrdup(cmdline, GFP_KERNEL); ++ pbuf = buf = kstrdup(cmdline, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + next_parts = parts; + +- while (next && *pbuf) { +- next = strchr(pbuf, ';'); +- if (next) +- *next = '\0'; +- +- ret = parse_parts(next_parts, pbuf); ++ while ((next = strsep(&pbuf, ";"))) { ++ ret = parse_parts(next_parts, next); + if (ret) + goto fail; + +- if (next) +- pbuf = ++next; +- + next_parts = &(*next_parts)->next_parts; + } + +@@ -250,7 +228,6 @@ static struct cmdline_parts *bdev_parts; + static int add_part(int slot, struct cmdline_subpart *subpart, + struct parsed_partitions *state) + { +- int label_min; + struct partition_meta_info *info; + char tmp[sizeof(info->volname) + 4]; + +@@ -262,9 +239,7 @@ static int add_part(int slot, struct cmd + + info = &state->parts[slot].info; + +- label_min = min_t(int, sizeof(info->volname) - 1, +- sizeof(subpart->name)); +- strscpy(info->volname, subpart->name, label_min); ++ strscpy(info->volname, subpart->name, sizeof(info->volname)); + + snprintf(tmp, sizeof(tmp), "(%s)", info->volname); + strlcat(state->pp_buf, tmp, PAGE_SIZE); diff --git a/target/linux/generic/pending-6.6/350-mips-kernel-fix-detect_memory_region-function.patch b/target/linux/generic/pending-6.6/350-mips-kernel-fix-detect_memory_region-function.patch index 4654bc14ef039b..3bf7ae98bf35f2 100644 --- a/target/linux/generic/pending-6.6/350-mips-kernel-fix-detect_memory_region-function.patch +++ b/target/linux/generic/pending-6.6/350-mips-kernel-fix-detect_memory_region-function.patch @@ -7,35 +7,45 @@ Subject: [PATCH] mips: kernel: fix detect_memory_region() function 2. Use a fixed pattern instead of a random function pointer as the magic value. 3. Flip magic value and double check it. +4. Enable this feature only for 32-bit CPUs. Currently, only ath79 and + ralink CPUs are using it. [1] 439a1bcac648 ("fortify: Use __builtin_dynamic_object_size() when available") Signed-off-by: Shiji Yang --- - arch/mips/kernel/setup.c | 16 +++++++++++----- - 1 file changed, 11 insertions(+), 5 deletions(-) + arch/mips/include/asm/bootinfo.h | 2 ++ + arch/mips/kernel/setup.c | 17 ++++++++++++----- + 2 files changed, 14 insertions(+), 5 deletions(-) +--- a/arch/mips/include/asm/bootinfo.h ++++ b/arch/mips/include/asm/bootinfo.h +@@ -93,7 +93,9 @@ const char *get_system_type(void); + + extern unsigned long mips_machtype; + ++#ifndef CONFIG_64BIT + extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max); ++#endif + + extern void prom_init(void); + extern void prom_free_prom_memory(void); --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c -@@ -46,6 +46,8 @@ - #include - #include - -+#define MIPS_MEM_TEST_PATTERN 0xaa5555aa -+ - #ifdef CONFIG_MIPS_ELF_APPENDED_DTB - char __section(".appended_dtb") __appended_dtb[0x100000]; - #endif /* CONFIG_MIPS_ELF_APPENDED_DTB */ -@@ -90,7 +92,7 @@ static struct resource bss_resource = { +@@ -90,21 +90,27 @@ static struct resource bss_resource = { unsigned long __kaslr_offset __ro_after_init; EXPORT_SYMBOL(__kaslr_offset); -static void *detect_magic __initdata = detect_memory_region; -+static u32 detect_magic __initdata; - +- #ifdef CONFIG_MIPS_AUTO_PFN_OFFSET unsigned long ARCH_PFN_OFFSET; -@@ -99,12 +101,16 @@ EXPORT_SYMBOL(ARCH_PFN_OFFSET); + EXPORT_SYMBOL(ARCH_PFN_OFFSET); + #endif ++#ifndef CONFIG_64BIT ++static u32 detect_magic __initdata; ++#define MIPS_MEM_TEST_PATTERN 0xaa5555aa ++ void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max) { - void *dm = &detect_magic; @@ -54,3 +64,11 @@ Signed-off-by: Shiji Yang } pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n", +@@ -115,6 +121,7 @@ void __init detect_memory_region(phys_ad + + memblock_add(start, size); + } ++#endif /* CONFIG_64BIT */ + + /* + * Manage initrd diff --git a/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch b/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch index 6205901707a24a..cd7762667713c3 100644 --- a/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch +++ b/target/linux/generic/pending-6.6/680-net-add-TCP-fraglist-GRO-support.patch @@ -21,7 +21,7 @@ Signe-off-by: Felix Fietkau --- a/include/net/gro.h +++ b/include/net/gro.h -@@ -430,6 +430,7 @@ static inline __wsum ip6_gro_compute_pse +@@ -439,6 +439,7 @@ static inline __wsum ip6_gro_compute_pse } int skb_gro_receive(struct sk_buff *p, struct sk_buff *skb); @@ -269,7 +269,7 @@ Signe-off-by: Felix Fietkau flush = NAPI_GRO_CB(p)->flush; flush |= (__force int)(flags & TCP_FLAG_CWR); flush |= (__force int)((flags ^ tcp_flag_word(th2)) & -@@ -269,6 +351,18 @@ found: +@@ -269,6 +351,19 @@ found: flush |= p->decrypted ^ skb->decrypted; #endif @@ -277,6 +277,7 @@ Signe-off-by: Felix Fietkau + flush |= (__force int)(flags ^ tcp_flag_word(th2)); + flush |= skb->ip_summed != p->ip_summed; + flush |= skb->csum_level != p->csum_level; ++ flush |= !pskb_may_pull(skb, skb_gro_offset(skb)); + flush |= NAPI_GRO_CB(p)->count >= 64; + + if (flush || skb_gro_receive_list(p, skb)) @@ -288,7 +289,7 @@ Signe-off-by: Felix Fietkau if (flush || skb_gro_receive(p, skb)) { mss = 1; goto out_check_final; -@@ -290,7 +384,6 @@ out_check_final: +@@ -290,7 +385,6 @@ out_check_final: if (p && (!NAPI_GRO_CB(skb)->same_flow || flush)) pp = p; @@ -296,7 +297,7 @@ Signe-off-by: Felix Fietkau NAPI_GRO_CB(skb)->flush |= (flush != 0); return pp; -@@ -314,18 +407,58 @@ void tcp_gro_complete(struct sk_buff *sk +@@ -314,18 +408,58 @@ void tcp_gro_complete(struct sk_buff *sk } EXPORT_SYMBOL(tcp_gro_complete); @@ -360,7 +361,7 @@ Signe-off-by: Felix Fietkau } INDIRECT_CALLABLE_SCOPE int tcp4_gro_complete(struct sk_buff *skb, int thoff) -@@ -333,6 +466,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com +@@ -333,6 +467,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com const struct iphdr *iph = ip_hdr(skb); struct tcphdr *th = tcp_hdr(skb); diff --git a/target/linux/generic/pending-6.6/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch b/target/linux/generic/pending-6.6/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch new file mode 100644 index 00000000000000..f181be933a02d4 --- /dev/null +++ b/target/linux/generic/pending-6.6/796-net-dsa-mt7530-detect-PHY-muxing-when-PHY-is-defined-on-switch-MDIO-bus.patch @@ -0,0 +1,136 @@ +From patchwork Tue Apr 30 05:01:33 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?= + +X-Patchwork-Id: 13648264 +X-Patchwork-Delegate: kuba@kernel.org +Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org + [10.30.226.201]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C9C114A89; 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Miller" , Eric Dumazet , + Jakub Kicinski , Paolo Abeni , + Matthias Brugger , + AngeloGioacchino Del Regno +Cc: Bartel Eerdekens , + mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, + linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-mediatek@lists.infradead.org, + =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= +X-Mailer: b4 0.13.0 +X-Developer-Signature: v=1; a=ed25519-sha256; t=1714453297; l=1949; + i=arinc.unal@arinc9.com; s=arinc9-PC; h=from:subject:message-id; + bh=c3IRARdnxa6x5otHszH4xrnla2RxJAal1114ej/d2wE=; + b=FL4WEHh4zYu1gBE7wbaN+X2OMCOIMJVsYBkXurHM0IC3CnI6XfpKE1V5QLUSXby75WZfvQ0se + lrMQos/eOAaCNbkyxUkmwb3opbC915iywMECA0lv/g0IAo6snRYzMae +X-Developer-Key: i=arinc.unal@arinc9.com; a=ed25519; + pk=Bd1s2kQtNfZAWyeLHg39jaWBDqt8Ud1WJXLFh7gxl20= +X-Endpoint-Received: by B4 Relay for arinc.unal@arinc9.com/arinc9-PC with + auth_id=158 +X-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= +Reply-To: arinc.unal@arinc9.com +X-Patchwork-Delegate: kuba@kernel.org + +From: Arınç ÜNAL + +Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide +direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO +bus the switch listens on. The PHY muxing feature makes use of this. + +This is problematic as the PHY may be attached before the switch is +initialised, in which case, the PHY will fail to be attached. + +Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration +of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of +the switch on the device tree. Extend the check to detect PHY muxing when +the PHY is defined on the MDIO bus of the switch on the device tree. + +When the PHY is described this way, the switch will be initialised first, +then the switch MDIO bus will be registered. Only after these steps, the +PHY will be attached. + +Signed-off-by: Arınç ÜNAL +--- +Changes in v2: +- Address the terminology on the patch log. +- Link to v1: https://lore.kernel.org/r/20240429-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v1-1-1f775983e155@arinc9.com +--- + drivers/net/dsa/mt7530.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + + +--- +base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c +change-id: 20240429-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-586269371c55 + +Best regards, + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2483,7 +2483,8 @@ mt7530_setup(struct dsa_switch *ds) + if (!phy_node) + continue; + +- if (phy_node->parent == priv->dev->of_node->parent) { ++ if (phy_node->parent == priv->dev->of_node->parent || ++ phy_node->parent->parent == priv->dev->of_node) { + ret = of_get_phy_mode(mac_np, &interface); + if (ret && ret != -ENODEV) { + of_node_put(mac_np); diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-1200.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-1200.dts index 7d683cdf652dbd..10f21a59473974 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-1200.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-fritzrepeater-1200.dts @@ -23,16 +23,6 @@ status = "okay"; }; - mdio@90000 { - status = "okay"; - pinctrl-0 = <&mdio_pins>; - pinctrl-names = "default"; - - ethphy: ethernet-phy@0 { - reg = <0x0>; - }; - }; - tcsr@1949000 { compatible = "qcom,tcsr"; reg = <0x1949000 0x100>; @@ -255,6 +245,16 @@ qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200"; }; +&mdio { + status = "okay"; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + ethphy: ethernet-phy@0 { + reg = <0x0>; + }; +}; + &gmac { status = "okay"; }; @@ -273,6 +273,10 @@ phy-mode = "rgmii-id"; }; +&qca807x { + status = "disabled"; +}; + ðphy1 { status = "disabled"; }; diff --git a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts index 0dec567bc466d9..69d4810277352a 100644 --- a/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts +++ b/target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts @@ -71,25 +71,6 @@ watchdog@b017000 { status = "okay"; }; - - i2c_0: i2c@78b7000 { - pinctrl-0 = <&i2c_0_pins>; - pinctrl-names = "default"; - status = "okay"; - - tpm@29 { - /* No Driver */ - compatible = "atmel,at97sc3203"; - reg = <0x29>; - read-only; - }; - - power-monitor@40 { - /* No driver */ - compatible = "isl,isl28022"; - reg = <0x40>; - }; - }; }; leds { @@ -214,7 +195,7 @@ pins = "gpio20", "gpio21"; function = "blsp_i2c0"; drive-strength = <4>; - bias-disable; + bias-pull-up; }; }; @@ -242,6 +223,28 @@ }; }; +&blsp1_i2c3 { + pinctrl-0 = <&i2c_0_pins>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = <400000>; + + tpm@29 { + /* No Driver */ + compatible = "atmel,at97sc3203"; + reg = <0x29>; + read-only; + }; + + power-monitor@40 { + /* No driver */ + /* Device also replies on address 0x3f, see */ + /* ISL28022 datasheet, "Broadcast Addressing" */ + compatible = "isl,isl28022"; + reg = <0x40>; + }; +}; + &blsp1_spi1 { pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; diff --git a/target/linux/ipq40xx/patches-6.6/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch b/target/linux/ipq40xx/patches-6.6/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch index 6a37cc1f5edf15..50c8e645342ae4 100644 --- a/target/linux/ipq40xx/patches-6.6/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch +++ b/target/linux/ipq40xx/patches-6.6/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch @@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi status = "disabled"; - ethphy0: ethernet-phy@0 { -+ ethernet-phy-package@0 { ++ qca807x: ethernet-phy-package@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,qca8075-package"; diff --git a/target/linux/loongarch64/Makefile b/target/linux/loongarch64/Makefile new file mode 100644 index 00000000000000..f8401c2b2e9693 --- /dev/null +++ b/target/linux/loongarch64/Makefile @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2024 Weijie Gao + +include $(TOPDIR)/rules.mk + +ARCH:=loongarch64 +BOARD:=loongarch64 +BOARDNAME:=Loongson LoongArch +FEATURES:=audio display ext4 pcie boot-part rootfs-part rtc usb targz +SUBTARGETS:=generic + +KERNEL_PATCHVER:=6.6 + +KERNELNAME:=vmlinuz.efi dtbs + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += \ + partx-utils blkid e2fsprogs grub2-efi-loongarch64 + +$(eval $(call BuildTarget)) diff --git a/target/linux/loongarch64/base-files.mk b/target/linux/loongarch64/base-files.mk new file mode 100644 index 00000000000000..e2b7d05f57379e --- /dev/null +++ b/target/linux/loongarch64/base-files.mk @@ -0,0 +1,8 @@ +GRUB_SERIAL:=$(call qstrip,$(CONFIG_TARGET_SERIAL)) +ifeq ($(GRUB_SERIAL),) +$(error This platform requires CONFIG_TARGET_SERIAL be set!) +endif + +define Package/base-files/install-target + $(SED) "s#@GRUB_SERIAL@#$(GRUB_SERIAL)#" $(1)/etc/inittab +endef diff --git a/target/linux/loongarch64/base-files/etc/inittab b/target/linux/loongarch64/base-files/etc/inittab new file mode 100644 index 00000000000000..584a4114d48056 --- /dev/null +++ b/target/linux/loongarch64/base-files/etc/inittab @@ -0,0 +1,4 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +@GRUB_SERIAL@::askfirst:/usr/libexec/login.sh +tty0::askfirst:/usr/libexec/login.sh diff --git a/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi b/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi new file mode 100644 index 00000000000000..4d9e92e544a203 --- /dev/null +++ b/target/linux/loongarch64/base-files/lib/preinit/01_sysinfo_acpi @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +sanitize_name_loongarch64() { + sed -e ' + y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/; + s/[^a-z0-9_-]\+/-/g; + s/^-//; + s/-$//; + ' "$@" +} + +do_sysinfo_loongarch64() { + local vendor product file + + for file in sys_vendor board_vendor; do + vendor="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)" + case "$vendor" in + empty | \ + System\ manufacturer | \ + To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.) + continue + ;; + esac + [ -n "$vendor" ] && break + done + + for file in product_name board_name; do + product="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)" + case "$vendor:$product" in + ?*:empty | \ + ?*:System\ Product\ Name | \ + ?*:To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.) + continue + ;; + ?*:?*) + break + ;; + esac + done + + [ -d "/sys/firmware/devicetree/base" ] && return + + [ -n "$vendor" -a -n "$product" ] || return + + mkdir -p /tmp/sysinfo + + echo "$vendor $product" > /tmp/sysinfo/model + + sanitize_name_loongarch64 /tmp/sysinfo/model > /tmp/sysinfo/board_name +} + +boot_hook_add preinit_main do_sysinfo_loongarch64 diff --git a/target/linux/loongarch64/base-files/lib/preinit/79_move_config b/target/linux/loongarch64/base-files/lib/preinit/79_move_config new file mode 100644 index 00000000000000..864d4dfa644fc7 --- /dev/null +++ b/target/linux/loongarch64/base-files/lib/preinit/79_move_config @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +move_config() { + local partdev parttype=ext4 + + . /lib/upgrade/common.sh + + if export_bootdevice && export_partdevice partdev 1; then + part_magic_fat "/dev/$partdev" && parttype=vfat + if mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt; then + if [ -f "/mnt/$BACKUP_FILE" ]; then + mv -f "/mnt/$BACKUP_FILE" / + fi + umount /mnt + fi + fi +} + +boot_hook_add preinit_mount_root move_config diff --git a/target/linux/loongarch64/base-files/lib/upgrade/platform.sh b/target/linux/loongarch64/base-files/lib/upgrade/platform.sh new file mode 100644 index 00000000000000..a0d4c2dcec7eb3 --- /dev/null +++ b/target/linux/loongarch64/base-files/lib/upgrade/platform.sh @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +RAMFS_COPY_BIN="/usr/sbin/blkid" + +platform_check_image() { + local board=$(board_name) + local diskdev partdev diff + [ "$#" -gt 1 ] && return 1 + + v "Board is ${board}" + + export_bootdevice && export_partdevice diskdev 0 || { + v "platform_check_image: Unable to determine upgrade device" + return 1 + } + + get_partitions "/dev/$diskdev" bootdisk + + v "Extract boot sector from the image" + get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b + + get_partitions /tmp/image.bs image + + #compare tables + diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)" + + rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image + + if [ -n "$diff" ]; then + v "Partition layout has changed. Full image will be written." + ask_bool 0 "Abort" && exit 1 + return 0 + fi +} + +platform_copy_config() { + local partdev parttype=ext4 + + if export_partdevice partdev 1; then + part_magic_fat "/dev/$partdev" && parttype=vfat + mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt + cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE" + umount /mnt + else + v "ERROR: Unable to find partition to copy config data to" + fi + + sleep 5 +} + +# To avoid writing over any firmware +# files (e.g ubootefi.var or firmware/X/ aka EBBR) +# Copy efi/openwrt and efi/boot from the new image +# to the existing ESP +platform_do_upgrade_efi_system_partition() { + local image_file=$1 + local target_partdev=$2 + local image_efisp_start=$3 + local image_efisp_size=$4 + + v "Updating ESP on ${target_partdev}" + NEW_ESP_DIR="/mnt/new_esp_loop" + CUR_ESP_DIR="/mnt/cur_esp" + mkdir "${NEW_ESP_DIR}" + mkdir "${CUR_ESP_DIR}" + + get_image_dd "$image_file" of="/tmp/new_efi_sys_part.img" \ + skip="$image_efisp_start" count="$image_efisp_size" + + mount -t vfat -o loop -o ro /tmp/new_efi_sys_part.img "${NEW_ESP_DIR}" + if [ ! -d "${NEW_ESP_DIR}/efi/boot" ]; then + v "ERROR: Image does not contain EFI boot files (/efi/boot)" + return 1 + fi + + mount -t vfat "/dev/$partdev" "${CUR_ESP_DIR}" + + for d in $(find "${NEW_ESP_DIR}/efi/" -mindepth 1 -maxdepth 1 -type d); do + v "Copying ${d}" + newdir_bname=$(basename "${d}") + rm -rf "${CUR_ESP_DIR}/efi/${newdir_bname}" + cp -r "${d}" "${CUR_ESP_DIR}/efi" + v "rm -rf \"${CUR_ESP_DIR}/efi/${newdir_bname}\"" + v "cp -r \"${d}\" \"${CUR_ESP_DIR}/efi\"" + done + + umount "${NEW_ESP_DIR}" + umount "${CUR_ESP_DIR}" +} + +platform_do_upgrade() { + local board=$(board_name) + local diskdev partdev diff + + export_bootdevice && export_partdevice diskdev 0 || { + v "platform_do_upgrade: Unable to determine upgrade device" + return 1 + } + + sync + + if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then + get_partitions "/dev/$diskdev" bootdisk + + v "Extract boot sector from the image" + get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b + + get_partitions /tmp/image.bs image + + #compare tables + diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)" + else + diff=1 + fi + + # Only change the partition table if sysupgrade -p is set, + # otherwise doing so could interfere with embedded "single storage" + # (e.g SoC boot from SD card) setups, as well as other user + # created storage (like uvol) + if [ -n "$diff" ] && [ "${UPGRADE_OPT_SAVE_PARTITIONS}" = "0" ]; then + # Need to remove partitions before dd, otherwise the partitions + # that are added after will have minor numbers offset + partx -d - "/dev/$diskdev" + + get_image_dd "$1" of="/dev/$diskdev" bs=4096 conv=fsync + + # Separate removal and addtion is necessary; otherwise, partition 1 + # will be missing if it overlaps with the old partition 2 + partx -a - "/dev/$diskdev" + + return 0 + fi + + #iterate over each partition from the image and write it to the boot disk + while read part start size; do + if export_partdevice partdev $part; then + v "Writing image to /dev/$partdev..." + if [ "$part" = "1" ]; then + platform_do_upgrade_efi_system_partition \ + $1 $partdev $start $size || return 1 + else + v "Normal partition, doing DD" + get_image_dd "$1" of="/dev/$partdev" ibs=512 obs=1M skip="$start" \ + count="$size" conv=fsync + fi + else + v "Unable to find partition $part device, skipped." + fi + done < /tmp/partmap.image + + local parttype=ext4 + + if (blkid > /dev/null) && export_partdevice partdev 1; then + part_magic_fat "/dev/$partdev" && parttype=vfat + mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt + if export_partdevice partdev 2; then + THIS_PART_BLKID=$(blkid -o value -s PARTUUID "/dev/${partdev}") + v "Setting rootfs PARTUUID=${THIS_PART_BLKID}" + sed -i "s/\(PARTUUID=\)[a-f0-9-]\+/\1${THIS_PART_BLKID}/ig" \ + /mnt/efi/openwrt/grub.cfg + fi + umount /mnt + fi + # Provide time for the storage medium to flush before system reset + # (despite the sync/umount it appears NVMe etc. do it in the background) + sleep 5 +} diff --git a/target/linux/loongarch64/config-6.6 b/target/linux/loongarch64/config-6.6 new file mode 100644 index 00000000000000..596301f0f4ab12 --- /dev/null +++ b/target/linux/loongarch64/config-6.6 @@ -0,0 +1,806 @@ +# CONFIG_16KB_2LEVEL is not set +CONFIG_16KB_3LEVEL=y +# CONFIG_4KB_3LEVEL is not set +# CONFIG_4KB_4LEVEL is not set +CONFIG_64BIT=y +# CONFIG_64KB_2LEVEL is not set +# CONFIG_64KB_3LEVEL is not set +CONFIG_AC97_BUS=y +CONFIG_ACPI=y +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPU_FREQ_PSS=y +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_DEBUGGER is not set +# CONFIG_ACPI_DOCK is not set +# CONFIG_ACPI_EC_DEBUGFS is not set +CONFIG_ACPI_FAN=y +# CONFIG_ACPI_FFH is not set +CONFIG_ACPI_GENERIC_GSI=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_ACPI_MCFG=y +# CONFIG_ACPI_PCI_SLOT is not set +# CONFIG_ACPI_PFRUT is not set +CONFIG_ACPI_PPTT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_SLEEP=y +# CONFIG_ACPI_SPCR_TABLE is not set +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +CONFIG_ACPI_TABLE_UPGRADE=y +# CONFIG_ACPI_TAD is not set +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_VIDEO=y +CONFIG_APERTURE_HELPERS=y +CONFIG_ARCH_DISABLE_KASAN_INLINE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +# CONFIG_ARCH_IOREMAP is not set +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_MMAP_RND_BITS=12 +CONFIG_ARCH_MMAP_RND_BITS_MAX=18 +CONFIG_ARCH_MMAP_RND_BITS_MIN=12 +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_STRICT_ALIGN=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +# CONFIG_ARCH_WRITECOMBINE is not set +CONFIG_ASN1=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ATA=y +CONFIG_ATA_ACPI=y +CONFIG_ATA_FORCE=y +# CONFIG_ATA_SFF is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_GENERIC=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_KTZ8866 is not set +CONFIG_BLK_CGROUP=y +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEBUG_FS_ZONED=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y +CONFIG_BLK_RQ_ALLOC_TIME=y +CONFIG_BLK_SED_OPAL=y +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BUFFER_HEAD=y +CONFIG_BUG_ON_DATA_CORRUPTION=y +CONFIG_CACHESTAT_SYSCALL=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_CDROM=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUPS=y +# CONFIG_CGROUP_BPF is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_HUGETLB is not set +# CONFIG_CGROUP_NET_CLASSID is not set +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_SCHED=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHR_DEV_SG=y +CONFIG_CLZ_TAB=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMDLINE_BOOTLOADER=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_LOONGSON2 is not set +# CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_VC3 is not set +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPUSETS=y +CONFIG_CPU_HAS_FPU=y +CONFIG_CPU_HAS_LASX=y +CONFIG_CPU_HAS_LBT=y +CONFIG_CPU_HAS_LSX=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRC64=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC_T10DIF=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32_LOONGARCH is not set +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_DCB=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_MISC=y +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_DEVFREQ_GOV_PASSIVE is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +CONFIG_DEVFREQ_THERMAL=y +CONFIG_DEVMEM=y +CONFIG_DEVTMPFS=y +# CONFIG_DMAPOOL_TEST is not set +CONFIG_DMA_CMA=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMI=y +CONFIG_DMIID=y +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +CONFIG_DMI_SYSFS=y +CONFIG_DRM=y +# CONFIG_DRM_ACCEL is not set +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_LOONGSON=y +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_SAMSUNG_DSIM is not set +CONFIG_DRM_TTM=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EFI=y +CONFIG_EFIVAR_FS=m +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +CONFIG_EFI_ZBOOT=y +CONFIG_ELF_CORE=y +CONFIG_ENCRYPTED_KEYS=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FAILOVER=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CORE=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_DEVICE=y +CONFIG_FB_EFI=y +CONFIG_FB_IOMEM_HELPERS=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SIMPLE=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_TILEBLITTING=y +CONFIG_FHANDLE=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FIX_EARLYCON_MEM=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_FONTS=y +# CONFIG_FONT_10x18 is not set +# CONFIG_FONT_6x10 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_SUN8x16 is not set +CONFIG_FONT_SUPPORT=y +CONFIG_FONT_TER16x32=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FW_CACHE=y +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_ENTRY=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIO_ACPI=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +# CONFIG_GPIO_DS4520 is not set +# CONFIG_GPIO_FXL6408 is not set +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_LOONGSON_64BIT is not set +CONFIG_HAMRADIO=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HDMI=y +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_HID_GENERIC=y +CONFIG_HID_SUPPORT=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_LS2X is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INIT_STACK_ALL_ZERO=y +# CONFIG_INIT_STACK_NONE is not set +CONFIG_INPUT=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_LEDS=y +# CONFIG_INPUT_MISC is not set +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_IOMMUFD is not set +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_LOONGARCH_CPU=y +CONFIG_IRQ_POLL=y +CONFIG_IRQ_WORK=y +# CONFIG_ISCSI_IBFT is not set +CONFIG_ISO9660_FS=y +CONFIG_JBD2=y +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KCMP=y +CONFIG_KEYS=y +CONFIG_KSM=y +CONFIG_L1_CACHE_SHIFT=6 +# CONFIG_LEDS_AW200XX is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_GROUP_MULTICOLOR is not set +# CONFIG_LEDS_LM3697 is not set +# CONFIG_LEDS_PCA995X is not set +CONFIG_LEDS_TRIGGER_AUDIO=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEGACY_TIOCSTI=y +CONFIG_LIBFDT=y +CONFIG_LIST_HARDENED=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOONGARCH=y +CONFIG_LOONGARCH_PLATFORM_DEVICES=y +# CONFIG_LOONGSON2_GUTS is not set +# CONFIG_LOONGSON2_PM is not set +# CONFIG_LOONGSON2_THERMAL is not set +CONFIG_LOONGSON_EIOINTC=y +CONFIG_LOONGSON_HTVEC=y +CONFIG_LOONGSON_LAPTOP=y +CONFIG_LOONGSON_LIOINTC=y +CONFIG_LOONGSON_PCH_LPC=y +CONFIG_LOONGSON_PCH_MSI=y +CONFIG_LOONGSON_PCH_PIC=y +CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo,bpf" +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_LOONGSON64=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6 +CONFIG_MAGIC_SYSRQ_SERIAL=y +# CONFIG_MAX31827 is not set +CONFIG_MAX_SKB_FRAGS=17 +# CONFIG_MEMCG is not set +CONFIG_MEMFD_CREATE=y +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_MFD_CS42L43_I2C is not set +# CONFIG_MFD_INTEL_M10_BMC_SPI is not set +# CONFIG_MFD_MAX5970 is not set +# CONFIG_MFD_MAX77541 is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_SMPRO is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6594_I2C is not set +# CONFIG_MFD_TPS6594_SPI is not set +CONFIG_MIGRATION=y +CONFIG_MMU_GATHER_MERGE_VMAS=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +CONFIG_MPILIB=y +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EGRESS=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NR_CPUS=64 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SYSFS=y +CONFIG_NVME_CORE=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_VERBOSE_ERRORS=y +# CONFIG_N_HDLC is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OID_REGISTRY=y +# CONFIG_OVERLAY_FS_DEBUG is not set +CONFIG_PADATA=y +CONFIG_PAGE_EXTENSION=y +CONFIG_PAGE_POISONING=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SIZE_16KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PATA_TIMINGS=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DPC=y +# CONFIG_PCIE_EDR is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_ATS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +# CONFIG_PCI_DYNAMIC_OF_NODES is not set +CONFIG_PCI_ECAM=y +CONFIG_PCI_IOV=y +CONFIG_PCI_LABEL=y +CONFIG_PCI_LOONGSON=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_ARCH_FALLBACKS=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCPU_DEV_REFCNT=y +# CONFIG_PDS_CORE is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_3LEVEL=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PM=y +# CONFIG_PMIC_OPREGION is not set +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_PM_CLK=y +CONFIG_PM_DEBUG=y +CONFIG_PM_DEVFREQ=y +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_STD_PARTITION="" +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PNP=y +CONFIG_PNPACPI=y +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPS=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PREEMPT_VOLUNTARY_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_EVENTS=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_PTP_1588_CLOCK=y +# CONFIG_PTP_1588_CLOCK_MOCK is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +# CONFIG_RANDOM_KMALLOC_CACHES is not set +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_RELAY=y +CONFIG_RELOCATABLE=y +CONFIG_RESET_ATTACK_MITIGATION=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RSEQ=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_EFI is not set +CONFIG_RTC_DRV_LOONGSON=y +CONFIG_RTC_I2C_AND_SPI=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_HOST=y +# CONFIG_SATA_ZPODD is not set +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SCHED_CORE is not set +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHED_MM_CID=y +CONFIG_SCHED_SMT=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SENSORS_HS3001 is not set +# CONFIG_SENSORS_MC34VR500 is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +# CONFIG_SERIAL_8250_PCI1XXXX is not set +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PERICOM=y +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_SERPORT=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +# CONFIG_SLAB_DEPRECATED is not set +# CONFIG_SLUB_TINY is not set +CONFIG_SMP=y +CONFIG_SND=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_CTL_LED=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_HDA=y +# CONFIG_SND_HDA_CODEC_ANALOG is not set +# CONFIG_SND_HDA_CODEC_CA0110 is not set +# CONFIG_SND_HDA_CODEC_CA0132 is not set +# CONFIG_SND_HDA_CODEC_CIRRUS is not set +# CONFIG_SND_HDA_CODEC_CMEDIA is not set +CONFIG_SND_HDA_CODEC_CONEXANT=y +CONFIG_SND_HDA_CODEC_HDMI=y +# CONFIG_SND_HDA_CODEC_REALTEK is not set +# CONFIG_SND_HDA_CODEC_SI3054 is not set +# CONFIG_SND_HDA_CODEC_SIGMATEL is not set +# CONFIG_SND_HDA_CODEC_VIA is not set +CONFIG_SND_HDA_CORE=y +# CONFIG_SND_HDA_CTL_DEV_ID is not set +CONFIG_SND_HDA_GENERIC=y +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_HWDEP=y +# CONFIG_SND_HDA_INPUT_BEEP is not set +CONFIG_SND_HDA_INTEL=y +# CONFIG_SND_HDA_PATCH_LOADER is not set +# CONFIG_SND_HDA_RECONFIG is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set +# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set +# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set +CONFIG_SND_HWDEP=y +CONFIG_SND_INTEL_DSP_CONFIG=y +CONFIG_SND_INTEL_NHLT=y +CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_SEQ_DEVICE=y +CONFIG_SND_SEQ_DUMMY=y +CONFIG_SND_SEQ_MIDI=y +CONFIG_SND_SEQ_MIDI_EVENT=y +CONFIG_SND_SEQ_VIRMIDI=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_LOONGSON_CARD=y +CONFIG_SND_SOC_LOONGSON_I2S_PCI=y +CONFIG_SND_TIMER=y +CONFIG_SND_VIRMIDI=y +CONFIG_SND_VMASTER=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_DYNAMIC=y +CONFIG_SPI_LOONGSON_CORE=y +CONFIG_SPI_LOONGSON_PCI=y +CONFIG_SPI_LOONGSON_PLATFORM=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_PCI1XXXX is not set +# CONFIG_SPI_SN_F_OSPI is not set +CONFIG_SPI_SPIDEV=y +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKTRACE=y +CONFIG_STRICT_DEVMEM=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_SYNC_FILE=y +CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y +CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASK_XACCT=y +# CONFIG_TEST_DHRY is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TMPFS_INODE64=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_QUOTA is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UCS2_STRING=y +# CONFIG_UEVENT_HELPER is not set +# CONFIG_UNWINDER_GUESS is not set +CONFIG_UNWINDER_PROLOGUE=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_UAS=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USERFAULTFD=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +# CONFIG_VCAP is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VGA_CONSOLE=y +CONFIG_VIDEO_CMDLINE=y +CONFIG_VIDEO_NOMODESET=y +CONFIG_VIRTIO_VSOCKETS_COMMON=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VSOCKETS=y +CONFIG_VSOCKETS_LOOPBACK=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_WPCM450_SOC is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set +CONFIG_XARRAY_MULTI=y +CONFIG_XPS=y +CONFIG_XXHASH=y +# CONFIG_ZONEFS_FS is not set +CONFIG_ZONE_DMA32=y diff --git a/target/linux/loongarch64/generic/target.mk b/target/linux/loongarch64/generic/target.mk new file mode 100644 index 00000000000000..f5cb1fb19b943f --- /dev/null +++ b/target/linux/loongarch64/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic diff --git a/target/linux/loongarch64/image/Makefile b/target/linux/loongarch64/image/Makefile new file mode 100644 index 00000000000000..7000356292c289 --- /dev/null +++ b/target/linux/loongarch64/image/Makefile @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Copyright (C) 2024 Weijie Gao + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +GRUB2_VARIANT = +GRUB_TERMINALS = +GRUB_SERIAL_CONFIG = +GRUB_TERMINAL_CONFIG = +GRUB_CONSOLE_CMDLINE = + +ifneq ($(CONFIG_GRUB_CONSOLE),) + GRUB_CONSOLE_CMDLINE += console=tty0 + GRUB_TERMINALS += console +endif + +GRUB_SERIAL:=$(call qstrip,$(CONFIG_TARGET_SERIAL)) + +GRUB_CONSOLE_CMDLINE += console=$(GRUB_SERIAL),$(CONFIG_GRUB_BAUDRATE)n8$(if $(CONFIG_GRUB_FLOWCONTROL),r,) +GRUB_SERIAL_CONFIG := serial --unit=0 --speed=$(CONFIG_GRUB_BAUDRATE) --word=8 --parity=no --stop=1 --rtscts=$(if $(CONFIG_GRUB_FLOWCONTROL),on,off) +GRUB_TERMINALS += serial + +GRUB_TERMINAL_CONFIG := terminal_input $(GRUB_TERMINALS); terminal_output $(GRUB_TERMINALS) + +ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME)) +ROOTPART:=$(if $(ROOTPART),$(ROOTPART),PARTUUID=$(IMG_PART_SIGNATURE)-02) +GPT_ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME)) +GPT_ROOTPART:=$(if $(GPT_ROOTPART),$(GPT_ROOTPART),PARTUUID=$(shell echo $(IMG_PART_DISKGUID) | sed 's/00$$/02/')) + +GRUB_TIMEOUT:=$(call qstrip,$(CONFIG_GRUB_TIMEOUT)) +GRUB_TITLE:=$(call qstrip,$(CONFIG_GRUB_TITLE)) + +BOOTOPTS:=$(call qstrip,$(CONFIG_GRUB_BOOTOPTS)) + +define Build/combined + $(INSTALL_DIR) $@.boot/ + $(CP) $(KDIR)/$(KERNEL_NAME) $@.boot/efi/openwrt/ + $(INSTALL_DIR) $@.boot/efi/boot + $(CP) $(STAGING_DIR_IMAGE)/grub2/bootloongarch64.efi $@.boot/efi/boot/ + KERNELPARTTYPE=ef FAT_TYPE="32" PADDING="1" SIGNATURE="$(IMG_PART_SIGNATURE)" \ + GUID="$(IMG_PART_DISKGUID)" $(SCRIPT_DIR)/gen_image_generic.sh \ + $@ \ + $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \ + $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \ + 256 +endef + +define Build/grub-config + rm -fR $@.boot + $(INSTALL_DIR) $@.boot/efi/openwrt/ + sed \ + -e 's#@SERIAL_CONFIG@#$(strip $(GRUB_SERIAL_CONFIG))#g' \ + -e 's#@TERMINAL_CONFIG@#$(strip $(GRUB_TERMINAL_CONFIG))#g' \ + -e 's#@ROOTPART@#root=$(ROOTPART) rootwait#g' \ + -e 's#@GPT_ROOTPART@#root=$(GPT_ROOTPART) rootwait#g' \ + -e 's#@CMDLINE@#$(BOOTOPTS) $(GRUB_CONSOLE_CMDLINE)#g' \ + -e 's#@TIMEOUT@#$(GRUB_TIMEOUT)#g' \ + -e 's#@TITLE@#$(GRUB_TITLE)#g' \ + -e 's#@KERNEL_NAME@#$(KERNEL_NAME)#g' \ + ./grub-$(1).cfg > $@.boot/efi/openwrt/grub.cfg +endef + +define Device/Default + KERNEL_INSTALL := 1 + ARTIFACTS := $$(ARTIFACTS-y) + SUPPORTED_DEVICES := +endef + +define Device/generic + DEVICE_VENDOR := Generic + DEVICE_MODEL := LoongArch64 + DEVICE_PACKAGES += kmod-r8169 kmod-drm-amdgpu + KERNEL := kernel-bin + KERNEL_NAME := vmlinuz.efi + IMAGE/rootfs.img := append-rootfs | pad-to $(ROOTFS_PARTSIZE) + IMAGE/rootfs.img.gz := append-rootfs | pad-to $(ROOTFS_PARTSIZE) | gzip + IMAGE/combined-efi.img := grub-config efi | combined | append-metadata + IMAGE/combined-efi.img.gz := grub-config efi | combined | gzip | append-metadata + ifeq ($(CONFIG_TARGET_IMAGES_GZIP),y) + IMAGES-y := rootfs.img.gz + IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img.gz + else + IMAGES-y := rootfs.img + IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img + endif + IMAGES := $$(IMAGES-y) +endef +TARGET_DEVICES += generic + +$(eval $(call BuildImage)) diff --git a/target/linux/loongarch64/image/grub-efi.cfg b/target/linux/loongarch64/image/grub-efi.cfg new file mode 100644 index 00000000000000..fd329e41e0ff2d --- /dev/null +++ b/target/linux/loongarch64/image/grub-efi.cfg @@ -0,0 +1,14 @@ +@SERIAL_CONFIG@ +@TERMINAL_CONFIG@ + +set default="0" +set timeout="@TIMEOUT@" + +menuentry "@TITLE@" { + search --set=root --label kernel + linux /efi/openwrt/@KERNEL_NAME@ @GPT_ROOTPART@ @CMDLINE@ noinitrd +} +menuentry "@TITLE@ (failsafe)" { + search --set=root --label kernel + linux /efi/openwrt/@KERNEL_NAME@ failsafe=true @GPT_ROOTPART@ @CMDLINE@ noinitrd +} diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index 288fb537a7b40d..f667081253d3fd 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -8,8 +8,7 @@ BOARDNAME:=MediaTek Ralink ARM SUBTARGETS:=mt7622 mt7623 mt7629 filogic FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb -KERNEL_PATCHVER:=6.1 -KERNEL_TESTING_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ diff --git a/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts b/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts index b62c2f421516ad..93a5bb86f3bb4c 100644 --- a/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts +++ b/target/linux/mediatek/dts/mt7986a-jdcloud-re-cp-03.dts @@ -23,7 +23,9 @@ }; chosen { + bootargs-override = "root=/dev/fit0 rootwait"; stdout-path = "serial0:115200n8"; + rootdisk = <&emmc_rootdisk>; }; memory@40000000 { @@ -157,6 +159,20 @@ vmmc-supply = <®_3p3v>; vqmmc-supply = <®_1p8v>; status = "okay"; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + emmc_rootdisk: block-partition-production { + partname = "production"; + }; + }; + }; + }; }; &pio { diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso deleted file mode 100644 index 4d0e5c04067b39..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; - - fragment@0 { - target = <&gmac1>; - __overlay__ { - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - }; - }; - - fragment@1 { - target = <&mdio_bus>; - __overlay__ { - reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; - reset-delay-us = <600>; - reset-post-delay-us = <20000>; - - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso deleted file mode 100644 index 710e6c0bcfbee2..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; - - fragment@0 { - target = <&sw_p5>; - __overlay__ { - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - status = "okay"; - }; - }; - - fragment@1 { - target = <&mdio_bus>; - __overlay__ { - reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>; - reset-delay-us = <600>; - reset-post-delay-us = <20000>; - - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso deleted file mode 100644 index 5b51dfd671c228..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; - - fragment@0 { - target = <&spi0>; - __overlay__ { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - spi_nand: spi_nand@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <10000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - }; - - partition@380000 { - label = "FIP"; - reg = <0x380000 0x0200000>; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x4000000>; - }; - }; - }; - }; - }; - - fragment@1 { - target = <&wifi>; - __overlay__ { - mediatek,mtd-eeprom = <&factory 0x0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts deleted file mode 100644 index b2bb6929562ebd..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981-rfb.dts +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7981.dtsi" - -/ { - model = "MediaTek MT7981 RFB"; - compatible = "mediatek,mt7981-rfb", "mediatek,mt7981"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x20000000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - linux,code = ; - gpios = <&pio 1 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&int_gbe_phy>; - }; -}; - -&mdio_bus { - switch: switch@1f { - compatible = "mediatek,mt7531"; - reg = <31>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&crypto { - status = "okay"; -}; - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; - drive-strength = ; - bias-pull-up = ; - }; - conf-pd { - pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; - drive-strength = ; - bias-pull-down = ; - }; - }; - -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - cs-gpios = <0>, <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - sw_p5: port@5 { - reg = <5>; - label = "lan5"; - status = "disabled"; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&xhci { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi deleted file mode 100644 index 54cfd0b4b9f745..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ /dev/null @@ -1,822 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Sam.Shih - * Author: Jianhui Zhao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7981"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x0>; - device_type = "cpu"; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a53"; - reg = <0x1>; - device_type = "cpu"; - enable-method = "psci"; - }; - }; - - ice: ice_debug { - compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug"; - clocks = <&infracfg CLK_INFRA_DBG_CK>; - clock-names = "ice_dbg"; - }; - - clk40m: oscillator-40m { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - clock-output-names = "clkxtal"; - #clock-cells = <0>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */ - cooling-levels = <0 63 95 127 159 191 223 255>; - #cooling-cells = <2>; - status = "disabled"; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - /* 64 KiB reserved for ramoops/pstore */ - ramoops@42ff0000 { - compatible = "ramoops"; - reg = <0 0x42ff0000 0 0x10000>; - record-size = <0x1000>; - }; - - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - - wmcpu_emi: wmcpu-reserved@47c80000 { - reg = <0 0x47c80000 0 0x100000>; - no-map; - }; - - wo_emi0: wo-emi@47d80000 { - reg = <0 0x47d80000 0 0x40000>; - no-map; - }; - - wo_data: wo-data@47dc0000 { - reg = <0 0x47dc0000 0 0x240000>; - no-map; - }; - }; - - soc { - compatible = "simple-bus"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>; /* GICR */ - interrupt-parent = <&gic>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - consys: consys@10000000 { - compatible = "mediatek,mt7981-consys"; - reg = <0 0x10000000 0 0x8600000>; - memory-region = <&wmcpu_emi>; - }; - - infracfg: clock-controller@10001000 { - compatible = "mediatek,mt7981-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - wed_pcie: wed_pcie@10003000 { - compatible = "mediatek,wed_pcie"; - reg = <0 0x10003000 0 0x10>; - }; - - topckgen: clock-controller@1001b000 { - compatible = "mediatek,mt7981-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - status = "disabled"; - }; - - apmixedsys: clock-controller@1001e000 { - compatible = "mediatek,mt7981-apmixedsys", "syscon"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7981-pwm"; - reg = <0 0x10048000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; - #pwm-cells = <2>; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; - reg = <0 0x10060000 0 0x1000>; - mediatek,pnswap; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x10320000 0 0x40000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <&topckgen CLK_TOP_EIP97B>; - clock-names = "top_eip97_ck"; - assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART0_SEL>, - <&infracfg CLK_INFRA_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART1_SEL>, - <&infracfg CLK_INFRA_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART2_SEL>, - <&infracfg CLK_INFRA_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - snand: snfi@11005000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; - reg-names = "nfi", "ecc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, - <&infracfg CLK_INFRA_NFI1_CK>, - <&infracfg CLK_INFRA_NFI_HCK_CK>; - clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, - <&topckgen CLK_TOP_CB_M_D8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>, - <&infracfg CLK_INFRA_I2C_MCK_CK>, - <&infracfg CLK_INFRA_I2C_PCK_CK>; - clock-names = "main", "dma", "arb", "pmic"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI2_CK>, - <&infracfg CLK_INFRA_SPI2_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@1100b000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - reg = <0 0x1100b000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - thermal: thermal@1100c800 { - compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "therm", "auxadc"; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - #thermal-sensor-cells = <1>; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - }; - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7981-auxadc", - "mediatek,mt7986-auxadc", - "mediatek,mt7622-auxadc"; - reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "main", "32k"; - #io-channel-cells = <1>; - }; - - xhci: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&infracfg CLK_INFRA_IUSB_CK>, - <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>; - clock-names = "sys_ck", - "ref_ck", - "mcu_ck", - "dma_ck", - "xhci_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - vusb33-supply = <®_3p3v>; - status = "disabled"; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, - <&infracfg CLK_INFRA_AUD_26M_CK>, - <&infracfg CLK_INFRA_AUD_L_CK>, - <&infracfg CLK_INFRA_AUD_AUD_CK>, - <&infracfg CLK_INFRA_AUD_EG2_CK>, - <&topckgen CLK_TOP_AUD_SEL>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>, - <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC_CK>, - <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_CB_NET2_D2>; - clock-names = "source", "hclk", "axi_cg", "ahb_cg"; - status = "disabled"; - }; - - pcie: pcie@11280000 { - compatible = "mediatek,mt7981-pcie", - "mediatek,mt7986-pcie"; - reg = <0 0x11280000 0 0x4000>; - reg-names = "pcie-mac"; - ranges = <0x82000000 0 0x20000000 - 0x0 0x20000000 0 0x10000000>; - device_type = "pci"; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, - <&infracfg CLK_INFRA_IPCIER_CK>, - <&infracfg CLK_INFRA_IPCIEB_CK>; - phys = <&u3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <0>; - }; - }; - - pio: pinctrl@11d00000 { - compatible = "mediatek,mt7981-pinctrl"; - reg = <0 0x11d00000 0 0x1000>, - <0 0x11c00000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rm", - "iocfg_rb", "iocfg_lb", "iocfg_bl", - "iocfg_tm", "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 56>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio_pins: mdc-mdio-pins { - mux { - function = "eth"; - groups = "smi_mdc_mdio"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - wifi_dbdc_pins: wifi-dbdc-pins { - mux { - function = "eth"; - groups = "wf0_mode1"; - }; - - conf { - pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", - "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", - "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", - "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", - "WF_CBA_RESETB", "WF_DIG_RESETB"; - drive-strength = <4>; - }; - }; - - gbe_led0_pins: gbe-led0-pins { - mux { - function = "led"; - groups = "gbe_led0"; - }; - }; - - gbe_led1_pins: gbe-led1-pins { - mux { - function = "led"; - groups = "gbe_led1"; - }; - }; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7981-topmisc", "syscon"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - }; - - usb_phy: usb-phy@11e10000 { - compatible = "mediatek,mt7981", - "mediatek,generic-tphy-v2"; - ranges = <0 0 0x11e10000 0x1700>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x900>; - clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - status = "okay"; - }; - }; - - efuse: efuse@11f20000 { - compatible = "mediatek,mt7981-efuse", - "mediatek,efuse"; - reg = <0 0x11f20000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - - thermal_calibration: thermal-calib@274 { - reg = <0x274 0xc>; - }; - - phy_calibration: phy-calib@8dc { - reg = <0x8dc 0x10>; - }; - - comb_rx_imp_p0: usb3-rx-imp@8c8 { - reg = <0x8c8 1>; - bits = <0 5>; - }; - - comb_tx_imp_p0: usb3-tx-imp@8c8 { - reg = <0x8c8 2>; - bits = <5 5>; - }; - - comb_intr_p0: usb3-intr@8c9 { - reg = <0x8c9 1>; - bits = <2 6>; - }; - }; - - ethsys: clock-controller@15000000 { - compatible = "mediatek,mt7981-ethsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wed: wed@15010000 { - compatible = "mediatek,mt7981-wed", - "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_data>; - memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7981-eth"; - reg = <0 0x15100000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETH_FE_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_WOCPU0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys0 CLK_SGM0_CK0_EN>, - <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <&sgmiisys1 CLK_SGM1_CK1_EN>, - <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, - <&topckgen CLK_TOP_SGM_REG>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>; - clock-names = "fe", "gp2", "gp1", "wocpu0", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "netsys0", "netsys1"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_SGM_325M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, - <&topckgen CLK_TOP_CB_SGM_325M>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,infracfg = <&topmisc>; - mediatek,wed = <&wed>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - phy-mode = "gmii"; - phy-is-integrated; - nvmem-cells = <&phy_calibration>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy_led0: int-gbe-phy-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - int_gbe_phy_led1: int-gbe-phy-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - wdma: wdma@15104800 { - compatible = "mediatek,wed-wdma"; - reg = <0 0x15104800 0 0x400>, - <0 0x15104c00 0 0x400>; - }; - - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; - }; - - ap2woccif: ap2woccif@151a5000 { - compatible = "mediatek,ap2woccif"; - reg = <0 0x151a5000 0 0x1000>, - <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = , - ; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wo_ilm0: syscon@151e0000 { - compatible = "mediatek,mt7986-wo-ilm", "syscon"; - reg = <0 0x151e0000 0 0x8000>; - }; - - wo_dlm0: syscon@151e8000 { - compatible = "mediatek,mt7986-wo-dlm", "syscon"; - reg = <0 0x151e8000 0 0x2000>; - }; - - wifi: wifi@18000000 { - compatible = "mediatek,mt7981-wmac"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; - pinctrl-0 = <&wifi_dbdc_pins>; - pinctrl-names = "dbdc"; - clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; - interrupts = , - , - , - ; - memory-region = <&wmcpu_emi>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - - trips { - cpu_trip_active_highest: active-highest { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_high: active-high { - temperature = <60000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <45000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_lowest: active-lowest { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-highest { - /* active: set fan to cooling level 7 */ - cooling-device = <&fan 7 7>; - trip = <&cpu_trip_active_highest>; - }; - - cpu-active-high { - /* active: set fan to cooling level 5 */ - cooling-device = <&fan 5 5>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-med { - /* active: set fan to cooling level 3 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_med>; - }; - - cpu-active-low { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_low>; - }; - - cpu-active-lowest { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_lowest>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - clock-frequency = <13000000>; - interrupts = , - , - , - ; - - }; - - trng { - compatible = "mediatek,mt7981-rng"; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts deleted file mode 100644 index ce007099d2ba32..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snand"; -}; - -&spi0 { - status = "okay"; - - spi_nand: spi_nand@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <10000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - }; - partition@380000 { - label = "FIP"; - reg = <0x380000 0x0200000>; - }; - partition@580000 { - label = "ubi"; - reg = <0x580000 0x4000000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts deleted file mode 100644 index ea148315f05534..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snor"; -}; - -&spi0 { - status = "okay"; - - spi_nor: spi_nor@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@00000 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - factory: partition@50000 { - label = "Factory"; - reg = <0x50000 0x00B0000>; - }; - partition@100000 { - label = "FIP"; - reg = <0x100000 0x0080000>; - }; - partition@180000 { - label = "firmware"; - reg = <0x180000 0xE00000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi deleted file mode 100644 index 26d560bd4bcb11..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7986a.dtsi" - -/ { - model = "MediaTek MT7986a RFB"; - compatible = "mediatek,mt7986a-rfb"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - -&mdio { - phy5: phy@5 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - - reset-gpios = <&pio 6 1>; - reset-deassert-us = <20000>; - }; - - phy6: phy@6 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - - switch: switch@1f { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 0>; - }; -}; - -&crypto { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; - }; - }; - - spic_pins_g2: spic-pins-29-to-32 { - mux { - function = "spi"; - groups = "spi1_2"; - }; - }; - - spi_flash_pins: spi-flash-pins-33-to-38 { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - conf-pd { - pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; - drive-strength = <8>; - mediatek,pull-down-adv = <0>; /* bias-disable */ - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf_dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - cs-gpios = <0>, <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic_pins_g2>; - status = "okay"; - - proslic_spi: proslic_spi@0 { - compatible = "silabs,proslic_spi"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-cpha = <1>; - spi-cpol = <1>; - channel_count = <1>; - debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ - reset_gpio = <&pio 7 0>; - ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ - }; -}; - -&gmac1 { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy-handle = <&phy6>; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "lan6"; - - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso deleted file mode 100644 index 4945185d699e85..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_emmc_51>; - pinctrl-1 = <&mmc0_pins_emmc_51>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x12814>; - vqmmc-supply = <®_1p8v>; - vmmc-supply = <®_3p3v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - card@0 { - compatible = "mmc-card"; - reg = <0>; - - block { - compatible = "block-device"; - partitions { - block-partition-env { - partname = "ubootenv"; - nvmem-layout { - compatible = "u-boot,env-layout"; - }; - }; - emmc_rootfs: block-partition-production { - partname = "production"; - }; - }; - }; - }; - }; - }; - - fragment@2 { - target-path = "/chosen"; - __overlay__ { - rootdisk-emmc = <&emmc_rootfs>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso deleted file mode 100644 index 39910b8cfee1a9..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-rtc.dtso +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 - * Author: Daniel Golle - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - - fragment@0 { - target = <&pcf8563>; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso deleted file mode 100644 index 1f5e1491a471e9..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - - fragment@1 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_sdcard>; - pinctrl-1 = <&mmc0_pins_sdcard>; - cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - no-mmc; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - card@0 { - compatible = "mmc-card"; - reg = <0>; - - block { - compatible = "block-device"; - partitions { - block-partition-env { - partname = "ubootenv"; - nvmem-layout { - compatible = "u-boot,env-layout"; - }; - }; - sd_rootfs: block-partition-production { - partname = "production"; - }; - }; - }; - }; - }; - }; - - fragment@2 { - target-path = "/chosen"; - __overlay__ { - rootdisk-sd = <&sd_rootfs>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso deleted file mode 100644 index 8a029b149ff7cd..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; - - fragment@0 { - target-path = "/"; - __overlay__ { - wifi_12v: regulator-wifi-12v { - compatible = "regulator-fixed"; - regulator-name = "wifi"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&pio 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - }; - }; - - fragment@1 { - target = <&i2c_wifi>; - __overlay__ { - // 5G WIFI MAC Address EEPROM - wifi_eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - address-bits = <8>; - page-size = <8>; - size = <256>; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_5g: macaddr@0 { - reg = <0x0 0x6>; - }; - }; - }; - - // 6G WIFI MAC Address EEPROM - wifi_eeprom@52 { - compatible = "atmel,24c02"; - reg = <0x52>; - address-bits = <8>; - page-size = <8>; - size = <256>; - - nvmem-layout { - compatible = "fixed-layout"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_6g: macaddr@0 { - reg = <0x0 0x6>; - }; - }; - }; - }; - }; - - fragment@2 { - target = <&pcie0>; - __overlay__ { - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - nvmem-cell-names = "mac-address"; - nvmem-cells = <&macaddr_5g>; - }; - }; - }; - }; - - fragment@3 { - target = <&pcie1>; - __overlay__ { - pcie@0,0 { - reg = <0x0000 0 0 0 0>; - - wifi@0,0 { - compatible = "mediatek,mt76"; - reg = <0x0000 0 0 0 0>; - nvmem-cell-names = "mac-address"; - nvmem-cells = <&macaddr_6g>; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts deleted file mode 100644 index 74f480e0a12622..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ /dev/null @@ -1,409 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a.dtsi" -#include -#include -#include -#include - -/ { - model = "Bananapi BPI-R4"; - compatible = "bananapi,bpi-r4", - "mediatek,mt7988a"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - serial0 = &uart0; - led-boot = &led_green; - led-failsafe = &led_green; - led-running = &led_green; - led-upgrade = &led_green; - }; - - chosen { - stdout-path = &uart0; - bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait"; - rootdisk-spim-nand = <&ubi_rootfs>; - }; - - memory { - reg = <0x00 0x40000000 0x00 0x10000000>; - }; - - /* SFP1 cage (WAN) */ - sfp1: sfp1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; - rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <3000>; - }; - - /* SFP2 cage (LAN) */ - sfp2: sfp2 { - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp2>; - los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; - rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; - maximum-power-milliwatt = <3000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - wps { - label = "WPS"; - linux,code = ; - gpios = <&pio 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - led_green: led-green { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&pio 79 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led_blue: led-blue { - function = LED_FUNCTION_WPS; - color = ; - gpios = <&pio 63 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -ð { - status = "okay"; -}; - -&gmac0 { - status = "okay"; -}; - -&gmac1 { - sfp = <&sfp2>; - managed = "in-band-status"; - phy-mode = "usxgmii"; - status = "okay"; -}; - -&gmac2 { - sfp = <&sfp1>; - managed = "in-band-status"; - phy-mode = "usxgmii"; - status = "okay"; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_port0 { - label = "wan"; -}; - -&gsw_phy0_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_phy1_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_phy2_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_phy3_led0 { - status = "okay"; - color = ; -}; - -&cpu0 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu1 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu2 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu3 { - proc-supply = <&rt5190_buck3>; -}; - -&cci { - proc-supply = <&rt5190_buck3>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - rt5190a_64: rt5190a@64 { - compatible = "richtek,rt5190a"; - reg = <0x64>; - vin2-supply = <&rt5190_buck1>; - vin3-supply = <&rt5190_buck1>; - vin4-supply = <&rt5190_buck1>; - - regulators { - rt5190_buck1: buck1 { - regulator-name = "rt5190a-buck1"; - regulator-min-microvolt = <5090000>; - regulator-max-microvolt = <5090000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - buck2 { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - rt5190_buck3: buck3 { - regulator-name = "vproc"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - buck4 { - regulator-name = "rt5190a-buck4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - ldo { - regulator-name = "rt5190a-ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_1_pins>; - status = "okay"; - - pca9545: i2c-switch@70 { - reg = <0x70>; - compatible = "nxp,pca9545"; - reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - - i2c_rtc: i2c@0 { //eeprom,rtc,ngff - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - address-bits = <8>; - page-size = <8>; - size = <256>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - address-bits = <8>; - page-size = <8>; - size = <256>; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "disabled"; - }; - }; - - i2c_sfp1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_sfp2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_wifi: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -/* mPCIe SIM2 */ -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; -}; - -/* mPCIe SIM3 */ -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - status = "okay"; -}; - -/* M.2 key-B SIM1 */ -&pcie2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - status = "okay"; -}; - -/* M.2 key-M SSD */ -&pcie3 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - status = "okay"; -}; - -&ssusb1 { - status = "okay"; -}; - -&tphy { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - }; -}; - -&spi_nand { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x200000>; - read-only; - }; - - partition@200000 { - label = "ubi"; - reg = <0x200000 0x7e00000>; - compatible = "linux,ubi"; - - volumes { - ubi-volume-ubootenv { - volname = "ubootenv"; - nvmem-layout { - compatible = "u-boot,env-redundant-bool-layout"; - }; - }; - - ubi-volume-ubootenv2 { - volname = "ubootenv2"; - nvmem-layout { - compatible = "u-boot,env-redundant-bool-layout"; - }; - }; - - ubi_rootfs: ubi-volume-fit { - volname = "fit"; - }; - }; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_2_lite_pins>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_3_pins>; -}; - -&watchdog { - status = "okay"; -}; - -&xphy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso deleted file mode 100644 index 3f8ac2ae382ba0..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mmc0>; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_emmc_51>; - pinctrl-1 = <&mmc0_pins_emmc_51>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x12814>; - vqmmc-supply = <®_1p8v>; - vmmc-supply = <®_3p3v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso deleted file mode 100644 index d21a61ad19fef3..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - }; - }; - - fragment@1 { - target = <&gmac1>; - __overlay__ { - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso deleted file mode 100644 index 86ab7566dc298e..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&gmac1>; - __overlay__ { - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&int_2p5g_phy>; - status = "okay"; - }; - }; - - fragment@1 { - target = <&int_2p5g_phy>; - __overlay__ { - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso deleted file mode 100644 index 34a23bbd7eb09e..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; - - fragment@1 { - target = <&gmac1>; - __overlay__ { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy = <&phy13>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso deleted file mode 100644 index ba40a119cbdfdc..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&i2c2>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_0_pins>; - status = "okay"; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - sfp_esp1: sfp@1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c2>; - mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; - los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - }; - }; - - fragment@2 { - target = <&gmac1>; - __overlay__ { - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_esp1>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso deleted file mode 100644 index 140391fc45a8f4..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - }; - }; - - fragment@1 { - target = <&gmac2>; - __overlay__ { - phy-mode = "usxgmii"; - phy-connection-type = "usxgmii"; - phy = <&phy8>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso deleted file mode 100644 index 19e0b2799fc848..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&mdio_bus>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - }; - }; - - fragment@1 { - target = <&gmac2>; - __overlay__ { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy = <&phy5>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso deleted file mode 100644 index b9aabd2726e2a2..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&i2c1>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_sfp_pins>; - status = "okay"; - }; - }; - - fragment@1 { - target-path = "/"; - __overlay__ { - sfp_esp0: sfp@0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>; - los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - }; - }; - - fragment@2 { - target = <&gmac2>; - __overlay__ { - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_esp0>; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso deleted file mode 100644 index 04472cc12dc816..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Frank Wunderlich - */ - -/dts-v1/; -/plugin/; - -#include - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@1 { - target-path = <&mmc0>; - __overlay__ { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_sdcard>; - pinctrl-1 = <&mmc0_pins_sdcard>; - cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>; - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - no-mmc; - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso deleted file mode 100644 index 86b0042f647768..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&snand>; - __overlay__ { - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; - }; - }; - }; - - fragment@1 { - target = <&bch>; - __overlay__ { - status = "okay"; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso deleted file mode 100644 index a9eca00d4416cb..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&spi0>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso deleted file mode 100644 index 33bd57b3fb63b3..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -/plugin/; - -/ { - compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a"; - - fragment@0 { - target = <&spi2>; - __overlay__ { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_flash_pins>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cal-enable; - spi-cal-mode = "read-data"; - spi-cal-datalen = <7>; - spi-cal-data = /bits/ 8 < - 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */ - spi-cal-addrlen = <1>; - spi-cal-addr = /bits/ 32 <0x0>; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - - partition@00000 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - partition@50000 { - label = "Factory"; - reg = <0x50000 0x0200000>; - }; - partition@250000 { - label = "FIP"; - reg = <0x250000 0x0080000>; - }; - partition@2D0000 { - label = "firmware"; - reg = <0x2D0000 0x1D30000>; - }; - }; - }; - }; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts deleted file mode 100644 index 5012e7a49899e8..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a.dtsi" -#include -#include -#include - -/ { - model = "MediaTek MT7988A Reference Board"; - compatible = "mediatek,mt7988a-rfb", - "mediatek,mt7988a"; - - chosen { - bootargs = "console=ttyS0,115200n1 loglevel=8 \ - earlycon=uart8250,mmio32,0x11000000 \ - pci=pcie_bus_perf"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -ð { - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; -}; - -&gmac0 { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu1 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu2 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu3 { - proc-supply = <&rt5190_buck3>; -}; - -&cci { - proc-supply = <&rt5190_buck3>; -}; - -ð { - status = "okay"; -}; - -&switch { - status = "okay"; -}; - -&gsw_phy0 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; -}; - -&gsw_phy0_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy1 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; -}; - -&gsw_phy1_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy2 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; -}; - -&gsw_phy2_led0 { - status = "okay"; - color = ; -}; - -&gsw_phy3 { - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; -}; - -&gsw_phy3_led0 { - status = "okay"; - color = ; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - rt5190a_64: rt5190a@64 { - compatible = "richtek,rt5190a"; - reg = <0x64>; - /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ - vin2-supply = <&rt5190_buck1>; - vin3-supply = <&rt5190_buck1>; - vin4-supply = <&rt5190_buck1>; - - regulators { - rt5190_buck1: buck1 { - regulator-name = "rt5190a-buck1"; - regulator-min-microvolt = <5090000>; - regulator-max-microvolt = <5090000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - buck2 { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - rt5190_buck3: buck3 { - regulator-name = "vproc"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - buck4 { - regulator-name = "rt5190a-buck4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - ldo { - regulator-name = "rt5190a-ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "disabled"; -}; - -&pcie3 { - status = "okay"; -}; - -&ssusb0 { - status = "okay"; -}; - -&ssusb1 { - status = "okay"; -}; - -&tphy { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&xphy { - status = "okay"; -}; diff --git a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi deleted file mode 100644 index caad6e5577e7f1..00000000000000 --- a/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ /dev/null @@ -1,1573 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Sam.Shih - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* TOPRGU resets */ -#define MT7988_TOPRGU_SGMII0_GRST 1 -#define MT7988_TOPRGU_SGMII1_GRST 2 -#define MT7988_TOPRGU_XFI0_GRST 12 -#define MT7988_TOPRGU_XFI1_GRST 13 -#define MT7988_TOPRGU_XFI_PEXTP0_GRST 14 -#define MT7988_TOPRGU_XFI_PEXTP1_GRST 15 -#define MT7988_TOPRGU_XFI_PLL_GRST 16 - -/ { - compatible = "mediatek,mt7988a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cci: cci { - compatible = "mediatek,mt7988-cci", - "mediatek,mt8183-cci"; - clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cci", "intermediate"; - operating-points-v2 = <&cci_opp>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a73"; - reg = <0x0>; - device_type = "cpu"; - enable-method = "psci"; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a73"; - reg = <0x1>; - device_type = "cpu"; - enable-method = "psci"; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a73"; - reg = <0x2>; - device_type = "cpu"; - enable-method = "psci"; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a73"; - reg = <0x3>; - device_type = "cpu"; - enable-method = "psci"; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <850000>; - }; - - opp01 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <850000>; - }; - - opp02 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <850000>; - }; - - opp03 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - }; - }; - - cci_opp: opp_table_cci { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <850000>; - }; - - opp01 { - opp-hz = /bits/ 64 <660000000>; - opp-microvolt = <850000>; - }; - - opp02 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <850000>; - }; - - opp03 { - opp-hz = /bits/ 64 <1080000000>; - opp-microvolt = <900000>; - }; - }; - - clk40m: oscillator@0 { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ - cooling-levels = <0 128 255>; - #cooling-cells = <2>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a73-pmu"; - interrupt-parent = <&gic>; - interrupt = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x50000>; - no-map; - }; - }; - - soc { - compatible = "simple-bus"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - interrupt-parent = <&gic>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - phyfw: phy-firmware@f000000 { - compatible = "mediatek,2p5gphy-fw"; - reg = <0 0x0f100000 0 0x20000>, - <0 0x0f0f0018 0 0x20>; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7988-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - topckgen: topckgen@1001b000 { - compatible = "mediatek,mt7988-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7988-wdt", - "mediatek,mt6589-wdt", - "syscon"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - }; - - apmixedsys: apmixedsys@1001e000 { - compatible = "mediatek,mt7988-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@1001f000 { - compatible = "mediatek,mt7988-pinctrl", "syscon"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d00000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio_base", "iocfg_tr_base", - "iocfg_br_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_tl_base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 84>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio0_pins: mdio0-pins { - mux { - function = "eth"; - groups = "mdc_mdio0"; - }; - - conf { - groups = "mdc_mdio0"; - drive-strength = ; - }; - }; - - i2c0_pins: i2c0-pins-g0 { - mux { - function = "i2c"; - groups = "i2c0_1"; - }; - }; - - i2c1_pins: i2c1-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c1_sfp_pins: i2c1-sfp-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_sfp"; - }; - }; - - i2c2_pins: i2c2-pins { - mux { - function = "i2c"; - groups = "i2c2"; - }; - }; - - i2c2_0_pins: i2c2-pins-g0 { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2c2_1_pins: i2c2-pins-g1 { - mux { - function = "i2c"; - groups = "i2c2_1"; - }; - }; - - gbe0_led0_pins: gbe0-led0-pins { - mux { - function = "led"; - groups = "gbe0_led0"; - }; - }; - - gbe1_led0_pins: gbe1-led0-pins { - mux { - function = "led"; - groups = "gbe1_led0"; - }; - }; - - gbe2_led0_pins: gbe2-led0-pins { - mux { - function = "led"; - groups = "gbe2_led0"; - }; - }; - - gbe3_led0_pins: gbe3-led0-pins { - mux { - function = "led"; - groups = "gbe3_led0"; - }; - }; - - gbe0_led1_pins: gbe0-led1-pins { - mux { - function = "led"; - groups = "gbe0_led1"; - }; - }; - - gbe1_led1_pins: gbe1-led1-pins { - mux { - function = "led"; - groups = "gbe1_led1"; - }; - }; - - gbe2_led1_pins: gbe2-led1-pins { - mux { - function = "led"; - groups = "gbe2_led1"; - }; - }; - - gbe3_led1_pins: gbe3-led1-pins { - mux { - function = "led"; - groups = "gbe3_led1"; - }; - }; - - i2p5gbe_led0_pins: 2p5gbe-led0-pins { - mux { - function = "led"; - groups = "2p5gbe_led0"; - }; - }; - - i2p5gbe_led1_pins: 2p5gbe-led1-pins { - mux { - function = "led"; - groups = "2p5gbe_led1"; - }; - }; - - mmc0_pins_emmc_45: mmc0-pins-emmc-45 { - mux { - function = "flash"; - groups = "emmc_45"; - }; - }; - - mmc0_pins_emmc_51: mmc0-pins-emmc-51 { - mux { - function = "flash"; - groups = "emmc_51"; - }; - }; - - mmc0_pins_sdcard: mmc0-pins-sdcard { - mux { - function = "flash"; - groups = "sdcard"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - uart1_0_pins: uart1-0-pins { - mux { - function = "uart"; - groups = "uart1_0"; - }; - }; - - uart1_1_pins: uart1-1-pins { - mux { - function = "uart"; - groups = "uart1_1"; - }; - }; - - uart1_2_pins: uart1-2-pins { - mux { - function = "uart"; - groups = "uart1_2"; - }; - }; - - uart1_2_lite_pins: uart1-2-lite-pins { - mux { - function = "uart"; - groups = "uart1_2_lite"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - uart2_0_pins: uart2-0-pins { - mux { - function = "uart"; - groups = "uart2_0"; - }; - }; - - uart2_1_pins: uart2-1-pins { - mux { - function = "uart"; - groups = "uart2_1"; - }; - }; - - uart2_2_pins: uart2-2-pins { - mux { - function = "uart"; - groups = "uart2_2"; - }; - }; - - uart2_3_pins: uart2-3-pins { - mux { - function = "uart"; - groups = "uart2_3"; - }; - }; - - snfi_pins: snfi-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spi0_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0"; - }; - }; - - spi0_flash_pins: spi0-flash-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; - - spi1_pins: spi1-pins { - mux { - function = "spi"; - groups = "spi1"; - }; - }; - - spi2_pins: spi2-pins { - mux { - function = "spi"; - groups = "spi2"; - }; - }; - - spi2_flash_pins: spi2-flash-pins { - mux { - function = "spi"; - groups = "spi2", "spi2_wp_hold"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", - "pcie_wake_n0_0"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", - "pcie_wake_n1_0"; - }; - }; - - pcie2_pins: pcie2-pins { - mux { - function = "pcie"; - groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", - "pcie_wake_n2_0"; - }; - }; - - pcie3_pins: pcie3-pins { - mux { - function = "pcie"; - groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", - "pcie_wake_n3_0"; - }; - }; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7988-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, - <&infracfg CLK_INFRA_66M_PWM_HCK>, - <&infracfg CLK_INFRA_66M_PWM_CK1>, - <&infracfg CLK_INFRA_66M_PWM_CK2>, - <&infracfg CLK_INFRA_66M_PWM_CK3>, - <&infracfg CLK_INFRA_66M_PWM_CK4>, - <&infracfg CLK_INFRA_66M_PWM_CK5>, - <&infracfg CLK_INFRA_66M_PWM_CK6>, - <&infracfg CLK_INFRA_66M_PWM_CK7>, - <&infracfg CLK_INFRA_66M_PWM_CK8>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", - "pwm4","pwm5","pwm6","pwm7","pwm8"; - status = "disabled"; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys0", - "syscon", - "simple-mfd"; - reg = <0 0x10060000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>; - #clock-cells = <1>; - - sgmiipcs0: pcs { - compatible = "mediatek,mt7988-sgmii"; - clocks = <&topckgen CLK_TOP_SGM_0_SEL>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>; - clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; - }; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys1", - "syscon", - "simple-mfd"; - reg = <0 0x10070000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>; - #clock-cells = <1>; - - sgmiipcs1: pcs { - compatible = "mediatek,mt7988-sgmii"; - clocks = <&topckgen CLK_TOP_SGM_1_SEL>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>; - clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx"; - }; - }; - - usxgmiisys0: pcs@10080000 { - compatible = "mediatek,mt7988-usxgmiisys"; - reg = <0 0x10080000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>; - clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>; - }; - - usxgmiisys1: pcs@10081000 { - compatible = "mediatek,mt7988-usxgmiisys"; - reg = <0 0x10081000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>; - clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>; - }; - - mcusys: mcusys@100e0000 { - compatible = "mediatek,mt7988-mcusys", "syscon"; - reg = <0 0x100e0000 0 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@11000000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "disabled"; - }; - - uart1: serial@11000100 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000100 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart2: serial@11000200 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000200 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - snand: spi@11001000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11001000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI>, - <&infracfg CLK_INFRA_NFI>; - clock-names = "pad_clk", "nfi_clk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>, - <&topckgen CLK_TOP_MPLL_D8>; - nand-ecc-engine = <&bch>; - mediatek,quad-spi; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&snfi_pins>; - status = "disabled"; - }; - - bch: ecc@11002000 { - compatible = "mediatek,mt7686-ecc"; - reg = <0 0x11002000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_NFI1X_SEL>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - i2c0: i2c@11003000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11004000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11004000 0 0x1000>, - <0 0x10217100 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11005000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x10217180 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@11007000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11007000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI0>, - <&infracfg CLK_INFRA_66M_SPI0_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11008000 { - compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm"; - reg = <0 0x11008000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI1>, - <&infracfg CLK_INFRA_66M_SPI1_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI2_BCK>, - <&infracfg CLK_INFRA_66M_SPI2_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - lvts: lvts@1100a000 { - compatible = "mediatek,mt7988-lvts-ap"; - reg = <0 0x1100a000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; - clock-names = "lvts_clk"; - interrupts = ; - resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; - nvmem-cells = <&lvts_calibration>; - nvmem-cell-names = "lvts-calib-data-1"; - #thermal-sensor-cells = <1>; - }; - - ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&xphyu2port0 PHY_TYPE_USB2>, - <&xphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS>, - <&infracfg CLK_INFRA_USB_XHCI>, - <&infracfg CLK_INFRA_USB_REF>, - <&infracfg CLK_INFRA_66M_USB_HCK>, - <&infracfg CLK_INFRA_133M_USB_HCK>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - mediatek,p0_speed_fixup; - status = "disabled"; - }; - - ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&tphyu2port0 PHY_TYPE_USB2>, - <&tphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, - <&infracfg CLK_INFRA_USB_CK_P1>, - <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, - <&infracfg CLK_INFRA_AUD_26M>, - <&infracfg CLK_INFRA_AUD_L>, - <&infracfg CLK_INFRA_AUD_AUD>, - <&infracfg CLK_INFRA_AUD_EG2>, - <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_AUD_I2S_M>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel", - "aud_i2s_m"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>, - <&apmixedsys CLK_APMIXED_APLL2>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11D60000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC400>, - <&infracfg CLK_INFRA_MSDC2_HCK>, - <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, - <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, - <&apmixedsys CLK_APMIXED_MSDCPLL>; - clock-names = "source", - "hclk", - "axi_cg", - "ahb_cg"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pcie2: pcie@11280000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11280000 0 0x2000>; - reg-names = "pcie-mac"; - ranges = <0x81000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x00200000>, - <0x82000000 0x00 0x20200000 0x00 - 0x20200000 0x00 0x07e00000>; - device_type = "pci"; - linux,pci-domain = <3>; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P2>, - <&topckgen CLK_TOP_PEXTP_P2_SEL>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m", "pextp_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - phys = <&xphyu3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc2 0>, - <0 0 0 2 &pcie_intc2 1>, - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc2: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie3: pcie@11290000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11290000 0 0x2000>; - reg-names = "pcie-mac"; - ranges = <0x81000000 0x00 0x28000000 0x00 - 0x28000000 0x00 0x00200000>, - <0x82000000 0x00 0x28200000 0x00 - 0x28200000 0x00 0x07e00000>; - device_type = "pci"; - linux,pci-domain = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P3>, - <&topckgen CLK_TOP_PEXTP_P3_SEL>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m", "pextp_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc3 0>, - <0 0 0 2 &pcie_intc3 1>, - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc3: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie0: pcie@11300000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11300000 0 0x2000>; - reg-names = "pcie-mac"; - ranges = <0x81000000 0x00 0x30000000 0x00 - 0x30000000 0x00 0x00200000>, - <0x82000000 0x00 0x30200000 0x00 - 0x30200000 0x00 0x07e00000>; - device_type = "pci"; - linux,pci-domain = <0>; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P0>, - <&topckgen CLK_TOP_PEXTP_P0_SEL>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m", "pextp_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc0: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie1: pcie@11310000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - reg = <0 0x11310000 0 0x2000>; - reg-names = "pcie-mac"; - ranges = <0x81000000 0x00 0x38000000 0x00 - 0x38000000 0x00 0x00200000>, - <0x82000000 0x00 0x38200000 0x00 - 0x38200000 0x00 0x07e00000>; - device_type = "pci"; - linux,pci-domain = <1>; - interrupts = ; - bus-range = <0x00 0xff>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P1>, - <&topckgen CLK_TOP_PEXTP_P1_SEL>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m", "pextp_clk"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie_intc1: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - tphy: tphy@11c50000 { - compatible = "mediatek,mt7988", - "mediatek,generic-tphy-v2"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - - tphyu2port0: usb-phy@11c50000 { - reg = <0 0x11c50000 0 0x700>; - clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - tphyu3port0: usb-phy@11c50700 { - reg = <0 0x11c50700 0 0x900>; - clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,usb3-pll-ssc-delta; - mediatek,usb3-pll-ssc-delta1; - }; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7988-topmisc", "syscon", - "mediatek,mt7988-power-controller"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - xphy: xphy@11e10000 { - compatible = "mediatek,mt7988", - "mediatek,xsphy"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - - xphyu2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x400>; - clocks = <&infracfg CLK_INFRA_USB_UTMI>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - xphyu3port0: usb-phy@11e13000 { - reg = <0 0x11e13400 0 0x500>; - clocks = <&infracfg CLK_INFRA_USB_PIPE>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - }; - }; - - xfi_tphy0: phy@11f20000 { - compatible = "mediatek,mt7988-xfi-tphy"; - reg = <0 0x11f20000 0 0x10000>; - resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>; - clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; - clock-names = "xfipll", "topxtal"; - mediatek,usxgmii-performance-errata; - #phy-cells = <0>; - }; - - xfi_tphy1: phy@11f30000 { - compatible = "mediatek,mt7988-xfi-tphy"; - reg = <0 0x11f30000 0 0x10000>; - resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>; - clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; - clock-names = "xfipll", "topxtal"; - #phy-cells = <0>; - }; - - xfi_pll: clock-controller@11f40000 { - compatible = "mediatek,mt7988-xfi-pll"; - reg = <0 0x11f40000 0 0x1000>; - resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>; - #clock-cells = <1>; - }; - - efuse: efuse@11f50000 { - compatible = "mediatek,efuse"; - reg = <0 0x11f50000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; - - phy_calibration_p0: calib@940 { - reg = <0x940 0x10>; - }; - - phy_calibration_p1: calib@954 { - reg = <0x954 0x10>; - }; - - phy_calibration_p2: calib@968 { - reg = <0x968 0x10>; - }; - - phy_calibration_p3: calib@97c { - reg = <0x97c 0x10>; - }; - - cpufreq_calibration: calib@278 { - reg = <0x278 0x1>; - }; - }; - - ethsys: syscon@15000000 { - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - }; - - switch: switch@15020000 { - compatible = "mediatek,mt7988-switch"; - reg = <0 0x15020000 0 0x8000>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; - #address-cells = <1>; - #size-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - gsw_port0: port@0 { - reg = <0>; - label = "lan0"; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - gsw_port1: port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - gsw_port2: port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - gsw_port3: port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - mediatek,pio = <&pio>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy0_led0: gsw-phy0-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy0_led1: gsw-phy0-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy1_led0: gsw-phy1-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy1_led1: gsw-phy1-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <2>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy2_led0: gsw-phy2-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy2_led1: gsw-phy2-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - phy-mode = "internal"; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - - leds { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy3_led0: gsw-phy3-led0@0 { - reg = <0>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - - gsw_phy3_led1: gsw-phy3-led1@1 { - reg = <1>; - function = LED_FUNCTION_LAN; - status = "disabled"; - }; - }; - }; - }; - }; - - ethwarp: clock-controller@15031000 { - compatible = "mediatek,mt7988-ethwarp"; - reg = <0 0x15031000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7988-eth"; - reg = <0 0x15100000 0 0x80000>, - <0 0x15400000 0 0x380000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETHDMA_XGP1_EN>, - <ðsys CLK_ETHDMA_XGP2_EN>, - <ðsys CLK_ETHDMA_XGP3_EN>, - <ðsys CLK_ETHDMA_FE_EN>, - <ðsys CLK_ETHDMA_GP2_EN>, - <ðsys CLK_ETHDMA_GP1_EN>, - <ðsys CLK_ETHDMA_GP3_EN>, - <ðsys CLK_ETHDMA_ESW_EN>, - <ðsys CLK_ETHDMA_CRYPT0_EN>, - <ðwarp CLK_ETHWARP_WOCPU2_EN>, - <ðwarp CLK_ETHWARP_WOCPU1_EN>, - <ðwarp CLK_ETHWARP_WOCPU0_EN>, - <&topckgen CLK_TOP_ETH_GMII_SEL>, - <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_SEL>, - <&topckgen CLK_TOP_ETH_XGMII_SEL>, - <&topckgen CLK_TOP_ETH_MII_SEL>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>, - <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_WARP_SEL>; - clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", - "gp3", "esw", "crypto", - "ethwarp_wocpu2", "ethwarp_wocpu1", - "ethwarp_wocpu0", "top_eth_gmii_sel", - "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", - "top_eth_sys_sel", "top_eth_xgmii_sel", - "top_eth_mii_sel", "top_netsys_sel", - "top_netsys_500m_sel", "top_netsys_pao_2x_sel", - "top_netsys_sync_250m_sel", - "top_netsys_ppefb_250m_sel", - "top_netsys_warp_sel"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_GSW_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, - <&topckgen CLK_TOP_NET1PLL_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&apmixedsys CLK_APMIXED_SGMPLL>, - <&apmixedsys CLK_APMIXED_SGMPLL>; - mediatek,ethsys = <ðsys>; - mediatek,infracfg = <&topmisc>; - #address-cells = <1>; - #size-cells = <0>; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - status = "disabled"; - pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>; - phys = <&xfi_tphy1>; - }; - - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - status = "disabled"; - pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>; - phys = <&xfi_tphy0>; - }; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* internal 2.5G PHY */ - int_2p5g_phy: ethernet-phy@15 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <15>; - phy-mode = "internal"; - }; - }; - }; - - crypto: crypto@15600000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0 0x15600000 0 0x180000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - status = "okay"; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&lvts 0>; - - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <40000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-low { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-passive { - /* passive: set fan to cooling level 0 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; -}; diff --git a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c deleted file mode 100644 index e2e06d1ecac8cf..00000000000000 --- a/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c +++ /dev/null @@ -1,316 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin" - -#define MD32_EN BIT(0) -#define PMEM_PRIORITY BIT(8) -#define DMEM_PRIORITY BIT(16) - -#define BASE100T_STATUS_EXTEND 0x10 -#define BASE1000T_STATUS_EXTEND 0x11 -#define EXTEND_CTRL_AND_STATUS 0x16 - -#define PHY_AUX_CTRL_STATUS 0x1d -#define PHY_AUX_DPX_MASK GENMASK(5, 5) -#define PHY_AUX_SPEED_MASK GENMASK(4, 2) - -/* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_LINK_STATUS_MISC 0xa2 -#define MTK_PHY_FDX_ENABLE BIT(5) - -#define MTK_PHY_LPI_PCS_DSP_CTRL 0x121 -#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8) - -/* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINK2500 BIT(7) -#define MTK_PHY_LED0_POLARITY BIT(14) - -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_FDX BIT(4) -#define MTK_PHY_LED1_ON_HDX BIT(5) -#define MTK_PHY_LED1_POLARITY BIT(14) - -#define MTK_EXT_PAGE_ACCESS 0x1f -#define MTK_PHY_PAGE_STANDARD 0x0000 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 - -struct mtk_i2p5ge_phy_priv { - bool fw_loaded; -}; - -enum { - PHY_AUX_SPD_10 = 0, - PHY_AUX_SPD_100, - PHY_AUX_SPD_1000, - PHY_AUX_SPD_2500, -}; - -static int mtk_2p5ge_phy_read_page(struct phy_device *phydev) -{ - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -} - -static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page) -{ - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -} - -static int mt7988_2p5ge_phy_probe(struct phy_device *phydev) -{ - struct mtk_i2p5ge_phy_priv *phy_priv; - - phy_priv = devm_kzalloc(&phydev->mdio.dev, - sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL); - if (!phy_priv) - return -ENOMEM; - - phydev->priv = phy_priv; - - return 0; -} - -static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev) -{ - int ret, i; - const struct firmware *fw; - struct device *dev = &phydev->mdio.dev; - struct device_node *np; - void __iomem *pmb_addr; - void __iomem *md32_en_cfg_base; - struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv; - u16 reg; - struct pinctrl *pinctrl; - - if (!phy_priv->fw_loaded) { - np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); - if (!np) - return -ENOENT; - pmb_addr = of_iomap(np, 0); - if (!pmb_addr) - return -ENOMEM; - md32_en_cfg_base = of_iomap(np, 1); - if (!md32_en_cfg_base) - return -ENOMEM; - - ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MT7988_2P5GE_PMB, ret); - return ret; - } - - reg = readw(md32_en_cfg_base); - if (reg & MD32_EN) { - phy_set_bits(phydev, 0, BIT(15)); - usleep_range(10000, 11000); - } - phy_set_bits(phydev, 0, BIT(11)); - - /* Write magic number to safely stall MCU */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100); - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df); - - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); - release_firmware(fw); - - writew(reg & ~MD32_EN, md32_en_cfg_base); - writew(reg | MD32_EN, md32_en_cfg_base); - phy_set_bits(phydev, 0, BIT(15)); - dev_info(dev, "Firmware loading/trigger ok.\n"); - - phy_priv->fw_loaded = true; - } - - /* Setup LED */ - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_ON_LINK10 | - MTK_PHY_LED0_ON_LINK100 | - MTK_PHY_LED0_ON_LINK1000 | - MTK_PHY_LED0_ON_LINK2500); - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX); - - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); - if (IS_ERR(pinctrl)) { - dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); - return PTR_ERR(pinctrl); - } - - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL, - MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0); - - /* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */ - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); - __phy_write(phydev, 0x11, 0xfbfa); - __phy_write(phydev, 0x12, 0xc3); - __phy_write(phydev, 0x10, 0x87f8); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - - return 0; -} - -static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev) -{ - bool changed = false; - u32 adv; - int ret; - - if (phydev->autoneg == AUTONEG_DISABLE) { - /* Configure half duplex with genphy_setup_forced, - * because genphy_c45_pma_setup_forced does not support. - */ - return phydev->duplex != DUPLEX_FULL - ? genphy_setup_forced(phydev) - : genphy_c45_pma_setup_forced(phydev); - } - - ret = genphy_c45_an_config_aneg(phydev); - if (ret < 0) - return ret; - if (ret > 0) - changed = true; - - adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); - ret = phy_modify_changed(phydev, MII_CTRL1000, - ADVERTISE_1000FULL | ADVERTISE_1000HALF, - adv); - if (ret < 0) - return ret; - if (ret > 0) - changed = true; - - return genphy_c45_check_and_restart_aneg(phydev, changed); -} - -static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev) -{ - int ret; - - ret = genphy_read_abilities(phydev); - if (ret) - return ret; - - /* We don't support HDX at MAC layer on mt7988. - * So mask phy's HDX capabilities, too. - */ - linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); - - return 0; -} - -static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev) -{ - int ret; - - ret = genphy_update_link(phydev); - if (ret) - return ret; - - phydev->speed = SPEED_UNKNOWN; - phydev->duplex = DUPLEX_UNKNOWN; - phydev->pause = 0; - phydev->asym_pause = 0; - - if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { - ret = genphy_c45_read_lpa(phydev); - if (ret < 0) - return ret; - - /* Read the link partner's 1G advertisement */ - ret = phy_read(phydev, MII_STAT1000); - if (ret < 0) - return ret; - mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); - } else if (phydev->autoneg == AUTONEG_DISABLE) { - linkmode_zero(phydev->lp_advertising); - } - - ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); - if (ret < 0) - return ret; - - switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { - case PHY_AUX_SPD_10: - phydev->speed = SPEED_10; - break; - case PHY_AUX_SPD_100: - phydev->speed = SPEED_100; - break; - case PHY_AUX_SPD_1000: - phydev->speed = SPEED_1000; - break; - case PHY_AUX_SPD_2500: - phydev->speed = SPEED_2500; - break; - } - - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC); - if (ret < 0) - return ret; - - phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF; - /* FIXME: The current firmware always enables rate adaptation mode. */ - phydev->rate_matching = RATE_MATCH_PAUSE; - - return 0; -} - -static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev, - phy_interface_t iface) -{ - return RATE_MATCH_PAUSE; -} - -static struct phy_driver mtk_gephy_driver[] = { - { - PHY_ID_MATCH_MODEL(0x00339c11), - .name = "MediaTek MT798x 2.5GbE PHY", - .probe = mt7988_2p5ge_phy_probe, - .config_init = mt7988_2p5ge_phy_config_init, - .config_aneg = mt7988_2p5ge_phy_config_aneg, - .get_features = mt7988_2p5ge_phy_get_features, - .read_status = mt7988_2p5ge_phy_read_status, - .get_rate_matching = mt7988_2p5ge_phy_get_rate_matching, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_2p5ge_phy_read_page, - .write_page = mtk_2p5ge_phy_write_page, - }, -}; - -module_phy_driver(mtk_gephy_driver); - -static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { - { PHY_ID_MATCH_VENDOR(0x00339c00) }, - { } -}; - -MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); -MODULE_AUTHOR("SkyLake Huang "); -MODULE_LICENSE("GPL"); - -MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); -MODULE_FIRMWARE(MT7988_2P5GE_PMB); diff --git a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c deleted file mode 100644 index 9f9291124522c9..00000000000000 --- a/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ /dev/null @@ -1,1517 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7988 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2020 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -enum MT7988_PINCTRL_REG_PAGE { - GPIO_BASE, - IOCFG_TR_BASE, - IOCFG_BR_BASE, - IOCFG_RB_BASE, - IOCFG_LB_BASE, - IOCFG_TL_BASE, -}; - -#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { - PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { - PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { - PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { - PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), - PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), - PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), - - PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), - PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), - PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), - PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), - PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), - PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), - PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), - PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), - PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), - PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), - PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), - PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), - - PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), - - PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), - PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), - PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), - - PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), - PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), - PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), - PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), - - PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), - PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), - PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), - PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), - PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), - PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), - PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), - PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), - PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), - PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), - PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), - PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), - - PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), - PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), - - PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), - - PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), - PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), - PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), - PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), - - PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), - - PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), - - PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), - - PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), - - PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), - PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), - - PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), - - PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), - PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), - PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), - PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), - PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), - PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), - PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), - PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), - PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), - PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), - PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), - PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), - - PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), - - PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), - - PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), - - PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { - PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), - - PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), - - PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), - - PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), - PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), - PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), - PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), - PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), - PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), - PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), - PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), - PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), - PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), - PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), - PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), - PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), - PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), - PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), - - PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), - PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), - - PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), - - PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), - - PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), - PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), -}; - -static const unsigned int mt7988_pull_type[] = { - MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ - MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ - MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ - MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/ - MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/ - MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ - MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/ - MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/ - MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/ - MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ - MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ - MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ - MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ - MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ - MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ - MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ - MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ - MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ - MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ - MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ - MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ - MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ - MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ - MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ - MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ - MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ - MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ - MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ - MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ - MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ - MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ - MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/ - MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ - MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ - MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ - MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/ - MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ - MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/ - MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/ - MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/ - MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ - MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/ -}; - -static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7988_pins[] = { - MT7988_PIN(0, "UART2_RXD"), - MT7988_PIN(1, "UART2_TXD"), - MT7988_PIN(2, "UART2_CTS"), - MT7988_PIN(3, "UART2_RTS"), - MT7988_PIN(4, "GPIO_A"), - MT7988_PIN(5, "SMI_0_MDC"), - MT7988_PIN(6, "SMI_0_MDIO"), - MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), - MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), - MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), - MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), - MT7988_PIN(11, "GPIO_P"), - MT7988_PIN(12, "WATCHDOG"), - MT7988_PIN(13, "GPIO_RESET"), - MT7988_PIN(14, "GPIO_WPS"), - MT7988_PIN(15, "PMIC_I2C_SCL"), - MT7988_PIN(16, "PMIC_I2C_SDA"), - MT7988_PIN(17, "I2C_1_SCL"), - MT7988_PIN(18, "I2C_1_SDA"), - MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), - MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), - MT7988_PIN(21, "PWMD1"), - MT7988_PIN(22, "SPI0_WP"), - MT7988_PIN(23, "SPI0_HOLD"), - MT7988_PIN(24, "SPI0_CSB"), - MT7988_PIN(25, "SPI0_MISO"), - MT7988_PIN(26, "SPI0_MOSI"), - MT7988_PIN(27, "SPI0_CLK"), - MT7988_PIN(28, "SPI1_CSB"), - MT7988_PIN(29, "SPI1_MISO"), - MT7988_PIN(30, "SPI1_MOSI"), - MT7988_PIN(31, "SPI1_CLK"), - MT7988_PIN(32, "SPI2_CLK"), - MT7988_PIN(33, "SPI2_MOSI"), - MT7988_PIN(34, "SPI2_MISO"), - MT7988_PIN(35, "SPI2_CSB"), - MT7988_PIN(36, "SPI2_HOLD"), - MT7988_PIN(37, "SPI2_WP"), - MT7988_PIN(38, "EMMC_RSTB"), - MT7988_PIN(39, "EMMC_DSL"), - MT7988_PIN(40, "EMMC_CK"), - MT7988_PIN(41, "EMMC_CMD"), - MT7988_PIN(42, "EMMC_DATA_7"), - MT7988_PIN(43, "EMMC_DATA_6"), - MT7988_PIN(44, "EMMC_DATA_5"), - MT7988_PIN(45, "EMMC_DATA_4"), - MT7988_PIN(46, "EMMC_DATA_3"), - MT7988_PIN(47, "EMMC_DATA_2"), - MT7988_PIN(48, "EMMC_DATA_1"), - MT7988_PIN(49, "EMMC_DATA_0"), - MT7988_PIN(50, "PCM_FS_I2S_LRCK"), - MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), - MT7988_PIN(52, "PCM_DRX_I2S_DIN"), - MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), - MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), - MT7988_PIN(55, "UART0_RXD"), - MT7988_PIN(56, "UART0_TXD"), - MT7988_PIN(57, "PWMD0"), - MT7988_PIN(58, "JTAG_JTDI"), - MT7988_PIN(59, "JTAG_JTDO"), - MT7988_PIN(60, "JTAG_JTMS"), - MT7988_PIN(61, "JTAG_JTCLK"), - MT7988_PIN(62, "JTAG_JTRST_N"), - MT7988_PIN(63, "USB_DRV_VBUS_P1"), - MT7988_PIN(64, "LED_A"), - MT7988_PIN(65, "LED_B"), - MT7988_PIN(66, "LED_C"), - MT7988_PIN(67, "LED_D"), - MT7988_PIN(68, "LED_E"), - MT7988_PIN(69, "GPIO_B"), - MT7988_PIN(70, "GPIO_C"), - MT7988_PIN(71, "I2C_2_SCL"), - MT7988_PIN(72, "I2C_2_SDA"), - MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), - MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), - MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), - MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), - MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), - MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), - MT7988_PIN(79, "USB_DRV_VBUS_P0"), - MT7988_PIN(80, "UART1_RXD"), - MT7988_PIN(81, "UART1_TXD"), - MT7988_PIN(82, "UART1_CTS"), - MT7988_PIN(83, "UART1_RTS"), -}; - -/* jtag */ -static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; - -static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; - -static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; - -static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; - -static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; - -static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; - -/* int_usxgmii */ -static int mt7988_int_usxgmii_pins[] = { 2, 3 }; -static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; - -/* pwm */ -static int mt7988_pwm0_pins[] = { 57 }; -static int mt7988_pwm0_funcs[] = { 1 }; - -static int mt7988_pwm1_pins[] = { 21 }; -static int mt7988_pwm1_funcs[] = { 1 }; - -static int mt7988_pwm2_pins[] = { 80 }; -static int mt7988_pwm2_funcs[] = { 2 }; - -static int mt7988_pwm3_pins[] = { 81 }; -static int mt7988_pwm3_funcs[] = { 2 }; - -static int mt7988_pwm4_pins[] = { 82 }; -static int mt7988_pwm4_funcs[] = { 2 }; - -static int mt7988_pwm5_pins[] = { 83 }; -static int mt7988_pwm5_funcs[] = { 2 }; - -static int mt7988_pwm6_pins[] = { 69 }; -static int mt7988_pwm6_funcs[] = { 3 }; - -static int mt7988_pwm7_pins[] = { 70 }; -static int mt7988_pwm7_funcs[] = { 3 }; - -/* dfd */ -static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2c */ -static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_0_pins[] = { 5, 6 }; -static int mt7988_i2c0_0_funcs[] = { 2, 2 }; - -static int mt7988_i2c1_sfp_pins[] = { 5, 6 }; -static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; - -static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_1_pins[] = { 15, 16 }; -static int mt7988_i2c0_1_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; -static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; - -static int mt7988_i2c1_0_pins[] = { 17, 18 }; -static int mt7988_i2c1_0_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; -static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; - -static int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c1_2_pins[] = { 69, 70 }; -static int mt7988_i2c1_2_funcs[] = { 2, 2 }; - -static int mt7988_i2c2_0_pins[] = { 69, 70 }; -static int mt7988_i2c2_0_funcs[] = { 4, 4 }; - -static int mt7988_i2c2_1_pins[] = { 71, 72 }; -static int mt7988_i2c2_1_funcs[] = { 1, 1 }; - -/* eth */ -static int mt7988_mdc_mdio0_pins[] = { 5, 6 }; -static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; - -static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; -static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; -static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_mdc_mdio1_pins[] = { 69, 70 }; -static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; - -/* pcie */ -static int mt7988_pcie_wake_n0_0_pins[] = { 7 }; -static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; -static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n3_0_pins[] = { 9 }; -static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n3_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; - -static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_pcie_wake_n0_1_pins[] = { 13 }; -static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_wake_n3_1_pins[] = { 14 }; -static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; -static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; -static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; -static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; -static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; -static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n1_0_pins[] = { 75 }; -static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n1_pins[] = { 76 }; -static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_0_pins[] = { 77 }; -static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; -static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_1_pins[] = { 79 }; -static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; - -/* pmic */ -static int mt7988_pmic_pins[] = { 11 }; -static int mt7988_pmic_funcs[] = { 1 }; - -/* watchdog */ -static int mt7988_watchdog_pins[] = { 12 }; -static int mt7988_watchdog_funcs[] = { 1 }; - -/* spi */ -static int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; -static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; - -static int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; -static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; -static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; -static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; -static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; - -/* flash */ -static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; -static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; - -static int mt7988_emmc_45_pins[] = { - 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 -}; -static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; - -static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; -static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; - -static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, - 44, 45, 46, 47, 48, 49 }; -static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; - -/* uart */ -static int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; -static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_tops_uart0_0_pins[] = { 22, 23 }; -static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; - -static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; -static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; -static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; -static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; -static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_tops_uart1_0_pins[] = { 28, 29 }; -static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart0_1_pins[] = { 30, 31 }; -static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart1_1_pins[] = { 36, 37 }; -static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; - -static int mt7988_uart0_pins[] = { 55, 56 }; -static int mt7988_uart0_funcs[] = { 1, 1 }; - -static int mt7988_tops_uart0_2_pins[] = { 55, 56 }; -static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; - -static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; -static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; -static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_uart1_2_lite_pins[] = { 80, 81 }; -static int mt7988_uart1_2_lite_funcs[] = { 1, 1 }; - -static int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -static int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; - -static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; -static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; -static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; -static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; - -/* udi */ -static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; -static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2s */ -static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; - -/* pcm */ -static int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; -static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; - -/* led */ -static int mt7988_gbe0_led1_pins[] = { 58 }; -static int mt7988_gbe0_led1_funcs[] = { 6 }; -static int mt7988_gbe1_led1_pins[] = { 59 }; -static int mt7988_gbe1_led1_funcs[] = { 6 }; -static int mt7988_gbe2_led1_pins[] = { 60 }; -static int mt7988_gbe2_led1_funcs[] = { 6 }; -static int mt7988_gbe3_led1_pins[] = { 61 }; -static int mt7988_gbe3_led1_funcs[] = { 6 }; - -static int mt7988_2p5gbe_led1_pins[] = { 62 }; -static int mt7988_2p5gbe_led1_funcs[] = { 6 }; - -static int mt7988_gbe0_led0_pins[] = { 64 }; -static int mt7988_gbe0_led0_funcs[] = { 1 }; -static int mt7988_gbe1_led0_pins[] = { 65 }; -static int mt7988_gbe1_led0_funcs[] = { 1 }; -static int mt7988_gbe2_led0_pins[] = { 66 }; -static int mt7988_gbe2_led0_funcs[] = { 1 }; -static int mt7988_gbe3_led0_pins[] = { 67 }; -static int mt7988_gbe3_led0_funcs[] = { 1 }; - -static int mt7988_2p5gbe_led0_pins[] = { 68 }; -static int mt7988_2p5gbe_led0_funcs[] = { 1 }; - -/* usb */ -static int mt7988_drv_vbus_p1_pins[] = { 63 }; -static int mt7988_drv_vbus_p1_funcs[] = { 1 }; - -static int mt7988_drv_vbus_pins[] = { 79 }; -static int mt7988_drv_vbus_funcs[] = { 1 }; - -static const struct group_desc mt7988_groups[] = { - /* @GPIO(0,1,2,3): uart2 */ - PINCTRL_PIN_GROUP("uart2", mt7988_uart2), - /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ - PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), - /* @GPIO(2,3): int_usxgmii */ - PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), - /* @GPIO(0,1,2,3,4): dfd */ - PINCTRL_PIN_GROUP("dfd", mt7988_dfd), - /* @GPIO(0,1): xfi_phy0_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), - /* @GPIO(0,1): xfi_phy1_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), - /* @GPIO(5,6) i2c0_0 */ - PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), - /* @GPIO(5,6) i2c1_sfp */ - PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), - /* @GPIO(5,6) xfi_pextp_phy0_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), - /* @GPIO(5,6) xfi_pextp_phy1_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), - /* @GPIO(5,6) mdc_mdio0 */ - PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), - /* @GPIO(7): pcie_wake_n0_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), - /* @GPIO(8): pcie_clk_req_n0_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), - /* @GPIO(9): pcie_wake_n3_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), - /* @GPIO(10): pcie_clk_req_n3 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), - /* @GPIO(10): pcie_clk_req_n0_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), - /* @GPIO(7,8) pcie_p0_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), - /* @GPIO(7,8) pcie_p1_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), - /* @GPIO(7,8) pcie_p2_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), - /* @GPIO(9,10) pcie_p3_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), - /* @GPIO(9,10) ckm_phy_i2c */ - PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), - /* @GPIO(11): pmic */ - PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), - /* @GPIO(12): watchdog */ - PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), - /* @GPIO(13): pcie_wake_n0_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), - /* @GPIO(14): pcie_wake_n3_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), - /* @GPIO(15,16) i2c0_1 */ - PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), - /* @GPIO(15,16) u30_phy_i2c0 */ - PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), - /* @GPIO(15,16) u32_phy_i2c0 */ - PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), - /* @GPIO(15,16) xfi_phy0_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), - /* @GPIO(15,16) xfi_phy1_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), - /* @GPIO(15,16) xfi_phy_pll_i2c2 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), - /* @GPIO(17,18) i2c1_0 */ - PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), - /* @GPIO(17,18) u30_phy_i2c1 */ - PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), - /* @GPIO(17,18) u32_phy_i2c1 */ - PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), - /* @GPIO(17,18) xfi_phy_pll_i2c3 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), - /* @GPIO(17,18) sgmii0_i2c */ - PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), - /* @GPIO(17,18) sgmii1_i2c */ - PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), - /* @GPIO(19): pcie_2l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), - /* @GPIO(20): pcie_1l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), - /* @GPIO(21): pwm1 */ - PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), - /* @GPIO(22,23) spi0_wp_hold */ - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), - /* @GPIO(24,25,26,27) spi0 */ - PINCTRL_PIN_GROUP("spi0", mt7988_spi0), - /* @GPIO(28,29,30,31) spi1 */ - PINCTRL_PIN_GROUP("spi1", mt7988_spi1), - /* @GPIO(32,33,34,35) spi2 */ - PINCTRL_PIN_GROUP("spi2", mt7988_spi2), - /* @GPIO(36,37) spi2_wp_hold */ - PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), - /* @GPIO(22,23,24,25,26,27) snfi */ - PINCTRL_PIN_GROUP("snfi", mt7988_snfi), - /* @GPIO(22,23) tops_uart0_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), - /* @GPIO(28,29,30,31) uart2_0 */ - PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), - /* @GPIO(32,33,34,35) uart1_0 */ - PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), - /* @GPIO(32,33,34,35) uart2_1 */ - PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), - /* @GPIO(28) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(29) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(30) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(28,29) tops_uart1_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), - /* @GPIO(30,31) tops_uart0_1 */ - PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), - /* @GPIO(36,37) tops_uart1_1 */ - PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), - /* @GPIO(32,33,34,35,36) udi */ - PINCTRL_PIN_GROUP("udi", mt7988_udi), - /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ - PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), - /* @GPIO(32,33,34,35,36,37) sdcard */ - PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), - /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ - PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), - /* @GPIO(28,29) 2p5g_ext_mdio */ - PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), - /* @GPIO(30,31) gbe_ext_mdio */ - PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), - /* @GPIO(50,51,52,53,54) i2s */ - PINCTRL_PIN_GROUP("i2s", mt7988_i2s), - /* @GPIO(50,51,52,53) pcm */ - PINCTRL_PIN_GROUP("pcm", mt7988_pcm), - /* @GPIO(55,56) uart0 */ - PINCTRL_PIN_GROUP("uart0", mt7988_uart0), - /* @GPIO(55,56) tops_uart0_2 */ - PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), - /* @GPIO(50,51,52,53) uart2_2 */ - PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), - /* @GPIO(50,51,52,53,54) wo0_jtag */ - PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), - /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ - PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), - /* @GPIO(50,51,52,53,54) wo2_jtag */ - PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), - /* @GPIO(57) pwm0 */ - PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), - /* @GPIO(58,59,60,61,62) jtag */ - PINCTRL_PIN_GROUP("jtag", mt7988_jtag), - /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ - PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), - /* @GPIO(58,59,60,61) uart2_3 */ - PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), - /* @GPIO(58,59,60,61) uart1_1 */ - PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), - /* @GPIO(58,59,60,61) gbe_led1 */ - PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), - PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), - PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), - PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), - /* @GPIO(62) 2p5gbe_led1 */ - PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), - /* @GPIO(64,65,66,67) gbe_led0 */ - PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), - PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), - PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), - PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), - /* @GPIO(68) 2p5gbe_led0 */ - PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), - /* @GPIO(63) drv_vbus_p1 */ - PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), - /* @GPIO(63) pcie_clk_req_n2_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), - /* @GPIO(69, 70) mdc_mdio1 */ - PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), - /* @GPIO(69, 70) i2c1_2 */ - PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), - /* @GPIO(69) pwm6 */ - PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), - /* @GPIO(70) pwm7 */ - PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), - /* @GPIO(69,70) i2c2_0 */ - PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), - /* @GPIO(71,72) i2c2_1 */ - PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), - /* @GPIO(73) pcie_2l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), - /* @GPIO(74) pcie_1l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), - /* @GPIO(75) pcie_wake_n1_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), - /* @GPIO(76) pcie_clk_req_n1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), - /* @GPIO(77) pcie_wake_n2_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), - /* @GPIO(78) pcie_clk_req_n2_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), - /* @GPIO(79) drv_vbus */ - PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), - /* @GPIO(79) pcie_wake_n2_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), - /* @GPIO(80,81,82,83) uart1_2 */ - PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), - /* @GPIO(80,81) uart1_2_lite */ - PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite), - /* @GPIO(80) pwm2 */ - PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), - /* @GPIO(81) pwm3 */ - PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), - /* @GPIO(82) pwm4 */ - PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), - /* @GPIO(83) pwm5 */ - PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), - /* @GPIO(80) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(81) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(82) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(80,81) tops_uart1_2 */ - PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), - /* @GPIO(80) net_wo0_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), - /* @GPIO(81) net_wo1_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), - /* @GPIO(82) net_wo2_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ -static const char * const mt7988_jtag_groups[] = { - "tops_jtag0_0", "wo0_jtag", "wo1_jtag", - "wo2_jtag", "jtag", "tops_jtag0_1", -}; -static const char * const mt7988_int_usxgmii_groups[] = { - "int_usxgmii", -}; -static const char * const mt7988_pwm_groups[] = { - "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" -}; -static const char * const mt7988_dfd_groups[] = { - "dfd", -}; -static const char * const mt7988_i2c_groups[] = { - "xfi_phy0_i2c0", - "xfi_phy1_i2c0", - "xfi_phy_pll_i2c0", - "xfi_phy_pll_i2c1", - "i2c0_0", - "i2c1_sfp", - "xfi_pextp_phy0_i2c", - "xfi_pextp_phy1_i2c", - "i2c0_1", - "u30_phy_i2c0", - "u32_phy_i2c0", - "xfi_phy0_i2c1", - "xfi_phy1_i2c1", - "xfi_phy_pll_i2c2", - "i2c1_0", - "u30_phy_i2c1", - "u32_phy_i2c1", - "xfi_phy_pll_i2c3", - "sgmii0_i2c", - "sgmii1_i2c", - "i2c1_2", - "i2c2_0", - "i2c2_1", -}; -static const char * const mt7988_ethernet_groups[] = { - "mdc_mdio0", - "2p5g_ext_mdio", - "gbe_ext_mdio", - "mdc_mdio1", -}; -static const char * const mt7988_pcie_groups[] = { - "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", - "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", - "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", - "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", - "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", - "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", - "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", - "pcie_clk_req_n0_1" -}; -static const char * const mt7988_pmic_groups[] = { - "pmic", -}; -static const char * const mt7988_wdt_groups[] = { - "watchdog", -}; -static const char * const mt7988_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", -}; -static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", - "emmc_51" }; -static const char * const mt7988_uart_groups[] = { - "uart2", - "tops_uart0_0", - "uart2_0", - "uart1_0", - "uart2_1", - "net_wo0_uart_txd_0", - "net_wo1_uart_txd_0", - "net_wo2_uart_txd_0", - "tops_uart1_0", - "ops_uart0_1", - "ops_uart1_1", - "uart0", - "tops_uart0_2", - "uart1_1", - "uart2_3", - "uart1_2", - "uart1_2_lite", - "tops_uart1_2", - "net_wo0_uart_txd_1", - "net_wo1_uart_txd_1", - "net_wo2_uart_txd_1", -}; -static const char * const mt7988_udi_groups[] = { - "udi", -}; -static const char * const mt7988_audio_groups[] = { - "i2s", "pcm", -}; -static const char * const mt7988_led_groups[] = { - "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", - "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", - "wf5g_led0", "wf5g_led1", -}; -static const char * const mt7988_usb_groups[] = { - "drv_vbus", - "drv_vbus_p1", -}; - -static const struct function_desc mt7988_functions[] = { - { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, - { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, - { "int_usxgmii", mt7988_int_usxgmii_groups, - ARRAY_SIZE(mt7988_int_usxgmii_groups) }, - { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, - { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, - { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, - { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, - { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, - { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, - { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, - { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, - { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, - { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, - { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, - { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, - { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, -}; - -static const struct mtk_eint_hw mt7988_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7988_pins), - .db_cnt = 16, -}; - -static const char * const mt7988_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_tr_base", "iocfg_br_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", -}; - -static struct mtk_pin_soc mt7988_data = { - .reg_cal = mt7988_reg_cals, - .pins = mt7988_pins, - .npins = ARRAY_SIZE(mt7988_pins), - .grps = mt7988_groups, - .ngrps = ARRAY_SIZE(mt7988_groups), - .funcs = mt7988_functions, - .nfuncs = ARRAY_SIZE(mt7988_functions), - .eint_hw = &mt7988_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7988_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, - .bias_disable_get = mtk_pinconf_bias_disable_get, - .bias_set = mtk_pinconf_bias_set, - .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7988_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7988_pinctrl_of_match[] = { - { - .compatible = "mediatek,mt7988-pinctrl", - }, - {} -}; - -static int mt7988_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7988_data); -} - -static struct platform_driver mt7988_pinctrl_driver = { - .driver = { - .name = "mt7988-pinctrl", - .of_match_table = mt7988_pinctrl_of_match, - }, - .probe = mt7988_pinctrl_probe, -}; - -static int __init mt7988_pinctrl_init(void) -{ - return platform_driver_register(&mt7988_pinctrl_driver); -} -arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c b/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c index 77369057044f83..5e1e3a35424637 100644 --- a/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c +++ b/target/linux/mediatek/files/drivers/leds/leds-smartrg-system.c @@ -7,7 +7,6 @@ #include #include #include -#include /** * Driver for SmartRG RGBW LED microcontroller. @@ -160,11 +159,7 @@ srg_led_init_led(struct srg_led_ctrl *sysled_ctrl, struct device_node *np) static int -#if LINUX_VERSION_CODE < KERNEL_VERSION(6,6,0) -srg_led_probe(struct i2c_client *client, const struct i2c_device_id *id) -#else srg_led_probe(struct i2c_client *client) -#endif { struct device_node *np = client->dev.of_node, *child; struct srg_led_ctrl *sysled_ctrl; @@ -198,21 +193,13 @@ static void srg_led_disable(struct i2c_client *client) srg_led_i2c_write(sysled_ctrl, i, 0); } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,16,0) static void -#else -static int -#endif srg_led_remove(struct i2c_client *client) { struct srg_led_ctrl *sysled_ctrl = i2c_get_clientdata(client); srg_led_disable(client); mutex_destroy(&sysled_ctrl->lock); - -#if LINUX_VERSION_CODE < KERNEL_VERSION(5,16,0) - return 0; -#endif } static const struct i2c_device_id srg_led_id[] = { diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 6f69706d79b7ac..ee0e8b62d752db 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -83,6 +83,7 @@ platform_do_upgrade() { bananapi,bpi-r3|\ bananapi,bpi-r3-mini|\ bananapi,bpi-r4|\ + jdcloud,re-cp-03|\ tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088|\ @@ -140,10 +141,6 @@ platform_do_upgrade() { CI_KERNPART="fit" nand_do_upgrade "$1" ;; - jdcloud,re-cp-03) - CI_KERNPART="production" - emmc_do_upgrade "$1" - ;; mercusys,mr90x-v1) CI_UBIPART="ubi0" nand_do_upgrade "$1" diff --git a/target/linux/mediatek/filogic/config-6.1 b/target/linux/mediatek/filogic/config-6.1 deleted file mode 100644 index 663bb054a285f2..00000000000000 --- a/target/linux/mediatek/filogic/config-6.1 +++ /dev/null @@ -1,486 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AIROHA_EN8801SC_PHY=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_NVMEM=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2712 is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7981=y -CONFIG_COMMON_CLK_MT7981_ETHSYS=y -CONFIG_COMMON_CLK_MT7986=y -CONFIG_COMMON_CLK_MT7986_ETHSYS=y -CONFIG_COMMON_CLK_MT7988=y -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8186 is not set -# CONFIG_COMMON_CLK_MT8195 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRC_CCITT=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA3=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_WATCHDOG=y -CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y -CONFIG_GRO_CELLS=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_LEDS_SMARTRG_LED=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAXLINEAR_GPHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_2P5G_PHY=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_GE_SOC_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_NVMEM=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_SOC_THERMAL=y -CONFIG_MTK_LVTS_THERMAL=y -CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -CONFIG_NET_DSA_MT7530_MMIO=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_MTK_EFUSE=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -# CONFIG_PCIE_MEDIATEK is not set -CONFIG_PCIE_MEDIATEK_GEN3=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PCS_MTK_USXGMII=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -CONFIG_PHY_MTK_XFI_TPHY=y -CONFIG_PHY_MTK_XSPHY=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6795 is not set -# CONFIG_PINCTRL_MT6797 is not set -# CONFIG_PINCTRL_MT7622 is not set -CONFIG_PINCTRL_MT7981=y -CONFIG_PINCTRL_MT7986=y -CONFIG_PINCTRL_MT7988=y -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -# CONFIG_PINCTRL_MT8186 is not set -# CONFIG_PINCTRL_MT8188 is not set -# CONFIG_PINCTRL_MT8516 is not set -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POLYNOMIAL=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_REGULATOR_RT5190A=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_TI_SYSCON=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPI_MTK_SNFI=y -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UIMAGE_FIT_BLK=y -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7622/config-6.1 b/target/linux/mediatek/mt7622/config-6.1 deleted file mode 100644 index 68bdd87074b65f..00000000000000 --- a/target/linux/mediatek/mt7622/config-6.1 +++ /dev/null @@ -1,479 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -# CONFIG_AIROHA_EN8801SC_PHY is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2712=y -# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set -# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set -# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set -# CONFIG_COMMON_CLK_MT2712_MMSYS is not set -# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -CONFIG_COMMON_CLK_MT7622=y -CONFIG_COMMON_CLK_MT7622_AUDSYS=y -CONFIG_COMMON_CLK_MT7622_ETHSYS=y -CONFIG_COMMON_CLK_MT7622_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8186 is not set -# CONFIG_COMMON_CLK_MT8195 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRC_CCITT=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -# CONFIG_FIT_PARTITION is not set -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -# CONFIG_LEDS_SMARTRG_LED is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAXLINEAR_GPHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MEDIATEK_2P5G_PHY is not set -CONFIG_MEDIATEK_GE_PHY=y -# CONFIG_MEDIATEK_GE_SOC_PHY is not set -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_NVMEM=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_SOC_THERMAL=y -# CONFIG_MTK_LVTS_THERMAL is not set -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_NVMEM_MTK_EFUSE=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6795 is not set -# CONFIG_PINCTRL_MT6797 is not set -CONFIG_PINCTRL_MT7622=y -# CONFIG_PINCTRL_MT7981 is not set -# CONFIG_PINCTRL_MT7986 is not set -# CONFIG_PINCTRL_MT7988 is not set -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -# CONFIG_PINCTRL_MT8186 is not set -# CONFIG_PINCTRL_MT8188 is not set -# CONFIG_PINCTRL_MT8516 is not set -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UIMAGE_FIT_BLK=y -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/config-6.1 b/target/linux/mediatek/mt7623/config-6.1 deleted file mode 100644 index 1407188e2ee5c3..00000000000000 --- a/target/linux/mediatek/mt7623/config-6.1 +++ /dev/null @@ -1,615 +0,0 @@ -# CONFIG_AIO is not set -# CONFIG_AIROHA_EN8801SC_PHY is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_LED=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2701=y -CONFIG_COMMON_CLK_MT2701_AUDSYS=y -CONFIG_COMMON_CLK_MT2701_BDPSYS=y -CONFIG_COMMON_CLK_MT2701_ETHSYS=y -CONFIG_COMMON_CLK_MT2701_G3DSYS=y -CONFIG_COMMON_CLK_MT2701_HIFSYS=y -CONFIG_COMMON_CLK_MT2701_IMGSYS=y -CONFIG_COMMON_CLK_MT2701_MMSYS=y -CONFIG_COMMON_CLK_MT2701_VDECSYS=y -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -# CONFIG_COMMON_CLK_MT7629 is not set -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_COREDUMP=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEBUG_MT6589_UART0=y -# CONFIG_DEBUG_MT8127_UART0 is not set -# CONFIG_DEBUG_MT8135_UART3 is not set -CONFIG_DEBUG_PREEMPT=y -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0x11004000 -CONFIG_DEBUG_UART_VIRT=0xf1004000 -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_DMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_LIMA=y -CONFIG_DRM_LVDS_CODEC=y -CONFIG_DRM_MEDIATEK=y -# CONFIG_DRM_MEDIATEK_DP is not set -CONFIG_DRM_MEDIATEK_HDMI=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_NOMODESET=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y -CONFIG_DRM_SCHED=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_ELF_CORE=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FIT_PARTITION is not set -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_WARN=1024 -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -# CONFIG_HARDEN_BRANCH_HISTORY is not set -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -CONFIG_IOMMU_DEFAULT_DMA_STRICT=y -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -# CONFIG_KEYBOARD_MT6779 is not set -CONFIG_KEYBOARD_MTK_PMIC=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_MT6323=y -# CONFIG_LEDS_QCOM_LPG is not set -# CONFIG_LEDS_SMARTRG_LED is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -CONFIG_MACH_MT7623=y -# CONFIG_MACH_MT7629 is not set -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_MT6397=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_NAND_ECC_MEDIATEK is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_ADSP_MBOX is not set -CONFIG_MTK_CMDQ=y -CONFIG_MTK_CMDQ_MBOX=y -CONFIG_MTK_CQDMA=y -# CONFIG_MTK_HSDMA is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_IOMMU=y -CONFIG_MTK_IOMMU_V1=y -CONFIG_MTK_MMSYS=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SMI=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_SOC_THERMAL=y -# CONFIG_MTK_LVTS_THERMAL is not set -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_MTK_EFUSE=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MTK_DP is not set -CONFIG_PHY_MTK_HDMI=y -CONFIG_PHY_MTK_MIPI_DSI=y -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT2701=y -# CONFIG_PINCTRL_MT6397 is not set -CONFIG_PINCTRL_MT7623=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_MT6323 is not set -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_BUILD=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MT6323=y -# CONFIG_REGULATOR_MT6331 is not set -# CONFIG_REGULATOR_MT6332 is not set -# CONFIG_REGULATOR_MT6358 is not set -# CONFIG_REGULATOR_MT6380 is not set -# CONFIG_REGULATOR_MT6397 is not set -# CONFIG_REGULATOR_QCOM_LABIBB is not set -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_MT6397 is not set -# CONFIG_RTC_DRV_MT7622 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SERIAL_8250_DMA is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -# CONFIG_SPMI_MTK_PMIF is not set -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -CONFIG_UBIFS_FS=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UIMAGE_FIT_BLK=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_F_ACM=y -CONFIG_USB_F_ECM=y -CONFIG_USB_F_MASS_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_G_MULTI=y -CONFIG_USB_G_MULTI_CDC=y -# CONFIG_USB_G_MULTI_RNDIS is not set -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_LIBCOMPOSITE=y -CONFIG_USB_MUSB_DUAL_ROLE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_MEDIATEK=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_U_ETHER=y -CONFIG_USB_U_SERIAL=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7629/config-6.1 b/target/linux/mediatek/mt7629/config-6.1 deleted file mode 100644 index 5a15286c468a46..00000000000000 --- a/target/linux/mediatek/mt7629/config-6.1 +++ /dev/null @@ -1,353 +0,0 @@ -# CONFIG_AIROHA_EN8801SC_PHY is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CACHE_L2X0=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CHR_DEV_SCH=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2701 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7629=y -CONFIG_COMMON_CLK_MT7629_ETHSYS=y -CONFIG_COMMON_CLK_MT7629_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEFAULT_HOSTNAME="(mt7629)" -CONFIG_DIMLIB=y -CONFIG_DMA_OPS=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -# CONFIG_FIT_PARTITION is not set -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_WARN=1024 -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -# CONFIG_HARDEN_BRANCH_HISTORY is not set -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LIBFDT=y -# CONFIG_LEDS_SMARTRG_LED is not set -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -# CONFIG_MACH_MT7623 is not set -CONFIG_MACH_MT7629=y -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -CONFIG_MTK_INFRACFG=y -# CONFIG_MTK_PMIC_WRAP is not set -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_TIMER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NETFILTER=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -# CONFIG_NVMEM_MTK_EFUSE is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT7629=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch b/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch deleted file mode 100644 index 17c5c6098aa67d..00000000000000 --- a/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001 -From: Andrew Davis -Date: Mon, 24 Oct 2022 12:34:28 -0500 -Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source - files - -Currently DTB Overlays (.dtbo) are build from source files with the same -extension (.dts) as the base DTs (.dtb). This may become confusing and -even lead to wrong results. For example, a composite DTB (created from a -base DTB and a set of overlays) might have the same name as one of the -overlays that create it. - -Different files should be generated from differently named sources. - .dtb <-> .dts - .dtbo <-> .dtso - -We do not remove the ability to compile DTBO files from .dts files here, -only add a new rule allowing the .dtso file name. The current .dts named -overlays can be renamed with time. After all have been renamed we can -remove the other rule. - -Signed-off-by: Andrew Davis -Reviewed-by: Geert Uytterhoeven -Tested-by: Geert Uytterhoeven -Reviewed-by: Frank Rowand -Tested-by: Frank Rowand -Link: https://lore.kernel.org/r/20221024173434.32518-2-afd@ti.com -Signed-off-by: Rob Herring ---- - scripts/Makefile.lib | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T - $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE - $(call if_changed_dep,dtc) - -+$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE -+ $(call if_changed_dep,dtc) -+ - dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) - - # Bzip2 diff --git a/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch b/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch deleted file mode 100644 index e6c6eb616614fa..00000000000000 --- a/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Sat, 5 Nov 2022 23:36:16 +0100 -Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX - Wireless Ethernet Dispatch - -Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet -Dispatch to offload traffic received by the wlan interface to lan/wan -one. - -Co-developed-by: Sujuan Chen -Signed-off-by: Sujuan Chen -Signed-off-by: Lorenzo Bianconi -Signed-off-by: David S. Miller ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++ - 1 file changed, 65 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -76,6 +76,47 @@ - no-map; - reg = <0 0x4fc00000 0 0x00100000>; - }; -+ -+ wo_emi0: wo-emi@4fd00000 { -+ reg = <0 0x4fd00000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_emi1: wo-emi@4fd40000 { -+ reg = <0 0x4fd40000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_ilm0: wo-ilm@151e0000 { -+ reg = <0 0x151e0000 0 0x8000>; -+ no-map; -+ }; -+ -+ wo_ilm1: wo-ilm@151f0000 { -+ reg = <0 0x151f0000 0 0x8000>; -+ no-map; -+ }; -+ -+ wo_data: wo-data@4fd80000 { -+ reg = <0 0x4fd80000 0 0x240000>; -+ no-map; -+ }; -+ -+ wo_dlm0: wo-dlm@151e8000 { -+ reg = <0 0x151e8000 0 0x2000>; -+ no-map; -+ }; -+ -+ wo_dlm1: wo-dlm@151f8000 { -+ reg = <0 0x151f8000 0 0x2000>; -+ no-map; -+ }; -+ -+ wo_boot: wo-boot@15194000 { -+ reg = <0 0x15194000 0 0x1000>; -+ no-map; -+ }; -+ - }; - - timer { -@@ -240,6 +281,11 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -+ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -+ <&wo_data>, <&wo_boot>; -+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -+ "wo-data", "wo-boot"; -+ mediatek,wo-ccif = <&wo_ccif0>; - }; - - wed1: wed@15011000 { -@@ -248,6 +294,25 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -+ memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -+ <&wo_data>, <&wo_boot>; -+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -+ "wo-data", "wo-boot"; -+ mediatek,wo-ccif = <&wo_ccif1>; -+ }; -+ -+ wo_ccif0: syscon@151a5000 { -+ compatible = "mediatek,mt7986-wo-ccif", "syscon"; -+ reg = <0 0x151a5000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ wo_ccif1: syscon@151ad000 { -+ compatible = "mediatek,mt7986-wo-ccif", "syscon"; -+ reg = <0 0x151ad000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; - }; - - eth: ethernet@15100000 { diff --git a/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch b/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch deleted file mode 100644 index b5091687a337c8..00000000000000 --- a/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:50:24 +0100 -Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order - -This arrange device tree nodes in alphabetical order. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++---------- - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++--- - 2 files changed, 58 insertions(+), 58 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -54,6 +54,53 @@ - }; - }; - -+&pio { -+ uart1_pins: uart1-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2"; -+ }; -+ }; -+ -+ wf_2g_5g_pins: wf-2g-5g-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_2g", "wf_5g"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_dbdc_pins: wf-dbdc-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_dbdc"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+}; -+ - &switch { - ports { - #address-cells = <1>; -@@ -121,50 +168,3 @@ - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; - }; -- --&pio { -- uart1_pins: uart1-pins { -- mux { -- function = "uart"; -- groups = "uart1"; -- }; -- }; -- -- uart2_pins: uart2-pins { -- mux { -- function = "uart"; -- groups = "uart2"; -- }; -- }; -- -- wf_2g_5g_pins: wf-2g-5g-pins { -- mux { -- function = "wifi"; -- groups = "wf_2g", "wf_5g"; -- }; -- conf { -- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -- "WF1_TOP_CLK", "WF1_TOP_DATA"; -- drive-strength = <4>; -- }; -- }; -- -- wf_dbdc_pins: wf-dbdc-pins { -- mux { -- function = "wifi"; -- groups = "wf_dbdc"; -- }; -- conf { -- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -- "WF0_TOP_CLK", "WF0_TOP_DATA"; -- drive-strength = <4>; -- }; -- }; --}; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -25,10 +25,6 @@ - }; - }; - --&uart0 { -- status = "okay"; --}; -- - ð { - status = "okay"; - -@@ -99,13 +95,6 @@ - }; - }; - --&wifi { -- status = "okay"; -- pinctrl-names = "default", "dbdc"; -- pinctrl-0 = <&wf_2g_5g_pins>; -- pinctrl-1 = <&wf_dbdc_pins>; --}; -- - &pio { - wf_2g_5g_pins: wf-2g-5g-pins { - mux { -@@ -138,3 +127,14 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&wifi { -+ status = "okay"; -+ pinctrl-names = "default", "dbdc"; -+ pinctrl-0 = <&wf_2g_5g_pins>; -+ pinctrl-1 = <&wf_dbdc_pins>; -+}; diff --git a/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch deleted file mode 100644 index fec048e68ec92f..00000000000000 --- a/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch +++ /dev/null @@ -1,68 +0,0 @@ -From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:50:27 +0100 -Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes - -This patch adds crypto engine support for MT7986. - -Signed-off-by: Vic Wu -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++ - 3 files changed, 23 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -25,6 +25,10 @@ - }; - }; - -+&crypto { -+ status = "okay"; -+}; -+ - ð { - status = "okay"; - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -224,6 +224,21 @@ - status = "disabled"; - }; - -+ crypto: crypto@10320000 { -+ compatible = "inside-secure,safexcel-eip97"; -+ reg = <0 0x10320000 0 0x40000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; -+ clocks = <&infracfg CLK_INFRA_EIP97_CK>; -+ clock-names = "infra_eip97_ck"; -+ assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; -+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; -+ status = "disabled"; -+ }; -+ - uart0: serial@11002000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -25,6 +25,10 @@ - }; - }; - -+&crypto { -+ status = "okay"; -+}; -+ - ð { - status = "okay"; - diff --git a/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch b/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch deleted file mode 100644 index 132940915b8e63..00000000000000 --- a/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch +++ /dev/null @@ -1,37 +0,0 @@ -From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 6 Nov 2022 09:50:29 +0100 -Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node - -Add i2c Node to mt7986 devicetree. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -280,6 +280,20 @@ - status = "disabled"; - }; - -+ i2c0: i2c@11008000 { -+ compatible = "mediatek,mt7986-i2c"; -+ reg = <0 0x11008000 0 0x90>, -+ <0 0x10217080 0 0x80>; -+ interrupts = ; -+ clock-div = <5>; -+ clocks = <&infracfg CLK_INFRA_I2C0_CK>, -+ <&infracfg CLK_INFRA_AP_DMA_CK>; -+ clock-names = "main", "dma"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; diff --git a/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch b/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch deleted file mode 100644 index 8201b47df614bb..00000000000000 --- a/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001 -From: Matthias Brugger -Date: Mon, 14 Nov 2022 13:16:53 +0100 -Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible - -Missing SoC compatible in the board file causes dt bindings check. - -Signed-off-by: Matthias Brugger -Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 + - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +- - arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 3 +++ - 4 files changed, 6 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -9,7 +9,7 @@ - - / { - model = "MediaTek MT7986a RFB"; -- compatible = "mediatek,mt7986a-rfb"; -+ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; - - aliases { - serial0 = &uart0; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -10,6 +10,7 @@ - #include - - / { -+ compatible = "mediatek,mt7986a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -9,7 +9,7 @@ - - / { - model = "MediaTek MT7986b RFB"; -- compatible = "mediatek,mt7986b-rfb"; -+ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; - - aliases { - serial0 = &uart0; ---- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi -@@ -5,6 +5,9 @@ - */ - - #include "mt7986a.dtsi" -+/ { -+ compatible = "mediatek,mt7986b"; -+}; - - &pio { - compatible = "mediatek,mt7986b-pinctrl"; diff --git a/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch deleted file mode 100644 index c45f183dc71435..00000000000000 --- a/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch +++ /dev/null @@ -1,157 +0,0 @@ -From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 18 Nov 2022 20:01:21 +0100 -Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes - -This patch adds spi support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++ - 3 files changed, 98 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -59,6 +59,20 @@ - }; - - &pio { -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ - uart1_pins: uart1-pins { - mux { - function = "uart"; -@@ -105,6 +119,27 @@ - }; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+}; -+ - &switch { - ports { - #address-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -295,6 +295,34 @@ - status = "disabled"; - }; - -+ spi0: spi@1100a000 { -+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0 0x1100a000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_SPI0_CK>, -+ <&infracfg CLK_INFRA_SPI0_HCK_CK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@1100b000 { -+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0 0x1100b000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPIM_MST_SEL>, -+ <&infracfg CLK_INFRA_SPI1_CK>, -+ <&infracfg CLK_INFRA_SPI1_HCK_CK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; -+ status = "disabled"; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -100,6 +100,20 @@ - }; - - &pio { -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ - wf_2g_5g_pins: wf-2g-5g-pins { - mux { - function = "wifi"; -@@ -132,6 +146,27 @@ - }; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ }; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+}; -+ - &uart0 { - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch deleted file mode 100644 index 603f33b150b7c9..00000000000000 --- a/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:42 +0100 -Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes - -This patch adds USB support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: Chunfeng Yun -Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 8 +++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 55 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 8 +++ - 3 files changed, 71 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -140,6 +140,10 @@ - status = "okay"; - }; - -+&ssusb { -+ status = "okay"; -+}; -+ - &switch { - ports { - #address-cells = <1>; -@@ -201,6 +205,10 @@ - status = "okay"; - }; - -+&usb_phy { -+ status = "okay"; -+}; -+ - &wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -323,6 +323,61 @@ - status = "disabled"; - }; - -+ ssusb: usb@11200000 { -+ compatible = "mediatek,mt7986-xhci", -+ "mediatek,mtk-xhci"; -+ reg = <0 0x11200000 0 0x2e00>, -+ <0 0x11203e00 0 0x0100>; -+ reg-names = "mac", "ippc"; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, -+ <&infracfg CLK_INFRA_IUSB_CK>, -+ <&infracfg CLK_INFRA_IUSB_133_CK>, -+ <&infracfg CLK_INFRA_IUSB_66M_CK>, -+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; -+ clock-names = "sys_ck", -+ "ref_ck", -+ "mcu_ck", -+ "dma_ck", -+ "xhci_ck"; -+ phys = <&u2port0 PHY_TYPE_USB2>, -+ <&u3port0 PHY_TYPE_USB3>, -+ <&u2port1 PHY_TYPE_USB2>; -+ status = "disabled"; -+ }; -+ -+ usb_phy: t-phy@11e10000 { -+ compatible = "mediatek,mt7986-tphy", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0 0x11e10000 0x1700>; -+ status = "disabled"; -+ -+ u2port0: usb-phy@0 { -+ reg = <0x0 0x700>; -+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, -+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; -+ clock-names = "ref", "da_ref"; -+ #phy-cells = <1>; -+ }; -+ -+ u3port0: usb-phy@700 { -+ reg = <0x700 0x900>; -+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ -+ u2port1: usb-phy@1000 { -+ reg = <0x1000 0x700>; -+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, -+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; -+ clock-names = "ref", "da_ref"; -+ #phy-cells = <1>; -+ }; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -167,10 +167,18 @@ - status = "okay"; - }; - -+&ssusb { -+ status = "okay"; -+}; -+ - &uart0 { - status = "okay"; - }; - -+&usb_phy { -+ status = "okay"; -+}; -+ - &wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; diff --git a/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch deleted file mode 100644 index 40e71cd429b398..00000000000000 --- a/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch +++ /dev/null @@ -1,160 +0,0 @@ -From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:43 +0100 -Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes - -This patch adds mmc support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230106152845.88717-4-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++ - 2 files changed, 111 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -5,6 +5,8 @@ - */ - - /dts-v1/; -+#include -+ - #include "mt7986a.dtsi" - - / { -@@ -23,6 +25,24 @@ - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; - }; - - &crypto { -@@ -58,7 +78,83 @@ - }; - }; - -+&mmc0 { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ pinctrl-1 = <&mmc0_pins_uhs>; -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x14014>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ - &pio { -+ mmc0_pins_default: mmc0-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ mmc0_pins_uhs: mmc0-uhs-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -346,6 +346,21 @@ - status = "disabled"; - }; - -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7986-mmc"; -+ reg = <0 0x11230000 0 0x1000>, -+ <0 0x11c20000 0 0x1000>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, -+ <&infracfg CLK_INFRA_MSDC_HCK_CK>, -+ <&infracfg CLK_INFRA_MSDC_CK>, -+ <&infracfg CLK_INFRA_MSDC_133M_CK>, -+ <&infracfg CLK_INFRA_MSDC_66M_CK>; -+ clock-names = "source", "hclk", "source_cg", "bus_clk", -+ "sys_cg"; -+ status = "disabled"; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch b/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch deleted file mode 100644 index ab039c335a1fa0..00000000000000 --- a/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:44 +0100 -Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes - -This patch adds PCIe support for MT7986. - -Signed-off-by: Jieyy Yang -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++ - 2 files changed, 68 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -93,6 +93,15 @@ - non-removable; - no-sd; - no-sdio; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pins>; -+ status = "okay"; -+}; -+ -+&pcie_phy { - status = "okay"; - }; - -@@ -155,6 +164,13 @@ - }; - }; - -+ pcie_pins: pcie-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_clk", "pcie_wake", "pcie_pereset"; -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7986a"; -@@ -361,6 +362,57 @@ - status = "disabled"; - }; - -+ pcie: pcie@11280000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0x00 0x11280000 0x00 0x4000>; -+ reg-names = "pcie-mac"; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0x00 0x20000000 0x00 -+ 0x20000000 0x00 0x10000000>; -+ clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, -+ <&infracfg CLK_INFRA_IPCIE_CK>, -+ <&infracfg CLK_INFRA_IPCIER_CK>, -+ <&infracfg CLK_INFRA_IPCIEB_CK>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; -+ status = "disabled"; -+ -+ phys = <&pcie_port PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc 0>, -+ <0 0 0 2 &pcie_intc 1>, -+ <0 0 0 3 &pcie_intc 2>, -+ <0 0 0 4 &pcie_intc 3>; -+ pcie_intc: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie_phy: t-phy@11c00000 { -+ compatible = "mediatek,mt7986-tphy", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ pcie_port: pcie-phy@11c00000 { -+ reg = <0 0x11c00000 0 0x20000>; -+ clocks = <&clk40m>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; diff --git a/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch b/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch deleted file mode 100644 index 38f159c74ee370..00000000000000 --- a/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch +++ /dev/null @@ -1,689 +0,0 @@ -From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 6 Jan 2023 16:28:45 +0100 -Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3 - -Add support for Bananapi R3 SBC. - -- SD/eMMC support (switching first 4 bits of data-bus with sw6/D) -- SPI-NAND/NOR support (switched CS by sw5/C) -- all rj45 ports and both SFP working (eth1/lan4) -- all USB-Ports + SIM-Slot tested -- i2c and all uarts tested -- wifi tested (with eeprom calibration data) - -The device can boot from all 4 storage options. Both, SPI and MMC, can -be switched using hardware switches on the board, see -https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/Makefile | 5 + - .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++ - .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++ - .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++ - .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 + - .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++ - 6 files changed, 630 insertions(+) - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts - ---- a/arch/arm64/boot/dts/mediatek/Makefile -+++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev - dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/mmc@11230000"; -+ __overlay__ { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x14014>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+ }; -+ }; -+}; -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -@@ -0,0 +1,55 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+/* -+ * Authors: Daniel Golle -+ * Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/spi@1100a000"; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "reserved"; -+ reg = <0x80000 0x300000>; -+ }; -+ -+ partition@380000 { -+ label = "fip"; -+ reg = <0x380000 0x200000>; -+ read-only; -+ }; -+ -+ partition@580000 { -+ label = "ubi"; -+ reg = <0x580000 0x7a80000>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -0,0 +1,68 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+/* -+ * Authors: Daniel Golle -+ * Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/spi@1100a000"; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x20000>; -+ read-only; -+ }; -+ -+ partition@20000 { -+ label = "reserved"; -+ reg = <0x20000 0x20000>; -+ }; -+ -+ partition@40000 { -+ label = "u-boot-env"; -+ reg = <0x40000 0x40000>; -+ }; -+ -+ partition@80000 { -+ label = "reserved2"; -+ reg = <0x80000 0x80000>; -+ }; -+ -+ partition@100000 { -+ label = "fip"; -+ reg = <0x100000 0x80000>; -+ read-only; -+ }; -+ -+ partition@180000 { -+ label = "recovery"; -+ reg = <0x180000 0xa80000>; -+ }; -+ -+ partition@c00000 { -+ label = "fit"; -+ reg = <0xc00000 0x1400000>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso -@@ -0,0 +1,23 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/mmc@11230000"; -+ __overlay__ { -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ status = "okay"; -+ }; -+ }; -+}; -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -0,0 +1,450 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Authors: Sam.Shih -+ * Frank Wunderlich -+ * Daniel Golle -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include -+ -+#include "mt7986a.dtsi" -+ -+/ { -+ model = "Bananapi BPI-R3"; -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ aliases { -+ serial0 = &uart0; -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ dcin: regulator-12vd { -+ compatible = "regulator-fixed"; -+ regulator-name = "12vd"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ reset-key { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&pio 9 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wps-key { -+ label = "wps"; -+ linux,code = ; -+ gpios = <&pio 10 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ /* i2c of the left SFP cage (wan) */ -+ i2c_sfp1: i2c-gpio-0 { -+ compatible = "i2c-gpio"; -+ sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ i2c-gpio,delay-us = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ /* i2c of the right SFP cage (lan) */ -+ i2c_sfp2: i2c-gpio-1 { -+ compatible = "i2c-gpio"; -+ sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ i2c-gpio,delay-us = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ green_led: led-0 { -+ color = ; -+ function = LED_FUNCTION_POWER; -+ gpios = <&pio 69 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ blue_led: led-1 { -+ color = ; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&pio 86 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1.8vd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&dcin>; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3.3vd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&dcin>; -+ }; -+ -+ /* left SFP cage (wan) */ -+ sfp1: sfp-1 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp1>; -+ los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ /* right SFP cage (lan) */ -+ sfp2: sfp-2 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp2>; -+ los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&crypto { -+ status = "okay"; -+}; -+ -+ð { -+ status = "okay"; -+ -+ gmac0: mac@0 { -+ compatible = "mediatek,eth-mac"; -+ reg = <0>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ gmac1: mac@1 { -+ compatible = "mediatek,eth-mac"; -+ reg = <1>; -+ phy-mode = "2500base-x"; -+ sfp = <&sfp1>; -+ managed = "in-band-status"; -+ }; -+ -+ mdio: mdio-bus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+}; -+ -+&mdio { -+ switch: switch@1f { -+ compatible = "mediatek,mt7531"; -+ reg = <31>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; -+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ pinctrl-1 = <&mmc0_pins_uhs>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c_pins>; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pins>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ status = "okay"; -+}; -+ -+&pio { -+ i2c_pins: i2c-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ mmc0_pins_uhs: mmc0-uhs-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ pcie_pins: pcie-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_clk", "pcie_pereset"; -+ }; -+ }; -+ -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_0"; -+ }; -+ }; -+ -+ uart1_pins: uart1-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1_rx_tx"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2_0_rx_tx"; -+ }; -+ }; -+ -+ wf_2g_5g_pins: wf-2g-5g-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_2g", "wf_5g"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_dbdc_pins: wf-dbdc-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_dbdc"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_led_pins: wf-led-pins { -+ mux { -+ function = "led"; -+ groups = "wifi_led"; -+ }; -+ }; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ status = "okay"; -+}; -+ -+&ssusb { -+ status = "okay"; -+}; -+ -+&switch { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan0"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan1"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan2"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan3"; -+ }; -+ -+ port5: port@5 { -+ reg = <5>; -+ label = "lan4"; -+ phy-mode = "2500base-x"; -+ sfp = <&sfp2>; -+ managed = "in-band-status"; -+ }; -+ -+ port@6 { -+ reg = <6>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ }; -+}; -+ -+&trng { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+ status = "okay"; -+}; -+ -+&usb_phy { -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "okay"; -+}; -+ -+&wifi { -+ status = "okay"; -+ pinctrl-names = "default", "dbdc"; -+ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; -+ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+}; -+ diff --git a/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch b/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch deleted file mode 100644 index 79038334c4e128..00000000000000 --- a/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch +++ /dev/null @@ -1,323 +0,0 @@ -From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Wed, 17 May 2023 12:11:08 +0200 -Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible - -The chassis-type string identifies the form-factor of the system: -add this property to all device trees of devices for which the form -factor is known. - -Signed-off-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 + - .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 1 + - 28 files changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT2712 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6755 EVB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts -@@ -10,6 +10,7 @@ - - / { - model = "MediaTek MT6779 EVB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6795 Evaluation Board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6797 Evaluation Board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts -@@ -12,6 +12,7 @@ - - / { - model = "Mediatek X20 Development Board"; -+ chassis-type = "embedded"; - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -15,6 +15,7 @@ - - / { - model = "Bananapi BPI-R64"; -+ chassis-type = "embedded"; - compatible = "bananapi,bpi-r64", "mediatek,mt7622"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -15,6 +15,7 @@ - - / { - model = "MediaTek MT7622 RFB1 board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -16,6 +16,7 @@ - - / { - model = "Bananapi BPI-R3"; -+ chassis-type = "embedded"; - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT7986a RFB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT7986b RFB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts -@@ -11,6 +11,7 @@ - - / { - model = "Pumpkin MT8167"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; - - memory@40000000 { ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Hanawl"; -+ chassis-type = "laptop"; - compatible = "google,hana-rev7", "mediatek,mt8173"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Hana"; -+ chassis-type = "laptop"; - compatible = "google,hana-rev6", "google,hana-rev5", - "google,hana-rev4", "google,hana-rev3", - "google,hana", "mediatek,mt8173"; ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Elm"; -+ chassis-type = "laptop"; - compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", - "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", - "google,elm", "mediatek,mt8173"; ---- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts -@@ -10,6 +10,7 @@ - - / { - model = "MediaTek MT8173 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT8183 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google burnet board"; -+ chassis-type = "convertible"; - compatible = "google,burnet", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google damu board"; -+ chassis-type = "convertible"; - compatible = "google,damu", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google juniper sku16 board"; -+ chassis-type = "convertible"; - compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek kakadu board sku22"; -+ chassis-type = "tablet"; - compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", - "google,kakadu", "mediatek,mt8183"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek kakadu board"; -+ chassis-type = "tablet"; - compatible = "google,kakadu-rev3", "google,kakadu-rev2", - "google,kakadu", "mediatek,mt8183"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku16 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku272 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku288 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts -@@ -14,6 +14,7 @@ - - / { - model = "MediaTek krane sku0 board"; -+ chassis-type = "tablet"; - compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts -@@ -14,6 +14,7 @@ - - / { - model = "MediaTek krane sku176 board"; -+ chassis-type = "tablet"; - compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts -@@ -7,6 +7,7 @@ - - / { - model = "MediaTek MT8186 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; - - aliases { diff --git a/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch b/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch deleted file mode 100644 index 915da7984e6970..00000000000000 --- a/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 21 Apr 2023 15:20:44 +0200 -Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM - -This adds pwm node to mt7986. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -241,6 +241,20 @@ - status = "disabled"; - }; - -+ pwm: pwm@10048000 { -+ compatible = "mediatek,mt7986-pwm"; -+ reg = <0 0x10048000 0 0x1000>; -+ #clock-cells = <1>; -+ #pwm-cells = <2>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_PWM_SEL>, -+ <&infracfg CLK_INFRA_PWM_STA>, -+ <&infracfg CLK_INFRA_PWM1_CK>, -+ <&infracfg CLK_INFRA_PWM2_CK>; -+ clock-names = "top", "main", "pwm1", "pwm2"; -+ status = "disabled"; -+ }; -+ - uart0: serial@11002000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; diff --git a/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch b/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch deleted file mode 100644 index ce908e3d31fa7e..00000000000000 --- a/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 21 Apr 2023 15:20:45 +0200 -Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3 - -Add pwm node and pinctrl to BananaPi R3 devicetree. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -275,6 +275,13 @@ - }; - }; - -+ pwm_pins: pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0", "pwm1_0"; -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; -@@ -345,6 +352,12 @@ - }; - }; - -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; diff --git a/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch b/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch deleted file mode 100644 index c7b38484f4fb37..00000000000000 --- a/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch +++ /dev/null @@ -1,27 +0,0 @@ -From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 5 Feb 2023 18:48:33 +0100 -Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3 - -Leds for Wifi are low-active, so add property to devicetree. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -460,5 +460,9 @@ - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; - pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+ -+ led { -+ led-active-low; -+ }; - }; - diff --git a/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch b/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch deleted file mode 100644 index 0b84f1463acf2c..00000000000000 --- a/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 28 May 2023 13:33:42 +0200 -Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for - bl2 - -To store uncompressed bl2 more space is required than partition is -actually defined. - -There is currently no known usage of this reserved partition. -Openwrt uses same partition layout. - -We added same change to u-boot with commit d7bb1099 [1]. - -[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e - -Cc: stable@vger.kernel.org -Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Daniel Golle -Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -27,15 +27,10 @@ - - partition@0 { - label = "bl2"; -- reg = <0x0 0x20000>; -+ reg = <0x0 0x40000>; - read-only; - }; - -- partition@20000 { -- label = "reserved"; -- reg = <0x20000 0x20000>; -- }; -- - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; diff --git a/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch b/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch deleted file mode 100644 index f1cb0eaf024057..00000000000000 --- a/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:33 +0200 -Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse - -Add thermal related nodes to mt7986 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++- - 1 file changed, 35 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -338,6 +338,15 @@ - status = "disabled"; - }; - -+ auxadc: adc@1100d000 { -+ compatible = "mediatek,mt7986-auxadc"; -+ reg = <0 0x1100d000 0 0x1000>; -+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; -+ clock-names = "main"; -+ #io-channel-cells = <1>; -+ status = "disabled"; -+ }; -+ - ssusb: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; -@@ -376,6 +385,21 @@ - status = "disabled"; - }; - -+ thermal: thermal@1100c800 { -+ #thermal-sensor-cells = <1>; -+ compatible = "mediatek,mt7986-thermal"; -+ reg = <0 0x1100c800 0 0x800>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_THERM_CK>, -+ <&infracfg CLK_INFRA_ADC_26M_CK>, -+ <&infracfg CLK_INFRA_ADC_FRC_CK>; -+ clock-names = "therm", "auxadc", "adc_32k"; -+ mediatek,auxadc = <&auxadc>; -+ mediatek,apmixedsys = <&apmixedsys>; -+ nvmem-cells = <&thermal_calibration>; -+ nvmem-cell-names = "calibration-data"; -+ }; -+ - pcie: pcie@11280000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; -@@ -427,6 +451,17 @@ - }; - }; - -+ efuse: efuse@11d00000 { -+ compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; -+ reg = <0 0x11d00000 0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ thermal_calibration: calib@274 { -+ reg = <0x274 0xc>; -+ }; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; -@@ -568,5 +603,4 @@ - memory-region = <&wmcpu_emi>; - }; - }; -- - }; diff --git a/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch b/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch deleted file mode 100644 index ad21fb8c3cc8f7..00000000000000 --- a/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:34 +0200 -Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones - -Add thermal-zones to mt7986 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -603,4 +603,32 @@ - memory-region = <&wmcpu_emi>; - }; - }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <1000>; -+ thermal-sensors = <&thermal 0>; -+ -+ trips { -+ cpu_trip_active_high: active-high { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_low: active-low { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_passive: passive { -+ temperature = <40000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ }; -+ }; -+ }; - }; diff --git a/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch b/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch deleted file mode 100644 index ca7d872a1bfbcc..00000000000000 --- a/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:35 +0200 -Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to - BPI-R3 dts - -Add pwm-fan and cooling-maps to BananaPi-R3 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 31 +++++++++++++++++++ - 1 file changed, 31 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -38,6 +38,15 @@ - regulator-always-on; - }; - -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ #cooling-cells = <2>; -+ /* cooling level (0, 1, 2) - pwm inverted */ -+ cooling-levels = <255 96 0>; -+ pwms = <&pwm 0 10000 0>; -+ status = "okay"; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - -@@ -133,6 +142,28 @@ - }; - }; - -+&cpu_thermal { -+ cooling-maps { -+ cpu-active-high { -+ /* active: set fan to cooling level 2 */ -+ cooling-device = <&fan 2 2>; -+ trip = <&cpu_trip_active_high>; -+ }; -+ -+ cpu-active-low { -+ /* active: set fan to cooling level 1 */ -+ cooling-device = <&fan 1 1>; -+ trip = <&cpu_trip_active_low>; -+ }; -+ -+ cpu-passive { -+ /* passive: set fan to cooling level 0 */ -+ cooling-device = <&fan 0 0>; -+ trip = <&cpu_trip_passive>; -+ }; -+ }; -+}; -+ - &crypto { - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch b/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch deleted file mode 100644 index 9cc6cad0af52ec..00000000000000 --- a/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 6 Jun 2023 16:43:20 +0100 -Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of - Bananapi R3 - -The bootrom burned into the MT7986 SoC will try multiple locations on -the SPI-NAND flash to load bl2 in case the bl2 image located at the the -previously attempted offset is corrupt. - -Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND, -allowing for up to four redundant copies of bl2 (typically sized a -bit less than 0x40000). - -Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3") -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -@@ -29,13 +29,13 @@ - - partition@0 { - label = "bl2"; -- reg = <0x0 0x80000>; -+ reg = <0x0 0x100000>; - read-only; - }; - -- partition@80000 { -+ partition@100000 { - label = "reserved"; -- reg = <0x80000 0x300000>; -+ reg = <0x100000 0x280000>; - }; - - partition@380000 { diff --git a/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch b/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch deleted file mode 100644 index 8cba3b2059c101..00000000000000 --- a/target/linux/mediatek/patches-6.1/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch +++ /dev/null @@ -1,34 +0,0 @@ -From f8ed4088ed9c61ae92193da6130d04c37e7b19f2 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 20 Aug 2023 17:31:33 +0200 -Subject: [PATCH 20/22] arm64: dts: mt7986: define 3W max power to both SFP on - BPI-R3 - -All SFP power supplies are connected to the system VDD33 which is 3v3/8A. -Set 3A per SFP slot to allow SFPs work which need more power than the -default 1W. - -Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -126,6 +126,7 @@ - compatible = "sff,sfp"; - i2c-bus = <&i2c_sfp1>; - los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; -+ maximum-power-milliwatt = <3000>; - mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; - tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; -@@ -137,6 +138,7 @@ - i2c-bus = <&i2c_sfp2>; - los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; -+ maximum-power-milliwatt = <3000>; - tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; - tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; - }; diff --git a/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch b/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch deleted file mode 100644 index 318ca43e13874c..00000000000000 --- a/target/linux/mediatek/patches-6.1/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch +++ /dev/null @@ -1,59 +0,0 @@ -From aa3d6df9803c267725dc72286bb91602b7579882 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 20 Aug 2023 17:31:34 +0200 -Subject: [PATCH 21/22] arm64: dts: mt7986: change cooling trips - -Add Critical and hot trips for emergency system shutdown and limiting -system load. - -Change passive trip to active to make sure fan is activated on the -lowest trip. - -Fixes: 1f5be05132f3 ("arm64: dts: mt7986: add thermal-zones") -Suggested-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++---- - 1 file changed, 16 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -611,22 +611,34 @@ - thermal-sensors = <&thermal 0>; - - trips { -+ cpu_trip_crit: crit { -+ temperature = <125000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu_trip_hot: hot { -+ temperature = <120000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - -- cpu_trip_active_low: active-low { -+ cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - -- cpu_trip_passive: passive { -- temperature = <40000>; -+ cpu_trip_active_low: active-low { -+ temperature = <60000>; - hysteresis = <2000>; -- type = "passive"; -+ type = "active"; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch b/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch deleted file mode 100644 index 7166ab6a1446d4..00000000000000 --- a/target/linux/mediatek/patches-6.1/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6ddf23526955b8dbedfeaa57e691261fd73f9d4e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 20 Aug 2023 17:31:35 +0200 -Subject: [PATCH 22/22] arm64: dts: mt7986: change thermal trips on BPI-R3 - -Apply new naming after mt7986 thermal trips were changed. - -Fixes: c26f779a2295 ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts") -Suggested-by: Daniel Golle -Signed-off-by: Frank Wunderlich ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -152,16 +152,16 @@ - trip = <&cpu_trip_active_high>; - }; - -- cpu-active-low { -+ cpu-active-med { - /* active: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; -- trip = <&cpu_trip_active_low>; -+ trip = <&cpu_trip_active_med>; - }; - -- cpu-passive { -- /* passive: set fan to cooling level 0 */ -+ cpu-active-low { -+ /* active: set fan to cooling level 0 */ - cooling-device = <&fan 0 0>; -- trip = <&cpu_trip_passive>; -+ trip = <&cpu_trip_active_low>; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch b/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch deleted file mode 100644 index bb87c20a91e15e..00000000000000 --- a/target/linux/mediatek/patches-6.1/041-block-fit-partition-parser.patch +++ /dev/null @@ -1,216 +0,0 @@ -From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001 -From: OpenWrt community -Date: Wed, 13 Jul 2022 13:37:33 +0200 -Subject: [PATCH] kernel: add block fit partition parser - ---- - block/blk.h | 2 ++ - block/partitions/Kconfig | 7 +++++++ - block/partitions/Makefile | 1 + - block/partitions/check.h | 3 +++ - block/partitions/core.c | 17 +++++++++++++++++ - block/partitions/efi.c | 8 ++++++++ - block/partitions/efi.h | 3 +++ - block/partitions/msdos.c | 10 ++++++++++ - drivers/mtd/mtd_blkdevs.c | 2 ++ - drivers/mtd/ubi/block.c | 3 +++ - include/linux/msdos_partition.h | 1 + - 11 files changed, 57 insertions(+) - ---- a/block/blk.h -+++ b/block/blk.h -@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min - #define ADDPART_FLAG_NONE 0 - #define ADDPART_FLAG_RAID 1 - #define ADDPART_FLAG_WHOLEDISK 2 -+#define ADDPART_FLAG_READONLY 4 -+#define ADDPART_FLAG_ROOTDEV 8 - int bdev_add_partition(struct gendisk *disk, int partno, sector_t start, - sector_t length); - int bdev_del_partition(struct gendisk *disk, int partno); ---- a/block/partitions/Kconfig -+++ b/block/partitions/Kconfig -@@ -103,6 +103,13 @@ config ATARI_PARTITION - Say Y here if you would like to use hard disks under Linux which - were partitioned under the Atari OS. - -+config FIT_PARTITION -+ bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED -+ default n -+ help -+ Say Y here if your system needs to mount the filesystem part of -+ a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot. -+ - config IBM_PARTITION - bool "IBM disk label and partition support" - depends on PARTITION_ADVANCED && S390 ---- a/block/partitions/Makefile -+++ b/block/partitions/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o - obj-$(CONFIG_AMIGA_PARTITION) += amiga.o - obj-$(CONFIG_ATARI_PARTITION) += atari.o - obj-$(CONFIG_AIX_PARTITION) += aix.o -+obj-$(CONFIG_FIT_PARTITION) += fit.o - obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o - obj-$(CONFIG_MAC_PARTITION) += mac.o - obj-$(CONFIG_LDM_PARTITION) += ldm.o ---- a/block/partitions/check.h -+++ b/block/partitions/check.h -@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit - int atari_partition(struct parsed_partitions *state); - int cmdline_partition(struct parsed_partitions *state); - int efi_partition(struct parsed_partitions *state); -+int fit_partition(struct parsed_partitions *state); - int ibm_partition(struct parsed_partitions *); - int karma_partition(struct parsed_partitions *state); - int ldm_partition(struct parsed_partitions *state); -@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio - int sun_partition(struct parsed_partitions *state); - int sysv68_partition(struct parsed_partitions *state); - int ultrix_partition(struct parsed_partitions *state); -+ -+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain); ---- a/block/partitions/core.c -+++ b/block/partitions/core.c -@@ -11,6 +11,9 @@ - #include - #include - #include -+#ifdef CONFIG_FIT_PARTITION -+#include -+#endif - - #include "check.h" - -@@ -48,6 +51,9 @@ static int (*check_part[])(struct parsed - #ifdef CONFIG_EFI_PARTITION - efi_partition, /* this must come before msdos */ - #endif -+#ifdef CONFIG_FIT_PARTITION -+ fit_partition, -+#endif - #ifdef CONFIG_SGI_PARTITION - sgi_partition, - #endif -@@ -439,6 +445,11 @@ static struct block_device *add_partitio - goto out_del; - } - -+#ifdef CONFIG_FIT_PARTITION -+ if (flags & ADDPART_FLAG_READONLY) -+ bdev->bd_read_only = true; -+#endif -+ - /* everything is up and running, commence */ - err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL); - if (err) -@@ -631,6 +642,11 @@ static bool blk_add_partition(struct gen - (state->parts[p].flags & ADDPART_FLAG_RAID)) - md_autodetect_dev(part->bd_dev); - -+#ifdef CONFIG_FIT_PARTITION -+ if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0) -+ ROOT_DEV = part->bd_dev; -+#endif -+ - return true; - } - ---- a/block/partitions/efi.c -+++ b/block/partitions/efi.c -@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio - gpt_entry *ptes = NULL; - u32 i; - unsigned ssz = queue_logical_block_size(state->disk->queue) / 512; -+#ifdef CONFIG_FIT_PARTITION -+ u32 extra_slot = 64; -+#endif - - if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) { - kfree(gpt); -@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio - ARRAY_SIZE(ptes[i].partition_name)); - utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname); - state->parts[i + 1].has_info = true; -+#ifdef CONFIG_FIT_PARTITION -+ /* If this is a U-Boot FIT volume it may have subpartitions */ -+ if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID)) -+ (void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1); -+#endif - } - kfree(ptes); - kfree(gpt); ---- a/block/partitions/efi.h -+++ b/block/partitions/efi.h -@@ -51,6 +51,9 @@ - #define PARTITION_LINUX_LVM_GUID \ - EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \ - 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28) -+#define PARTITION_LINUX_FIT_GUID \ -+ EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \ -+ 0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93) - - typedef struct _gpt_header { - __le64 signature; ---- a/block/partitions/msdos.c -+++ b/block/partitions/msdos.c -@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa - #endif /* CONFIG_MINIX_SUBPARTITION */ - } - -+static void parse_fit_mbr(struct parsed_partitions *state, -+ sector_t offset, sector_t size, int origin) -+{ -+#ifdef CONFIG_FIT_PARTITION -+ u32 extra_slot = 64; -+ (void) parse_fit_partitions(state, offset, size, &extra_slot, 1); -+#endif /* CONFIG_FIT_PARTITION */ -+} -+ - static struct { - unsigned char id; - void (*parse)(struct parsed_partitions *, sector_t, sector_t, int); -@@ -575,6 +584,7 @@ static struct { - {UNIXWARE_PARTITION, parse_unixware}, - {SOLARIS_X86_PARTITION, parse_solaris_x86}, - {NEW_SOLARIS_X86_PARTITION, parse_solaris_x86}, -+ {FIT_PARTITION, parse_fit_mbr}, - {0, NULL}, - }; - ---- a/drivers/mtd/mtd_blkdevs.c -+++ b/drivers/mtd/mtd_blkdevs.c -@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt - } else { - snprintf(gd->disk_name, sizeof(gd->disk_name), - "%s%d", tr->name, new->devnum); -- gd->flags |= GENHD_FL_NO_PART; -+ -+ if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd)) -+ gd->flags |= GENHD_FL_NO_PART; - } - - set_capacity(gd, ((u64)new->size * tr->blksize) >> 9); ---- a/drivers/mtd/ubi/block.c -+++ b/drivers/mtd/ubi/block.c -@@ -432,7 +432,9 @@ int ubiblock_create(struct ubi_volume_in - ret = -ENODEV; - goto out_cleanup_disk; - } -- gd->flags |= GENHD_FL_NO_PART; -+ if (!IS_ENABLED(CONFIG_FIT_PARTITION)) -+ gd->flags |= GENHD_FL_NO_PART; -+ - gd->private_data = dev; - sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id); - set_capacity(gd, disk_capacity); ---- a/include/linux/msdos_partition.h -+++ b/include/linux/msdos_partition.h -@@ -31,6 +31,7 @@ enum msdos_sys_ind { - LINUX_LVM_PARTITION = 0x8e, - LINUX_RAID_PARTITION = 0xfd, /* autodetect RAID partition */ - -+ FIT_PARTITION = 0x2e, /* U-Boot uImage.FIT */ - SOLARIS_X86_PARTITION = 0x82, /* also Linux swap partitions */ - NEW_SOLARIS_X86_PARTITION = 0xbf, - diff --git a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch deleted file mode 100644 index 1eeed82c1b4a0e..00000000000000 --- a/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch +++ /dev/null @@ -1,107 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -1,7 +1,6 @@ - /* -- * Copyright (c) 2017 MediaTek Inc. -- * Author: Ming Huang -- * Sean Wang -+ * Copyright (c) 2018 MediaTek Inc. -+ * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ -@@ -24,7 +23,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { -@@ -45,18 +44,18 @@ - key-factory { - label = "factory"; - linux,code = ; -- gpios = <&pio 0 0>; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - - key-wps { - label = "wps"; - linux,code = ; -- gpios = <&pio 102 0>; -+ gpios = <&pio 102 GPIO_ACTIVE_LOW>; - }; - }; - - memory@40000000 { -- reg = <0 0x40000000 0 0x20000000>; -+ reg = <0 0x40000000 0 0x40000000>; - device_type = "memory"; - }; - -@@ -133,22 +132,22 @@ - - port@0 { - reg = <0>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@1 { - reg = <1>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@2 { - reg = <2>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@3 { - reg = <3>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@4 { -@@ -241,7 +240,22 @@ - status = "okay"; - }; - -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; -+}; -+ - &pio { -+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -+ * SATA functions. i.e. output-high: PCIe, output-low: SATA -+ */ -+ asm_sel { -+ gpio-hog; -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; -+ - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { -@@ -518,11 +532,11 @@ - }; - - &sata { -- status = "okay"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "okay"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch deleted file mode 100644 index b1770371b00f63..00000000000000 --- a/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -18,6 +18,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; - }; - - gpio-keys { -@@ -70,6 +71,10 @@ - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; -+ -+ nvmem-cells = <&macaddr_factory_2a>; -+ nvmem-cell-names = "mac-address"; -+ - fixed-link { - speed = <2500>; - full-duplex; -@@ -82,6 +87,9 @@ - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; -+ -+ nvmem-cells = <&macaddr_factory_24>; -+ nvmem-cell-names = "mac-address"; - }; - - mdio: mdio-bus { -@@ -133,8 +141,9 @@ - }; - - partition@b0000 { -- label = "kernel"; -+ label = "firmware"; - reg = <0xb0000 0xb50000>; -+ compatible = "denx,fit"; - }; - }; - }; -@@ -273,3 +282,17 @@ - pinctrl-0 = <&watchdog_pins>; - status = "okay"; - }; -+ -+&factory { -+ compatible = "nvmem-cells"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_factory_24: macaddr@24 { -+ reg = <0x24 0x6>; -+ }; -+ -+ macaddr_factory_2a: macaddr@2a { -+ reg = <0x2a 0x6>; -+ }; -+}; diff --git a/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch deleted file mode 100644 index 04df7b927b1cb0..00000000000000 --- a/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch +++ /dev/null @@ -1,20 +0,0 @@ -From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Fri, 29 Apr 2022 10:40:56 +0800 -Subject: [PATCH] arm: mediatek: select arch timer for mt7623 - -Signed-off-by: Chuanhong Guo ---- - arch/arm/mach-mediatek/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -26,6 +26,7 @@ config MACH_MT6592 - config MACH_MT7623 - bool "MediaTek MT7623 SoCs support" - default ARCH_MEDIATEK -+ select HAVE_ARM_ARCH_TIMER - - config MACH_MT7629 - bool "MediaTek MT7629 SoCs support" diff --git a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch deleted file mode 100644 index 0d9c91f44dd712..00000000000000 --- a/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -578,6 +578,7 @@ - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; -+ interrupts = ; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; diff --git a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch deleted file mode 100644 index 93da722e72419c..00000000000000 --- a/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -134,6 +134,13 @@ - #size-cells = <2>; - ranges; - -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch b/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch deleted file mode 100644 index ac8594b3963f45..00000000000000 --- a/target/linux/mediatek/patches-6.1/106-dts-mt7622-disable_btif.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -109,10 +109,6 @@ - status = "disabled"; - }; - --&btif { -- status = "okay"; --}; -- - &cir { - pinctrl-names = "default"; - pinctrl-0 = <&irrx_pins>; ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -90,10 +90,6 @@ - status = "disabled"; - }; - --&btif { -- status = "okay"; --}; -- - &cir { - pinctrl-names = "default"; - pinctrl-0 = <&irrx_pins>; diff --git a/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch deleted file mode 100644 index 8dc53d2985fac5..00000000000000 --- a/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,6 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -+ bootargs = "console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch deleted file mode 100644 index f77f10cb955159..00000000000000 --- a/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -24,7 +24,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { diff --git a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch deleted file mode 100644 index 2cc0efdadecd80..00000000000000 --- a/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -20,6 +20,7 @@ - - aliases { - serial0 = &uart0; -+ ethernet0 = &gmac0; - }; - - chosen { -@@ -161,22 +162,22 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@6 { diff --git a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch deleted file mode 100644 index 1cca6f353410f2..00000000000000 --- a/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch +++ /dev/null @@ -1,49 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -21,6 +21,12 @@ - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { -@@ -44,8 +50,8 @@ - compatible = "gpio-keys"; - - factory-key { -- label = "factory"; -- linux,code = ; -+ label = "reset"; -+ linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - -@@ -59,17 +65,17 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ led_system_green: led-0 { - label = "bpi-r64:pio:green"; - color = ; - gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - -- led-1 { -- label = "bpi-r64:pio:red"; -- color = ; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ led_system_blue: led-1 { -+ label = "bpi-r64:pio:blue"; -+ color = ; -+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch deleted file mode 100644 index 119de1c4576800..00000000000000 --- a/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -557,12 +557,16 @@ - status = "okay"; - }; - -+&rtc { -+ status = "disabled"; -+}; -+ - &sata { -- status = "disable"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "disable"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch b/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch deleted file mode 100644 index 6eac51f825b188..00000000000000 --- a/target/linux/mediatek/patches-6.1/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch +++ /dev/null @@ -1,70 +0,0 @@ -From d278f43f25beedfd0cb784d1dd0a9e7e8c8f123f Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 19 Apr 2023 20:15:53 +0100 -Subject: [PATCH] arm64: dts: mt7622: declare SPI-NAND present on BPI-R64 - -The SPI-NOR node in the device tree of the BananaPi R64 has most likely -been copied from the reference board's device tree even though the R64 -comes with an SPI-NAND chip rather than SPI-NOR. - -Setup the Serial NAND Flash Interface (SNFI) controller, enable -hardware BCH error detection and correction engine and add the SPI-NAND -chip including basic partitions, - -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/ZEA96dmaXqTpk8u8@makrotopia.org -Signed-off-by: Matthias Brugger ---- - .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 38 ++++++++++++++++--- - 1 file changed, 33 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -254,14 +254,42 @@ - status = "disabled"; - }; - --&nor_flash { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -+&bch { -+ status = "okay"; -+}; - -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; - flash@0 { -- compatible = "jedec,spi-nor"; -+ compatible = "spi-nand"; - reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; -+ -+ ubi: partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch deleted file mode 100644 index ff5521c44eafd5..00000000000000 --- a/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_ - static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) - { - struct spinand_device *spinand = nand_to_spinand(nand); -- u8 marker[2] = { }; -+ u8 marker[1] = { }; - struct nand_page_io_req req = { - .pos = *pos, - .ooblen = sizeof(marker), -@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de - - spinand_select_target(spinand, pos->target); - spinand_read_page(spinand, &req); -- if (marker[0] != 0xff || marker[1] != 0xff) -+ if (marker[0] != 0xff) - return true; - - return false; diff --git a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch deleted file mode 100644 index 82654e683c3605..00000000000000 --- a/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch +++ /dev/null @@ -1,94 +0,0 @@ -From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 -From: Xiangsheng Hou -Date: Thu, 6 Jun 2019 16:29:04 +0800 -Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 - -Signed-off-by: Xiangsheng Hou ---- - arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++ - 3 files changed, 79 insertions(+) - ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,27 @@ - status = "disabled"; - }; - -+ snfi: spi@1100d000 { -+ compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; -+ clock-names = "nfi_clk", "pad_clk"; -+ nand-ecc-engine = <&bch>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ bch: ecc@1100e000 { -+ compatible = "mediatek,mt7622-ecc"; -+ reg = <0x1100e000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfiecc_clk"; -+ status = "disabled"; -+ }; -+ - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -255,6 +255,50 @@ - }; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; -+ -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; diff --git a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch deleted file mode 100644 index 1a0e3237c8a538..00000000000000 --- a/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -535,6 +535,65 @@ - status = "disabled"; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; -+ -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; -+ -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; -+ -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; diff --git a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch deleted file mode 100644 index 208046ad16c979..00000000000000 --- a/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -576,7 +576,7 @@ - reg = <0x140000 0x0080000>; - }; - -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -637,5 +637,6 @@ - &wmac { - pinctrl-names = "default"; - pinctrl-0 = <&wmac_pins>; -+ mediatek,mtd-eeprom = <&factory 0x0000>; - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch deleted file mode 100644 index 0860a22c37fae2..00000000000000 --- a/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -984,17 +984,15 @@ - }; - - crypto: crypto@1b240000 { -- compatible = "mediatek,eip97-crypto"; -+ compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , -- , -- ; -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; -- clock-names = "cryp"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; -- status = "disabled"; -+ status = "okay"; - }; - - bdpsys: syscon@1c000000 { diff --git a/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch deleted file mode 100644 index 091cffc3c07c1f..00000000000000 --- a/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,7 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "console=ttyS2,115200n8 console=tty1"; -+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch deleted file mode 100644 index d1bafc15260903..00000000000000 --- a/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,8 @@ - - aliases { - serial2 = &uart2; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { diff --git a/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch deleted file mode 100644 index f6745add5b380d..00000000000000 --- a/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -17,6 +17,10 @@ - serial2 = &uart2; - mmc0 = &mmc0; - mmc1 = &mmc1; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -112,13 +116,13 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - -- blue { -+ led_system_blue: blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - -- green { -+ led_system_green: green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; diff --git a/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch deleted file mode 100644 index b1dd75a41400a6..00000000000000 --- a/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,7 @@ - - aliases { - serial2 = &uart2; -+ ethernet0 = &gmac0; - mmc0 = &mmc0; - mmc1 = &mmc1; - led-boot = &led_system_green; diff --git a/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch b/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch deleted file mode 100644 index f617211c9aa441..00000000000000 --- a/target/linux/mediatek/patches-6.1/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch +++ /dev/null @@ -1,55 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -26,7 +26,9 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; -+ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; -+ rootdisk-emmc = <&emmc_rootdisk>; -+ rootdisk-sd = <&sd_rootdisk>; - }; - - connector { -@@ -315,6 +317,20 @@ - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ block { -+ compatible = "block-device"; -+ partitions { -+ emmc_rootdisk: block-partition-fit { -+ partno = <3>; -+ }; -+ }; -+ }; -+ }; - }; - - &mmc1 { -@@ -328,6 +344,20 @@ - cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ block { -+ compatible = "block-device"; -+ partitions { -+ sd_rootdisk: block-partition-fit { -+ partno = <3>; -+ }; -+ }; -+ }; -+ }; - }; - - &mt6323_leds { diff --git a/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch b/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch deleted file mode 100644 index d396d38f203c6b..00000000000000 --- a/target/linux/mediatek/patches-6.1/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 983f37ee08acb60435744f1b1e2afea2d2a09c48 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 19 Apr 2023 20:16:29 +0100 -Subject: [PATCH] arm64: dts: mt7622: handle interrupts from MT7531 switch on - BPI-R64 - -Since commit ba751e28d442 ("net: dsa: mt7530: add interrupt support") -the mt7530 driver can act as an interrupt controller. Wire up irq line -of the MT7531 switch on the BananaPi BPi-R64 board, so the status of -the PHYs of the five 1000Base-T ports doesn't need to be polled any -more. - -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/ZEA-DV_OsmFg5egL@makrotopia.org -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -155,6 +155,10 @@ - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 54 0>; - - ports { diff --git a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch deleted file mode 100644 index 1e04d23a0e9804..00000000000000 --- a/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch +++ /dev/null @@ -1,106 +0,0 @@ -From patchwork Tue Apr 26 19:51:36 2022 -Content-Type: text/plain; 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bh=OWGSxvlKoyPWz6b629RNINucULo6oOdFssAIiJETWRg=; b=T0HEjee0FX3hlb - x5jl7xLK5sKM0pkE2oRgwzthbFlNg8ST1j/2GkgcgT0S2Bi0vRfFxHeu/RKzS9RmiVnKJnPGL8ctg - WoBLyO5i+NcmosGoy6MmoOjGTNhj/+3q3Z1jRLBSJ4ySSP22X77YeuJTmVzySPUllQhWvDhjMVCR9 - QBRmQdc6gCAg3IYGEbWwS2TG+UHveDCeZRWxMzrwI8UPadNCRFROwugmiQ3mdU41lHCTDpnlfuRJh - o1igLKfMBLz+D8rFYvDh7FfkcKkY6lNoswA2HKUun1MEzgoyQKmITPnG2maX/BvJJuj/B3ZJShh4k - AZHmXoQxq1mrsm2FxfnQ==; -Received: from localhost ([::1] helo=bombadil.infradead.org) - by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) - id 1njRE5-00G05D-9z; Tue, 26 Apr 2022 19:51:57 +0000 -Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000 -Received: from local - by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) - (Exim 4.94.2) (envelope-from ) - id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200 -Date: Tue, 26 Apr 2022 20:51:36 +0100 -From: Daniel Golle -To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, - linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org -Cc: Rob Herring , - Krzysztof Kozlowski , - Matthias Brugger -Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range -Message-ID: -MIME-Version: 1.0 -Content-Disposition: inline -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C -X-CRM114-Status: GOOD ( 12.45 ) -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - -With the current range specified for the CPU interface there is an -error message at boot: - -GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set - -Setting irqchip.gicv2_force_probe=1 in bootargs results in: - -GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB -GIC: Adjusting CPU interface base to 0x000000001032f000 -GIC: Using split EOI/Deactivate mode - -Using the adjusted CPU interface base and 8K size results in only the -final line remaining and fully working system as well as /proc/interrupts -showing additional IPI3,4,5,6: - -IPI3: 0 0 CPU stop (for crash dump) interrupts -IPI4: 0 0 Timer broadcast interrupts -IPI5: 0 0 IRQ work interrupts -IPI6: 0 0 CPU wake-up interrupts - -Signed-off-by: Daniel Golle ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -346,7 +346,7 @@ - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10310000 0 0x1000>, -- <0 0x10320000 0 0x1000>, -+ <0 0x1032f000 0 0x2000>, - <0 0x10340000 0 0x2000>, - <0 0x10360000 0 0x2000>; - }; diff --git a/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch b/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch deleted file mode 100644 index 1cfb53d6208918..00000000000000 --- a/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001 -From: Bruno Umuarama -Date: Thu, 13 Oct 2022 21:18:21 +0000 -Subject: [PATCH] mediatek: mt7623: fix thermal zone -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Raising the temperatures for passive and active trips. @VA1DER -proposed at issue 9396 to remove passive trip. This commit relates to -his suggestion. - -Without this patch. the CPU will be throttled all the way down to 98MHz -if the temperature rises even a degree above the trip point, and it was -further discovered that if the internal temperature of the device is -above the first trip point temperature when it boots then it will start -in a throttled state and even -$ echo disabled > /sys/class/thermal/thermal_zone0/mode -will have no effect. - -The patch increases the passive trip point and active cooling map. The -throttling temperature will then be at 77°C and 82°C, which is still a -low enough temperature for ARM devices to not be in the real danger -zone, and gives some operational headroom. - -Signed-off-by: Bruno Umuarama ---- - arch/arm/boot/dts/mt7623.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -160,13 +160,13 @@ - - trips { - cpu_passive: cpu-passive { -- temperature = <57000>; -+ temperature = <77000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { -- temperature = <67000>; -+ temperature = <82000>; - hysteresis = <2000>; - type = "active"; - }; diff --git a/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch b/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch deleted file mode 100644 index 161c1e75168cff..00000000000000 --- a/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch +++ /dev/null @@ -1,17 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -68,6 +68,14 @@ - #address-cells = <2>; - #size-cells = <2>; - ranges; -+ -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch deleted file mode 100644 index 336920bafea67a..00000000000000 --- a/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch +++ /dev/null @@ -1,196 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -23,6 +23,10 @@ - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; -+ led-boot = &green_led; -+ led-failsafe = &green_led; -+ led-running = &green_led; -+ led-upgrade = &blue_led; - }; - - chosen { -@@ -419,27 +423,27 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port5: port@5 { - reg = <5>; -- label = "lan4"; -+ label = "sfp2"; - phy-mode = "2500base-x"; - sfp = <&sfp2>; - managed = "in-band-status"; -@@ -490,9 +494,137 @@ - - &wifi { - status = "okay"; -- pinctrl-names = "default", "dbdc"; -+ pinctrl-names = "default"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; -- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+ -+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 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0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; - - led { - led-active-low; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -55,6 +55,7 @@ - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; -+ compatible = "denx,fit"; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch b/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch deleted file mode 100644 index 38510c0fc7911a..00000000000000 --- a/target/linux/mediatek/patches-6.1/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch +++ /dev/null @@ -1,131 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso -@@ -23,7 +23,27 @@ - no-sd; - no-sdio; - status = "okay"; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ block { -+ compatible = "block-device"; -+ partitions { -+ emmc_rootdisk: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+ }; - }; - }; --}; - -+ fragment@1 { -+ target-path = "/chosen"; -+ __overlay__ { -+ rootdisk-emmc = <&emmc_rootdisk>; -+ }; -+ }; -+}; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -@@ -29,27 +29,30 @@ - - partition@0 { - label = "bl2"; -- reg = <0x0 0x100000>; -+ reg = <0x0 0x200000>; - read-only; - }; - -- partition@100000 { -- label = "reserved"; -- reg = <0x100000 0x280000>; -- }; -- -- partition@380000 { -- label = "fip"; -- reg = <0x380000 0x200000>; -- read-only; -- }; -- -- partition@580000 { -+ partition@200000 { - label = "ubi"; -- reg = <0x580000 0x7a80000>; -+ reg = <0x200000 0x7e00000>; -+ compatible = "linux,ubi"; -+ -+ volumes { -+ nand_rootdisk: ubi-volume-fit { -+ volname = "fit"; -+ }; -+ }; - }; - }; - }; - }; - }; -+ -+ fragment@1 { -+ target-path = "/chosen"; -+ __overlay__ { -+ rootdisk-spim-nand = <&nand_rootdisk>; -+ }; -+ }; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -52,7 +52,7 @@ - reg = <0x180000 0xa80000>; - }; - -- partition@c00000 { -+ nor_rootdisk: partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; - compatible = "denx,fit"; -@@ -61,4 +61,11 @@ - }; - }; - }; -+ -+ fragment@1 { -+ target-path = "/chosen"; -+ __overlay__ { -+ rootdisk-nor = <&nor_rootdisk>; -+ }; -+ }; - }; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso -@@ -17,6 +17,27 @@ - max-frequency = <52000000>; - cap-sd-highspeed; - status = "okay"; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ block { -+ compatible = "block-device"; -+ partitions { -+ sd_rootdisk: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target-path = "/chosen"; -+ __overlay__ { -+ rootdisk-sd = <&sd_rootdisk>; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch deleted file mode 100644 index 6347533aa8f883..00000000000000 --- a/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 -From: Kristian Evensen -Date: Mon, 30 Apr 2018 14:38:01 +0200 -Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support - ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -17,6 +17,8 @@ - #include - #include - #include -+#include -+#include - - #include "phy-mtk-io.h" - -@@ -264,6 +266,9 @@ - - #define TPHY_CLKS_CNT 2 - -+#define HIF_SYSCFG1 0x14 -+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) -+ - enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, -@@ -331,6 +336,7 @@ struct mtk_tphy { - void __iomem *sif_base; /* only shared sif */ - const struct mtk_phy_pdata *pdata; - struct mtk_phy_instance **phys; -+ struct regmap *hif; - int nphys; - int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ - int src_coef; /* coefficient for slew rate calibrate */ -@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc - if (tphy->pdata->version != MTK_PHY_V1) - return; - -+ if (tphy->hif) -+ regmap_update_bits(tphy->hif, HIF_SYSCFG1, -+ HIF_SYSCFG1_PHY2_MASK, 0); -+ - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, - P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, - FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | -@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor - &tphy->src_coef); - } - -+ if (of_find_property(np, "mediatek,phy-switch", NULL)) { -+ tphy->hif = syscon_regmap_lookup_by_phandle(np, -+ "mediatek,phy-switch"); -+ if (IS_ERR(tphy->hif)) { -+ dev_err(&pdev->dev, -+ "missing \"mediatek,phy-switch\" phandle\n"); -+ return PTR_ERR(tphy->hif); -+ } -+ } -+ - port = 0; - for_each_child_of_node(np, child_np) { - struct mtk_phy_instance *instance; diff --git a/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch b/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch deleted file mode 100644 index 3e16a533e1bb07..00000000000000 --- a/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch +++ /dev/null @@ -1,88 +0,0 @@ -From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sat, 8 Oct 2022 18:48:06 +0200 -Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts - separately - -Some mt7986 boards use uart rts/cts pins as gpio, -This patch allows to change rts/cts to gpio mode, but keep -rx/tx as UART function. - -Signed-off-by: Frank Wunderlich -Signed-off-by: Sam Shih -Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++----- - 1 file changed, 25 insertions(+), 7 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4, - static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; - static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; --static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; -+static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; -+static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; - --static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; --static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; -+static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; -+static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; -+ -+static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; -+static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; -+ -+static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; -+static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; - - static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; - static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; -@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = { - static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; - static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; - -+static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; -+static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; -+ -+static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; -+static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; -+ - static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; - static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; - -@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr - PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), - PINCTRL_PIN_GROUP("i2c", mt7986_i2c), - PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), -+ PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), -+ PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), - PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), - PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), - PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), -@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr - PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), - PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), - PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), -- PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), -- PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), -+ PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), -+ PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), -+ PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), -+ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), - PINCTRL_PIN_GROUP("spi0", mt7986_spi0), - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), - PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), -@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] = - static const char *mt7986_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; - static const char *mt7986_uart_groups[] = { -- "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", -+ "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", -+ "uart1_2_rx_tx", "uart1_2_cts_rts", -+ "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", - "uart2_0", "uart2_1", "uart0", "uart1", "uart2", - }; - static const char *mt7986_wdt_groups[] = { "watchdog", }; diff --git a/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch b/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch deleted file mode 100644 index 47ded1aeb5f25b..00000000000000 --- a/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:01:13 +0100 -Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek - MT7986 SoC - -Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -add SoC specify 'pull_type' attribute for bias configuration. - -This patch add pull_type attribute to pinctrl-mt7986.c, and make -bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++ - 1 file changed, 56 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), - }; - -+static const unsigned int mt7986_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ -+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ -+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ -+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ -+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ -+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ -+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ -+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ -+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ -+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ -+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ -+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ -+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ -+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ -+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ -+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ -+ MTK_PULL_PU_PD_TYPE,/*100*/ -+}; -+ - static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), -@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, -@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, diff --git a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch b/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch deleted file mode 100644 index 46dfa24b7b7b52..00000000000000 --- a/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch +++ /dev/null @@ -1,1094 +0,0 @@ -From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 00:34:56 +0000 -Subject: [PATCH] pinctrl: add mt7981 pinctrl driver - -Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver -which can also be found the SDK. - -Signed-off-by: Daniel Golle -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/Kconfig | 5 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++ - 3 files changed, 1054 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -127,6 +127,11 @@ config PINCTRL_MT7622 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7981 -+ bool "Mediatek MT7981 pin control" -+ depends on OF -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT7986 - bool "Mediatek MT7986 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -+obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -0,0 +1,1048 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * The MT7981 driver based on Linux generic pinctrl binding. -+ * -+ * Copyright (C) 2020 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include "pinctrl-moore.h" -+ -+#define MT7981_PIN(_number, _name) \ -+ MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 1) -+ -+static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { -+ PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { -+ PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { -+ PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { -+ PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { -+ PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { -+ PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), -+ -+ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), -+ -+ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), -+}; -+ -+static const unsigned int mt7981_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ -+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ -+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ -+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ -+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ -+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ -+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ -+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ -+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ -+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ -+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ -+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ -+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ -+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ -+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ -+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ -+ MTK_PULL_PU_PD_TYPE,/*100*/ -+}; -+ -+static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7981_pins[] = { -+ MT7981_PIN(0, "GPIO_WPS"), -+ MT7981_PIN(1, "GPIO_RESET"), -+ MT7981_PIN(2, "SYS_WATCHDOG"), -+ MT7981_PIN(3, "PCIE_PERESET_N"), -+ MT7981_PIN(4, "JTAG_JTDO"), -+ MT7981_PIN(5, "JTAG_JTDI"), -+ MT7981_PIN(6, "JTAG_JTMS"), -+ MT7981_PIN(7, "JTAG_JTCLK"), -+ MT7981_PIN(8, "JTAG_JTRST_N"), -+ MT7981_PIN(9, "WO_JTAG_JTDO"), -+ MT7981_PIN(10, "WO_JTAG_JTDI"), -+ MT7981_PIN(11, "WO_JTAG_JTMS"), -+ MT7981_PIN(12, "WO_JTAG_JTCLK"), -+ MT7981_PIN(13, "WO_JTAG_JTRST_N"), -+ MT7981_PIN(14, "USB_VBUS"), -+ MT7981_PIN(15, "PWM0"), -+ MT7981_PIN(16, "SPI0_CLK"), -+ MT7981_PIN(17, "SPI0_MOSI"), -+ MT7981_PIN(18, "SPI0_MISO"), -+ MT7981_PIN(19, "SPI0_CS"), -+ MT7981_PIN(20, "SPI0_HOLD"), -+ MT7981_PIN(21, "SPI0_WP"), -+ MT7981_PIN(22, "SPI1_CLK"), -+ MT7981_PIN(23, "SPI1_MOSI"), -+ MT7981_PIN(24, "SPI1_MISO"), -+ MT7981_PIN(25, "SPI1_CS"), -+ MT7981_PIN(26, "SPI2_CLK"), -+ MT7981_PIN(27, "SPI2_MOSI"), -+ MT7981_PIN(28, "SPI2_MISO"), -+ MT7981_PIN(29, "SPI2_CS"), -+ MT7981_PIN(30, "SPI2_HOLD"), -+ MT7981_PIN(31, "SPI2_WP"), -+ MT7981_PIN(32, "UART0_RXD"), -+ MT7981_PIN(33, "UART0_TXD"), -+ MT7981_PIN(34, "PCIE_CLK_REQ"), -+ MT7981_PIN(35, "PCIE_WAKE_N"), -+ MT7981_PIN(36, "SMI_MDC"), -+ MT7981_PIN(37, "SMI_MDIO"), -+ MT7981_PIN(38, "GBE_INT"), -+ MT7981_PIN(39, "GBE_RESET"), -+ MT7981_PIN(40, "WF_DIG_RESETB"), -+ MT7981_PIN(41, "WF_CBA_RESETB"), -+ MT7981_PIN(42, "WF_XO_REQ"), -+ MT7981_PIN(43, "WF_TOP_CLK"), -+ MT7981_PIN(44, "WF_TOP_DATA"), -+ MT7981_PIN(45, "WF_HB1"), -+ MT7981_PIN(46, "WF_HB2"), -+ MT7981_PIN(47, "WF_HB3"), -+ MT7981_PIN(48, "WF_HB4"), -+ MT7981_PIN(49, "WF_HB0"), -+ MT7981_PIN(50, "WF_HB0_B"), -+ MT7981_PIN(51, "WF_HB5"), -+ MT7981_PIN(52, "WF_HB6"), -+ MT7981_PIN(53, "WF_HB7"), -+ MT7981_PIN(54, "WF_HB8"), -+ MT7981_PIN(55, "WF_HB9"), -+ MT7981_PIN(56, "WF_HB10"), -+}; -+ -+/* List all groups consisting of these pins dedicated to the enablement of -+ * certain hardware block and the corresponding mode for all of the pins. -+ * The hardware probably has multiple combinations of these pinouts. -+ */ -+ -+/* WA_AICE */ -+static int mt7981_wa_aice1_pins[] = { 0, 1, }; -+static int mt7981_wa_aice1_funcs[] = { 2, 2, }; -+ -+static int mt7981_wa_aice2_pins[] = { 0, 1, }; -+static int mt7981_wa_aice2_funcs[] = { 3, 3, }; -+ -+static int mt7981_wa_aice3_pins[] = { 28, 29, }; -+static int mt7981_wa_aice3_funcs[] = { 3, 3, }; -+ -+static int mt7981_wm_aice1_pins[] = { 9, 10, }; -+static int mt7981_wm_aice1_funcs[] = { 2, 2, }; -+ -+static int mt7981_wm_aice2_pins[] = { 30, 31, }; -+static int mt7981_wm_aice2_funcs[] = { 5, 5, }; -+ -+/* WM_UART */ -+static int mt7981_wm_uart_0_pins[] = { 0, 1, }; -+static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; -+ -+static int mt7981_wm_uart_1_pins[] = { 20, 21, }; -+static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; -+ -+static int mt7981_wm_uart_2_pins[] = { 30, 31, }; -+static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; -+ -+/* DFD */ -+static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; -+static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; -+ -+/* SYS_WATCHDOG */ -+static int mt7981_watchdog_pins[] = { 2, }; -+static int mt7981_watchdog_funcs[] = { 1, }; -+ -+static int mt7981_watchdog1_pins[] = { 13, }; -+static int mt7981_watchdog1_funcs[] = { 5, }; -+ -+/* PCIE_PERESET_N */ -+static int mt7981_pcie_pereset_pins[] = { 3, }; -+static int mt7981_pcie_pereset_funcs[] = { 1, }; -+ -+/* JTAG */ -+static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; -+static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; -+ -+/* WM_JTAG */ -+static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; -+static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; -+ -+static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; -+static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+ -+/* WO0_JTAG */ -+static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; -+static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; -+ -+static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; -+static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+ -+/* UART2 */ -+static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; -+static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; -+ -+/* GBE_LED0 */ -+static int mt7981_gbe_led0_pins[] = { 8, }; -+static int mt7981_gbe_led0_funcs[] = { 3, }; -+ -+/* PTA_EXT */ -+static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; -+static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; -+ -+static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; -+static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; -+ -+/* PWM2 */ -+static int mt7981_pwm2_pins[] = { 7, }; -+static int mt7981_pwm2_funcs[] = { 4, }; -+ -+/* NET_WO0_UART_TXD */ -+static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; -+static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; -+ -+static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; -+static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; -+ -+static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; -+static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; -+ -+/* SPI1 */ -+static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; -+static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; -+ -+/* I2C */ -+static int mt7981_i2c0_0_pins[] = { 6, 7, }; -+static int mt7981_i2c0_0_funcs[] = { 6, 6, }; -+ -+static int mt7981_i2c0_1_pins[] = { 30, 31, }; -+static int mt7981_i2c0_1_funcs[] = { 4, 4, }; -+ -+static int mt7981_i2c0_2_pins[] = { 36, 37, }; -+static int mt7981_i2c0_2_funcs[] = { 2, 2, }; -+ -+static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; -+static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; -+ -+static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; -+ -+static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; -+ -+static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; -+ -+/* DFD_NTRST */ -+static int mt7981_dfd_ntrst_pins[] = { 8, }; -+static int mt7981_dfd_ntrst_funcs[] = { 6, }; -+ -+/* PWM0 */ -+static int mt7981_pwm0_0_pins[] = { 13, }; -+static int mt7981_pwm0_0_funcs[] = { 2, }; -+ -+static int mt7981_pwm0_1_pins[] = { 15, }; -+static int mt7981_pwm0_1_funcs[] = { 1, }; -+ -+/* PWM1 */ -+static int mt7981_pwm1_0_pins[] = { 14, }; -+static int mt7981_pwm1_0_funcs[] = { 2, }; -+ -+static int mt7981_pwm1_1_pins[] = { 15, }; -+static int mt7981_pwm1_1_funcs[] = { 3, }; -+ -+/* GBE_LED1 */ -+static int mt7981_gbe_led1_pins[] = { 13, }; -+static int mt7981_gbe_led1_funcs[] = { 3, }; -+ -+/* PCM */ -+static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; -+static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; -+ -+/* UDI */ -+static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; -+static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; -+ -+/* DRV_VBUS */ -+static int mt7981_drv_vbus_pins[] = { 14, }; -+static int mt7981_drv_vbus_funcs[] = { 1, }; -+ -+/* EMMC */ -+static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -+static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ -+/* SNFI */ -+static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; -+static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; -+ -+/* SPI0 */ -+static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; -+static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI0 */ -+static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; -+static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; -+ -+/* SPI1 */ -+static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; -+static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI2 */ -+static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; -+static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI2 */ -+static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; -+static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; -+ -+/* UART1 */ -+static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; -+static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; -+ -+static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; -+static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; -+ -+/* UART2 */ -+static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; -+static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -+ -+/* UART0 */ -+static int mt7981_uart0_pins[] = { 32, 33, }; -+static int mt7981_uart0_funcs[] = { 1, 1, }; -+ -+/* PCIE_CLK_REQ */ -+static int mt7981_pcie_clk_pins[] = { 34, }; -+static int mt7981_pcie_clk_funcs[] = { 2, }; -+ -+/* PCIE_WAKE_N */ -+static int mt7981_pcie_wake_pins[] = { 35, }; -+static int mt7981_pcie_wake_funcs[] = { 2, }; -+ -+/* MDC_MDIO */ -+static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; -+static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; -+ -+static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; -+static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; -+ -+/* WF0_MODE1 */ -+static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; -+static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; -+ -+/* WF0_MODE3 */ -+static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; -+static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+ -+/* WF2G_LED */ -+static int mt7981_wf2g_led0_pins[] = { 30, }; -+static int mt7981_wf2g_led0_funcs[] = { 2, }; -+ -+static int mt7981_wf2g_led1_pins[] = { 34, }; -+static int mt7981_wf2g_led1_funcs[] = { 1, }; -+ -+/* WF5G_LED */ -+static int mt7981_wf5g_led0_pins[] = { 31, }; -+static int mt7981_wf5g_led0_funcs[] = { 2, }; -+ -+static int mt7981_wf5g_led1_pins[] = { 35, }; -+static int mt7981_wf5g_led1_funcs[] = { 1, }; -+ -+/* MT7531_INT */ -+static int mt7981_mt7531_int_pins[] = { 38, }; -+static int mt7981_mt7531_int_funcs[] = { 1, }; -+ -+/* ANT_SEL */ -+static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; -+static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; -+ -+static const struct group_desc mt7981_groups[] = { -+ /* @GPIO(0,1): WA_AICE(2) */ -+ PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), -+ /* @GPIO(0,1): WA_AICE(3) */ -+ PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), -+ /* @GPIO(0,1): WM_UART(5) */ -+ PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), -+ /* @GPIO(0,1,4,5): DFD(6) */ -+ PINCTRL_PIN_GROUP("dfd", mt7981_dfd), -+ /* @GPIO(2): SYS_WATCHDOG(1) */ -+ PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), -+ /* @GPIO(3): PCIE_PERESET_N(1) */ -+ PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), -+ /* @GPIO(4,8) JTAG(1) */ -+ PINCTRL_PIN_GROUP("jtag", mt7981_jtag), -+ /* @GPIO(4,8) WM_JTAG(2) */ -+ PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), -+ /* @GPIO(9,13) WO0_JTAG(1) */ -+ PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), -+ /* @GPIO(4,7) WM_JTAG(3) */ -+ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), -+ /* @GPIO(8) GBE_LED0(3) */ -+ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), -+ /* @GPIO(4,6) PTA_EXT(4) */ -+ PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), -+ /* @GPIO(7) PWM2(4) */ -+ PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), -+ /* @GPIO(8) NET_WO0_UART_TXD(4) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), -+ /* @GPIO(4,7) SPI1(5) */ -+ PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), -+ /* @GPIO(6,7) I2C(5) */ -+ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), -+ /* @GPIO(0,1,4,5): DFD_NTRST(6) */ -+ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), -+ /* @GPIO(9,10): WM_AICE(2) */ -+ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), -+ /* @GPIO(13): PWM0(2) */ -+ PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), -+ /* @GPIO(15): PWM0(1) */ -+ PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), -+ /* @GPIO(14): PWM1(2) */ -+ PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), -+ /* @GPIO(15): PWM1(3) */ -+ PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), -+ /* @GPIO(14) NET_WO0_UART_TXD(3) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), -+ /* @GPIO(15) NET_WO0_UART_TXD(4) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), -+ /* @GPIO(13) GBE_LED0(3) */ -+ PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), -+ /* @GPIO(9,13) PCM(4) */ -+ PINCTRL_PIN_GROUP("pcm", mt7981_pcm), -+ /* @GPIO(13): SYS_WATCHDOG1(5) */ -+ PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), -+ /* @GPIO(9,13) UDI(4) */ -+ PINCTRL_PIN_GROUP("udi", mt7981_udi), -+ /* @GPIO(14) DRV_VBUS(1) */ -+ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), -+ /* @GPIO(15,25): EMMC(2) */ -+ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), -+ /* @GPIO(16,21): SNFI(3) */ -+ PINCTRL_PIN_GROUP("snfi", mt7981_snfi), -+ /* @GPIO(16,19): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi0", mt7981_spi0), -+ /* @GPIO(20,21): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), -+ /* @GPIO(22,25) SPI1(1) */ -+ PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), -+ /* @GPIO(26,29): SPI2(1) */ -+ PINCTRL_PIN_GROUP("spi2", mt7981_spi2), -+ /* @GPIO(30,31): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), -+ /* @GPIO(16,19): UART1(4) */ -+ PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), -+ /* @GPIO(26,29): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), -+ /* @GPIO(22,25): UART1(3) */ -+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), -+ /* @GPIO(22,24) PTA_EXT(4) */ -+ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), -+ /* @GPIO(20,21): WM_UART(4) */ -+ PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), -+ /* @GPIO(30,31): WM_UART(3) */ -+ PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), -+ /* @GPIO(20,24) WM_JTAG(5) */ -+ PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), -+ /* @GPIO(25,29) WO0_JTAG(5) */ -+ PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), -+ /* @GPIO(28,29): WA_AICE(3) */ -+ PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), -+ /* @GPIO(30,31): WM_AICE(5) */ -+ PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), -+ /* @GPIO(30,31): I2C(4) */ -+ PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), -+ /* @GPIO(30,31): I2C(6) */ -+ PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), -+ /* @GPIO(32,33): I2C(1) */ -+ PINCTRL_PIN_GROUP("uart0", mt7981_uart0), -+ /* @GPIO(32,33): I2C(2) */ -+ PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), -+ /* @GPIO(32,33): I2C(3) */ -+ PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), -+ /* @GPIO(32,33): I2C(5) */ -+ PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), -+ /* @GPIO(34): PCIE_CLK_REQ(2) */ -+ PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), -+ /* @GPIO(35): PCIE_WAKE_N(2) */ -+ PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), -+ /* @GPIO(36,37): I2C(2) */ -+ PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), -+ /* @GPIO(36,37): MDC_MDIO(1) */ -+ PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), -+ /* @GPIO(36,37): MDC_MDIO(3) */ -+ PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), -+ /* @GPIO(69,85): WF0_MODE1(1) */ -+ PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), -+ /* @GPIO(74,80): WF0_MODE3(3) */ -+ PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), -+ /* @GPIO(30): WF2G_LED(2) */ -+ PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), -+ /* @GPIO(34): WF2G_LED(1) */ -+ PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), -+ /* @GPIO(31): WF5G_LED(2) */ -+ PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), -+ /* @GPIO(35): WF5G_LED(1) */ -+ PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), -+ /* @GPIO(38): MT7531_INT(1) */ -+ PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), -+ /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ -+ PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), -+}; -+ -+/* Joint those groups owning the same capability in user point of view which -+ * allows that people tend to use through the device tree. -+ */ -+static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", -+ "wa_aice3", "wm_aice1_2", }; -+static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", -+ "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", -+ "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; -+static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; -+static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; -+static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; -+static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", -+ "wo0_jtag_1", "wm_jtag_1", }; -+static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", -+ "wf2g_led1", "wf5g_led0", "wf5g_led1", }; -+static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; -+static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", -+ "pwm1_0", "pwm1_1", }; -+static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", -+ "spi2_wp_hold", }; -+static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", -+ "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; -+static const char *mt7981_pcm_groups[] = { "pcm", }; -+static const char *mt7981_udi_groups[] = { "udi", }; -+static const char *mt7981_usb_groups[] = { "drv_vbus", }; -+static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; -+static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", -+ "wf0_mode1", "wf0_mode3", "mt7531_int", }; -+static const char *mt7981_ant_groups[] = { "ant_sel", }; -+ -+static const struct function_desc mt7981_functions[] = { -+ {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, -+ {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, -+ {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, -+ {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, -+ {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, -+ {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, -+ {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, -+ {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, -+ {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, -+ {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, -+ {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, -+ {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, -+ {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, -+ {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, -+ {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, -+ {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, -+ {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, -+}; -+ -+static const struct mtk_eint_hw mt7981_eint_hw = { -+ .port_mask = 7, -+ .ports = 7, -+ .ap_num = ARRAY_SIZE(mt7981_pins), -+ .db_cnt = 16, -+}; -+ -+static const char * const mt7981_pinctrl_register_base_names[] = { -+ "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", -+ "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", -+}; -+ -+static struct mtk_pin_soc mt7981_data = { -+ .reg_cal = mt7981_reg_cals, -+ .pins = mt7981_pins, -+ .npins = ARRAY_SIZE(mt7981_pins), -+ .grps = mt7981_groups, -+ .ngrps = ARRAY_SIZE(mt7981_groups), -+ .funcs = mt7981_functions, -+ .nfuncs = ARRAY_SIZE(mt7981_functions), -+ .eint_hw = &mt7981_eint_hw, -+ .gpio_m = 0, -+ .ies_present = false, -+ .base_names = mt7981_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), -+ .pull_type = mt7981_pull_type, -+ .bias_set_combo = mtk_pinconf_bias_set_combo, -+ .bias_get_combo = mtk_pinconf_bias_get_combo, -+ .drive_set = mtk_pinconf_drive_set_rev1, -+ .drive_get = mtk_pinconf_drive_get_rev1, -+ .adv_pull_get = mtk_pinconf_adv_pull_get, -+ .adv_pull_set = mtk_pinconf_adv_pull_set, -+}; -+ -+static const struct of_device_id mt7981_pinctrl_of_match[] = { -+ { .compatible = "mediatek,mt7981-pinctrl", }, -+ {} -+}; -+ -+static int mt7981_pinctrl_probe(struct platform_device *pdev) -+{ -+ return mtk_moore_pinctrl_probe(pdev, &mt7981_data); -+} -+ -+static struct platform_driver mt7981_pinctrl_driver = { -+ .driver = { -+ .name = "mt7981-pinctrl", -+ .of_match_table = mt7981_pinctrl_of_match, -+ }, -+ .probe = mt7981_pinctrl_probe, -+}; -+ -+static int __init mt7981_pinctrl_init(void) -+{ -+ return platform_driver_register(&mt7981_pinctrl_driver); -+} -+arch_initcall(mt7981_pinctrl_init); diff --git a/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch b/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch deleted file mode 100644 index 995e0dc7ed844d..00000000000000 --- a/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Sat, 18 Feb 2023 09:51:06 +0300 -Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There are options missing from PINCTRL_MT7981 whilst being on every other -pin controller. Add them. - -Signed-off-by: Arınç ÜNAL -Acked-by: Daniel Golle -Link: https://lore.kernel.org/r/20230218065108.8958-1-arinc.unal@arinc9.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/Kconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -130,6 +130,8 @@ config PINCTRL_MT7622 - config PINCTRL_MT7981 - bool "Mediatek MT7981 pin control" - depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - - config PINCTRL_MT7986 diff --git a/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch b/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch deleted file mode 100644 index db2561695bf38c..00000000000000 --- a/target/linux/mediatek/patches-6.1/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 8f6f16fe1553ce63edfb98a39ef9d4754a0c39bf Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 18 Aug 2023 04:02:35 +0100 -Subject: [PATCH] pinctrl: mediatek: fix pull_type data for MT7981 - -MediaTek has released pull_type data for MT7981 in their SDK. -Use it and set functions to configure pin bias. - -Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver") -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 44 +++++++---------------- - 1 file changed, 13 insertions(+), 31 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_ty - MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ - MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ - MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -- MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ -- MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ -- MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ -- MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ -- MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ -- MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ -- MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ -- MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ -- MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ -- MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ -- MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ -- MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ -- MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ -- MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ -- MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ -- MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ -- MTK_PULL_PU_PD_TYPE,/*100*/ -+ MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ -+ MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ -+ MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ -+ MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ -+ MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ -+ MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ -+ MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ -+ MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ -+ MTK_PULL_PU_PD_TYPE,/*56*/ - }; - - static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { -@@ -1014,6 +992,10 @@ static struct mtk_pin_soc mt7981_data = - .ies_present = false, - .base_names = mt7981_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7981_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch b/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch deleted file mode 100644 index d2f055836baaf3..00000000000000 --- a/target/linux/mediatek/patches-6.1/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 26 Aug 2023 21:06:14 +0100 -Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups - -Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups. - -Signed-off-by: Daniel Golle ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++--- - 1 file changed, 13 insertions(+), 3 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = { - static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; - static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; - -+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; -+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; -+ - /* GBE_LED0 */ - static int mt7981_gbe_led0_pins[] = { 8, }; - static int mt7981_gbe_led0_funcs[] = { 3, }; -@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4, - static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; - static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; - -+static int mt7981_uart1_2_pins[] = { 9, 10, }; -+static int mt7981_uart1_2_funcs[] = { 2, 2, }; -+ - /* UART2 */ - static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; - static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), - /* @GPIO(4,7) WM_JTAG(3) */ - PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), -+ /* @GPIO(4,5) WM_JTAG(4) */ -+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), - /* @GPIO(8) GBE_LED0(3) */ - PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), - /* @GPIO(4,6) PTA_EXT(4) */ -@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), - /* @GPIO(26,29): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), -+ /* @GPIO(9,10): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), - /* @GPIO(22,25): UART1(3) */ - PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), - /* @GPIO(22,24) PTA_EXT(4) */ -@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr - */ - static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", - "wa_aice3", "wm_aice1_2", }; --static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", -- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", -- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; -+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", -+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0", -+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; - static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; - static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; - static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; diff --git a/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch b/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch deleted file mode 100644 index 7992a026774fe0..00000000000000 --- a/target/linux/mediatek/patches-6.1/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 0d8387fba9f151220e48dc3dcdc2335539708f13 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 18 Aug 2023 04:03:26 +0100 -Subject: [PATCH] pinctrl: mediatek: assign functions to configure pin bias on - MT7986 - -Assign bias_disable_get/set and bias_get/set functions to allow -configuring pin bias on MT7986. - -Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC") -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, -@@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .bias_disable_set = mtk_pinconf_bias_disable_set, -+ .bias_disable_get = mtk_pinconf_bias_disable_get, -+ .bias_set = mtk_pinconf_bias_set, -+ .bias_get = mtk_pinconf_bias_get, - .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, diff --git a/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch b/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch deleted file mode 100644 index af5715e1f5deb1..00000000000000 --- a/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch +++ /dev/null @@ -1,536 +0,0 @@ -From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:33 +0100 -Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with - mtk_clk_register_gates() - -Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device") -introduces a helper function for the sole purpose of propagating a -struct device pointer to the clk API when registering the mtk-gate -clocks to take advantage of Runtime PM when/where needed and where -a power domain is defined in devicetree. - -Function mtk_clk_register_gates() then becomes a wrapper around the -new mtk_clk_register_gates_with_dev() function that will simply pass -NULL as struct device: this is essential when registering drivers -with CLK_OF_DECLARE instead of as a platform device, as there will -be no struct device to pass... but we can as well simply have only -one function that always takes such pointer as a param and pass NULL -when unavoidable. - -This commit removes the mtk_clk_register_gates() wrapper and renames -mtk_clk_register_gates_with_dev() to the former and all of the calls -to either of the two functions were fixed in all drivers in order to -reflect this change; also, to improve consistency with other kernel -functions, the pointer to struct device was moved as the first param. - -Since a lot of MediaTek clock drivers are actually registering as a -platform device, but were still registering the mtk-gate clocks -without passing any struct device to the clock framework, they've -been changed to pass a valid one now, as to make all those platforms -able to use runtime power management where available. - -While at it, some much needed indentation changes were also done. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Reviewed-by: Markus Schneider-Pargmann -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: dropped parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-gate.c | 23 +++++++--------------- - drivers/clk/mediatek/clk-gate.h | 7 +------ - drivers/clk/mediatek/clk-mt2701-aud.c | 4 ++-- - drivers/clk/mediatek/clk-mt2701-eth.c | 4 ++-- - drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- - drivers/clk/mediatek/clk-mt2701-hif.c | 4 ++-- - drivers/clk/mediatek/clk-mt2701-mm.c | 4 ++-- - drivers/clk/mediatek/clk-mt2701.c | 12 +++++------ - drivers/clk/mediatek/clk-mt2712-mm.c | 4 ++-- - drivers/clk/mediatek/clk-mt2712.c | 12 +++++------ - drivers/clk/mediatek/clk-mt7622-aud.c | 4 ++-- - drivers/clk/mediatek/clk-mt7622-eth.c | 8 ++++---- - drivers/clk/mediatek/clk-mt7622-hif.c | 8 ++++---- - drivers/clk/mediatek/clk-mt7622.c | 14 ++++++------- - drivers/clk/mediatek/clk-mt7629-eth.c | 7 ++++--- - drivers/clk/mediatek/clk-mt7629-hif.c | 8 ++++---- - drivers/clk/mediatek/clk-mt7629.c | 10 +++++----- - drivers/clk/mediatek/clk-mt7986-eth.c | 10 +++++----- - drivers/clk/mediatek/clk-mt7986-infracfg.c | 4 ++-- - 19 files changed, 68 insertions(+), 81 deletions(-) - ---- a/drivers/clk/mediatek/clk-gate.c -+++ b/drivers/clk/mediatek/clk-gate.c -@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no - }; - EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv); - --static struct clk_hw *mtk_clk_register_gate(const char *name, -+static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name, - const char *parent_name, - struct regmap *regmap, int set_ofs, - int clr_ofs, int sta_ofs, u8 bit, - const struct clk_ops *ops, -- unsigned long flags, struct device *dev) -+ unsigned long flags) - { - struct mtk_clk_gate *cg; - int ret; -@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru - kfree(cg); - } - --int mtk_clk_register_gates_with_dev(struct device_node *node, -- const struct mtk_gate *clks, int num, -- struct clk_hw_onecell_data *clk_data, -- struct device *dev) -+int mtk_clk_register_gates(struct device *dev, struct device_node *node, -+ const struct mtk_gate *clks, int num, -+ struct clk_hw_onecell_data *clk_data) - { - int i; - struct clk_hw *hw; -@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru - continue; - } - -- hw = mtk_clk_register_gate(gate->name, gate->parent_name, -+ hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name, - regmap, - gate->regs->set_ofs, - gate->regs->clr_ofs, - gate->regs->sta_ofs, - gate->shift, gate->ops, -- gate->flags, dev); -+ gate->flags); - - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", gate->name, -@@ -261,14 +260,6 @@ err: - - return PTR_ERR(hw); - } --EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev); -- --int mtk_clk_register_gates(struct device_node *node, -- const struct mtk_gate *clks, int num, -- struct clk_hw_onecell_data *clk_data) --{ -- return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); --} - EXPORT_SYMBOL_GPL(mtk_clk_register_gates); - - void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, ---- a/drivers/clk/mediatek/clk-gate.h -+++ b/drivers/clk/mediatek/clk-gate.h -@@ -50,15 +50,10 @@ struct mtk_gate { - #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \ - GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0) - --int mtk_clk_register_gates(struct device_node *node, -+int mtk_clk_register_gates(struct device *dev, struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data); - --int mtk_clk_register_gates_with_dev(struct device_node *node, -- const struct mtk_gate *clks, int num, -- struct clk_hw_onecell_data *clk_data, -- struct device *dev); -- - void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data); - ---- a/drivers/clk/mediatek/clk-mt2701-aud.c -+++ b/drivers/clk/mediatek/clk-mt2701-aud.c -@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p - - clk_data = mtk_alloc_clk_data(CLK_AUD_NR); - -- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, audio_clks, -+ ARRAY_SIZE(audio_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { ---- a/drivers/clk/mediatek/clk-mt2701-eth.c -+++ b/drivers/clk/mediatek/clk-mt2701-eth.c -@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p - - clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); - -- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, eth_clks, -+ ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt2701-g3d.c -+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c -@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct - - clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); - -- mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), -+ mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks), - clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ---- a/drivers/clk/mediatek/clk-mt2701-hif.c -+++ b/drivers/clk/mediatek/clk-mt2701-hif.c -@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p - - clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); - -- mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, hif_clks, -+ ARRAY_SIZE(hif_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { ---- a/drivers/clk/mediatek/clk-mt2701-mm.c -+++ b/drivers/clk/mediatek/clk-mt2701-mm.c -@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl - - clk_data = mtk_alloc_clk_data(CLK_MM_NR); - -- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, mm_clks, -+ ARRAY_SIZE(mm_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt2701.c -+++ b/drivers/clk/mediatek/clk-mt2701.c -@@ -685,8 +685,8 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt2701_clk_lock, clk_data); - -- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, top_clks, -+ ARRAY_SIZE(top_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - } -@@ -789,8 +789,8 @@ static int mtk_infrasys_init(struct plat - } - } - -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- infra_clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), infra_clk_data); - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - -@@ -902,8 +902,8 @@ static int mtk_pericfg_init(struct platf - if (!clk_data) - return -ENOMEM; - -- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, peri_clks, -+ ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, - &mt2701_clk_lock, clk_data); ---- a/drivers/clk/mediatek/clk-mt2712-mm.c -+++ b/drivers/clk/mediatek/clk-mt2712-mm.c -@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - -- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, mm_clks, -+ ARRAY_SIZE(mm_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - ---- a/drivers/clk/mediatek/clk-mt2712.c -+++ b/drivers/clk/mediatek/clk-mt2712.c -@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt2712_clk_lock, top_clk_data); -- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), -- top_clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, top_clks, -+ ARRAY_SIZE(top_clks), top_clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - -@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - -@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - -- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, peri_clks, -+ ARRAY_SIZE(peri_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - ---- a/drivers/clk/mediatek/clk-mt7622-aud.c -+++ b/drivers/clk/mediatek/clk-mt7622-aud.c -@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - -- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, audio_clks, -+ ARRAY_SIZE(audio_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { ---- a/drivers/clk/mediatek/clk-mt7622-eth.c -+++ b/drivers/clk/mediatek/clk-mt7622-eth.c -@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct - - clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); - -- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, eth_clks, -+ ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); - -- mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks, -+ ARRAY_SIZE(sgmii_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt7622-hif.c -+++ b/drivers/clk/mediatek/clk-mt7622-hif.c -@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - -- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -+ ARRAY_SIZE(ssusb_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - -- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -+ ARRAY_SIZE(pcie_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt7622.c -+++ b/drivers/clk/mediatek/clk-mt7622.c -@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt7622_clk_lock, clk_data); - -- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, top_clks, -+ ARRAY_SIZE(top_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - } -@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), clk_data); - - mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), - clk_data); -@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), - clk_data); - -- mtk_clk_register_gates(node, apmixed_clks, -+ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - -- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, peri_clks, -+ ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, - &mt7622_clk_lock, clk_data); ---- a/drivers/clk/mediatek/clk-mt7629-eth.c -+++ b/drivers/clk/mediatek/clk-mt7629-eth.c -@@ -82,7 +82,8 @@ static int clk_mt7629_ethsys_init(struct - if (!clk_data) - return -ENOMEM; - -- mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, eth_clks, -+ CLK_ETH_NR_CLK, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -106,8 +107,8 @@ static int clk_mt7629_sgmiisys_init(stru - if (!clk_data) - return -ENOMEM; - -- mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK, -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++], -+ CLK_SGMII_NR_CLK, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt7629-hif.c -+++ b/drivers/clk/mediatek/clk-mt7629-hif.c -@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - -- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -+ ARRAY_SIZE(ssusb_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - -- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -+ ARRAY_SIZE(pcie_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt7629.c -+++ b/drivers/clk/mediatek/clk-mt7629.c -@@ -585,8 +585,8 @@ static int mtk_infrasys_init(struct plat - if (!clk_data) - return -ENOMEM; - -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), clk_data); - - mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), - clk_data); -@@ -610,8 +610,8 @@ static int mtk_pericfg_init(struct platf - if (!clk_data) - return -ENOMEM; - -- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, peri_clks, -+ ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, - &mt7629_clk_lock, clk_data); -@@ -637,7 +637,7 @@ static int mtk_apmixedsys_init(struct pl - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), - clk_data); - -- mtk_clk_register_gates(node, apmixed_clks, -+ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); ---- a/drivers/clk/mediatek/clk-mt7986-eth.c -+++ b/drivers/clk/mediatek/clk-mt7986-eth.c -@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - -- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), -- clk_data); -+ mtk_clk_register_gates(NULL, node, sgmii0_clks, -+ ARRAY_SIZE(sgmii0_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - -- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), -- clk_data); -+ mtk_clk_register_gates(NULL, node, sgmii1_clks, -+ ARRAY_SIZE(sgmii1_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - -@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); - -- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); -+ mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - ---- a/drivers/clk/mediatek/clk-mt7986-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c -@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform - if (!clk_data) - return -ENOMEM; - -- r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks, -- clk_data, &pdev->dev); -+ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks, -+ clk_data); - if (r) - goto free_data; - diff --git a/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch b/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch deleted file mode 100644 index 223155c59b8940..00000000000000 --- a/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch +++ /dev/null @@ -1,140 +0,0 @@ -From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:34 +0100 -Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where - possible - -Take a pointer to a struct device in mtk_clk_register_cpumuxes() and -propagate the same to mtk_clk_register_cpumux() => clk_hw_register(). -Even though runtime pm is unlikely to be used with CPU muxes, this -helps with code consistency and possibly opens to commonization of -some mtk_clk_register_(x) functions. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Reviewed-by: Markus Schneider-Pargmann -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-5-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-cpumux.c | 8 ++++---- - drivers/clk/mediatek/clk-cpumux.h | 2 +- - drivers/clk/mediatek/clk-mt2701.c | 2 +- - drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++- - drivers/clk/mediatek/clk-mt7622.c | 4 ++-- - drivers/clk/mediatek/clk-mt7629.c | 4 ++-- - drivers/clk/mediatek/clk-mt8173.c | 4 ++-- - 7 files changed, 14 insertions(+), 13 deletions(-) - ---- a/drivers/clk/mediatek/clk-cpumux.c -+++ b/drivers/clk/mediatek/clk-cpumux.c -@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o - }; - - static struct clk_hw * --mtk_clk_register_cpumux(const struct mtk_composite *mux, -+mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux, - struct regmap *regmap) - { - struct mtk_clk_cpumux *cpumux; -@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk - cpumux->regmap = regmap; - cpumux->hw.init = &init; - -- ret = clk_hw_register(NULL, &cpumux->hw); -+ ret = clk_hw_register(dev, &cpumux->hw); - if (ret) { - kfree(cpumux); - return ERR_PTR(ret); -@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st - kfree(cpumux); - } - --int mtk_clk_register_cpumuxes(struct device_node *node, -+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node, - const struct mtk_composite *clks, int num, - struct clk_hw_onecell_data *clk_data) - { -@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev - continue; - } - -- hw = mtk_clk_register_cpumux(mux, regmap); -+ hw = mtk_clk_register_cpumux(dev, mux, regmap); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", mux->name, - hw); ---- a/drivers/clk/mediatek/clk-cpumux.h -+++ b/drivers/clk/mediatek/clk-cpumux.h -@@ -11,7 +11,7 @@ struct clk_hw_onecell_data; - struct device_node; - struct mtk_composite; - --int mtk_clk_register_cpumuxes(struct device_node *node, -+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node, - const struct mtk_composite *clks, int num, - struct clk_hw_onecell_data *clk_data); - ---- a/drivers/clk/mediatek/clk-mt2701.c -+++ b/drivers/clk/mediatek/clk-mt2701.c -@@ -761,7 +761,7 @@ static void __init mtk_infrasys_init_ear - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - -- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), -+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - infra_clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, ---- a/drivers/clk/mediatek/clk-mt6795-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c -@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str - if (ret) - goto free_clk_data; - -- ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); -+ ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, -+ ARRAY_SIZE(cpu_muxes), clk_data); - if (ret) - goto unregister_gates; - ---- a/drivers/clk/mediatek/clk-mt7622.c -+++ b/drivers/clk/mediatek/clk-mt7622.c -@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - -- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, -+ ARRAY_SIZE(infra_muxes), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - clk_data); ---- a/drivers/clk/mediatek/clk-mt7629.c -+++ b/drivers/clk/mediatek/clk-mt7629.c -@@ -588,8 +588,8 @@ static int mtk_infrasys_init(struct plat - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - -- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, -+ ARRAY_SIZE(infra_muxes), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - clk_data); ---- a/drivers/clk/mediatek/clk-mt8173.c -+++ b/drivers/clk/mediatek/clk-mt8173.c -@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str - clk_data); - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - -- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, -+ ARRAY_SIZE(cpu_muxes), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) diff --git a/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch b/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch deleted file mode 100644 index eca1b614cdfc35..00000000000000 --- a/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch +++ /dev/null @@ -1,181 +0,0 @@ -From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:35 +0100 -Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for - composites - -Like done for cpumux clocks, propagate struct device for composite -clocks registered through clk-mtk helpers to be able to get runtime -pm support for MTK clocks. - -Signed-off-by: AngeloGioacchino Del Regno -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: remove parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-mt2701.c | 10 ++++++---- - drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++---- - drivers/clk/mediatek/clk-mt7622.c | 8 +++++--- - drivers/clk/mediatek/clk-mt7629.c | 8 +++++--- - drivers/clk/mediatek/clk-mtk.c | 11 ++++++----- - drivers/clk/mediatek/clk-mtk.h | 3 ++- - 6 files changed, 32 insertions(+), 20 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt2701.c -+++ b/drivers/clk/mediatek/clk-mt2701.c -@@ -679,8 +679,9 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), - clk_data); - -- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), -- base, &mt2701_clk_lock, clk_data); -+ mtk_clk_register_composites(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), base, -+ &mt2701_clk_lock, clk_data); - - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt2701_clk_lock, clk_data); -@@ -905,8 +906,9 @@ static int mtk_pericfg_init(struct platf - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - -- mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, -- &mt2701_clk_lock, clk_data); -+ mtk_clk_register_composites(&pdev->dev, peri_muxs, -+ ARRAY_SIZE(peri_muxs), base, -+ &mt2701_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt2712.c -+++ b/drivers/clk/mediatek/clk-mt2712.c -@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); -- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, -- &mt2712_clk_lock, top_clk_data); -+ mtk_clk_register_composites(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), base, -+ &mt2712_clk_lock, top_clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_gates(&pdev->dev, node, top_clks, -@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p - - clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); - -- mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, -- &mt2712_clk_lock, clk_data); -+ r = mtk_clk_register_composites(&pdev->dev, mcu_muxes, -+ ARRAY_SIZE(mcu_muxes), base, -+ &mt2712_clk_lock, clk_data); -+ if (r) -+ dev_err(&pdev->dev, "Could not register composites: %d\n", r); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - ---- a/drivers/clk/mediatek/clk-mt7622.c -+++ b/drivers/clk/mediatek/clk-mt7622.c -@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), - clk_data); - -- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), -- base, &mt7622_clk_lock, clk_data); -+ mtk_clk_register_composites(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), base, -+ &mt7622_clk_lock, clk_data); - - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt7622_clk_lock, clk_data); -@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - -- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, -+ mtk_clk_register_composites(&pdev->dev, peri_muxes, -+ ARRAY_SIZE(peri_muxes), base, - &mt7622_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ---- a/drivers/clk/mediatek/clk-mt7629.c -+++ b/drivers/clk/mediatek/clk-mt7629.c -@@ -566,8 +566,9 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), - clk_data); - -- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), -- base, &mt7629_clk_lock, clk_data); -+ mtk_clk_register_composites(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), base, -+ &mt7629_clk_lock, clk_data); - - clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); -@@ -613,7 +614,8 @@ static int mtk_pericfg_init(struct platf - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - -- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, -+ mtk_clk_register_composites(&pdev->dev, peri_muxes, -+ ARRAY_SIZE(peri_muxes), base, - &mt7629_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st - } - EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors); - --static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc, -- void __iomem *base, spinlock_t *lock) -+static struct clk_hw *mtk_clk_register_composite(struct device *dev, -+ const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock) - { - struct clk_hw *hw; - struct clk_mux *mux = NULL; -@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c - div_ops = &clk_divider_ops; - } - -- hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents, -+ hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents, - mux_hw, mux_ops, - div_hw, div_ops, - gate_hw, gate_ops, -@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite - kfree(mux); - } - --int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, -+int mtk_clk_register_composites(struct device *dev, -+ const struct mtk_composite *mcs, int num, - void __iomem *base, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data) - { -@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st - continue; - } - -- hw = mtk_clk_register_composite(mc, base, lock); -+ hw = mtk_clk_register_composite(dev, mc, base, lock); - - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", mc->name, ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -149,7 +149,8 @@ struct mtk_composite { - .flags = 0, \ - } - --int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, -+int mtk_clk_register_composites(struct device *dev, -+ const struct mtk_composite *mcs, int num, - void __iomem *base, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data); - void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, diff --git a/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch b/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch deleted file mode 100644 index a50422da588387..00000000000000 --- a/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:36 +0100 -Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for - mtk-mux - -Like done for other clocks, propagate struct device for mtk mux clocks -registered through clk-mux helpers to enable runtime pm support. - -Signed-off-by: AngeloGioacchino Del Regno -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: removed parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-mt7986-infracfg.c | 3 ++- - drivers/clk/mediatek/clk-mt7986-topckgen.c | 3 ++- - drivers/clk/mediatek/clk-mux.c | 14 ++++++++------ - drivers/clk/mediatek/clk-mux.h | 3 ++- - 4 files changed, 14 insertions(+), 9 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c -@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str - return -ENOMEM; - - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); -- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, -+ mtk_clk_register_muxes(&pdev->dev, infra_muxes, -+ ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); ---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c -@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, -+ mtk_clk_register_muxes(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data); - - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); ---- a/drivers/clk/mediatek/clk-mux.c -+++ b/drivers/clk/mediatek/clk-mux.c -@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se - }; - EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops); - --static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux, -- struct regmap *regmap, -- spinlock_t *lock) -+static struct clk_hw *mtk_clk_register_mux(struct device *dev, -+ const struct mtk_mux *mux, -+ struct regmap *regmap, -+ spinlock_t *lock) - { - struct mtk_clk_mux *clk_mux; - struct clk_init_data init = {}; -@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m - clk_mux->lock = lock; - clk_mux->hw.init = &init; - -- ret = clk_hw_register(NULL, &clk_mux->hw); -+ ret = clk_hw_register(dev, &clk_mux->hw); - if (ret) { - kfree(clk_mux); - return ERR_PTR(ret); -@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc - kfree(mux); - } - --int mtk_clk_register_muxes(const struct mtk_mux *muxes, -+int mtk_clk_register_muxes(struct device *dev, -+ const struct mtk_mux *muxes, - int num, struct device_node *node, - spinlock_t *lock, - struct clk_hw_onecell_data *clk_data) -@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct - continue; - } - -- hw = mtk_clk_register_mux(mux, regmap, lock); -+ hw = mtk_clk_register_mux(dev, mux, regmap, lock); - - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", mux->name, ---- a/drivers/clk/mediatek/clk-mux.h -+++ b/drivers/clk/mediatek/clk-mux.h -@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate - 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \ - mtk_mux_clr_set_upd_ops) - --int mtk_clk_register_muxes(const struct mtk_mux *muxes, -+int mtk_clk_register_muxes(struct device *dev, -+ const struct mtk_mux *muxes, - int num, struct device_node *node, - spinlock_t *lock, - struct clk_hw_onecell_data *clk_data); diff --git a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch b/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch deleted file mode 100644 index de2e6976c31968..00000000000000 --- a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch +++ /dev/null @@ -1,74 +0,0 @@ -From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:37 +0100 -Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops - -In order to migrate some (few) old clock drivers to the common -mtk_clk_simple_probe() function, add dummy clock ops to be able -to insert a dummy clock with ID 0 at the beginning of the list. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++ - drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ - 2 files changed, 35 insertions(+) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -18,6 +18,22 @@ - #include "clk-mtk.h" - #include "clk-gate.h" - -+const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; -+EXPORT_SYMBOL_GPL(cg_regs_dummy); -+ -+static int mtk_clk_dummy_enable(struct clk_hw *hw) -+{ -+ return 0; -+} -+ -+static void mtk_clk_dummy_disable(struct clk_hw *hw) { } -+ -+const struct clk_ops mtk_clk_dummy_ops = { -+ .enable = mtk_clk_dummy_enable, -+ .disable = mtk_clk_dummy_disable, -+}; -+EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); -+ - static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, - unsigned int clk_num) - { ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -22,6 +22,25 @@ - - struct platform_device; - -+/* -+ * We need the clock IDs to start from zero but to maintain devicetree -+ * backwards compatibility we can't change bindings to start from zero. -+ * Only a few platforms are affected, so we solve issues given by the -+ * commonized MTK clocks probe function(s) by adding a dummy clock at -+ * the beginning where needed. -+ */ -+#define CLK_DUMMY 0 -+ -+extern const struct clk_ops mtk_clk_dummy_ops; -+extern const struct mtk_gate_regs cg_regs_dummy; -+ -+#define GATE_DUMMY(_id, _name) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .regs = &cg_regs_dummy, \ -+ .ops = &mtk_clk_dummy_ops, \ -+ } -+ - struct mtk_fixed_clk { - int id; - const char *name; diff --git a/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch b/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch deleted file mode 100644 index becfcd0ed815a5..00000000000000 --- a/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch +++ /dev/null @@ -1,790 +0,0 @@ -From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:41 +0100 -Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where - possible - -mtk_clk_simple_probe() is a function that registers mtk gate clocks -and, if reset data is present, a reset controller and across all of -the MTK clock drivers, such a function is duplicated many times: -switch to the common mtk_clk_simple_probe() function for all of the -clock drivers that are registering as platform drivers. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: removed parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++---- - drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++-------- - drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++-------------- - drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++-------- - drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++++---------------- - drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++----------- - drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++--------------------- - drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++---------------------- - drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++---------------------- - 9 files changed, 144 insertions(+), 406 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt2701-aud.c -+++ b/drivers/clk/mediatek/clk-mt2701-aud.c -@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3 - }; - - static const struct mtk_gate audio_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "aud_dummy"), - /* AUDIO0 */ - GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), - GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), -@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[ - GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), - }; - -+static const struct mtk_clk_desc audio_desc = { -+ .clks = audio_clks, -+ .num_clks = ARRAY_SIZE(audio_clks), -+}; -+ - static const struct of_device_id of_match_clk_mt2701_aud[] = { -- { .compatible = "mediatek,mt2701-audsys", }, -- {} -+ { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc }, -+ { /* sentinel */ } - }; - - static int clk_mt2701_aud_probe(struct platform_device *pdev) - { -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; - int r; - -- clk_data = mtk_alloc_clk_data(CLK_AUD_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, audio_clks, -- ARRAY_SIZE(audio_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ r = mtk_clk_simple_probe(pdev); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - -- goto err_clk_provider; -+ return r; - } - - r = devm_of_platform_populate(&pdev->dev); -@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p - return 0; - - err_plat_populate: -- of_clk_del_provider(node); --err_clk_provider: -+ mtk_clk_simple_remove(pdev); - return r; - } - -+static int clk_mt2701_aud_remove(struct platform_device *pdev) -+{ -+ of_platform_depopulate(&pdev->dev); -+ return mtk_clk_simple_remove(pdev); -+} -+ - static struct platform_driver clk_mt2701_aud_drv = { - .probe = clk_mt2701_aud_probe, -+ .remove = clk_mt2701_aud_remove, - .driver = { - .name = "clk-mt2701-aud", - .of_match_table = of_match_clk_mt2701_aud, ---- a/drivers/clk/mediatek/clk-mt2701-eth.c -+++ b/drivers/clk/mediatek/clk-mt2701-eth.c -@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg - GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - - static const struct mtk_gate eth_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "eth_dummy"), - GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), - GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), - GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), -@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static const struct of_device_id of_match_clk_mt2701_eth[] = { -- { .compatible = "mediatek,mt2701-ethsys", }, -- {} -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+ .rst_desc = &clk_rst_desc, - }; - --static int clk_mt2701_eth_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, eth_clks, -- ARRAY_SIZE(eth_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -+static const struct of_device_id of_match_clk_mt2701_eth[] = { -+ { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc }, -+ { /* sentinel */ } -+}; - - static struct platform_driver clk_mt2701_eth_drv = { -- .probe = clk_mt2701_eth_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-eth", - .of_match_table = of_match_clk_mt2701_eth, ---- a/drivers/clk/mediatek/clk-mt2701-g3d.c -+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c -@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg - }; - - static const struct mtk_gate g3d_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "g3d_dummy"), - GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), - }; - -@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt2701_g3dsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks), -- clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -+static const struct mtk_clk_desc g3d_desc = { -+ .clks = g3d_clks, -+ .num_clks = ARRAY_SIZE(g3d_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt2701_g3d[] = { -- { -- .compatible = "mediatek,mt2701-g3dsys", -- .data = clk_mt2701_g3dsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt2701_g3d_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt2701_g3d_drv = { -- .probe = clk_mt2701_g3d_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-g3d", - .of_match_table = of_match_clk_mt2701_g3d, ---- a/drivers/clk/mediatek/clk-mt2701-hif.c -+++ b/drivers/clk/mediatek/clk-mt2701-hif.c -@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg - GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - - static const struct mtk_gate hif_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "hif_dummy"), - GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21), - GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22), - GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24), -@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static const struct of_device_id of_match_clk_mt2701_hif[] = { -- { .compatible = "mediatek,mt2701-hifsys", }, -- {} -+static const struct mtk_clk_desc hif_desc = { -+ .clks = hif_clks, -+ .num_clks = ARRAY_SIZE(hif_clks), -+ .rst_desc = &clk_rst_desc, - }; - --static int clk_mt2701_hif_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, hif_clks, -- ARRAY_SIZE(hif_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) { -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- return r; -- } -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return 0; --} -+static const struct of_device_id of_match_clk_mt2701_hif[] = { -+ { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc }, -+ { /* sentinel */ } -+}; - - static struct platform_driver clk_mt2701_hif_drv = { -- .probe = clk_mt2701_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-hif", - .of_match_table = of_match_clk_mt2701_hif, ---- a/drivers/clk/mediatek/clk-mt2712.c -+++ b/drivers/clk/mediatek/clk-mt2712.c -@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p - return r; - } - --static int clk_mt2712_infra_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, infra_clks, -- ARRAY_SIZE(infra_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r != 0) -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); -- -- return r; --} -- --static int clk_mt2712_peri_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, peri_clks, -- ARRAY_SIZE(peri_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r != 0) -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); -- -- return r; --} -- - static int clk_mt2712_mcu_probe(struct platform_device *pdev) - { - struct clk_hw_onecell_data *clk_data; -@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc - .compatible = "mediatek,mt2712-topckgen", - .data = clk_mt2712_top_probe, - }, { -- .compatible = "mediatek,mt2712-infracfg", -- .data = clk_mt2712_infra_probe, -- }, { -- .compatible = "mediatek,mt2712-pericfg", -- .data = clk_mt2712_peri_probe, -- }, { - .compatible = "mediatek,mt2712-mcucfg", - .data = clk_mt2712_mcu_probe, - }, { -@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf - return r; - } - -+static const struct mtk_clk_desc infra_desc = { -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .rst_desc = &clk_rst_desc[0], -+}; -+ -+static const struct mtk_clk_desc peri_desc = { -+ .clks = peri_clks, -+ .num_clks = ARRAY_SIZE(peri_clks), -+ .rst_desc = &clk_rst_desc[1], -+}; -+ -+static const struct of_device_id of_match_clk_mt2712_simple[] = { -+ { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, -+ { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt2712_simple_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt2712-simple", -+ .of_match_table = of_match_clk_mt2712_simple, -+ }, -+}; -+ - static struct platform_driver clk_mt2712_drv = { - .probe = clk_mt2712_probe, - .driver = { -@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712 - - static int __init clk_mt2712_init(void) - { -- return platform_driver_register(&clk_mt2712_drv); -+ int ret = platform_driver_register(&clk_mt2712_drv); -+ -+ if (ret) -+ return ret; -+ return platform_driver_register(&clk_mt2712_simple_drv); - } - - arch_initcall(clk_mt2712_init); ---- a/drivers/clk/mediatek/clk-mt7622-aud.c -+++ b/drivers/clk/mediatek/clk-mt7622-aud.c -@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[ - GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), - }; - --static int clk_mt7622_audiosys_init(struct platform_device *pdev) -+static const struct mtk_clk_desc audio_desc = { -+ .clks = audio_clks, -+ .num_clks = ARRAY_SIZE(audio_clks), -+}; -+ -+static int clk_mt7622_aud_probe(struct platform_device *pdev) - { -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; - int r; - -- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, audio_clks, -- ARRAY_SIZE(audio_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ r = mtk_clk_simple_probe(pdev); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - -- goto err_clk_provider; -+ return r; - } - - r = devm_of_platform_populate(&pdev->dev); -@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru - return 0; - - err_plat_populate: -- of_clk_del_provider(node); --err_clk_provider: -+ mtk_clk_simple_remove(pdev); - return r; - } - --static const struct of_device_id of_match_clk_mt7622_aud[] = { -- { -- .compatible = "mediatek,mt7622-audsys", -- .data = clk_mt7622_audiosys_init, -- }, { -- /* sentinel */ -- } --}; -- --static int clk_mt7622_aud_probe(struct platform_device *pdev) -+static int clk_mt7622_aud_remove(struct platform_device *pdev) - { -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; -+ of_platform_depopulate(&pdev->dev); -+ return mtk_clk_simple_remove(pdev); - } - -+static const struct of_device_id of_match_clk_mt7622_aud[] = { -+ { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, -+ { /* sentinel */ } -+}; -+ - static struct platform_driver clk_mt7622_aud_drv = { - .probe = clk_mt7622_aud_probe, -+ .remove = clk_mt7622_aud_remove, - .driver = { - .name = "clk-mt7622-aud", - .of_match_table = of_match_clk_mt7622_aud, ---- a/drivers/clk/mediatek/clk-mt7622-eth.c -+++ b/drivers/clk/mediatek/clk-mt7622-eth.c -@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7622_ethsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, eth_clks, -- ARRAY_SIZE(eth_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, sgmii_clks, -- ARRAY_SIZE(sgmii_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc sgmii_desc = { -+ .clks = sgmii_clks, -+ .num_clks = ARRAY_SIZE(sgmii_clks), -+}; - - static const struct of_device_id of_match_clk_mt7622_eth[] = { -- { -- .compatible = "mediatek,mt7622-ethsys", -- .data = clk_mt7622_ethsys_init, -- }, { -- .compatible = "mediatek,mt7622-sgmiisys", -- .data = clk_mt7622_sgmiisys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, -+ { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7622_eth_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7622_eth_drv = { -- .probe = clk_mt7622_eth_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7622-eth", - .of_match_table = of_match_clk_mt7622_eth, ---- a/drivers/clk/mediatek/clk-mt7622-hif.c -+++ b/drivers/clk/mediatek/clk-mt7622-hif.c -@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -- ARRAY_SIZE(ssusb_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7622_pciesys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -- ARRAY_SIZE(pcie_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -+static const struct mtk_clk_desc ssusb_desc = { -+ .clks = ssusb_clks, -+ .num_clks = ARRAY_SIZE(ssusb_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc pcie_desc = { -+ .clks = pcie_clks, -+ .num_clks = ARRAY_SIZE(pcie_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt7622_hif[] = { -- { -- .compatible = "mediatek,mt7622-pciesys", -- .data = clk_mt7622_pciesys_init, -- }, { -- .compatible = "mediatek,mt7622-ssusbsys", -- .data = clk_mt7622_ssusbsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, -+ { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7622_hif_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7622_hif_drv = { -- .probe = clk_mt7622_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7622-hif", - .of_match_table = of_match_clk_mt7622_hif, ---- a/drivers/clk/mediatek/clk-mt7629-hif.c -+++ b/drivers/clk/mediatek/clk-mt7629-hif.c -@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -- ARRAY_SIZE(ssusb_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7629_pciesys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -- ARRAY_SIZE(pcie_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -+static const struct mtk_clk_desc ssusb_desc = { -+ .clks = ssusb_clks, -+ .num_clks = ARRAY_SIZE(ssusb_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc pcie_desc = { -+ .clks = pcie_clks, -+ .num_clks = ARRAY_SIZE(pcie_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt7629_hif[] = { -- { -- .compatible = "mediatek,mt7629-pciesys", -- .data = clk_mt7629_pciesys_init, -- }, { -- .compatible = "mediatek,mt7629-ssusbsys", -- .data = clk_mt7629_ssusbsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc }, -+ { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7629_hif_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7629_hif_drv = { -- .probe = clk_mt7629_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7629-hif", - .of_match_table = of_match_clk_mt7629_hif, diff --git a/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch b/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch deleted file mode 100644 index ad02df10b6f47e..00000000000000 --- a/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:42 +0100 -Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() - -As a preparation to increase probe functions commonization across -various MediaTek SoC clock controller drivers, extend function -mtk_clk_simple_probe() to be able to register not only gates, but -also fixed clocks, factors, muxes and composites. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-13-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++--- - drivers/clk/mediatek/clk-mtk.h | 10 ++++ - 2 files changed, 103 insertions(+), 8 deletions(-) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -11,12 +11,14 @@ - #include - #include - #include -+#include - #include - #include - #include - - #include "clk-mtk.h" - #include "clk-gate.h" -+#include "clk-mux.h" - - const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; - EXPORT_SYMBOL_GPL(cg_regs_dummy); -@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform - const struct mtk_clk_desc *mcd; - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; -- int r; -+ void __iomem *base; -+ int num_clks, r; - - mcd = of_device_get_match_data(&pdev->dev); - if (!mcd) - return -EINVAL; - -- clk_data = mtk_alloc_clk_data(mcd->num_clks); -+ /* Composite clocks needs us to pass iomem pointer */ -+ if (mcd->composite_clks) { -+ if (!mcd->shared_io) -+ base = devm_platform_ioremap_resource(pdev, 0); -+ else -+ base = of_iomap(node, 0); -+ -+ if (IS_ERR_OR_NULL(base)) -+ return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM; -+ } -+ -+ /* Calculate how many clk_hw_onecell_data entries to allocate */ -+ num_clks = mcd->num_clks + mcd->num_composite_clks; -+ num_clks += mcd->num_fixed_clks + mcd->num_factor_clks; -+ num_clks += mcd->num_mux_clks; -+ -+ clk_data = mtk_alloc_clk_data(num_clks); - if (!clk_data) - return -ENOMEM; - -- r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks, -- clk_data); -- if (r) -- goto free_data; -+ if (mcd->fixed_clks) { -+ r = mtk_clk_register_fixed_clks(mcd->fixed_clks, -+ mcd->num_fixed_clks, clk_data); -+ if (r) -+ goto free_data; -+ } -+ -+ if (mcd->factor_clks) { -+ r = mtk_clk_register_factors(mcd->factor_clks, -+ mcd->num_factor_clks, clk_data); -+ if (r) -+ goto unregister_fixed_clks; -+ } -+ -+ if (mcd->mux_clks) { -+ r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks, -+ mcd->num_mux_clks, node, -+ mcd->clk_lock, clk_data); -+ if (r) -+ goto unregister_factors; -+ }; -+ -+ if (mcd->composite_clks) { -+ /* We don't check composite_lock because it's optional */ -+ r = mtk_clk_register_composites(&pdev->dev, -+ mcd->composite_clks, -+ mcd->num_composite_clks, -+ base, mcd->clk_lock, clk_data); -+ if (r) -+ goto unregister_muxes; -+ } -+ -+ if (mcd->clks) { -+ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, -+ mcd->num_clks, clk_data); -+ if (r) -+ goto unregister_composites; -+ } - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform - return r; - - unregister_clks: -- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); -+ if (mcd->clks) -+ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); -+unregister_composites: -+ if (mcd->composite_clks) -+ mtk_clk_unregister_composites(mcd->composite_clks, -+ mcd->num_composite_clks, clk_data); -+unregister_muxes: -+ if (mcd->mux_clks) -+ mtk_clk_unregister_muxes(mcd->mux_clks, -+ mcd->num_mux_clks, clk_data); -+unregister_factors: -+ if (mcd->factor_clks) -+ mtk_clk_unregister_factors(mcd->factor_clks, -+ mcd->num_factor_clks, clk_data); -+unregister_fixed_clks: -+ if (mcd->fixed_clks) -+ mtk_clk_unregister_fixed_clks(mcd->fixed_clks, -+ mcd->num_fixed_clks, clk_data); - free_data: - mtk_free_clk_data(clk_data); -+ if (mcd->shared_io && base) -+ iounmap(base); - return r; - } - EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); -@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor - struct device_node *node = pdev->dev.of_node; - - of_clk_del_provider(node); -- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); -+ if (mcd->clks) -+ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); -+ if (mcd->composite_clks) -+ mtk_clk_unregister_composites(mcd->composite_clks, -+ mcd->num_composite_clks, clk_data); -+ if (mcd->mux_clks) -+ mtk_clk_unregister_muxes(mcd->mux_clks, -+ mcd->num_mux_clks, clk_data); -+ if (mcd->factor_clks) -+ mtk_clk_unregister_factors(mcd->factor_clks, -+ mcd->num_factor_clks, clk_data); -+ if (mcd->fixed_clks) -+ mtk_clk_unregister_fixed_clks(mcd->fixed_clks, -+ mcd->num_fixed_clks, clk_data); - mtk_free_clk_data(clk_data); - - return 0; ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc - struct mtk_clk_desc { - const struct mtk_gate *clks; - size_t num_clks; -+ const struct mtk_composite *composite_clks; -+ size_t num_composite_clks; -+ const struct mtk_fixed_clk *fixed_clks; -+ size_t num_fixed_clks; -+ const struct mtk_fixed_factor *factor_clks; -+ size_t num_factor_clks; -+ const struct mtk_mux *mux_clks; -+ size_t num_mux_clks; - const struct mtk_clk_rst_desc *rst_desc; -+ spinlock_t *clk_lock; -+ bool shared_io; - }; - - int mtk_clk_simple_probe(struct platform_device *pdev); diff --git a/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch b/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch deleted file mode 100644 index bf9a172926eaf5..00000000000000 --- a/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:52 +0100 -Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some - clocks enabled - -Instead of calling clk_prepare_enable() on a bunch of clocks at probe -time, set the CLK_IS_CRITICAL flag to the same as these are required -to be always on, and this is the right way of achieving that. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Reviewed-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++----------- - 1 file changed, 24 insertions(+), 22 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c -@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[] - MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", - f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, - 0x1C0, 10), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, -- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", -+ f_26m_adc_parents, 0x020, 0x024, 0x028, -+ 24, 1, 31, 0x1C0, 11, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - /* CLK_CFG_3 */ -- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, -- 0x1C0, 12), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, -- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, -- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -+ dramc_md32_parents, 0x030, 0x034, 0x038, -+ 0, 1, 7, 0x1C0, 12, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", -+ sysaxi_parents, 0x030, 0x034, 0x038, -+ 8, 2, 15, 0x1C0, 13, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", -+ sysapb_parents, 0x030, 0x034, 0x038, -+ 16, 2, 23, 0x1C0, 14, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", - arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, - 31, 0x1C0, 15), -@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[] - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", - sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, - 0x1C0, 21), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", -- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, -- 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", -+ sgm_reg_parents, 0x050, 0x054, 0x058, -+ 16, 1, 23, 0x1C0, 22, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), - /* CLK_CFG_6 */ -@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[] - f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, - 0x1C0, 27), - /* CLK_CFG_7 */ -- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", -- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, -- 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", -+ f_26m_adc_parents, 0x070, 0x074, 0x078, -+ 0, 1, 7, 0x1C0, 28, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", -@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str - ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data); - -- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk); -- - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) { diff --git a/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch b/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch deleted file mode 100644 index d77b859f005f78..00000000000000 --- a/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:53 +0100 -Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to - mtk_clk_simple_probe() - -There are no more non-common calls in clk_mt7986_topckgen_probe(): -migrate this driver to mtk_clk_simple_probe(). - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++----------------- - 1 file changed, 13 insertions(+), 42 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c -@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[] - 0x1C4, 5), - }; - --static int clk_mt7986_topckgen_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- void __iomem *base; -- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + -- ARRAY_SIZE(top_muxes); -- -- base = of_iomap(node, 0); -- if (!base) { -- pr_err("%s(): ioremap failed\n", __func__); -- return -ENOMEM; -- } -- -- clk_data = mtk_alloc_clk_data(nr); -- if (!clk_data) -- return -ENOMEM; -- -- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), -- clk_data); -- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -- mtk_clk_register_muxes(&pdev->dev, top_muxes, -- ARRAY_SIZE(top_muxes), node, -- &mt7986_clk_lock, clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r) { -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- goto free_topckgen_data; -- } -- return r; -- --free_topckgen_data: -- mtk_free_clk_data(clk_data); -- return r; --} -+static const struct mtk_clk_desc topck_desc = { -+ .fixed_clks = top_fixed_clks, -+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .clk_lock = &mt7986_clk_lock, -+}; - - static const struct of_device_id of_match_clk_mt7986_topckgen[] = { -- { .compatible = "mediatek,mt7986-topckgen", }, -- {} -+ { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, -+ { /* sentinel */ } - }; - - static struct platform_driver clk_mt7986_topckgen_drv = { -- .probe = clk_mt7986_topckgen_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7986-topckgen", - .of_match_table = of_match_clk_mt7986_topckgen, diff --git a/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch b/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch deleted file mode 100644 index a47dd4b0539598..00000000000000 --- a/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Mon, 6 Mar 2023 15:05:21 +0100 -Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set - critical clock - -Instead of calling clk_prepare_enable() at probe time, add the PLL_AO -flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Tested-by: Daniel Golle -Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-apmixed.c -+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c -@@ -42,7 +42,7 @@ - "clkxtal") - - static const struct mtk_pll_data plls[] = { -- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32, -+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32, - 0x0200, 4, 0, 0x0204, 0), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32, - 0x0210, 4, 0, 0x0214, 0), -@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - -- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); -- - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", diff --git a/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch b/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch deleted file mode 100644 index ae76940e1d88d8..00000000000000 --- a/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch +++ /dev/null @@ -1,237 +0,0 @@ -From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 03:34:05 +0000 -Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs - -Add MT7981 clock dt-bindings, include topckgen, apmixedsys, -infracfg, and ethernet subsystem clocks. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Jianhui Zhao -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Stephen Boyd ---- - .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 ++++++++++++++++++ - 1 file changed, 215 insertions(+) - create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h - ---- /dev/null -+++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h -@@ -0,0 +1,215 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Wenzhen.Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7981_H -+#define _DT_BINDINGS_CLK_MT7981_H -+ -+/* TOPCKGEN */ -+#define CLK_TOP_CB_CKSQ_40M 0 -+#define CLK_TOP_CB_M_416M 1 -+#define CLK_TOP_CB_M_D2 2 -+#define CLK_TOP_CB_M_D3 3 -+#define CLK_TOP_M_D3_D2 4 -+#define CLK_TOP_CB_M_D4 5 -+#define CLK_TOP_CB_M_D8 6 -+#define CLK_TOP_M_D8_D2 7 -+#define CLK_TOP_CB_MM_720M 8 -+#define CLK_TOP_CB_MM_D2 9 -+#define CLK_TOP_CB_MM_D3 10 -+#define CLK_TOP_CB_MM_D3_D5 11 -+#define CLK_TOP_CB_MM_D4 12 -+#define CLK_TOP_CB_MM_D6 13 -+#define CLK_TOP_MM_D6_D2 14 -+#define CLK_TOP_CB_MM_D8 15 -+#define CLK_TOP_CB_APLL2_196M 16 -+#define CLK_TOP_APLL2_D2 17 -+#define CLK_TOP_APLL2_D4 18 -+#define CLK_TOP_NET1_2500M 19 -+#define CLK_TOP_CB_NET1_D4 20 -+#define CLK_TOP_CB_NET1_D5 21 -+#define CLK_TOP_NET1_D5_D2 22 -+#define CLK_TOP_NET1_D5_D4 23 -+#define CLK_TOP_CB_NET1_D8 24 -+#define CLK_TOP_NET1_D8_D2 25 -+#define CLK_TOP_NET1_D8_D4 26 -+#define CLK_TOP_CB_NET2_800M 27 -+#define CLK_TOP_CB_NET2_D2 28 -+#define CLK_TOP_CB_NET2_D4 29 -+#define CLK_TOP_NET2_D4_D2 30 -+#define CLK_TOP_NET2_D4_D4 31 -+#define CLK_TOP_CB_NET2_D6 32 -+#define CLK_TOP_CB_WEDMCU_208M 33 -+#define CLK_TOP_CB_SGM_325M 34 -+#define CLK_TOP_CKSQ_40M_D2 35 -+#define CLK_TOP_CB_RTC_32K 36 -+#define CLK_TOP_CB_RTC_32P7K 37 -+#define CLK_TOP_USB_TX250M 38 -+#define CLK_TOP_FAUD 39 -+#define CLK_TOP_NFI1X 40 -+#define CLK_TOP_USB_EQ_RX250M 41 -+#define CLK_TOP_USB_CDR_CK 42 -+#define CLK_TOP_USB_LN0_CK 43 -+#define CLK_TOP_SPINFI_BCK 44 -+#define CLK_TOP_SPI 45 -+#define CLK_TOP_SPIM_MST 46 -+#define CLK_TOP_UART_BCK 47 -+#define CLK_TOP_PWM_BCK 48 -+#define CLK_TOP_I2C_BCK 49 -+#define CLK_TOP_PEXTP_TL 50 -+#define CLK_TOP_EMMC_208M 51 -+#define CLK_TOP_EMMC_400M 52 -+#define CLK_TOP_DRAMC_REF 53 -+#define CLK_TOP_DRAMC_MD32 54 -+#define CLK_TOP_SYSAXI 55 -+#define CLK_TOP_SYSAPB 56 -+#define CLK_TOP_ARM_DB_MAIN 57 -+#define CLK_TOP_AP2CNN_HOST 58 -+#define CLK_TOP_NETSYS 59 -+#define CLK_TOP_NETSYS_500M 60 -+#define CLK_TOP_NETSYS_WED_MCU 61 -+#define CLK_TOP_NETSYS_2X 62 -+#define CLK_TOP_SGM_325M 63 -+#define CLK_TOP_SGM_REG 64 -+#define CLK_TOP_F26M 65 -+#define CLK_TOP_EIP97B 66 -+#define CLK_TOP_USB3_PHY 67 -+#define CLK_TOP_AUD 68 -+#define CLK_TOP_A1SYS 69 -+#define CLK_TOP_AUD_L 70 -+#define CLK_TOP_A_TUNER 71 -+#define CLK_TOP_U2U3_REF 72 -+#define CLK_TOP_U2U3_SYS 73 -+#define CLK_TOP_U2U3_XHCI 74 -+#define CLK_TOP_USB_FRMCNT 75 -+#define CLK_TOP_NFI1X_SEL 76 -+#define CLK_TOP_SPINFI_SEL 77 -+#define CLK_TOP_SPI_SEL 78 -+#define CLK_TOP_SPIM_MST_SEL 79 -+#define CLK_TOP_UART_SEL 80 -+#define CLK_TOP_PWM_SEL 81 -+#define CLK_TOP_I2C_SEL 82 -+#define CLK_TOP_PEXTP_TL_SEL 83 -+#define CLK_TOP_EMMC_208M_SEL 84 -+#define CLK_TOP_EMMC_400M_SEL 85 -+#define CLK_TOP_F26M_SEL 86 -+#define CLK_TOP_DRAMC_SEL 87 -+#define CLK_TOP_DRAMC_MD32_SEL 88 -+#define CLK_TOP_SYSAXI_SEL 89 -+#define CLK_TOP_SYSAPB_SEL 90 -+#define CLK_TOP_ARM_DB_MAIN_SEL 91 -+#define CLK_TOP_AP2CNN_HOST_SEL 92 -+#define CLK_TOP_NETSYS_SEL 93 -+#define CLK_TOP_NETSYS_500M_SEL 94 -+#define CLK_TOP_NETSYS_MCU_SEL 95 -+#define CLK_TOP_NETSYS_2X_SEL 96 -+#define CLK_TOP_SGM_325M_SEL 97 -+#define CLK_TOP_SGM_REG_SEL 98 -+#define CLK_TOP_EIP97B_SEL 99 -+#define CLK_TOP_USB3_PHY_SEL 100 -+#define CLK_TOP_AUD_SEL 101 -+#define CLK_TOP_A1SYS_SEL 102 -+#define CLK_TOP_AUD_L_SEL 103 -+#define CLK_TOP_A_TUNER_SEL 104 -+#define CLK_TOP_U2U3_SEL 105 -+#define CLK_TOP_U2U3_SYS_SEL 106 -+#define CLK_TOP_U2U3_XHCI_SEL 107 -+#define CLK_TOP_USB_FRMCNT_SEL 108 -+#define CLK_TOP_AUD_I2S_M 109 -+ -+/* INFRACFG */ -+#define CLK_INFRA_66M_MCK 0 -+#define CLK_INFRA_UART0_SEL 1 -+#define CLK_INFRA_UART1_SEL 2 -+#define CLK_INFRA_UART2_SEL 3 -+#define CLK_INFRA_SPI0_SEL 4 -+#define CLK_INFRA_SPI1_SEL 5 -+#define CLK_INFRA_SPI2_SEL 6 -+#define CLK_INFRA_PWM1_SEL 7 -+#define CLK_INFRA_PWM2_SEL 8 -+#define CLK_INFRA_PWM3_SEL 9 -+#define CLK_INFRA_PWM_BSEL 10 -+#define CLK_INFRA_PCIE_SEL 11 -+#define CLK_INFRA_GPT_STA 12 -+#define CLK_INFRA_PWM_HCK 13 -+#define CLK_INFRA_PWM_STA 14 -+#define CLK_INFRA_PWM1_CK 15 -+#define CLK_INFRA_PWM2_CK 16 -+#define CLK_INFRA_PWM3_CK 17 -+#define CLK_INFRA_CQ_DMA_CK 18 -+#define CLK_INFRA_AUD_BUS_CK 19 -+#define CLK_INFRA_AUD_26M_CK 20 -+#define CLK_INFRA_AUD_L_CK 21 -+#define CLK_INFRA_AUD_AUD_CK 22 -+#define CLK_INFRA_AUD_EG2_CK 23 -+#define CLK_INFRA_DRAMC_26M_CK 24 -+#define CLK_INFRA_DBG_CK 25 -+#define CLK_INFRA_AP_DMA_CK 26 -+#define CLK_INFRA_SEJ_CK 27 -+#define CLK_INFRA_SEJ_13M_CK 28 -+#define CLK_INFRA_THERM_CK 29 -+#define CLK_INFRA_I2C0_CK 30 -+#define CLK_INFRA_UART0_CK 31 -+#define CLK_INFRA_UART1_CK 32 -+#define CLK_INFRA_UART2_CK 33 -+#define CLK_INFRA_SPI2_CK 34 -+#define CLK_INFRA_SPI2_HCK_CK 35 -+#define CLK_INFRA_NFI1_CK 36 -+#define CLK_INFRA_SPINFI1_CK 37 -+#define CLK_INFRA_NFI_HCK_CK 38 -+#define CLK_INFRA_SPI0_CK 39 -+#define CLK_INFRA_SPI1_CK 40 -+#define CLK_INFRA_SPI0_HCK_CK 41 -+#define CLK_INFRA_SPI1_HCK_CK 42 -+#define CLK_INFRA_FRTC_CK 43 -+#define CLK_INFRA_MSDC_CK 44 -+#define CLK_INFRA_MSDC_HCK_CK 45 -+#define CLK_INFRA_MSDC_133M_CK 46 -+#define CLK_INFRA_MSDC_66M_CK 47 -+#define CLK_INFRA_ADC_26M_CK 48 -+#define CLK_INFRA_ADC_FRC_CK 49 -+#define CLK_INFRA_FBIST2FPC_CK 50 -+#define CLK_INFRA_I2C_MCK_CK 51 -+#define CLK_INFRA_I2C_PCK_CK 52 -+#define CLK_INFRA_IUSB_133_CK 53 -+#define CLK_INFRA_IUSB_66M_CK 54 -+#define CLK_INFRA_IUSB_SYS_CK 55 -+#define CLK_INFRA_IUSB_CK 56 -+#define CLK_INFRA_IPCIE_CK 57 -+#define CLK_INFRA_IPCIE_PIPE_CK 58 -+#define CLK_INFRA_IPCIER_CK 59 -+#define CLK_INFRA_IPCIEB_CK 60 -+ -+/* APMIXEDSYS */ -+#define CLK_APMIXED_ARMPLL 0 -+#define CLK_APMIXED_NET2PLL 1 -+#define CLK_APMIXED_MMPLL 2 -+#define CLK_APMIXED_SGMPLL 3 -+#define CLK_APMIXED_WEDMCUPLL 4 -+#define CLK_APMIXED_NET1PLL 5 -+#define CLK_APMIXED_MPLL 6 -+#define CLK_APMIXED_APLL2 7 -+ -+/* SGMIISYS_0 */ -+#define CLK_SGM0_TX_EN 0 -+#define CLK_SGM0_RX_EN 1 -+#define CLK_SGM0_CK0_EN 2 -+#define CLK_SGM0_CDR_CK0_EN 3 -+ -+/* SGMIISYS_1 */ -+#define CLK_SGM1_TX_EN 0 -+#define CLK_SGM1_RX_EN 1 -+#define CLK_SGM1_CK1_EN 2 -+#define CLK_SGM1_CDR_CK1_EN 3 -+ -+/* ETHSYS */ -+#define CLK_ETH_FE_EN 0 -+#define CLK_ETH_GP2_EN 1 -+#define CLK_ETH_GP1_EN 2 -+#define CLK_ETH_WOCPU0_EN 3 -+ -+#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch b/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch deleted file mode 100644 index f9dd94a78a51a8..00000000000000 --- a/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch +++ /dev/null @@ -1,932 +0,0 @@ -From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 03:34:24 +0000 -Subject: [PATCH] clk: mediatek: add MT7981 clock support - -Add MT7981 clock support, include topckgen, apmixedsys, infracfg and -ethernet subsystem clocks. - -The drivers are based on clk-mt7981.c which can be found in MediaTek's -SDK sources. To be fit for upstream inclusion the driver has been split -into clock domains and the infracfg part has been significantly -de-bloated by removing all the 1:1 factors (aliases). - -Signed-off-by: Jianhui Zhao -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org -Reviewed-by: AngeloGioacchino Del Regno -[sboyd@kernel.org: Add module license] -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/Kconfig | 17 + - drivers/clk/mediatek/Makefile | 4 + - drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 +++++ - drivers/clk/mediatek/clk-mt7981-eth.c | 118 ++++++ - drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++ - drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++ - 6 files changed, 870 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c - ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS - This driver supports MediaTek MT7629 HIFSYS clocks providing - to PCI-E and USB. - -+config COMMON_CLK_MT7981 -+ bool "Clock driver for MediaTek MT7981" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7981 basic clocks and clocks -+ required for various peripherals found on this SoC. -+ -+config COMMON_CLK_MT7981_ETHSYS -+ tristate "Clock driver for MediaTek MT7981 ETHSYS" -+ depends on COMMON_CLK_MT7981 -+ default COMMON_CLK_MT7981 -+ help -+ This driver adds support for clocks for Ethernet and SGMII -+ required on MediaTek MT7981 SoC. -+ - config COMMON_CLK_MT7986 - bool "Clock driver for MediaTek MT7986" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + - obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o - obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o - obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c -@@ -0,0 +1,102 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-gate.h" -+#include "clk-mtk.h" -+#include "clk-mux.h" -+#include "clk-pll.h" -+ -+#include -+#include -+ -+#define MT7981_PLL_FMAX (2500UL * MHZ) -+#define CON0_MT7981_RST_BAR BIT(27) -+ -+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ -+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ -+ _div_table, _parent_name) \ -+ { \ -+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ -+ .en_mask = _en_mask, .flags = _flags, \ -+ .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \ -+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ -+ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ -+ .pcw_shift = _pcw_shift, .div_table = _div_table, \ -+ .parent_name = _parent_name, \ -+ } -+ -+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ -+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ -+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ -+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ -+ "clkxtal") -+ -+static const struct mtk_pll_data plls[] = { -+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, -+ 32, 0x0200, 4, 0, 0x0204, 0), -+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, -+ 0x0210, 4, 0, 0x0214, 0), -+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, -+ 0x0220, 4, 0, 0x0224, 0), -+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, -+ 0x0230, 4, 0, 0x0234, 0), -+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, -+ 0x0240, 4, 0, 0x0244, 0), -+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, -+ 0x0250, 4, 0, 0x0254, 0), -+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, -+ 0x0260, 4, 0, 0x0264, 0), -+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, -+ 0x0278, 4, 0, 0x027C, 0), -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_apmixed[] = { -+ { .compatible = "mediatek,mt7981-apmixedsys", }, -+ { /* sentinel */ } -+}; -+ -+static int clk_mt7981_apmixed_probe(struct platform_device *pdev) -+{ -+ struct clk_hw_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -+ -+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ if (r) { -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+ goto free_apmixed_data; -+ } -+ return r; -+ -+free_apmixed_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+} -+ -+static struct platform_driver clk_mt7981_apmixed_drv = { -+ .probe = clk_mt7981_apmixed_probe, -+ .driver = { -+ .name = "clk-mt7981-apmixed", -+ .of_match_table = of_match_clk_mt7981_apmixed, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_apmixed_drv); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-eth.c -@@ -0,0 +1,118 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-mtk.h" -+#include "clk-gate.h" -+ -+#include -+ -+static const struct mtk_gate_regs sgmii0_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII0(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii0_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii0_clks[] __initconst = { -+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2), -+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3), -+ GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4), -+ GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5), -+}; -+ -+static const struct mtk_gate_regs sgmii1_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII1(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii1_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii1_clks[] __initconst = { -+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2), -+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3), -+ GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4), -+ GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5), -+}; -+ -+static const struct mtk_gate_regs eth_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETH(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = ð_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate eth_clks[] __initconst = { -+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6), -+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7), -+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8), -+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15), -+}; -+ -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+}; -+ -+static const struct mtk_clk_desc sgmii0_desc = { -+ .clks = sgmii0_clks, -+ .num_clks = ARRAY_SIZE(sgmii0_clks), -+}; -+ -+static const struct mtk_clk_desc sgmii1_desc = { -+ .clks = sgmii1_clks, -+ .num_clks = ARRAY_SIZE(sgmii1_clks), -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_eth[] = { -+ { .compatible = "mediatek,mt7981-ethsys", .data = ð_desc }, -+ { .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc }, -+ { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_eth_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-eth", -+ .of_match_table = of_match_clk_mt7981_eth, -+ }, -+}; -+module_platform_driver(clk_mt7981_eth_drv); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c -@@ -0,0 +1,207 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+ -+#include -+#include -+ -+static DEFINE_SPINLOCK(mt7981_clk_lock); -+ -+static const struct mtk_fixed_factor infra_divs[] = { -+ FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2), -+}; -+ -+static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_spi0_parents[] __initconst = { "i2c_sel", -+ "spi_sel" }; -+ -+static const char *const infra_spi1_parents[] __initconst = { "i2c_sel", -+ "spim_mst_sel" }; -+ -+static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" }; -+ -+static const char *const infra_pwm_bsel_parents[] __initconst = { -+ "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel" -+}; -+ -+static const char *const infra_pcie_parents[] __initconst = { -+ "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel" -+}; -+ -+static const struct mtk_mux infra_muxes[] = { -+ /* MODULE_CLK_SEL_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", -+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", -+ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", -+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", -+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, -+ 2, -1, -1, -1), -+ /* MODULE_CLK_SEL_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", -+ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, -+ -1, -1, -1), -+}; -+ -+static const struct mtk_gate_regs infra0_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra1_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra2_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra0_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra1_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra2_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+static const struct mtk_gate infra_clks[] = { -+ /* INFRA0 */ -+ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0), -+ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1), -+ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), -+ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), -+ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), -+ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6), -+ -+ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8), -+ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), -+ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10), -+ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11), -+ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13), -+ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", -+ 14), -+ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15), -+ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16), -+ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24), -+ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), -+ GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27), -+ /* INFRA1 */ -+ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), -+ GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1), -+ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), -+ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), -+ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), -+ GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6), -+ GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7), -+ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8), -+ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9), -+ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10), -+ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), -+ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), -+ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", -+ 13), -+ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", -+ 14), -+ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15), -+ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16), -+ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17), -+ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18), -+ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19), -+ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), -+ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21), -+ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23), -+ GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25), -+ GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26), -+ /* INFRA2 */ -+ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0), -+ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1), -+ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2), -+ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3), -+ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12), -+ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", -+ 13), -+ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14), -+ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15), -+}; -+ -+static const struct mtk_clk_desc infracfg_desc = { -+ .factor_clks = infra_divs, -+ .num_factor_clks = ARRAY_SIZE(infra_divs), -+ .mux_clks = infra_muxes, -+ .num_mux_clks = ARRAY_SIZE(infra_muxes), -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .clk_lock = &mt7981_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_infracfg[] = { -+ { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_infracfg_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-infracfg", -+ .of_match_table = of_match_clk_mt7981_infracfg, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_infracfg_drv); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c -@@ -0,0 +1,422 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+ -+#include -+#include -+ -+static DEFINE_SPINLOCK(mt7981_clk_lock); -+ -+static const struct mtk_fixed_factor top_divs[] = { -+ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), -+ FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), -+ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), -+ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), -+ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), -+ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), -+ FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), -+ FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), -+ FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), -+ FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), -+ FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), -+ FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), -+ FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), -+ FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), -+ FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), -+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), -+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), -+ FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), -+ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), -+ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), -+ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), -+ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), -+ FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), -+ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), -+ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), -+ FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), -+ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), -+ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), -+ FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), -+ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), -+ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), -+ FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), -+ FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), -+ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), -+ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), -+ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), -+ FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), -+ FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), -+ FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), -+ FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), -+ FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), -+ FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), -+ FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), -+ FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), -+ FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), -+ FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), -+ FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), -+ FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), -+ FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), -+ FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), -+ FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), -+ FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), -+ FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), -+ FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), -+ FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), -+ FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), -+ FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), -+ FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), -+ FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), -+ FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), -+ FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), -+ FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), -+ FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), -+}; -+ -+static const char * const nfi1x_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_net2_d6", -+ "cb_m_d4", -+ "cb_mm_d8", -+ "net1_d8_d4", -+ "cb_m_d8" -+}; -+ -+static const char * const spinfi_parents[] __initconst = { -+ "cksq_40m_d2", -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "cb_mm_d8", -+ "net1_d8_d4", -+ "mm_d6_d2", -+ "cb_m_d8" -+}; -+ -+static const char * const spi_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_net2_d6", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "net1_d8_d4" -+}; -+ -+static const char * const uart_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d8", -+ "m_d8_d2" -+}; -+ -+static const char * const pwm_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d2", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "m_d8_d2", -+ "cb_rtc_32k" -+}; -+ -+static const char * const i2c_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "net1_d8_d4" -+}; -+ -+static const char * const pextp_tl_ck_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "cb_rtc_32k" -+}; -+ -+static const char * const emmc_208m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_net2_d4", -+ "cb_apll2_196m", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_mm_d6" -+}; -+ -+static const char * const emmc_400m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d2", -+ "cb_mm_d2", -+ "cb_net2_d2" -+}; -+ -+static const char * const csw_f26m_parents[] __initconst = { -+ "cksq_40m_d2", -+ "m_d8_d2" -+}; -+ -+static const char * const dramc_md32_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_wedmcu_208m" -+}; -+ -+static const char * const sysaxi_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d2" -+}; -+ -+static const char * const sysapb_parents[] __initconst = { -+ "cb_cksq_40m", -+ "m_d3_d2" -+}; -+ -+static const char * const arm_db_main_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d6" -+}; -+ -+static const char * const ap2cnn_host_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d4" -+}; -+ -+static const char * const netsys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d2" -+}; -+ -+static const char * const netsys_500m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net1_d5" -+}; -+ -+static const char * const netsys_mcu_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_720m", -+ "cb_net1_d4", -+ "cb_net1_d5", -+ "cb_m_416m" -+}; -+ -+static const char * const netsys_2x_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_800m", -+ "cb_mm_720m" -+}; -+ -+static const char * const sgm_325m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_sgm_325m" -+}; -+ -+static const char * const sgm_reg_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d4" -+}; -+ -+static const char * const eip97b_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net1_d5", -+ "cb_m_416m", -+ "cb_mm_d2", -+ "net1_d5_d2" -+}; -+ -+static const char * const aud_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_apll2_196m" -+}; -+ -+static const char * const a1sys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "apll2_d4" -+}; -+ -+static const char * const aud_l_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_apll2_196m", -+ "m_d8_d2" -+}; -+ -+static const char * const a_tuner_parents[] __initconst = { -+ "cb_cksq_40m", -+ "apll2_d4", -+ "m_d8_d2" -+}; -+ -+static const char * const u2u3_parents[] __initconst = { -+ "cb_cksq_40m", -+ "m_d8_d2" -+}; -+ -+static const char * const u2u3_sys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4" -+}; -+ -+static const char * const usb_frmcnt_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d3_d5" -+}; -+ -+static const struct mtk_mux top_muxes[] = { -+ /* CLK_CFG_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, -+ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, -+ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, -+ 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, -+ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), -+ /* CLK_CFG_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, -+ 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, -+ 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, -+ 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", -+ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, -+ 0x1C0, 7), -+ /* CLK_CFG_2 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", -+ emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, -+ 0x1C0, 8), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", -+ emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, -+ 0x1C0, 9), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", -+ csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, -+ 0x1C0, 10, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", -+ csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, -+ 31, 0x1C0, 11, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ /* CLK_CFG_3 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -+ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, -+ 7, 0x1C0, 12, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", -+ sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, -+ 0x1C0, 13, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", -+ sysapb_parents, 0x030, 0x034, 0x038, 16, 1, -+ 23, 0x1C0, 14, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", -+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, -+ 0x1C0, 15), -+ /* CLK_CFG_4 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", -+ ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, -+ 0x1C0, 16), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, -+ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", -+ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, -+ 0x1C0, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", -+ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, -+ 0x1C0, 19), -+ /* CLK_CFG_5 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", -+ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, -+ 0x1C0, 20), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", -+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, -+ 0x1C0, 21), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, -+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, -+ 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), -+ /* CLK_CFG_6 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", -+ csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, -+ 7, 0x1C0, 24), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, -+ 0x064, 0x068, 8, 1, 15, 0x1C0, 25), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, -+ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, -+ 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), -+ /* CLK_CFG_7 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", -+ a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, -+ 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, -+ 0x074, 0x078, 8, 1, 15, 0x1C0, 29), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", -+ u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, -+ 0x1C0, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", -+ u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, -+ 0x1C4, 0), -+ /* CLK_CFG_8 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", -+ usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, -+ 0x1C4, 1), -+}; -+ -+static struct mtk_composite top_aud_divs[] = { -+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", -+ 0x0420, 0, 0x0420, 8, 8), -+}; -+ -+static const struct mtk_clk_desc topck_desc = { -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .composite_clks = top_aud_divs, -+ .num_composite_clks = ARRAY_SIZE(top_aud_divs), -+ .clk_lock = &mt7981_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_topckgen[] = { -+ { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_topckgen_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-topckgen", -+ .of_match_table = of_match_clk_mt7981_topckgen, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_topckgen_drv); diff --git a/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch b/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch deleted file mode 100644 index 8820d57f01fe35..00000000000000 --- a/target/linux/mediatek/patches-6.1/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch +++ /dev/null @@ -1,30 +0,0 @@ -From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 18 Feb 2024 01:59:59 +0000 -Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical - -Without the SGM_REG_SEL clock enabled the system freezes if trying to -access registers used by MT7981 clock drivers itself. -Mark SGM_REG_SEL as critical to make sure it is always enabled to -prevent freezes on boot depending on probe order. - -Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support") -Signed-off-by: Daniel Golle ---- - drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7981-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c -@@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[] - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", - sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, - 0x1C0, 21), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, -- 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, -+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, - 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), - /* CLK_CFG_6 */ diff --git a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch deleted file mode 100644 index a365f0860bbc33..00000000000000 --- a/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -141,6 +141,13 @@ config PINCTRL_MT7986 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7988 -+ bool "Mediatek MT7988 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "Mediatek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch b/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch deleted file mode 100644 index ad4ecdf83ffd38..00000000000000 --- a/target/linux/mediatek/patches-6.1/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch +++ /dev/null @@ -1,75 +0,0 @@ -From cc4d9e0c77494fcf6bccbc57e23db0007cf681b7 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 03:33:46 +0000 -Subject: [PATCH] dt-bindings: clock: Add compatibles for MT7981 - -Add compatible string for MT7981 to existing bindings at - - mediatek,apmixedsys.yaml - - mediatek,topckgen.yaml - - mediatek,ethsys.txt - - mediatek,infracfg.yaml - - mediatek,sgmiisys.txt - -Signed-off-by: Jianhui Zhao -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/cc85ee470c781ff4013f6c21c92c0a21574b12b2.1674703830.git.daniel@makrotopia.org -Signed-off-by: Stephen Boyd ---- - .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + - .../devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml | 1 + - .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 2 ++ - .../devicetree/bindings/clock/mediatek,apmixedsys.yaml | 1 + - Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml | 1 + - 5 files changed, 6 insertions(+) - ---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt -+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt -@@ -10,6 +10,7 @@ Required Properties: - - "mediatek,mt7622-ethsys", "syscon" - - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" - - "mediatek,mt7629-ethsys", "syscon" -+ - "mediatek,mt7981-ethsys", "syscon" - - "mediatek,mt7986-ethsys", "syscon" - - #clock-cells: Must be 1 - - #reset-cells: Must be 1 ---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml -+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml -@@ -28,6 +28,7 @@ properties: - - mediatek,mt6797-infracfg - - mediatek,mt7622-infracfg - - mediatek,mt7629-infracfg -+ - mediatek,mt7981-infracfg - - mediatek,mt7986-infracfg - - mediatek,mt8135-infracfg - - mediatek,mt8167-infracfg ---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt -+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt -@@ -8,6 +8,8 @@ Required Properties: - - compatible: Should be: - - "mediatek,mt7622-sgmiisys", "syscon" - - "mediatek,mt7629-sgmiisys", "syscon" -+ - "mediatek,mt7981-sgmiisys_0", "syscon" -+ - "mediatek,mt7981-sgmiisys_1", "syscon" - - "mediatek,mt7986-sgmiisys_0", "syscon" - - "mediatek,mt7986-sgmiisys_1", "syscon" - - #clock-cells: Must be 1 ---- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml -+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml -@@ -20,6 +20,7 @@ properties: - - enum: - - mediatek,mt6797-apmixedsys - - mediatek,mt7622-apmixedsys -+ - mediatek,mt7981-apmixedsys - - mediatek,mt7986-apmixedsys - - mediatek,mt8135-apmixedsys - - mediatek,mt8173-apmixedsys ---- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml -+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml -@@ -35,6 +35,7 @@ properties: - - mediatek,mt6779-topckgen - - mediatek,mt6795-topckgen - - mediatek,mt7629-topckgen -+ - mediatek,mt7981-topckgen - - mediatek,mt7986-topckgen - - mediatek,mt8167-topckgen - - mediatek,mt8183-topckgen diff --git a/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch b/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch deleted file mode 100644 index 48d3d4e90cec0c..00000000000000 --- a/target/linux/mediatek/patches-6.1/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch +++ /dev/null @@ -1,107 +0,0 @@ -From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 19 Mar 2023 12:56:52 +0000 -Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT - schema - -Convert mediatek,sgmiiisys bindings to DT schema format. -Add maintainer Matthias Brugger, no maintainers were listed in the -original documentation. -As this node is also referenced by the Ethernet controller and used -as SGMII PCS add this fact to the description. -Move the file to Documentation/devicetree/bindings/net/pcs/ which seems -more appropriate given that the great majority of registers are related -to SGMII PCS functionality and only one register represents clock bits. - -Reviewed-by: Rob Herring -Signed-off-by: Daniel Golle -Signed-off-by: Jakub Kicinski ---- - .../arm/mediatek/mediatek,sgmiisys.txt | 27 ---------- - .../bindings/net/pcs/mediatek,sgmiisys.yaml | 49 +++++++++++++++++++ - 2 files changed, 49 insertions(+), 27 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt - create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml - ---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt -+++ /dev/null -@@ -1,27 +0,0 @@ --MediaTek SGMIISYS controller --============================ -- --The MediaTek SGMIISYS controller provides various clocks to the system. -- --Required Properties: -- --- compatible: Should be: -- - "mediatek,mt7622-sgmiisys", "syscon" -- - "mediatek,mt7629-sgmiisys", "syscon" -- - "mediatek,mt7981-sgmiisys_0", "syscon" -- - "mediatek,mt7981-sgmiisys_1", "syscon" -- - "mediatek,mt7986-sgmiisys_0", "syscon" -- - "mediatek,mt7986-sgmiisys_1", "syscon" --- #clock-cells: Must be 1 -- --The SGMIISYS controller uses the common clk binding from --Documentation/devicetree/bindings/clock/clock-bindings.txt --The available clocks are defined in dt-bindings/clock/mt*-clk.h. -- --Example: -- --sgmiisys: sgmiisys@1b128000 { -- compatible = "mediatek,mt7622-sgmiisys", "syscon"; -- reg = <0 0x1b128000 0 0x1000>; -- #clock-cells = <1>; --}; ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml -@@ -0,0 +1,49 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek SGMIISYS Controller -+ -+maintainers: -+ - Matthias Brugger -+ -+description: -+ The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks -+ to the ethernet subsystem to which it is attached. -+ -+properties: -+ compatible: -+ items: -+ - enum: -+ - mediatek,mt7622-sgmiisys -+ - mediatek,mt7629-sgmiisys -+ - mediatek,mt7986-sgmiisys_0 -+ - mediatek,mt7986-sgmiisys_1 -+ - const: syscon -+ -+ reg: -+ maxItems: 1 -+ -+ '#clock-cells': -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - '#clock-cells' -+ -+additionalProperties: false -+ -+examples: -+ - | -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ sgmiisys: syscon@1b128000 { -+ compatible = "mediatek,mt7622-sgmiisys", "syscon"; -+ reg = <0 0x1b128000 0 0x1000>; -+ #clock-cells = <1>; -+ }; -+ }; diff --git a/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch deleted file mode 100644 index 62a64b9dd03a2d..00000000000000 --- a/target/linux/mediatek/patches-6.1/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 4f7eb19c4f44078100659f6ba073b0cc7191bc91 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 19 Mar 2023 12:57:04 +0000 -Subject: [PATCH 2/2] dt-bindings: net: pcs: mediatek,sgmiisys: add MT7981 SoC - -Add mediatek,pnswap boolean property needed on many boards using the -MediaTek MT7981 SoC. - -Reviewed-by: Rob Herring -Signed-off-by: Daniel Golle -Signed-off-by: Jakub Kicinski ---- - .../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml -+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml -@@ -19,6 +19,8 @@ properties: - - enum: - - mediatek,mt7622-sgmiisys - - mediatek,mt7629-sgmiisys -+ - mediatek,mt7981-sgmiisys_0 -+ - mediatek,mt7981-sgmiisys_1 - - mediatek,mt7986-sgmiisys_0 - - mediatek,mt7986-sgmiisys_1 - - const: syscon -@@ -29,6 +31,10 @@ properties: - '#clock-cells': - const: 1 - -+ mediatek,pnswap: -+ description: Invert polarity of the SGMII data lanes -+ type: boolean -+ - required: - - compatible - - reg diff --git a/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch b/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch deleted file mode 100644 index 946db82235c6e9..00000000000000 --- a/target/linux/mediatek/patches-6.1/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sun, 19 Nov 2023 22:24:16 +0100 -Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert - to DT schema -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -DT schema helps validating DTS files. Binding was moved to clock/ as -this hardware is a clock provider. Example required a small fix for -"reg" value (1 address cell + 1 size cell). - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com -Signed-off-by: Stephen Boyd ---- - .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ---------- - .../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++ - 2 files changed, 54 insertions(+), 29 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt - create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml - ---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt -+++ /dev/null -@@ -1,29 +0,0 @@ --Mediatek ethsys controller --============================ -- --The Mediatek ethsys controller provides various clocks to the system. -- --Required Properties: -- --- compatible: Should be: -- - "mediatek,mt2701-ethsys", "syscon" -- - "mediatek,mt7622-ethsys", "syscon" -- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" -- - "mediatek,mt7629-ethsys", "syscon" -- - "mediatek,mt7981-ethsys", "syscon" -- - "mediatek,mt7986-ethsys", "syscon" --- #clock-cells: Must be 1 --- #reset-cells: Must be 1 -- --The ethsys controller uses the common clk binding from --Documentation/devicetree/bindings/clock/clock-bindings.txt --The available clocks are defined in dt-bindings/clock/mt*-clk.h. -- --Example: -- --ethsys: clock-controller@1b000000 { -- compatible = "mediatek,mt2701-ethsys", "syscon"; -- reg = <0 0x1b000000 0 0x1000>; -- #clock-cells = <1>; -- #reset-cells = <1>; --}; ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml -@@ -0,0 +1,54 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Mediatek ethsys controller -+ -+description: -+ The available clocks are defined in dt-bindings/clock/mt*-clk.h. -+ -+maintainers: -+ - James Liao -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - mediatek,mt2701-ethsys -+ - mediatek,mt7622-ethsys -+ - mediatek,mt7629-ethsys -+ - mediatek,mt7981-ethsys -+ - mediatek,mt7986-ethsys -+ - const: syscon -+ - items: -+ - const: mediatek,mt7623-ethsys -+ - const: mediatek,mt2701-ethsys -+ - const: syscon -+ -+ reg: -+ maxItems: 1 -+ -+ "#clock-cells": -+ const: 1 -+ -+ "#reset-cells": -+ const: 1 -+ -+required: -+ - reg -+ - "#clock-cells" -+ - "#reset-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ clock-controller@1b000000 { -+ compatible = "mediatek,mt2701-ethsys", "syscon"; -+ reg = <0x1b000000 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; diff --git a/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch b/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch deleted file mode 100644 index 47f05e93c620f0..00000000000000 --- a/target/linux/mediatek/patches-6.1/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 17 Dec 2023 21:49:45 +0000 -Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset - IDs - -Add reset ID for ethwarp subsystem allowing to reset the built-in -Ethernet switch of the MediaTek MT7988 SoC. - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Acked-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org -Signed-off-by: Stephen Boyd ---- - include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h - ---- /dev/null -+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h -@@ -0,0 +1,13 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2023 Daniel Golle -+ * Author: Daniel Golle -+ */ -+ -+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988 -+#define _DT_BINDINGS_RESET_CONTROLLER_MT7988 -+ -+/* ETHWARP resets */ -+#define MT7988_ETHWARP_RST_SWITCH 0 -+ -+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ diff --git a/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch b/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch deleted file mode 100644 index cf5cae634105f2..00000000000000 --- a/target/linux/mediatek/patches-6.1/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch +++ /dev/null @@ -1,302 +0,0 @@ -From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 17 Dec 2023 21:49:33 +0000 -Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs - -Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg, -ethernet and xfipll subsystem clocks. - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle -Acked-by: Krzysztof Kozlowski -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org -Signed-off-by: Stephen Boyd ---- - .../dt-bindings/clock/mediatek,mt7988-clk.h | 280 ++++++++++++++++++ - 1 file changed, 280 insertions(+) - create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h - ---- /dev/null -+++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h -@@ -0,0 +1,280 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7988_H -+#define _DT_BINDINGS_CLK_MT7988_H -+ -+/* APMIXEDSYS */ -+ -+#define CLK_APMIXED_NETSYSPLL 0 -+#define CLK_APMIXED_MPLL 1 -+#define CLK_APMIXED_MMPLL 2 -+#define CLK_APMIXED_APLL2 3 -+#define CLK_APMIXED_NET1PLL 4 -+#define CLK_APMIXED_NET2PLL 5 -+#define CLK_APMIXED_WEDMCUPLL 6 -+#define CLK_APMIXED_SGMPLL 7 -+#define CLK_APMIXED_ARM_B 8 -+#define CLK_APMIXED_CCIPLL2_B 9 -+#define CLK_APMIXED_USXGMIIPLL 10 -+#define CLK_APMIXED_MSDCPLL 11 -+ -+/* TOPCKGEN */ -+ -+#define CLK_TOP_XTAL 0 -+#define CLK_TOP_XTAL_D2 1 -+#define CLK_TOP_RTC_32K 2 -+#define CLK_TOP_RTC_32P7K 3 -+#define CLK_TOP_MPLL_D2 4 -+#define CLK_TOP_MPLL_D3_D2 5 -+#define CLK_TOP_MPLL_D4 6 -+#define CLK_TOP_MPLL_D8 7 -+#define CLK_TOP_MPLL_D8_D2 8 -+#define CLK_TOP_MMPLL_D2 9 -+#define CLK_TOP_MMPLL_D3_D5 10 -+#define CLK_TOP_MMPLL_D4 11 -+#define CLK_TOP_MMPLL_D6_D2 12 -+#define CLK_TOP_MMPLL_D8 13 -+#define CLK_TOP_APLL2_D4 14 -+#define CLK_TOP_NET1PLL_D4 15 -+#define CLK_TOP_NET1PLL_D5 16 -+#define CLK_TOP_NET1PLL_D5_D2 17 -+#define CLK_TOP_NET1PLL_D5_D4 18 -+#define CLK_TOP_NET1PLL_D8 19 -+#define CLK_TOP_NET1PLL_D8_D2 20 -+#define CLK_TOP_NET1PLL_D8_D4 21 -+#define CLK_TOP_NET1PLL_D8_D8 22 -+#define CLK_TOP_NET1PLL_D8_D16 23 -+#define CLK_TOP_NET2PLL_D2 24 -+#define CLK_TOP_NET2PLL_D4 25 -+#define CLK_TOP_NET2PLL_D4_D4 26 -+#define CLK_TOP_NET2PLL_D4_D8 27 -+#define CLK_TOP_NET2PLL_D6 28 -+#define CLK_TOP_NET2PLL_D8 29 -+#define CLK_TOP_NETSYS_SEL 30 -+#define CLK_TOP_NETSYS_500M_SEL 31 -+#define CLK_TOP_NETSYS_2X_SEL 32 -+#define CLK_TOP_NETSYS_GSW_SEL 33 -+#define CLK_TOP_ETH_GMII_SEL 34 -+#define CLK_TOP_NETSYS_MCU_SEL 35 -+#define CLK_TOP_NETSYS_PAO_2X_SEL 36 -+#define CLK_TOP_EIP197_SEL 37 -+#define CLK_TOP_AXI_INFRA_SEL 38 -+#define CLK_TOP_UART_SEL 39 -+#define CLK_TOP_EMMC_250M_SEL 40 -+#define CLK_TOP_EMMC_400M_SEL 41 -+#define CLK_TOP_SPI_SEL 42 -+#define CLK_TOP_SPIM_MST_SEL 43 -+#define CLK_TOP_NFI1X_SEL 44 -+#define CLK_TOP_SPINFI_SEL 45 -+#define CLK_TOP_PWM_SEL 46 -+#define CLK_TOP_I2C_SEL 47 -+#define CLK_TOP_PCIE_MBIST_250M_SEL 48 -+#define CLK_TOP_PEXTP_TL_SEL 49 -+#define CLK_TOP_PEXTP_TL_P1_SEL 50 -+#define CLK_TOP_PEXTP_TL_P2_SEL 51 -+#define CLK_TOP_PEXTP_TL_P3_SEL 52 -+#define CLK_TOP_USB_SYS_SEL 53 -+#define CLK_TOP_USB_SYS_P1_SEL 54 -+#define CLK_TOP_USB_XHCI_SEL 55 -+#define CLK_TOP_USB_XHCI_P1_SEL 56 -+#define CLK_TOP_USB_FRMCNT_SEL 57 -+#define CLK_TOP_USB_FRMCNT_P1_SEL 58 -+#define CLK_TOP_AUD_SEL 59 -+#define CLK_TOP_A1SYS_SEL 60 -+#define CLK_TOP_AUD_L_SEL 61 -+#define CLK_TOP_A_TUNER_SEL 62 -+#define CLK_TOP_SSPXTP_SEL 63 -+#define CLK_TOP_USB_PHY_SEL 64 -+#define CLK_TOP_USXGMII_SBUS_0_SEL 65 -+#define CLK_TOP_USXGMII_SBUS_1_SEL 66 -+#define CLK_TOP_SGM_0_SEL 67 -+#define CLK_TOP_SGM_SBUS_0_SEL 68 -+#define CLK_TOP_SGM_1_SEL 69 -+#define CLK_TOP_SGM_SBUS_1_SEL 70 -+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 -+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 -+#define CLK_TOP_SYSAXI_SEL 73 -+#define CLK_TOP_SYSAPB_SEL 74 -+#define CLK_TOP_ETH_REFCK_50M_SEL 75 -+#define CLK_TOP_ETH_SYS_200M_SEL 76 -+#define CLK_TOP_ETH_SYS_SEL 77 -+#define CLK_TOP_ETH_XGMII_SEL 78 -+#define CLK_TOP_BUS_TOPS_SEL 79 -+#define CLK_TOP_NPU_TOPS_SEL 80 -+#define CLK_TOP_DRAMC_SEL 81 -+#define CLK_TOP_DRAMC_MD32_SEL 82 -+#define CLK_TOP_INFRA_F26M_SEL 83 -+#define CLK_TOP_PEXTP_P0_SEL 84 -+#define CLK_TOP_PEXTP_P1_SEL 85 -+#define CLK_TOP_PEXTP_P2_SEL 86 -+#define CLK_TOP_PEXTP_P3_SEL 87 -+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 -+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 -+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 -+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 -+#define CLK_TOP_CKM_SEL 92 -+#define CLK_TOP_DA_SEL 93 -+#define CLK_TOP_PEXTP_SEL 94 -+#define CLK_TOP_TOPS_P2_26M_SEL 95 -+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 -+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 -+#define CLK_TOP_MACSEC_SEL 98 -+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 -+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 -+#define CLK_TOP_NETSYS_WARP_SEL 101 -+#define CLK_TOP_ETH_MII_SEL 102 -+#define CLK_TOP_NPU_SEL 103 -+#define CLK_TOP_AUD_I2S_M 104 -+ -+/* MCUSYS */ -+ -+#define CLK_MCU_BUS_DIV_SEL 0 -+#define CLK_MCU_ARM_DIV_SEL 1 -+ -+/* INFRACFG_AO */ -+ -+#define CLK_INFRA_MUX_UART0_SEL 0 -+#define CLK_INFRA_MUX_UART1_SEL 1 -+#define CLK_INFRA_MUX_UART2_SEL 2 -+#define CLK_INFRA_MUX_SPI0_SEL 3 -+#define CLK_INFRA_MUX_SPI1_SEL 4 -+#define CLK_INFRA_MUX_SPI2_SEL 5 -+#define CLK_INFRA_PWM_SEL 6 -+#define CLK_INFRA_PWM_CK1_SEL 7 -+#define CLK_INFRA_PWM_CK2_SEL 8 -+#define CLK_INFRA_PWM_CK3_SEL 9 -+#define CLK_INFRA_PWM_CK4_SEL 10 -+#define CLK_INFRA_PWM_CK5_SEL 11 -+#define CLK_INFRA_PWM_CK6_SEL 12 -+#define CLK_INFRA_PWM_CK7_SEL 13 -+#define CLK_INFRA_PWM_CK8_SEL 14 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 -+ -+/* INFRACFG */ -+ -+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 -+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 -+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 -+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 -+#define CLK_INFRA_66M_GPT_BCK 23 -+#define CLK_INFRA_66M_PWM_HCK 24 -+#define CLK_INFRA_66M_PWM_BCK 25 -+#define CLK_INFRA_66M_PWM_CK1 26 -+#define CLK_INFRA_66M_PWM_CK2 27 -+#define CLK_INFRA_66M_PWM_CK3 28 -+#define CLK_INFRA_66M_PWM_CK4 29 -+#define CLK_INFRA_66M_PWM_CK5 30 -+#define CLK_INFRA_66M_PWM_CK6 31 -+#define CLK_INFRA_66M_PWM_CK7 32 -+#define CLK_INFRA_66M_PWM_CK8 33 -+#define CLK_INFRA_133M_CQDMA_BCK 34 -+#define CLK_INFRA_66M_AUD_SLV_BCK 35 -+#define CLK_INFRA_AUD_26M 36 -+#define CLK_INFRA_AUD_L 37 -+#define CLK_INFRA_AUD_AUD 38 -+#define CLK_INFRA_AUD_EG2 39 -+#define CLK_INFRA_DRAMC_F26M 40 -+#define CLK_INFRA_133M_DBG_ACKM 41 -+#define CLK_INFRA_66M_AP_DMA_BCK 42 -+#define CLK_INFRA_66M_SEJ_BCK 43 -+#define CLK_INFRA_PRE_CK_SEJ_F13M 44 -+#define CLK_INFRA_26M_THERM_SYSTEM 45 -+#define CLK_INFRA_I2C_BCK 46 -+#define CLK_INFRA_52M_UART0_CK 47 -+#define CLK_INFRA_52M_UART1_CK 48 -+#define CLK_INFRA_52M_UART2_CK 49 -+#define CLK_INFRA_NFI 50 -+#define CLK_INFRA_SPINFI 51 -+#define CLK_INFRA_66M_NFI_HCK 52 -+#define CLK_INFRA_104M_SPI0 53 -+#define CLK_INFRA_104M_SPI1 54 -+#define CLK_INFRA_104M_SPI2_BCK 55 -+#define CLK_INFRA_66M_SPI0_HCK 56 -+#define CLK_INFRA_66M_SPI1_HCK 57 -+#define CLK_INFRA_66M_SPI2_HCK 58 -+#define CLK_INFRA_66M_FLASHIF_AXI 59 -+#define CLK_INFRA_RTC 60 -+#define CLK_INFRA_26M_ADC_BCK 61 -+#define CLK_INFRA_RC_ADC 62 -+#define CLK_INFRA_MSDC400 63 -+#define CLK_INFRA_MSDC2_HCK 64 -+#define CLK_INFRA_133M_MSDC_0_HCK 65 -+#define CLK_INFRA_66M_MSDC_0_HCK 66 -+#define CLK_INFRA_133M_CPUM_BCK 67 -+#define CLK_INFRA_BIST2FPC 68 -+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 -+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 -+#define CLK_INFRA_133M_USB_HCK 71 -+#define CLK_INFRA_133M_USB_HCK_CK_P1 72 -+#define CLK_INFRA_66M_USB_HCK 73 -+#define CLK_INFRA_66M_USB_HCK_CK_P1 74 -+#define CLK_INFRA_USB_SYS 75 -+#define CLK_INFRA_USB_SYS_CK_P1 76 -+#define CLK_INFRA_USB_REF 77 -+#define CLK_INFRA_USB_CK_P1 78 -+#define CLK_INFRA_USB_FRMCNT 79 -+#define CLK_INFRA_USB_FRMCNT_CK_P1 80 -+#define CLK_INFRA_USB_PIPE 81 -+#define CLK_INFRA_USB_PIPE_CK_P1 82 -+#define CLK_INFRA_USB_UTMI 83 -+#define CLK_INFRA_USB_UTMI_CK_P1 84 -+#define CLK_INFRA_USB_XHCI 85 -+#define CLK_INFRA_USB_XHCI_CK_P1 86 -+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 -+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 -+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 -+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 -+#define CLK_INFRA_PCIE_PIPE_P0 91 -+#define CLK_INFRA_PCIE_PIPE_P1 92 -+#define CLK_INFRA_PCIE_PIPE_P2 93 -+#define CLK_INFRA_PCIE_PIPE_P3 94 -+#define CLK_INFRA_133M_PCIE_CK_P0 95 -+#define CLK_INFRA_133M_PCIE_CK_P1 96 -+#define CLK_INFRA_133M_PCIE_CK_P2 97 -+#define CLK_INFRA_133M_PCIE_CK_P3 98 -+ -+/* ETHDMA */ -+ -+#define CLK_ETHDMA_XGP1_EN 0 -+#define CLK_ETHDMA_XGP2_EN 1 -+#define CLK_ETHDMA_XGP3_EN 2 -+#define CLK_ETHDMA_FE_EN 3 -+#define CLK_ETHDMA_GP2_EN 4 -+#define CLK_ETHDMA_GP1_EN 5 -+#define CLK_ETHDMA_GP3_EN 6 -+#define CLK_ETHDMA_ESW_EN 7 -+#define CLK_ETHDMA_CRYPT0_EN 8 -+#define CLK_ETHDMA_NR_CLK 9 -+ -+/* SGMIISYS_0 */ -+ -+#define CLK_SGM0_TX_EN 0 -+#define CLK_SGM0_RX_EN 1 -+#define CLK_SGMII0_NR_CLK 2 -+ -+/* SGMIISYS_1 */ -+ -+#define CLK_SGM1_TX_EN 0 -+#define CLK_SGM1_RX_EN 1 -+#define CLK_SGMII1_NR_CLK 2 -+ -+/* ETHWARP */ -+ -+#define CLK_ETHWARP_WOCPU2_EN 0 -+#define CLK_ETHWARP_WOCPU1_EN 1 -+#define CLK_ETHWARP_WOCPU0_EN 2 -+#define CLK_ETHWARP_NR_CLK 3 -+ -+/* XFIPLL */ -+#define CLK_XFIPLL_PLL 0 -+#define CLK_XFIPLL_PLL_EN 1 -+ -+#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch b/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch deleted file mode 100644 index 79088b461be3f7..00000000000000 --- a/target/linux/mediatek/patches-6.1/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch +++ /dev/null @@ -1,260 +0,0 @@ -From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 17 Dec 2023 21:49:55 +0000 -Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of - MT7988 - -Add various clock controllers found in the MT7988 SoC to existing -bindings (if applicable) and add files for the new ethwarp, mcusys -and xfi-pll clock controllers not previously present in any SoC. - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Stephen Boyd ---- - .../arm/mediatek/mediatek,infracfg.yaml | 1 + - .../bindings/clock/mediatek,apmixedsys.yaml | 1 + - .../bindings/clock/mediatek,ethsys.yaml | 1 + - .../clock/mediatek,mt7988-ethwarp.yaml | 52 +++++++++++++++ - .../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++ - .../bindings/clock/mediatek,topckgen.yaml | 2 + - .../bindings/net/pcs/mediatek,sgmiisys.yaml | 65 ++++++++++++++++--- - 7 files changed, 161 insertions(+), 9 deletions(-) - create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml - create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml - ---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml -+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml -@@ -30,6 +30,7 @@ properties: - - mediatek,mt7629-infracfg - - mediatek,mt7981-infracfg - - mediatek,mt7986-infracfg -+ - mediatek,mt7988-infracfg - - mediatek,mt8135-infracfg - - mediatek,mt8167-infracfg - - mediatek,mt8173-infracfg ---- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml -+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml -@@ -22,6 +22,7 @@ properties: - - mediatek,mt7622-apmixedsys - - mediatek,mt7981-apmixedsys - - mediatek,mt7986-apmixedsys -+ - mediatek,mt7988-apmixedsys - - mediatek,mt8135-apmixedsys - - mediatek,mt8173-apmixedsys - - mediatek,mt8516-apmixedsys ---- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml -+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml -@@ -22,6 +22,7 @@ properties: - - mediatek,mt7629-ethsys - - mediatek,mt7981-ethsys - - mediatek,mt7986-ethsys -+ - mediatek,mt7988-ethsys - - const: syscon - - items: - - const: mediatek,mt7623-ethsys ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml -@@ -0,0 +1,52 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MT7988 ethwarp Controller -+ -+maintainers: -+ - Daniel Golle -+ -+description: -+ The Mediatek MT7988 ethwarp controller provides clocks and resets for the -+ Ethernet related subsystems found the MT7988 SoC. -+ The clock values can be found in . -+ -+properties: -+ compatible: -+ items: -+ - const: mediatek,mt7988-ethwarp -+ -+ reg: -+ maxItems: 1 -+ -+ '#clock-cells': -+ const: 1 -+ -+ '#reset-cells': -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - '#clock-cells' -+ - '#reset-cells' -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ clock-controller@15031000 { -+ compatible = "mediatek,mt7988-ethwarp"; -+ reg = <0 0x15031000 0 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ }; ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml -@@ -0,0 +1,48 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MT7988 XFI PLL Clock Controller -+ -+maintainers: -+ - Daniel Golle -+ -+description: -+ The MediaTek XFI PLL controller provides the 156.25MHz clock for the -+ Ethernet SerDes PHY from the 40MHz top_xtal clock. -+ -+properties: -+ compatible: -+ const: mediatek,mt7988-xfi-pll -+ -+ reg: -+ maxItems: 1 -+ -+ resets: -+ maxItems: 1 -+ -+ '#clock-cells': -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - resets -+ - '#clock-cells' -+ -+additionalProperties: false -+ -+examples: -+ - | -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ clock-controller@11f40000 { -+ compatible = "mediatek,mt7988-xfi-pll"; -+ reg = <0 0x11f40000 0 0x1000>; -+ resets = <&watchdog 16>; -+ #clock-cells = <1>; -+ }; -+ }; ---- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml -+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml -@@ -37,6 +37,8 @@ properties: - - mediatek,mt7629-topckgen - - mediatek,mt7981-topckgen - - mediatek,mt7986-topckgen -+ - mediatek,mt7988-mcusys -+ - mediatek,mt7988-topckgen - - mediatek,mt8167-topckgen - - mediatek,mt8183-topckgen - - const: syscon ---- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml -+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml -@@ -15,15 +15,22 @@ description: - - properties: - compatible: -- items: -- - enum: -- - mediatek,mt7622-sgmiisys -- - mediatek,mt7629-sgmiisys -- - mediatek,mt7981-sgmiisys_0 -- - mediatek,mt7981-sgmiisys_1 -- - mediatek,mt7986-sgmiisys_0 -- - mediatek,mt7986-sgmiisys_1 -- - const: syscon -+ oneOf: -+ - items: -+ - enum: -+ - mediatek,mt7622-sgmiisys -+ - mediatek,mt7629-sgmiisys -+ - mediatek,mt7981-sgmiisys_0 -+ - mediatek,mt7981-sgmiisys_1 -+ - mediatek,mt7986-sgmiisys_0 -+ - mediatek,mt7986-sgmiisys_1 -+ - const: syscon -+ - items: -+ - enum: -+ - mediatek,mt7988-sgmiisys0 -+ - mediatek,mt7988-sgmiisys1 -+ - const: simple-mfd -+ - const: syscon - - reg: - maxItems: 1 -@@ -35,11 +42,51 @@ properties: - description: Invert polarity of the SGMII data lanes - type: boolean - -+ pcs: -+ type: object -+ description: MediaTek LynxI HSGMII PCS -+ properties: -+ compatible: -+ const: mediatek,mt7988-sgmii -+ -+ clocks: -+ maxItems: 3 -+ -+ clock-names: -+ items: -+ - const: sgmii_sel -+ - const: sgmii_tx -+ - const: sgmii_rx -+ -+ required: -+ - compatible -+ - clocks -+ - clock-names -+ -+ additionalProperties: false -+ - required: - - compatible - - reg - - '#clock-cells' - -+allOf: -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - mediatek,mt7988-sgmiisys0 -+ - mediatek,mt7988-sgmiisys1 -+ -+ then: -+ required: -+ - pcs -+ -+ else: -+ properties: -+ pcs: false -+ - additionalProperties: false - - examples: diff --git a/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch b/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch deleted file mode 100644 index ca37fc793a791a..00000000000000 --- a/target/linux/mediatek/patches-6.1/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch +++ /dev/null @@ -1,50 +0,0 @@ -From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 17 Dec 2023 21:50:07 +0000 -Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 - -Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead -of the previously hardcoded PCW_CHG_MASK macro if set. -This will needed for clocks on the MT7988 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-pll.c | 5 +++-- - drivers/clk/mediatek/clk-pll.h | 1 + - 2 files changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/clk/mediatek/clk-pll.c -+++ b/drivers/clk/mediatek/clk-pll.c -@@ -23,7 +23,7 @@ - #define CON0_BASE_EN BIT(0) - #define CON0_PWR_ON BIT(0) - #define CON0_ISO_EN BIT(1) --#define PCW_CHG_MASK BIT(31) -+#define PCW_CHG_BIT 31 - - #define AUDPLL_TUNER_EN BIT(31) - -@@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct - pll->data->pcw_shift); - val |= pcw << pll->data->pcw_shift; - writel(val, pll->pcw_addr); -- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; -+ chg = readl(pll->pcw_chg_addr) | -+ BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT); - writel(chg, pll->pcw_chg_addr); - if (pll->tuner_addr) - writel(val + 1, pll->tuner_addr); ---- a/drivers/clk/mediatek/clk-pll.h -+++ b/drivers/clk/mediatek/clk-pll.h -@@ -46,6 +46,7 @@ struct mtk_pll_data { - const char *parent_name; - u32 en_reg; - u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ -+ u8 pcw_chg_bit; - }; - - int mtk_clk_register_plls(struct device_node *node, diff --git a/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch b/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch deleted file mode 100644 index 61664b934cbb63..00000000000000 --- a/target/linux/mediatek/patches-6.1/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch +++ /dev/null @@ -1,1026 +0,0 @@ -From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 17 Dec 2023 21:50:15 +0000 -Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC - -Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are -typical MediaTek designs. - -Also add driver for XFIPLL clock generating the 156.25MHz clock for -the XFI SerDes. It needs an undocumented software workaround and has -an unknown internal design. - -Signed-off-by: Sam Shih -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org -[sboyd@kernel.org: Add module license to infracfg file] -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/Kconfig | 9 + - drivers/clk/mediatek/Makefile | 5 + - drivers/clk/mediatek/clk-mt7988-apmixed.c | 114 ++++++++ - drivers/clk/mediatek/clk-mt7988-eth.c | 150 ++++++++++ - drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++ - drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++ - drivers/clk/mediatek/clk-mt7988-xfipll.c | 82 ++++++ - 7 files changed, 960 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c - create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c - create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c - create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c - create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c - ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS - This driver adds support for clocks for Ethernet and SGMII - required on MediaTek MT7986 SoC. - -+config COMMON_CLK_MT7988 -+ tristate "Clock driver for MediaTek MT7988" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7988 basic clocks and clocks -+ required for various periperals found on this SoC. -+ - config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" - depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -60,6 +60,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o - obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o - obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o - obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o - obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c -@@ -0,0 +1,114 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include "clk-pll.h" -+#include -+ -+#define MT7988_PLL_FMAX (2500UL * MHZ) -+#define MT7988_PCW_CHG_BIT 2 -+ -+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \ -+ _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \ -+ _pcw_chg_reg) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .reg = _reg, \ -+ .pwr_reg = _pwr_reg, \ -+ .en_mask = _en_mask, \ -+ .flags = _flags, \ -+ .rst_bar_mask = BIT(_rst_bar_mask), \ -+ .fmax = MT7988_PLL_FMAX, \ -+ .pcwbits = _pcwbits, \ -+ .pd_reg = _pd_reg, \ -+ .pd_shift = _pd_shift, \ -+ .tuner_reg = _tuner_reg, \ -+ .tuner_en_reg = _tuner_en_reg, \ -+ .tuner_en_bit = _tuner_en_bit, \ -+ .pcw_reg = _pcw_reg, \ -+ .pcw_shift = _pcw_shift, \ -+ .pcw_chg_reg = _pcw_chg_reg, \ -+ .pcw_chg_bit = MT7988_PCW_CHG_BIT, \ -+ .parent_name = "clkxtal", \ -+ } -+ -+static const struct mtk_pll_data plls[] = { -+ PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0, -+ 0, 0, 0x0108, 0, 0x0104), -+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4, -+ 0, 0, 0, 0x0118, 0, 0x0114), -+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4, -+ 0, 0, 0, 0x0128, 0, 0x0124), -+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704, -+ 0x0700, 1, 0x0138, 0, 0x0134), -+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32, -+ 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), -+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, -+ 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154), -+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0, -+ 0, 0, 0x0168, 0, 0x0164), -+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0, -+ 0x0178, 0, 0x0174), -+ PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32, -+ 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204), -+ PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32, -+ 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), -+ PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32, -+ 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), -+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0, -+ 0, 0x0318, 0, 0x0314), -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_apmixed[] = { -+ { .compatible = "mediatek,mt7988-apmixedsys" }, -+ { /* sentinel */ } -+}; -+ -+static int clk_mt7988_apmixed_probe(struct platform_device *pdev) -+{ -+ struct clk_hw_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -+ if (r) -+ goto free_apmixed_data; -+ -+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ if (r) -+ goto unregister_plls; -+ -+ return r; -+ -+unregister_plls: -+ mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -+free_apmixed_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+} -+ -+static struct platform_driver clk_mt7988_apmixed_drv = { -+ .probe = clk_mt7988_apmixed_probe, -+ .driver = { -+ .name = "clk-mt7988-apmixed", -+ .of_match_table = of_match_clk_mt7988_apmixed, -+ }, -+}; -+builtin_platform_driver(clk_mt7988_apmixed_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-eth.c -@@ -0,0 +1,150 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "reset.h" -+#include -+#include -+ -+static const struct mtk_gate_regs ethdma_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETHDMA(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = ðdma_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate ethdma_clks[] = { -+ GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), -+ GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), -+ GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), -+ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), -+ GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), -+ GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), -+ GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), -+ GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), -+ GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29), -+}; -+ -+static const struct mtk_clk_desc ethdma_desc = { -+ .clks = ethdma_clks, -+ .num_clks = ARRAY_SIZE(ethdma_clks), -+}; -+ -+static const struct mtk_gate_regs sgmii_cg_regs = { -+ .set_ofs = 0xe4, -+ .clr_ofs = 0xe4, -+ .sta_ofs = 0xe4, -+}; -+ -+#define GATE_SGMII(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii0_clks[] = { -+ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), -+ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), -+}; -+ -+static const struct mtk_clk_desc sgmii0_desc = { -+ .clks = sgmii0_clks, -+ .num_clks = ARRAY_SIZE(sgmii0_clks), -+}; -+ -+static const struct mtk_gate sgmii1_clks[] = { -+ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), -+ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), -+}; -+ -+static const struct mtk_clk_desc sgmii1_desc = { -+ .clks = sgmii1_clks, -+ .num_clks = ARRAY_SIZE(sgmii1_clks), -+}; -+ -+static const struct mtk_gate_regs ethwarp_cg_regs = { -+ .set_ofs = 0x14, -+ .clr_ofs = 0x14, -+ .sta_ofs = 0x14, -+}; -+ -+#define GATE_ETHWARP(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = ðwarp_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate ethwarp_clks[] = { -+ GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13), -+ GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14), -+ GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15), -+}; -+ -+static u16 ethwarp_rst_ofs[] = { 0x8 }; -+ -+static u16 ethwarp_idx_map[] = { -+ [MT7988_ETHWARP_RST_SWITCH] = 9, -+}; -+ -+static const struct mtk_clk_rst_desc ethwarp_rst_desc = { -+ .version = MTK_RST_SIMPLE, -+ .rst_bank_ofs = ethwarp_rst_ofs, -+ .rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs), -+ .rst_idx_map = ethwarp_idx_map, -+ .rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map), -+}; -+ -+static const struct mtk_clk_desc ethwarp_desc = { -+ .clks = ethwarp_clks, -+ .num_clks = ARRAY_SIZE(ethwarp_clks), -+ .rst_desc = ðwarp_rst_desc, -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_eth[] = { -+ { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc }, -+ { .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc }, -+ { .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc }, -+ { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth); -+ -+static struct platform_driver clk_mt7988_eth_drv = { -+ .driver = { -+ .name = "clk-mt7988-eth", -+ .of_match_table = of_match_clk_mt7988_eth, -+ }, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7988_eth_drv); -+ -+MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c -@@ -0,0 +1,275 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include -+ -+static DEFINE_SPINLOCK(mt7988_clk_lock); -+ -+static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" }; -+ -+static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" }; -+ -+static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k", -+ "csw_infra_f26m_sel", "sysaxi_sel", -+ "pwm_sel" }; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { -+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel" -+}; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { -+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel" -+}; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { -+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel" -+}; -+ -+static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { -+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel" -+}; -+ -+static const struct mtk_mux infra_muxes[] = { -+ /* MODULE_CLK_SEL_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", -+ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", -+ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", -+ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents, -+ 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents, -+ 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents, -+ 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018, -+ 0x0010, 0x0014, 14, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents, -+ 0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1), -+ /* MODULE_CLK_SEL_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel", -+ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, -+ -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel", -+ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1, -+ -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel", -+ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1, -+ -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel", -+ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1, -+ -1, -1), -+}; -+ -+static const struct mtk_gate_regs infra0_cg_regs = { -+ .set_ofs = 0x10, -+ .clr_ofs = 0x14, -+ .sta_ofs = 0x18, -+}; -+ -+static const struct mtk_gate_regs infra1_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra2_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra3_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ -+ GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ -+ _flags) -+ -+#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ -+ GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ -+ _flags) -+ -+#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ -+ GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ -+ _flags) -+ -+#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ -+ GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \ -+ _flags) -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) -+ -+#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) -+ -+static const struct mtk_gate infra_clks[] = { -+ /* INFRA0 */ -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0", -+ "csw_infra_f26m_sel", 7), -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1", -+ "csw_infra_f26m_sel", 8), -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2", -+ "csw_infra_f26m_sel", 9), -+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3", -+ "csw_infra_f26m_sel", 10), -+ /* INFRA1 */ -+ GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9), -+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10), -+ GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12), -+ GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13), -+ GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14), -+ GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), -+ GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), -+ GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), -+ GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19, -+ CLK_IS_CRITICAL), -+ /* JTAG */ -+ GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20, -+ CLK_IS_CRITICAL), -+ GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21), -+ GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29), -+ GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30), -+ /* INFRA2 */ -+ GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel", -+ 0), -+ GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), -+ GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3), -+ GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4), -+ GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5), -+ GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), -+ GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), -+ GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11, -+ CLK_IS_CRITICAL), -+ GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12, -+ CLK_IS_CRITICAL), -+ GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13), -+ GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14), -+ GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15, -+ CLK_IS_CRITICAL), -+ GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16), -+ GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17), -+ GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18), -+ GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL), -+ GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20), -+ GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21), -+ GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22), -+ GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23), -+ GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24), -+ GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25), -+ GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26), -+ GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), -+ GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), -+ GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), -+ /* INFRA3 */ -+ GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0), -+ GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1), -+ GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2), -+ GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3), -+ GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), -+ GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5), -+ GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), -+ GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), -+ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8, -+ CLK_IS_CRITICAL), -+ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel", -+ 9, CLK_IS_CRITICAL), -+ GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), -+ GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11), -+ GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), -+ GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13), -+ GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), -+ GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", -+ "infra_pcie_gfmux_tl_o_p0_sel", 20), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", -+ "infra_pcie_gfmux_tl_o_p1_sel", 21), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", -+ "infra_pcie_gfmux_tl_o_p2_sel", 22), -+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", -+ "infra_pcie_gfmux_tl_o_p3_sel", 23), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26), -+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30), -+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), -+}; -+ -+static const struct mtk_clk_desc infra_desc = { -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .mux_clks = infra_muxes, -+ .num_mux_clks = ARRAY_SIZE(infra_muxes), -+ .clk_lock = &mt7988_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_infracfg[] = { -+ { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg); -+ -+static struct platform_driver clk_mt7988_infracfg_drv = { -+ .driver = { -+ .name = "clk-mt7988-infracfg", -+ .of_match_table = of_match_clk_mt7988_infracfg, -+ }, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7988_infracfg_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c -@@ -0,0 +1,325 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Xiufeng Li -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+#include -+ -+static DEFINE_SPINLOCK(mt7988_clk_lock); -+ -+static const struct mtk_fixed_clk top_fixed_clks[] = { -+ FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), -+}; -+ -+static const struct mtk_fixed_factor top_divs[] = { -+ FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), -+ FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), -+ FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), -+ FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), -+ FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), -+ FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), -+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), -+ FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), -+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), -+ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), -+ FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), -+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), -+ FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), -+ FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), -+ FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), -+ FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), -+ FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), -+ FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), -+ FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), -+ FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), -+ FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), -+ FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), -+ FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), -+ FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), -+ FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), -+ FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), -+ FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), -+}; -+ -+static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" }; -+static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" }; -+static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" }; -+static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" }; -+static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; -+static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", "mmpll", -+ "net1pll_d4", "net1pll_d5", "mpll" }; -+static const char *const eip197_parents[] = { "top_xtal", "netsyspll", "net2pll", -+ "mmpll", "net1pll_d4", "net1pll_d5" }; -+static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; -+static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" }; -+static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" }; -+static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", "mmpll_d2", -+ "mpll_d2", "mmpll_d4", "net1pll_d8_d2" }; -+static const char *const spi_parents[] = { "top_xtal", "mpll_d2", "mmpll_d4", -+ "net1pll_d8_d2", "net2pll_d6", "net1pll_d5_d4", -+ "mpll_d4", "net1pll_d8_d4" }; -+static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6", -+ "mpll_d4", "mmpll_d8", "net1pll_d8_d4", "mpll_d8" }; -+static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4", -+ "mpll_d4", "mmpll_d8", "net1pll_d8_d4", -+ "mmpll_d6_d2", "mpll_d8" }; -+static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4", -+ "mpll_d4", "mpll_d8_d2", "top_rtc_32k" }; -+static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4", -+ "net1pll_d8_d4" }; -+static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" }; -+static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8", -+ "mpll_d8_d2", "top_rtc_32k" }; -+static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; -+static const char *const aud_parents[] = { "top_xtal", "apll2" }; -+static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; -+static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" }; -+static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; -+static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" }; -+static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; -+static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; -+static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" }; -+static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; -+static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" }; -+static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" }; -+static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; -+static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" }; -+static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" }; -+static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" }; -+static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" }; -+static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" }; -+static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" }; -+ -+static const struct mtk_mux top_muxes[] = { -+ /* CLK_CFG_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008, -+ 0, 2, 7, 0x1c0, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000, -+ 0x004, 0x008, 8, 2, 15, 0x1C0, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000, -+ 0x004, 0x008, 16, 2, 23, 0x1C0, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000, -+ 0x004, 0x008, 24, 2, 31, 0x1C0, 3), -+ /* CLK_CFG_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014, -+ 0x018, 0, 1, 7, 0x1C0, 4), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010, -+ 0x014, 0x018, 8, 3, 15, 0x1C0, 5), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents, -+ 0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018, -+ 24, 3, 31, 0x1c0, 7), -+ /* CLK_CFG_2 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020, -+ 0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2, -+ 15, 0x1c0, 9), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020, -+ 0x024, 0x028, 16, 2, 23, 0x1C0, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020, -+ 0x024, 0x028, 24, 3, 31, 0x1C0, 11), -+ /* CLK_CFG_3 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7, -+ 0x1c0, 12), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038, -+ 8, 3, 15, 0x1c0, 13), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16, -+ 3, 23, 0x1c0, 14), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038, -+ 24, 3, 31, 0x1c0, 15), -+ /* CLK_CFG_4 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7, -+ 0x1c0, 16), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15, -+ 0x1c0, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", -+ pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040, -+ 0x044, 0x048, 24, 3, 31, 0x1C0, 19), -+ /* CLK_CFG_5 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050, -+ 0x054, 0x058, 0, 3, 7, 0x1C0, 20), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050, -+ 0x054, 0x058, 8, 3, 15, 0x1C0, 21), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050, -+ 0x054, 0x058, 16, 3, 23, 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054, -+ 0x058, 24, 1, 31, 0x1C0, 23), -+ /* CLK_CFG_6 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060, -+ 0x064, 0x068, 0, 1, 7, 0x1C0, 24), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064, -+ 0x068, 8, 1, 15, 0x1C0, 25), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060, -+ 0x064, 0x068, 16, 1, 23, 0x1C0, 26), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060, -+ 0x064, 0x068, 24, 1, 31, 0x1C0, 27), -+ /* CLK_CFG_7 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents, -+ 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15, -+ 0x1c0, 29), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16, -+ 1, 23, 0x1c0, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24, -+ 2, 31, 0x1c4, 0), -+ /* CLK_CFG_8 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088, -+ 0, 1, 7, 0x1c4, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088, -+ 8, 1, 15, 0x1c4, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084, -+ 0x088, 16, 1, 23, 0x1c4, 3), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", -+ usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4), -+ /* CLK_CFG_9 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", -+ usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8, -+ 1, 15, 0x1c4, 6), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, -+ 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24, -+ 1, 31, 0x1c4, 8), -+ /* CLK_CFG_10 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, -+ 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, -+ 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, -+ 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11), -+ /* CLK_CFG_11 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0, -+ 0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4, -+ 0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents, -+ 0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents, -+ 0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0, -+ 0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16), -+ /* CLK_CFG_12 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0, -+ 0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4, -+ 0x0c8, 8, 2, 15, 0x1C4, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4, -+ 0x0c8, 16, 1, 23, 0x1C4, 19), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4, -+ 0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL), -+ /* CLK_CFG_13 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, -+ 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, -+ 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4, -+ 0x0d8, 16, 1, 23, 0x1C4, 23), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4, -+ 0x0d8, 24, 1, 31, 0x1C4, 24), -+ /* CLK_CFG_14 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4, -+ 0x0e8, 0, 1, 7, 0x1C4, 25), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4, -+ 0x0e8, 8, 1, 15, 0x1C4, 26), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents, -+ 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents, -+ 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28), -+ /* CLK_CFG_15 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents, -+ 0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents, -+ 0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1, -+ 23, 0x1c8, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, -+ 31, 0x1C8, 1), -+ /* CLK_CFG_16 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108, -+ 0, 1, 7, 0x1c8, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100, -+ 0x104, 0x108, 8, 1, 15, 0x1C8, 3), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", -+ mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", -+ pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), -+ /* CLK_CFG_17 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118, -+ 0, 2, 7, 0x1c8, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", -+ netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", -+ pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110, -+ 0x114, 0x118, 24, 2, 31, 0x1C8, 9), -+ /* CLK_CFG_18 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124, -+ 0x128, 0, 1, 7, 0x1c8, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128, -+ 8, 2, 15, 0x1c8, 11), -+}; -+ -+static const struct mtk_composite top_aud_divs[] = { -+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8), -+}; -+ -+static const struct mtk_clk_desc topck_desc = { -+ .fixed_clks = top_fixed_clks, -+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .composite_clks = top_aud_divs, -+ .num_composite_clks = ARRAY_SIZE(top_aud_divs), -+ .clk_lock = &mt7988_clk_lock, -+}; -+ -+static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" }; -+ -+static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" }; -+ -+static struct mtk_composite mcu_muxes[] = { -+ /* bus_pll_divider_cfg */ -+ MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1, -+ CLK_IS_CRITICAL), -+ /* mp2_pll_divider_cfg */ -+ MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1, -+ CLK_IS_CRITICAL), -+}; -+ -+static const struct mtk_clk_desc mcusys_desc = { -+ .composite_clks = mcu_muxes, -+ .num_composite_clks = ARRAY_SIZE(mcu_muxes), -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_topckgen[] = { -+ { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc }, -+ { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen); -+ -+static struct platform_driver clk_mt7988_topckgen_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7988-topckgen", -+ .of_match_table = of_match_clk_mt7988_topckgen, -+ }, -+}; -+module_platform_driver(clk_mt7988_topckgen_drv); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c -@@ -0,0 +1,82 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2023 Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include -+ -+/* Register to control USXGMII XFI PLL analog */ -+#define XFI_PLL_ANA_GLB8 0x108 -+#define RG_XFI_PLL_ANA_SWWA 0x02283248 -+ -+static const struct mtk_gate_regs xfipll_cg_regs = { -+ .set_ofs = 0x8, -+ .clr_ofs = 0x8, -+ .sta_ofs = 0x8, -+}; -+ -+#define GATE_XFIPLL(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &xfipll_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_fixed_factor xfipll_divs[] = { -+ FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32), -+}; -+ -+static const struct mtk_gate xfipll_clks[] = { -+ GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31), -+}; -+ -+static const struct mtk_clk_desc xfipll_desc = { -+ .clks = xfipll_clks, -+ .num_clks = ARRAY_SIZE(xfipll_clks), -+ .factor_clks = xfipll_divs, -+ .num_factor_clks = ARRAY_SIZE(xfipll_divs), -+}; -+ -+static int clk_mt7988_xfipll_probe(struct platform_device *pdev) -+{ -+ struct device_node *node = pdev->dev.of_node; -+ void __iomem *base = of_iomap(node, 0); -+ -+ if (!base) -+ return -ENOMEM; -+ -+ /* Apply software workaround for USXGMII PLL TCL issue */ -+ writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8); -+ iounmap(base); -+ -+ return mtk_clk_simple_probe(pdev); -+}; -+ -+static const struct of_device_id of_match_clk_mt7988_xfipll[] = { -+ { .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll); -+ -+static struct platform_driver clk_mt7988_xfipll_drv = { -+ .driver = { -+ .name = "clk-mt7988-xfipll", -+ .of_match_table = of_match_clk_mt7988_xfipll, -+ }, -+ .probe = clk_mt7988_xfipll_probe, -+ .remove = mtk_clk_simple_remove, -+}; -+module_platform_driver(clk_mt7988_xfipll_drv); -+ -+MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch b/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch deleted file mode 100644 index cecf095e92c1de..00000000000000 --- a/target/linux/mediatek/patches-6.1/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Wed, 17 Jan 2024 19:41:11 +0100 -Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988 - -Infracfg can also operate as reset controller, add support for it. - -Signed-off-by: Frank Wunderlich ---- - drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c -@@ -14,6 +14,10 @@ - #include "clk-gate.h" - #include "clk-mux.h" - #include -+#include -+ -+#define MT7988_INFRA_RST0_SET_OFFSET 0x70 -+#define MT7988_INFRA_RST1_SET_OFFSET 0x80 - - static DEFINE_SPINLOCK(mt7988_clk_lock); - -@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[ - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), - }; - -+static u16 infra_rst_ofs[] = { -+ MT7988_INFRA_RST0_SET_OFFSET, -+ MT7988_INFRA_RST1_SET_OFFSET, -+}; -+ -+static u16 infra_idx_map[] = { -+ [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6, -+ [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9, -+}; -+ -+static struct mtk_clk_rst_desc infra_rst_desc = { -+ .version = MTK_RST_SET_CLR, -+ .rst_bank_ofs = infra_rst_ofs, -+ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), -+ .rst_idx_map = infra_idx_map, -+ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map), -+}; -+ - static const struct mtk_clk_desc infra_desc = { - .clks = infra_clks, - .num_clks = ARRAY_SIZE(infra_clks), - .mux_clks = infra_muxes, - .num_mux_clks = ARRAY_SIZE(infra_muxes), - .clk_lock = &mt7988_clk_lock, -+ .rst_desc = &infra_rst_desc, - }; - - static const struct of_device_id of_match_clk_mt7988_infracfg[] = { diff --git a/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch b/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch deleted file mode 100644 index d353074e84a0f7..00000000000000 --- a/target/linux/mediatek/patches-6.1/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Wed, 17 Jan 2024 19:41:10 +0100 -Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs - -Add reset constants for using as index in driver and dts. - -Signed-off-by: Frank Wunderlich ---- - include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/include/dt-bindings/reset/mediatek,mt7988-resets.h -+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h -@@ -10,4 +10,10 @@ - /* ETHWARP resets */ - #define MT7988_ETHWARP_RST_SWITCH 0 - -+/* INFRA resets */ -+#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 -+#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 -+ -+ - #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ -+ diff --git a/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch b/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch deleted file mode 100644 index cb49ce1d253139..00000000000000 --- a/target/linux/mediatek/patches-6.1/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 20 Nov 2023 18:22:31 +0000 -Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support - -Add support for watchdog and reset generator unit of the MediaTek -MT7988 SoC. - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++ - 1 file changed, 42 insertions(+) - ---- a/drivers/watchdog/mtk_wdt.c -+++ b/drivers/watchdog/mtk_wdt.c -@@ -56,9 +56,13 @@ - #define WDT_SWSYSRST 0x18U - #define WDT_SWSYS_RST_KEY 0x88000000 - -+#define WDT_SWSYSRST_EN 0xfc -+ - #define DRV_NAME "mtk-wdt" - #define DRV_VERSION "1.0" - -+#define MT7988_TOPRGU_SW_RST_NUM 24 -+ - static bool nowayout = WATCHDOG_NOWAYOUT; - static unsigned int timeout; - -@@ -68,10 +72,12 @@ struct mtk_wdt_dev { - spinlock_t lock; /* protects WDT_SWSYSRST reg */ - struct reset_controller_dev rcdev; - bool disable_wdt_extrst; -+ bool has_swsysrst_en; - }; - - struct mtk_wdt_data { - int toprgu_sw_rst_num; -+ bool has_swsysrst_en; - }; - - static const struct mtk_wdt_data mt2712_data = { -@@ -82,6 +88,11 @@ static const struct mtk_wdt_data mt7986_ - .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM, - }; - -+static const struct mtk_wdt_data mt7988_data = { -+ .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM, -+ .has_swsysrst_en = true, -+}; -+ - static const struct mtk_wdt_data mt8183_data = { - .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, - }; -@@ -98,6 +109,28 @@ static const struct mtk_wdt_data mt8195_ - .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM, - }; - -+/** -+ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit -+ * @data: Pointer to instance of driver data. -+ * @id: Bit number identifying the reset to be enabled or disabled. -+ * @enable: If true, enable software control for that bit, disable otherwise. -+ * -+ * Context: The caller must hold lock of struct mtk_wdt_dev. -+ */ -+static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data, -+ unsigned long id, bool enable) -+{ -+ u32 tmp; -+ -+ tmp = readl(data->wdt_base + WDT_SWSYSRST_EN); -+ if (enable) -+ tmp |= BIT(id); -+ else -+ tmp &= ~BIT(id); -+ -+ writel(tmp, data->wdt_base + WDT_SWSYSRST_EN); -+} -+ - static int toprgu_reset_update(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) - { -@@ -108,6 +141,9 @@ static int toprgu_reset_update(struct re - - spin_lock_irqsave(&data->lock, flags); - -+ if (assert && data->has_swsysrst_en) -+ toprgu_reset_sw_en_unlocked(data, id, true); -+ - tmp = readl(data->wdt_base + WDT_SWSYSRST); - if (assert) - tmp |= BIT(id); -@@ -116,6 +152,9 @@ static int toprgu_reset_update(struct re - tmp |= WDT_SWSYS_RST_KEY; - writel(tmp, data->wdt_base + WDT_SWSYSRST); - -+ if (!assert && data->has_swsysrst_en) -+ toprgu_reset_sw_en_unlocked(data, id, false); -+ - spin_unlock_irqrestore(&data->lock, flags); - - return 0; -@@ -393,6 +432,8 @@ static int mtk_wdt_probe(struct platform - wdt_data->toprgu_sw_rst_num); - if (err) - return err; -+ -+ mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en; - } - - mtk_wdt->disable_wdt_extrst = -@@ -427,6 +468,7 @@ static const struct of_device_id mtk_wdt - { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, - { .compatible = "mediatek,mt6589-wdt" }, - { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, -+ { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data }, - { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, - { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, - { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, diff --git a/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch b/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch deleted file mode 100644 index c4760b9eff9278..00000000000000 --- a/target/linux/mediatek/patches-6.1/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch +++ /dev/null @@ -1,31 +0,0 @@ -From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 11 Mar 2024 17:14:19 +0000 -Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port - -Due to what seems to be an undocumented oddity in MediaTek's MT7988 -SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires -CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled. - -This currently leads to PCIe port 2 not working in Linux. - -Reflect the apparent relationship in the clk driver to make sure PCIe -port 2 of the MT7988 SoC works. - -Suggested-by: Sam Shih -Signed-off-by: Daniel Golle ---- - drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c -@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[ - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1", - "csw_infra_f26m_sel", 8), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2", -- "csw_infra_f26m_sel", 9), -+ "infra_pcie_peri_ck_26m_ck_p3", 9), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3", - "csw_infra_f26m_sel", 10), - /* INFRA1 */ diff --git a/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch b/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch deleted file mode 100644 index 1e53777d655f70..00000000000000 --- a/target/linux/mediatek/patches-6.1/253-pinctrl-mediatek-mt7981-add-additional-uart-group.patch +++ /dev/null @@ -1,63 +0,0 @@ -From patchwork Wed Jan 17 12:42:33 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Jean Thomas -X-Patchwork-Id: 13521682 -Return-Path: - -From: Jean Thomas -To: sean.wang@kernel.org, - linus.walleij@linaro.org, - matthias.bgg@gmail.com, - angelogioacchino.delregno@collabora.com, - linux-mediatek@lists.infradead.org, - linux-gpio@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org -Cc: Jean Thomas -Subject: [PATCH 1/2] pinctrl: mediatek: mt7981: add additional uart group -Date: Wed, 17 Jan 2024 13:42:33 +0100 -Message-Id: <20240117124234.3137050-1-jean.thomas@wifirst.fr> -MIME-Version: 1.0 -List-Id: - -Add uart1_3 (pins 26, 27) group to the pinctrl driver for the -MediaTek MT7981 SoC. - -Signed-off-by: Jean Thomas -Reviewed-by: Daniel Golle ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -737,6 +737,9 @@ static int mt7981_uart1_1_funcs[] = { 2, - static int mt7981_uart1_2_pins[] = { 9, 10, }; - static int mt7981_uart1_2_funcs[] = { 2, 2, }; - -+static int mt7981_uart1_3_pins[] = { 26, 27, }; -+static int mt7981_uart1_3_funcs[] = { 2, 2, }; -+ - /* UART2 */ - static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; - static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -@@ -871,6 +874,8 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), - /* @GPIO(9,10): UART1(2) */ - PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), -+ /* @GPIO(26,27): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), - /* @GPIO(22,25): UART1(3) */ - PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), - /* @GPIO(22,24) PTA_EXT(4) */ -@@ -933,7 +938,7 @@ static const struct group_desc mt7981_gr - static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", - "wa_aice3", "wm_aice1_2", }; - static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", -- "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0", -+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0", - "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; - static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; - static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; diff --git a/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch b/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch deleted file mode 100644 index df4d82c9d949c5..00000000000000 --- a/target/linux/mediatek/patches-6.1/254-pinctrl-mediatek-mt7981-add-additional-emmc-group.patch +++ /dev/null @@ -1,82 +0,0 @@ -From patchwork Wed Jan 17 14:55:47 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Jean Thomas -X-Patchwork-Id: 13521855 -Return-Path: - -From: Jean Thomas -To: sean.wang@kernel.org, - linus.walleij@linaro.org, - matthias.bgg@gmail.com, - angelogioacchino.delregno@collabora.com, - linux-mediatek@lists.infradead.org, - linux-gpio@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org -Cc: Jean Thomas , - Daniel Golle -Subject: [PATCH v2 2/2] pinctrl: mediatek: mt7981: add additional emmc groups -Date: Wed, 17 Jan 2024 15:55:47 +0100 -Message-Id: <20240117145547.3354242-1-jean.thomas@wifirst.fr> -List-Id: - -Add new emmc groups in the pinctrl driver for the -MediaTek MT7981 SoC: -* emmc reset, with pin 15. -* emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25. -* emmc 8-bit bus-width, with pins 16 to 25. - -The existing emmc_45 group is kept for legacy reasons, even -if this is the union of emmc_reset and emmc_8 groups. - -Signed-off-by: Jean Thomas -Reviewed-by: Daniel Golle ---- - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - --- -2.39.2 - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -700,6 +700,15 @@ static int mt7981_drv_vbus_pins[] = { 14 - static int mt7981_drv_vbus_funcs[] = { 1, }; - - /* EMMC */ -+static int mt7981_emmc_reset_pins[] = { 15, }; -+static int mt7981_emmc_reset_funcs[] = { 2, }; -+ -+static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; -+static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; -+ -+static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -+static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ - static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; - static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; - -@@ -854,6 +863,12 @@ static const struct group_desc mt7981_gr - PINCTRL_PIN_GROUP("udi", mt7981_udi), - /* @GPIO(14) DRV_VBUS(1) */ - PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), -+ /* @GPIO(15): EMMC_RSTB(2) */ -+ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), -+ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ -+ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), -+ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ -+ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), - /* @GPIO(15,25): EMMC(2) */ - PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), - /* @GPIO(16,21): SNFI(3) */ -@@ -957,7 +972,7 @@ static const char *mt7981_i2c_groups[] = - static const char *mt7981_pcm_groups[] = { "pcm", }; - static const char *mt7981_udi_groups[] = { "udi", }; - static const char *mt7981_usb_groups[] = { "drv_vbus", }; --static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; -+static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", }; - static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", - "wf0_mode1", "wf0_mode3", "mt7531_int", }; - static const char *mt7981_ant_groups[] = { "ant_sel", }; diff --git a/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch b/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch deleted file mode 100644 index 5e3afd856f7b7b..00000000000000 --- a/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 25 Oct 2022 15:29:53 +0200 -Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC - -Adding mt7986 own characteristics and of_device_id to have support -of MT7986 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221025132953.81286-7-linux@fw-web.de -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m - .support_64g = false, - }; - -+static const struct mtk_mmc_compatible mt7986_compat = { -+ .clk_div_bits = 12, -+ .recheck_sdio_irq = true, -+ .hs400_tune = false, -+ .pad_tune_reg = MSDC_PAD_TUNE0, -+ .async_fifo = true, -+ .data_tune = true, -+ .busy_check = true, -+ .stop_clk_fix = true, -+ .enhance_rx = true, -+ .support_64g = true, -+}; -+ - static const struct mtk_mmc_compatible mt8135_compat = { - .clk_div_bits = 8, - .recheck_sdio_irq = true, -@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of - { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, - { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, - { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, -+ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, - { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, - { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, - { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, diff --git a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch b/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch deleted file mode 100644 index db2802bd0f4511..00000000000000 --- a/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001 -From: Mengqi Zhang -Date: Sun, 6 Nov 2022 11:39:24 +0800 -Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control - -Add crypto clock control and ungate it before CQHCI init. - -Signed-off-by: Mengqi Zhang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106033924.9854-2-mengqi.zhang@mediatek.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -452,6 +452,7 @@ struct msdc_host { - struct clk *bus_clk; /* bus clock which used to access register */ - struct clk *src_clk_cg; /* msdc source clock control gate */ - struct clk *sys_clk_cg; /* msdc subsys clock control gate */ -+ struct clk *crypto_clk; /* msdc crypto clock control gate */ - struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; - u32 mclk; /* mmc subsystem clock frequency */ - u32 src_clk_freq; /* source clock frequency */ -@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct - static void msdc_gate_clock(struct msdc_host *host) - { - clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); -+ clk_disable_unprepare(host->crypto_clk); - clk_disable_unprepare(host->src_clk_cg); - clk_disable_unprepare(host->src_clk); - clk_disable_unprepare(host->bus_clk); -@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc - clk_prepare_enable(host->bus_clk); - clk_prepare_enable(host->src_clk); - clk_prepare_enable(host->src_clk_cg); -+ clk_prepare_enable(host->crypto_clk); - ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); - if (ret) { - dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); -@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor - goto host_free; - } - -+ /* only eMMC has crypto property */ -+ if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { -+ host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); -+ if (IS_ERR(host->crypto_clk)) -+ host->crypto_clk = NULL; -+ else -+ mmc->caps2 |= MMC_CAP2_CRYPTO; -+ } -+ - host->irq = platform_get_irq(pdev, 0); - if (host->irq < 0) { - ret = host->irq; diff --git a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch b/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch deleted file mode 100644 index 921d249f8cc5d8..00000000000000 --- a/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001 -From: Yu Zhe -Date: Thu, 10 Nov 2022 15:28:19 +0800 -Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment - -spelling mistake fix : "alreay" -> "already" - "checksume" -> "checksum" - -Signed-off-by: Yu Zhe -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221110072819.11530-1-yuzhe@nfschina.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct - else - bd[j].bd_info &= ~BDMA_DESC_EOL; - -- /* checksume need to clear first */ -+ /* checksum need to clear first */ - bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; - bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; - } -@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho - !host->hs400_tuning)) - /* - * should not clear fifo/interrupt as the tune data -- * may have alreay come when cmd19/cmd21 gets response -+ * may have already come when cmd19/cmd21 gets response - * CRC error. - */ - msdc_reset_hw(host); diff --git a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch b/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch deleted file mode 100644 index 8e2151e16bd468..00000000000000 --- a/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001 -From: ChanWoo Lee -Date: Thu, 24 Nov 2022 17:00:31 +0900 -Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning() - -Replace code with the already defined function. No functional changes. - -Signed-off-by: ChanWoo Lee -Reviewed-by: Adrian Hunter -Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 8 ++------ - 1 file changed, 2 insertions(+), 6 deletions(-) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho - - if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { - if (events & MSDC_INT_CMDTMO || -- (cmd->opcode != MMC_SEND_TUNING_BLOCK && -- cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && -- !host->hs400_tuning)) -+ (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) - /* - * should not clear fifo/interrupt as the tune data - * may have already come when cmd19/cmd21 gets response -@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho - { - if ((cmd->error && - !(cmd->error == -EILSEQ && -- (cmd->opcode == MMC_SEND_TUNING_BLOCK || -- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || -- host->hs400_tuning))) || -+ (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || - (mrq->sbc && mrq->sbc->error)) - msdc_request_done(host, mrq); - else if (cmd == mrq->sbc) diff --git a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch deleted file mode 100644 index 55a308e46cfd9c..00000000000000 --- a/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) - { -@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_attach(mtd); - ret = mtd_device_register(mtd, NULL, 0); - if (ret) - goto err_spinand_cleanup; -@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem - return 0; - - err_spinand_cleanup: -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return ret; -@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return 0; diff --git a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch deleted file mode 100644 index a6f98fdf83f898..00000000000000 --- a/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -549,6 +549,7 @@ - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - nand-ecc-engine = <&snfi>; -+ mediatek,bmt-v2; - - partitions { - compatible = "fixed-partitions"; diff --git a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch deleted file mode 100644 index ec66363dc9d32a..00000000000000 --- a/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 -From: Davide Fioravanti -Date: Fri, 8 Jan 2021 15:35:24 +0100 -Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA - -Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf - -Signed-off-by: Davide Fioravanti ---- - drivers/mtd/nand/spi/Makefile | 2 +- - drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ - include/linux/mtd/spinand.h | 1 + - 4 files changed, 79 insertions(+), 1 deletion(-) - create mode 100644 drivers/mtd/nand/spi/fidelix.c - ---- a/drivers/mtd/nand/spi/Makefile -+++ b/drivers/mtd/nand/spi/Makefile -@@ -1,3 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o ato.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o -+spinand-objs := core.o ato.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o - obj-$(CONFIG_MTD_SPI_NAND) += spinand.o ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -940,6 +940,7 @@ static const struct nand_ops spinand_ops - static const struct spinand_manufacturer *spinand_manufacturers[] = { - &ato_spinand_manufacturer, - &esmt_c8_spinand_manufacturer, -+ &fidelix_spinand_manufacturer, - &etron_spinand_manufacturer, - &gigadevice_spinand_manufacturer, - ¯onix_spinand_manufacturer, ---- /dev/null -+++ b/drivers/mtd/nand/spi/fidelix.c -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2020 Davide Fioravanti -+ */ -+ -+#include -+#include -+#include -+ -+#define SPINAND_MFR_FIDELIX 0xE5 -+#define FIDELIX_ECCSR_MASK 0x0F -+ -+static SPINAND_OP_VARIANTS(read_cache_variants, -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(write_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(update_cache_variants, -+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), -+ SPINAND_PROG_LOAD(false, 0, NULL, 0)); -+ -+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 8; -+ region->length = 8; -+ -+ return 0; -+} -+ -+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 2; -+ region->length = 6; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { -+ .ecc = fm35x1ga_ooblayout_ecc, -+ .free = fm35x1ga_ooblayout_free, -+}; -+ -+static const struct spinand_info fidelix_spinand_table[] = { -+ SPINAND_INFO("FM35X1GA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), -+}; -+ -+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { -+}; -+ -+const struct spinand_manufacturer fidelix_spinand_manufacturer = { -+ .id = SPINAND_MFR_FIDELIX, -+ .name = "Fidelix", -+ .chips = fidelix_spinand_table, -+ .nchips = ARRAY_SIZE(fidelix_spinand_table), -+ .ops = &fidelix_spinand_manuf_ops, -+}; ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -263,6 +263,7 @@ struct spinand_manufacturer { - extern const struct spinand_manufacturer ato_spinand_manufacturer; - extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; - extern const struct spinand_manufacturer etron_spinand_manufacturer; -+extern const struct spinand_manufacturer fidelix_spinand_manufacturer; - extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; - extern const struct spinand_manufacturer macronix_spinand_manufacturer; - extern const struct spinand_manufacturer micron_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch deleted file mode 100644 index 96bc7cebd06775..00000000000000 --- a/target/linux/mediatek/patches-6.1/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch +++ /dev/null @@ -1,61 +0,0 @@ -From patchwork Fri Apr 19 16:59:07 2024 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 13636668 -Return-Path: - -Date: Fri, 19 Apr 2024 17:59:07 +0100 -From: Daniel Golle -To: "Rafael J. Wysocki" , - Viresh Kumar , - Matthias Brugger , - AngeloGioacchino Del Regno , - linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-mediatek@lists.infradead.org -Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A -Message-ID: - -Content-Disposition: inline -List-Id: - -From: Sam Shih - -This add cpufreq support for mediatek MT7988A SoC. - -The platform data of MT7988A is different from previous MediaTek SoCs, -so we add a new compatible and platform data for it. - -Signed-off-by: Sam Shih ---- - drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -709,6 +709,15 @@ static const struct mtk_cpufreq_platform - .ccifreq_supported = false, - }; - -+static const struct mtk_cpufreq_platform_data mt7988_platform_data = { -+ .min_volt_shift = 100000, -+ .max_volt_shift = 200000, -+ .proc_max_volt = 900000, -+ .sram_min_volt = 0, -+ .sram_max_volt = 1150000, -+ .ccifreq_supported = true, -+}; -+ - static const struct mtk_cpufreq_platform_data mt8183_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -@@ -742,6 +751,7 @@ static const struct of_device_id mtk_cpu - { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, - { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, -+ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data }, - { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, - { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch b/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch deleted file mode 100644 index 1fcb1e64c7dd80..00000000000000 --- a/target/linux/mediatek/patches-6.1/351-pinctrl-add-mt7988-pd-pulltype-support.patch +++ /dev/null @@ -1,99 +0,0 @@ ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c -@@ -601,6 +601,30 @@ out: - return err; - } - -+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 pullup, u32 arg) -+{ -+ int err, pd; -+ -+ if (arg == MTK_DISABLE) -+ pd = 0; -+ else if ((arg == MTK_ENABLE) && pullup) -+ pd = 0; -+ else if ((arg == MTK_ENABLE) && !pullup) -+ pd = 1; -+ else { -+ err = -EINVAL; -+ goto out; -+ } -+ -+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd); -+ -+out: -+ return err; -+ -+} -+ - static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 pullup, u32 arg) -@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt - return err; - } - -+ if (try_all_type & MTK_PULL_PD_TYPE) { -+ err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg); -+ if (!err) -+ return err; -+ } -+ - if (try_all_type & MTK_PULL_PU_PD_TYPE) { - err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg); - if (!err) -@@ -875,6 +905,29 @@ out: - return err; - } - -+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw, -+ const struct mtk_pin_desc *desc, -+ u32 *pullup, u32 *enable) -+{ -+ int err, pd; -+ -+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd); -+ if (err) -+ goto out; -+ -+ if (pd == 0) { -+ *pullup = 0; -+ *enable = MTK_DISABLE; -+ } else if (pd == 1) { -+ *pullup = 0; -+ *enable = MTK_ENABLE; -+ } else -+ err = -EINVAL; -+ -+out: -+ return err; -+} -+ - static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw, - const struct mtk_pin_desc *desc, - u32 *pullup, u32 *enable) -@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt - if (!err) - return err; - } -+ -+ if (try_all_type & MTK_PULL_PD_TYPE) { -+ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable); -+ if (!err) -+ return err; -+ } - - if (try_all_type & MTK_PULL_PU_PD_TYPE) { - err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable); ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h -@@ -24,6 +24,7 @@ - * turned on/off itself. But it can't be selected pull up/down - */ - #define MTK_PULL_RSEL_TYPE BIT(3) -+#define MTK_PULL_PD_TYPE BIT(4) - /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by - * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. - */ diff --git a/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch deleted file mode 100644 index 25ca9485e41bd9..00000000000000 --- a/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.c -+++ b/drivers/crypto/inside-secure/safexcel.c -@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex - val |= EIP197_MST_CTRL_TX_MAX_CMD(5); - writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); - } -+ /* -+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 -+ */ -+ else { -+ val = 0; -+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); -+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); -+ } - - /* Configure wr/rd cache values */ - writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -315,6 +315,7 @@ - #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) - #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) -+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) - #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) - #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch deleted file mode 100644 index 186c66f6878a1c..00000000000000 --- a/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -737,6 +737,9 @@ enum safexcel_eip_version { - /* Priority we use for advertising our algorithms */ - #define SAFEXCEL_CRA_PRIORITY 300 - -+/* System cache line size */ -+#define SYSTEM_CACHELINE_SIZE 64 -+ - /* SM3 digest result for zero length message */ - #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ - "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ ---- a/drivers/crypto/inside-secure/safexcel_hash.c -+++ b/drivers/crypto/inside-secure/safexcel_hash.c -@@ -55,9 +55,9 @@ struct safexcel_ahash_req { - u8 block_sz; /* block size, only set once */ - u8 digest_sz; /* output digest size, only set once */ - __le32 state[SHA3_512_BLOCK_SIZE / -- sizeof(__le32)] __aligned(sizeof(__le32)); -+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); - -- u64 len; -+ u64 len __aligned(SYSTEM_CACHELINE_SIZE); - u64 processed; - - u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch b/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch deleted file mode 100644 index 615a1a1d714f82..00000000000000 --- a/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch +++ /dev/null @@ -1,43 +0,0 @@ -From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001 -From: "Mingming.Su" -Date: Sat, 8 Oct 2022 18:45:53 +0200 -Subject: [PATCH] hwrng: mtk - add mt7986 support - -1. Add trng compatible name for MT7986 -2. Fix mtk_rng_wait_ready() function - -Signed-off-by: Mingming.Su -Signed-off-by: Frank Wunderlich -Signed-off-by: Herbert Xu ---- - drivers/char/hw_random/mtk-rng.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/char/hw_random/mtk-rng.c -+++ b/drivers/char/hw_random/mtk-rng.c -@@ -22,7 +22,7 @@ - #define RNG_AUTOSUSPEND_TIMEOUT 100 - - #define USEC_POLL 2 --#define TIMEOUT_POLL 20 -+#define TIMEOUT_POLL 60 - - #define RNG_CTRL 0x00 - #define RNG_EN BIT(0) -@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw - readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready, - ready & RNG_READY, USEC_POLL, - TIMEOUT_POLL); -- return !!ready; -+ return !!(ready & RNG_READY); - } - - static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p - #endif /* CONFIG_PM */ - - static const struct of_device_id mtk_rng_match[] = { -+ { .compatible = "mediatek,mt7986-rng" }, - { .compatible = "mediatek,mt7623-rng" }, - {}, - }; diff --git a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch deleted file mode 100644 index fa232b5d4e557b..00000000000000 --- a/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/drivers/tty/serial/8250/8250.h -+++ b/drivers/tty/serial/8250/8250.h -@@ -86,6 +86,7 @@ struct serial8250_config { - * STOP PARITY EPAR SPAR WLEN5 WLEN6 - */ - #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */ -+#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */ - - #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ - #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ ---- a/drivers/tty/serial/8250/8250_port.c -+++ b/drivers/tty/serial/8250/8250_port.c -@@ -287,7 +287,7 @@ static const struct serial8250_config ua - .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, -- .flags = UART_CAP_FIFO, -+ .flags = UART_CAP_FIFO | UART_CAP_NMOD, - }, - [PORT_NPCM] = { - .name = "Nuvoton 16550", -@@ -2767,6 +2767,11 @@ serial8250_do_set_termios(struct uart_po - unsigned long flags; - unsigned int baud, quot, frac = 0; - -+ if (up->capabilities & UART_CAP_NMOD) { -+ termios->c_cflag = 0; -+ return; -+ } -+ - if (up->capabilities & UART_CAP_MINI) { - termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); - if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch deleted file mode 100644 index 95fc7f4668226c..00000000000000 --- a/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch +++ /dev/null @@ -1,130 +0,0 @@ -From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:29:51 +0800 -Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private - data - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 29 +++++++++--------------- - include/linux/platform_data/spi-mt65xx.h | 17 -------------- - 2 files changed, 11 insertions(+), 35 deletions(-) - delete mode 100644 include/linux/platform_data/spi-mt65xx.h - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -14,7 +14,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -171,6 +170,8 @@ struct mtk_spi { - struct device *dev; - dma_addr_t tx_dma; - dma_addr_t rx_dma; -+ u32 sample_sel; -+ u32 get_tick_dly; - }; - - static const struct mtk_spi_compatible mtk_common_compat; -@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m - .no_need_unprepare = true, - }; - --/* -- * A piece of default chip info unless the platform -- * supplies it. -- */ --static const struct mtk_chip_config mtk_default_chip_info = { -- .sample_sel = 0, -- .tick_delay = 0, --}; -- - static const struct of_device_id mtk_spi_of_match[] = { - { .compatible = "mediatek,spi-ipm", - .data = (void *)&mtk_ipm_compat, -@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma - { - u16 cpha, cpol; - u32 reg_val; -- struct mtk_chip_config *chip_config = spi->controller_data; - struct mtk_spi *mdata = spi_master_get_devdata(master); - - cpha = spi->mode & SPI_CPHA ? 1 : 0; -@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma - else - reg_val &= ~SPI_CMD_CS_POL; - -- if (chip_config->sample_sel) -+ if (mdata->sample_sel) - reg_val |= SPI_CMD_SAMPLE_SEL; - else - reg_val &= ~SPI_CMD_SAMPLE_SEL; -@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma - if (mdata->dev_comp->ipm_design) { - reg_val = readl(mdata->base + SPI_CMD_REG); - reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CMD_IPM_GET_TICKDLY_OFFSET); - writel(reg_val, mdata->base + SPI_CMD_REG); - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CFG1_GET_TICK_DLY_OFFSET); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; -- reg_val |= ((chip_config->tick_delay & 0x3) -+ reg_val |= ((mdata->get_tick_dly & 0x3) - << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } -@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi - { - struct mtk_spi *mdata = spi_master_get_devdata(spi->master); - -- if (!spi->controller_data) -- spi->controller_data = (void *)&mtk_default_chip_info; -- - if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) - /* CS de-asserted, gpiolib will handle inversion */ - gpiod_direction_output(spi->cs_gpiod, 0); -@@ -1140,6 +1128,10 @@ static int mtk_spi_probe(struct platform - mdata = spi_master_get_devdata(master); - mdata->dev_comp = device_get_match_data(dev); - -+ /* Set device configs to default first. Calibrate it later. */ -+ mdata->sample_sel = 0; -+ mdata->get_tick_dly = 2; -+ - if (mdata->dev_comp->enhance_timing) - master->mode_bits |= SPI_CS_HIGH; - ---- a/include/linux/platform_data/spi-mt65xx.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ --/* -- * MTK SPI bus driver definitions -- * -- * Copyright (c) 2015 MediaTek Inc. -- * Author: Leilk Liu -- */ -- --#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H --#define ____LINUX_PLATFORM_DATA_SPI_MTK_H -- --/* Board specific platform_data */ --struct mtk_chip_config { -- u32 sample_sel; -- u32 tick_delay; --}; --#endif diff --git a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch deleted file mode 100644 index b2c9df4386a446..00000000000000 --- a/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ /dev/null @@ -1,236 +0,0 @@ -From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:35:52 +0800 -Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++ - include/linux/spi/spi.h | 42 ++++++++++++ - 2 files changed, 179 insertions(+) - ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -1385,6 +1385,70 @@ static int spi_transfer_wait(struct spi_ - return 0; - } - -+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv) -+{ -+ int datalen = ctlr->cal_rule->datalen; -+ int addrlen = ctlr->cal_rule->addrlen; -+ u8 *buf; -+ int ret; -+ int i; -+ struct list_head *cal_head, *listptr; -+ struct spi_cal_target *target; -+ -+ /* Calculate calibration result */ -+ int hit_val, total_hit, origin; -+ bool hit; -+ -+ /* Make sure we can start calibration */ -+ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata) -+ return 0; -+ -+ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL); -+ if(!buf) -+ return -ENOMEM; -+ -+ ret = ctlr->append_caldata(ctlr); -+ if (ret) -+ goto cal_end; -+ -+ cal_head = ctlr->cal_target; -+ list_for_each(listptr, cal_head) { -+ target = list_entry(listptr, struct spi_cal_target, list); -+ -+ hit = false; -+ hit_val = 0; -+ total_hit = 0; -+ origin = *target->cal_item; -+ -+ for(i=target->cal_min; i<=target->cal_max; i+=target->step) { -+ *target->cal_item = i; -+ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen); -+ if(ret) -+ break; -+ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i); -+ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) { -+ hit = true; -+ hit_val += i; -+ total_hit++; -+ dev_dbg(&spi->dev, "golden data matches data read!\n"); -+ } -+ } -+ if(hit) { -+ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit); -+ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item); -+ } else { -+ *target->cal_item = origin; -+ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin); -+ } -+ } -+ -+cal_end: -+ kfree(buf); -+ return ret? ret: 0; -+} -+EXPORT_SYMBOL_GPL(spi_do_calibration); -+ - static void _spi_transfer_delay_ns(u32 ns) - { - if (!ns) -@@ -2223,6 +2287,75 @@ void spi_flush_queue(struct spi_controll - /*-------------------------------------------------------------------------*/ - - #if defined(CONFIG_OF) -+static inline void alloc_cal_data(struct list_head **cal_target, -+ struct spi_cal_rule **cal_rule, bool enable) -+{ -+ if(enable) { -+ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL); -+ INIT_LIST_HEAD(*cal_target); -+ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL); -+ } else { -+ kfree(*cal_target); -+ kfree(*cal_rule); -+ } -+} -+ -+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi, -+ struct device_node *nc) -+{ -+ u32 value; -+ int rc; -+ const char *cal_mode; -+ -+ rc = of_property_read_bool(nc, "spi-cal-enable"); -+ if (rc) -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true); -+ else -+ return 0; -+ -+ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode); -+ if(!rc) { -+ if(strcmp("read-data", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_DATA; -+ } else if(strcmp("read-pp", cal_mode) == 0) { -+ ctlr->cal_rule->mode = SPI_CAL_READ_PP; -+ return 0; -+ } else if(strcmp("read-sfdp", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP; -+ return 0; -+ } -+ } else -+ goto err; -+ -+ ctlr->cal_rule->datalen = 0; -+ rc = of_property_read_u32(nc, "spi-cal-datalen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->datalen = value; -+ -+ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL); -+ rc = of_property_read_u8_array(nc, "spi-cal-data", -+ ctlr->cal_rule->match_data, value); -+ if(rc) -+ kfree(ctlr->cal_rule->match_data); -+ } -+ -+ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->addrlen = value; -+ -+ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL); -+ rc = of_property_read_u32_array(nc, "spi-cal-addr", -+ ctlr->cal_rule->addr, value); -+ if(rc) -+ kfree(ctlr->cal_rule->addr); -+ } -+ return 0; -+ -+err: -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false); -+ return 0; -+} -+ - static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, - struct device_node *nc) - { -@@ -2341,6 +2474,10 @@ of_register_spi_device(struct spi_contro - if (rc) - goto err_out; - -+ rc = of_spi_parse_cal_dt(ctlr, spi, nc); -+ if (rc) -+ goto err_out; -+ - /* Store a pointer to the node in the device structure */ - of_node_get(nc); - spi->dev.of_node = nc; ---- a/include/linux/spi/spi.h -+++ b/include/linux/spi/spi.h -@@ -318,6 +318,40 @@ struct spi_driver { - struct device_driver driver; - }; - -+enum { -+ SPI_CAL_READ_DATA = 0, -+ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */ -+ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */ -+}; -+ -+struct nand_addr { -+ unsigned int lun; -+ unsigned int plane; -+ unsigned int eraseblock; -+ unsigned int page; -+ unsigned int dataoffs; -+}; -+ -+/** -+ * Read calibration rule from device dts node. -+ * Once calibration result matches the rule, we regard is as success. -+ */ -+struct spi_cal_rule { -+ int datalen; -+ u8 *match_data; -+ int addrlen; -+ u32 *addr; -+ int mode; -+}; -+ -+struct spi_cal_target { -+ u32 *cal_item; -+ int cal_min; /* min of cal_item */ -+ int cal_max; /* max of cal_item */ -+ int step; /* Increase/decrease cal_item */ -+ struct list_head list; -+}; -+ - static inline struct spi_driver *to_spi_driver(struct device_driver *drv) - { - return drv ? container_of(drv, struct spi_driver, driver) : NULL; -@@ -703,6 +737,11 @@ struct spi_controller { - void *dummy_rx; - void *dummy_tx; - -+ /* For calibration */ -+ int (*append_caldata)(struct spi_controller *ctlr); -+ struct list_head *cal_target; -+ struct spi_cal_rule *cal_rule; -+ - int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); - - /* -@@ -1510,6 +1549,9 @@ spi_register_board_info(struct spi_board - { return 0; } - #endif - -+extern int spi_do_calibration(struct spi_controller *ctlr, -+ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv); -+ - /* If you're hotplugging an adapter with devices (parport, usb, etc) - * use spi_new_device() to describe each device. You can also call - * spi_unregister_device() to start making that device vanish, but diff --git a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch deleted file mode 100644 index e87d63db69850a..00000000000000 --- a/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:37:55 +0800 -Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mem.c | 8 ++++++++ - include/linux/spi/spi-mem.h | 4 ++++ - 2 files changed, 12 insertions(+) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem, - } - EXPORT_SYMBOL_GPL(spi_mem_exec_op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), -+ void *priv) -+{ -+ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv); -+} -+EXPORT_SYMBOL_GPL(spi_mem_do_calibration); -+ - /** - * spi_mem_get_name() - Return the SPI mem device name to be used by the - * upper layer if necessary ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem - int spi_mem_exec_op(struct spi_mem *mem, - const struct spi_mem_op *op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *, u32 *, int, u8 *, int), -+ void *priv); -+ - const char *spi_mem_get_name(struct spi_mem *mem); - - struct spi_mem_dirmap_desc * diff --git a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch deleted file mode 100644 index dbdb1947aa2e63..00000000000000 --- a/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch +++ /dev/null @@ -1,43 +0,0 @@ -From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:03 +0800 -Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration - paramter - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -834,6 +834,21 @@ static irqreturn_t mtk_spi_interrupt(int - return IRQ_HANDLED; - } - -+static int mtk_spi_append_caldata(struct spi_controller *ctlr) -+{ -+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL); -+ struct mtk_spi *mdata = spi_master_get_devdata(ctlr); -+ -+ cal_target->cal_item = &mdata->get_tick_dly; -+ cal_target->cal_min = 0; -+ cal_target->cal_max = 7; -+ cal_target->step = 1; -+ -+ list_add(&cal_target->list, ctlr->cal_target); -+ -+ return 0; -+} -+ - static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, - struct spi_mem_op *op) - { -@@ -1124,6 +1139,7 @@ static int mtk_spi_probe(struct platform - master->setup = mtk_spi_setup; - master->set_cs_timing = mtk_spi_set_hw_cs_timing; - master->use_gpio_descriptors = true; -+ master->append_caldata = mtk_spi_append_caldata; - - mdata = spi_master_get_devdata(master); - mdata->dev_comp = device_get_match_data(dev); diff --git a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch deleted file mode 100644 index 3991d8925a4a15..00000000000000 --- a/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:56 +0800 -Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for - spinand - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -978,6 +978,56 @@ static int spinand_manufacturer_match(st - return -ENOTSUPP; - } - -+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) { -+ struct spinand_device *spinand = (struct spinand_device *)priv; -+ struct device *dev = &spinand->spimem->spi->dev; -+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen); -+ struct nand_pos pos; -+ struct nand_page_io_req req; -+ u8 status; -+ int ret; -+ -+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) { -+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n"); -+ return -EINVAL; -+ } -+ -+ ret = spinand_reset_op(spinand); -+ if (ret) -+ return ret; -+ -+ /* We should store our golden data in first target because -+ * we can't switch target at this moment. -+ */ -+ pos = (struct nand_pos){ -+ .target = 0, -+ .lun = *addr, -+ .plane = *(addr+1), -+ .eraseblock = *(addr+2), -+ .page = *(addr+3), -+ }; -+ -+ req = (struct nand_page_io_req){ -+ .pos = pos, -+ .dataoffs = *(addr+4), -+ .datalen = readlen, -+ .databuf.in = buf, -+ .mode = MTD_OPS_AUTO_OOB, -+ }; -+ -+ ret = spinand_load_page_op(spinand, &req); -+ if (ret) -+ return ret; -+ -+ ret = spinand_wait(spinand, &status); -+ if (ret < 0) -+ return ret; -+ -+ ret = spi_mem_exec_op(spinand->spimem, &op); -+ -+ return 0; -+} -+ - static int spinand_id_detect(struct spinand_device *spinand) - { - u8 *id = spinand->id.data; -@@ -1228,6 +1278,10 @@ static int spinand_init(struct spinand_d - if (!spinand->scratchbuf) - return -ENOMEM; - -+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand); -+ if (ret) -+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret); -+ - ret = spinand_detect(spinand); - if (ret) - goto err_free_bufs; diff --git a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch deleted file mode 100644 index ac8a55e1879e7d..00000000000000 --- a/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch +++ /dev/null @@ -1,57 +0,0 @@ -From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:40:59 +0800 -Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for - spi-nor - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 5 ++++- - drivers/mtd/spi-nor/core.c | 15 +++++++++++++++ - 2 files changed, 19 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1019,7 +1019,10 @@ int spinand_cal_read(void *priv, u32 *ad - if (ret) - return ret; - -- ret = spinand_wait(spinand, &status); -+ ret = spinand_wait(spinand, -+ SPINAND_READ_INITIAL_DELAY_US, -+ SPINAND_READ_POLL_DELAY_US, -+ &status); - if (ret < 0) - return ret; - ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -2922,6 +2922,18 @@ static const struct flash_info *spi_nor_ - return NULL; - } - -+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) -+{ -+ struct spi_nor *nor = (struct spi_nor *)priv; -+ -+ nor->reg_proto = SNOR_PROTO_1_1_1; -+ nor->read_proto = SNOR_PROTO_1_1_1; -+ nor->read_opcode = SPINOR_OP_READ; -+ nor->read_dummy = 0; -+ -+ return nor->controller_ops->read(nor, *addr, readlen, buf); -+} -+ - static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, - const char *name) - { -@@ -3025,6 +3037,9 @@ int spi_nor_scan(struct spi_nor *nor, co - if (!nor->bouncebuf) - return -ENOMEM; - -+ if(nor->spimem) -+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor); -+ - info = spi_nor_get_flash_info(nor, name); - if (IS_ERR(info)) - return PTR_ERR(info); diff --git a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch deleted file mode 100644 index 487990ab77ca52..00000000000000 --- a/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -384,6 +384,12 @@ config ROCKCHIP_PHY - help - Currently supports the integrated Ethernet PHY. - -+config RTL8367S_GSW -+ tristate "rtl8367 Gigabit Switch support for mt7622" -+ depends on NET_VENDOR_MEDIATEK -+ help -+ This driver supports rtl8367s in mt7622 -+ - config SMSC_PHY - tristate "SMSC PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o -+obj-$(CONFIG_RTL8367S_GSW) += rtk/ - obj-$(CONFIG_SMSC_PHY) += smsc.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch deleted file mode 100644 index 983fde707f2445..00000000000000 --- a/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: qizhong cheng -Date: Mon, 27 Dec 2021 21:31:10 +0800 -Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to - stabilize -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Described in PCIe CEM specification sections 2.2 (PERST# Signal) and -2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should -be delayed 100ms (TPVPERL) for the power and clock to become stable. - -Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com -Signed-off-by: qizhong cheng -Signed-off-by: Lorenzo Pieralisi -Acked-by: Pali Rohár ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru - */ - msleep(100); - -+ /* -+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and -+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should -+ * be delayed 100ms (TPVPERL) for the power and clock to become stable. -+ */ -+ msleep(100); -+ - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val = readl(port->base + PCIE_RST_CTRL); - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | diff --git a/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch deleted file mode 100644 index bf479ab53b2cc6..00000000000000 --- a/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -849,6 +849,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - pcie1: pcie@1a145000 { -@@ -887,6 +893,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - sata: sata@1a200000 { diff --git a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch deleted file mode 100644 index 2a49b2275c4f02..00000000000000 --- a/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ /dev/null @@ -1,23 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:33:27 +0200 -Subject: [PATCH] pcie-mediatek: fix clearing interrupt status - -Clearing the status needs to happen after running the handler, otherwise -we will get an extra spurious interrupt after the cause has been cleared - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct - if (status & INTX_MASK) { - for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ -- writel(1 << bit, port->base + PCIE_INT_STATUS); - generic_handle_domain_irq(port->irq_domain, - bit - INTX_SHIFT); -+ writel(1 << bit, port->base + PCIE_INT_STATUS); - } - } - diff --git a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch deleted file mode 100644 index 32b4237d822cc6..00000000000000 --- a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch +++ /dev/null @@ -1,17 +0,0 @@ ---- a/drivers/pci/controller/pcie-mediatek-gen3.c -+++ b/drivers/pci/controller/pcie-mediatek-gen3.c -@@ -375,7 +375,13 @@ static int mtk_pcie_startup_port(struct - msleep(100); - - /* De-assert reset signals */ -- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); -+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB); -+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); -+ -+ msleep(100); -+ -+ /* De-assert PERST# signals */ -+ val &= ~(PCIE_PE_RSTB); - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - - /* Check if the link is up or not */ diff --git a/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch b/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch deleted file mode 100644 index a597f70caa549c..00000000000000 --- a/target/linux/mediatek/patches-6.1/615-phy-phy-mtk-xsphy-support-type-switch-by-pericfg.patch +++ /dev/null @@ -1,167 +0,0 @@ -From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 2 Jun 2023 13:06:26 +0800 -Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg - -Patch from Sam Shih found in MediaTek SDK -released under GPL. - -Get syscon and use it to set the PHY type. -Extend support to PCIe and SGMII mode in addition to USB2 and USB3. - -Signed-off-by: Daniel Golle ---- - drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++- - 1 file changed, 80 insertions(+), 1 deletion(-) - ---- a/drivers/phy/mediatek/phy-mtk-xsphy.c -+++ b/drivers/phy/mediatek/phy-mtk-xsphy.c -@@ -11,10 +11,12 @@ - #include - #include - #include -+#include - #include - #include - #include - #include -+#include - - #include "phy-mtk-io.h" - -@@ -81,12 +83,22 @@ - #define XSP_SR_COEF_DIVISOR 1000 - #define XSP_FM_DET_CYCLE_CNT 1024 - -+/* PHY switch between pcie/usb3/sgmii */ -+#define USB_PHY_SWITCH_CTRL 0x0 -+#define RG_PHY_SW_TYPE GENMASK(3, 0) -+#define RG_PHY_SW_PCIE 0x0 -+#define RG_PHY_SW_USB3 0x1 -+#define RG_PHY_SW_SGMII 0x2 -+ - struct xsphy_instance { - struct phy *phy; - void __iomem *port_base; - struct clk *ref_clk; /* reference clock of anolog phy */ - u32 index; - u32 type; -+ struct regmap *type_sw; -+ u32 type_sw_reg; -+ u32 type_sw_index; - /* only for HQA test */ - int efuse_intr; - int efuse_tx_imp; -@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt - inst->efuse_intr, inst->efuse_tx_imp, - inst->efuse_rx_imp); - break; -+ case PHY_TYPE_PCIE: -+ case PHY_TYPE_SGMII: -+ /* nothing to do */ -+ break; - default: - dev_err(xsphy->dev, "incompatible phy type\n"); - return; -@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_ - RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp); - } - -+/* type switch for usb3/pcie/sgmii */ -+static int phy_type_syscon_get(struct xsphy_instance *instance, -+ struct device_node *dn) -+{ -+ struct of_phandle_args args; -+ int ret; -+ -+ /* type switch function is optional */ -+ if (!of_property_read_bool(dn, "mediatek,syscon-type")) -+ return 0; -+ -+ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", -+ 2, 0, &args); -+ if (ret) -+ return ret; -+ -+ instance->type_sw_reg = args.args[0]; -+ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ -+ instance->type_sw = syscon_node_to_regmap(args.np); -+ of_node_put(args.np); -+ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", -+ instance->type_sw_reg, instance->type_sw_index); -+ -+ return PTR_ERR_OR_ZERO(instance->type_sw); -+} -+ -+static int phy_type_set(struct xsphy_instance *instance) -+{ -+ int type; -+ u32 offset; -+ -+ if (!instance->type_sw) -+ return 0; -+ -+ switch (instance->type) { -+ case PHY_TYPE_USB3: -+ type = RG_PHY_SW_USB3; -+ break; -+ case PHY_TYPE_PCIE: -+ type = RG_PHY_SW_PCIE; -+ break; -+ case PHY_TYPE_SGMII: -+ type = RG_PHY_SW_SGMII; -+ break; -+ case PHY_TYPE_USB2: -+ default: -+ return 0; -+ } -+ -+ offset = instance->type_sw_index * BITS_PER_BYTE; -+ regmap_update_bits(instance->type_sw, instance->type_sw_reg, -+ RG_PHY_SW_TYPE << offset, type << offset); -+ -+ return 0; -+} -+ - static int mtk_phy_init(struct phy *phy) - { - struct xsphy_instance *inst = phy_get_drvdata(phy); -@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy) - case PHY_TYPE_USB3: - u3_phy_props_set(xsphy, inst); - break; -+ case PHY_TYPE_PCIE: -+ case PHY_TYPE_SGMII: -+ /* nothing to do, only used to set type */ -+ break; - default: - dev_err(xsphy->dev, "incompatible phy type\n"); - clk_disable_unprepare(inst->ref_clk); -@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct - - inst->type = args->args[0]; - if (!(inst->type == PHY_TYPE_USB2 || -- inst->type == PHY_TYPE_USB3)) { -+ inst->type == PHY_TYPE_USB3 || -+ inst->type == PHY_TYPE_PCIE || -+ inst->type == PHY_TYPE_SGMII)) { - dev_err(dev, "unsupported phy type: %d\n", inst->type); - return ERR_PTR(-EINVAL); - } - - phy_parse_property(xsphy, inst); -+ phy_type_set(inst); - - return inst->phy; - } -@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo - retval = PTR_ERR(inst->ref_clk); - goto put_child; - } -+ -+ retval = phy_type_syscon_get(inst, child_np); -+ if (retval) -+ goto put_child; - } - - provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); diff --git a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch deleted file mode 100644 index 76ee2fc89abdad..00000000000000 --- a/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ /dev/null @@ -1,82 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:42:42 +0200 -Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA - -It improves performance by eliminating the need for a cache flush for DMA on -attached devices - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -837,6 +837,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; -@@ -881,6 +884,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,6 +140,11 @@ - #define PCIE_LINK_STATUS_V2 0x804 - #define PCIE_PORT_LINKUP_V2 BIT(10) - -+/* DMA channel mapping */ -+#define HIFSYS_DMA_AG_MAP 0x008 -+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) -+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) -+ - struct mtk_pcie_port; - - /** -@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci - struct mtk_pcie_port *port, *tmp; - int err, slot; - -+ if (of_dma_is_coherent(node)) { -+ struct regmap *con; -+ u32 mask; -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,cci-control"); -+ /* enable CPU/bus coherency */ -+ if (!IS_ERR(con)) -+ regmap_write(con, 0, 3); -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,hifsys"); -+ if (IS_ERR(con)) { -+ dev_err(dev, "missing hifsys node\n"); -+ return PTR_ERR(con); -+ } -+ -+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; -+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); -+ } -+ - slot = of_get_pci_domain_nr(dev->of_node); - if (slot < 0) { - for_each_available_child_of_node(node, child) { diff --git a/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch deleted file mode 100644 index f9a5fdbd0d837d..00000000000000 --- a/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Jip de Beer -Date: Sun, 9 Jan 2022 13:14:04 +0100 -Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts - -The lowest frequency should be 300MHz, since that is the label -assigned to the OPP in the mt7622.dtsi device tree, while there is one -missing zero in the actual value. - -To be clear, the lowest frequency should be 300MHz instead of 30MHz. - -As mentioned @dangowrt on the OpenWrt forum there is no benefit in -leaving 30MHz as the lowest frequency. - -Signed-off-by: Jip de Beer -Signed-off-by: Fritz D. Ansel ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -24,7 +24,7 @@ - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { -- opp-hz = /bits/ 64 <30000000>; -+ opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000>; - }; - diff --git a/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch deleted file mode 100644 index 52069496ca822b..00000000000000 --- a/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -23,11 +23,17 @@ - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; -- opp-300000000 { -- opp-hz = /bits/ 64 <300000000>; -- opp-microvolt = <950000>; -- }; -- -+ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low -+ * voltage condition that can cause a hang when rebooting the RT3200/E8450. -+ * -+ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 -+ * -+ * opp-300000000 { -+ * opp-hz = /bits/ 64 <300000000>; -+ * opp-microvolt = <950000>; -+ * }; -+ * -+ */ - opp-437500000 { - opp-hz = /bits/ 64 <437500000>; - opp-microvolt = <1000000>; diff --git a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch deleted file mode 100644 index 4022b2a842496e..00000000000000 --- a/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch +++ /dev/null @@ -1,1204 +0,0 @@ -From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 11 Jun 2023 00:48:10 +0100 -Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs - -Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet -PHYs which require calibration data from the SoC's efuse. -Despite the similar design the driver doesn't share any code with the -existing mediatek-ge.c. -Add support for such PHYs by introducing a new driver with basic -support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs. - -Signed-off-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - MAINTAINERS | 9 + - drivers/net/phy/Kconfig | 12 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++ - drivers/net/phy/mediatek-ge.c | 3 +- - 5 files changed, 1140 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/phy/mediatek-ge-soc.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -12945,6 +12945,15 @@ F: drivers/net/pcs/pcs-mtk-usxgmii.c - F: include/linux/pcs/pcs-mtk-lynxi.h - F: include/linux/pcs/pcs-mtk-usxgmii.h - -+MEDIATEK ETHERNET PHY DRIVERS -+M: Daniel Golle -+M: Qingfang Deng -+M: SkyLake Huang -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/net/phy/mediatek-ge-soc.c -+F: drivers/net/phy/mediatek-ge.c -+ - MEDIATEK I2C CONTROLLER DRIVER - M: Qii Wang - L: linux-i2c@vger.kernel.org ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -314,6 +314,18 @@ config MEDIATEK_GE_PHY - help - Supports the MediaTek Gigabit Ethernet PHYs. - -+config MEDIATEK_GE_SOC_PHY -+ tristate "MediaTek SoC Ethernet PHYs" -+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST -+ select NVMEM_MTK_EFUSE -+ help -+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. -+ -+ Include support for built-in Ethernet PHYs which are present in -+ the MT7981 and MT7988 SoCs. These PHYs need calibration data -+ present in the SoCs efuse and will dynamically calibrate VCM -+ (common-mode voltage) during startup. -+ - config MICREL_PHY - tristate "Micrel PHYs" - depends on PTP_1588_CLOCK_OPTIONAL ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o -+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_MICREL_PHY) += micrel.o ---- /dev/null -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -0,0 +1,1116 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MTK_GPHY_ID_MT7981 0x03a29461 -+#define MTK_GPHY_ID_MT7988 0x03a29481 -+ -+#define MTK_EXT_PAGE_ACCESS 0x1f -+#define MTK_PHY_PAGE_STANDARD 0x0000 -+#define MTK_PHY_PAGE_EXTENDED_3 0x0003 -+ -+#define MTK_PHY_LPI_REG_14 0x14 -+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) -+ -+#define MTK_PHY_LPI_REG_1c 0x1c -+#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) -+ -+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 -+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 -+ -+#define ANALOG_INTERNAL_OPERATION_MAX_US 20 -+#define TXRESERVE_MIN 0 -+#define TXRESERVE_MAX 7 -+ -+#define MTK_PHY_ANARG_RG 0x10 -+#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) -+ -+/* Registers on MDIO_MMD_VEND1 */ -+#define MTK_PHY_TXVLD_DA_RG 0x12 -+#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) -+#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 -+#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) -+#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 -+#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 -+#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 -+#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 -+#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 -+#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 -+#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_RXADC_CTRL_RG7 0xc6 -+#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) -+ -+#define MTK_PHY_RXADC_CTRL_RG9 0xc8 -+#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) -+#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) -+#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) -+#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) -+ -+#define MTK_PHY_LDO_OUTPUT_V 0xd7 -+ -+#define MTK_PHY_RG_ANA_CAL_RG0 0xdb -+#define MTK_PHY_RG_CAL_CKINV BIT(12) -+#define MTK_PHY_RG_ANA_CALEN BIT(8) -+#define MTK_PHY_RG_ZCALEN_A BIT(0) -+ -+#define MTK_PHY_RG_ANA_CAL_RG1 0xdc -+#define MTK_PHY_RG_ZCALEN_B BIT(12) -+#define MTK_PHY_RG_ZCALEN_C BIT(8) -+#define MTK_PHY_RG_ZCALEN_D BIT(4) -+#define MTK_PHY_RG_TXVOS_CALEN BIT(0) -+ -+#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 -+#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) -+ -+#define MTK_PHY_RG_TX_FILTER 0xfe -+ -+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 -+#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) -+#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) -+ -+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 -+#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) -+ -+#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 -+#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) -+ -+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 -+#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) -+#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) -+ -+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 -+#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) -+#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) -+ -+#define MTK_PHY_RG_AD_CAL_COMP 0x17a -+#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) -+ -+#define MTK_PHY_RG_AD_CAL_CLK 0x17b -+#define MTK_PHY_DA_CAL_CLK BIT(0) -+ -+#define MTK_PHY_RG_AD_CALIN 0x17c -+#define MTK_PHY_DA_CALIN_FLAG BIT(0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d -+#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e -+#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f -+#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 -+#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 -+#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 -+#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 -+#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 -+#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DEV1E_REG19b 0x19b -+#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) -+ -+#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a -+#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b -+#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c -+#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d -+#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e -+#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f -+#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 -+#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 -+#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 -+#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 -+ -+#define MTK_PHY_RG_DEV1E_REG234 0x234 -+#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) -+#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) -+#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) -+ -+#define MTK_PHY_RG_LPF_CNT_VAL 0x235 -+ -+#define MTK_PHY_RG_DEV1E_REG238 0x238 -+#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) -+#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) -+ -+#define MTK_PHY_RG_DEV1E_REG239 0x239 -+#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) -+#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) -+ -+#define MTK_PHY_RG_DEV1E_REG27C 0x27c -+#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) -+#define MTK_PHY_RG_DEV1E_REG27D 0x27d -+#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) -+ -+#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 -+#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) -+#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) -+ -+#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 -+#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) -+#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) -+#define MTK_PHY_LPI_TR_READY BIT(9) -+#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) -+ -+#define MTK_PHY_RG_DEV1E_REG323 0x323 -+#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) -+#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) -+ -+#define MTK_PHY_RG_DEV1E_REG324 0x324 -+#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) -+#define MTK_PHY_SMI_DET_MAX_EN BIT(8) -+ -+#define MTK_PHY_RG_DEV1E_REG326 0x326 -+#define MTK_PHY_LPI_MODE_SD_ON BIT(0) -+#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) -+#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) -+#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) -+#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) -+ -+#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 -+#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 -+ -+#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d -+#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e -+#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f -+#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 -+ -+#define MTK_PHY_RG_BG_RASEL 0x115 -+#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) -+ -+/* These macro privides efuse parsing for internal phy. */ -+#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) -+ -+#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) -+ -+#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) -+ -+#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) -+#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) -+ -+enum { -+ NO_PAIR, -+ PAIR_A, -+ PAIR_B, -+ PAIR_C, -+ PAIR_D, -+}; -+ -+enum { -+ GPHY_PORT0, -+ GPHY_PORT1, -+ GPHY_PORT2, -+ GPHY_PORT3, -+}; -+ -+enum calibration_mode { -+ EFUSE_K, -+ SW_K -+}; -+ -+enum CAL_ITEM { -+ REXT, -+ TX_OFFSET, -+ TX_AMP, -+ TX_R50, -+ TX_VCM -+}; -+ -+enum CAL_MODE { -+ EFUSE_M, -+ SW_M -+}; -+ -+static int mtk_socphy_read_page(struct phy_device *phydev) -+{ -+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -+} -+ -+static int mtk_socphy_write_page(struct phy_device *phydev, int page) -+{ -+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -+} -+ -+/* One calibration cycle consists of: -+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high -+ * until AD_CAL_COMP is ready to output calibration result. -+ * 2.Wait until DA_CAL_CLK is available. -+ * 3.Fetch AD_CAL_COMP_OUT. -+ */ -+static int cal_cycle(struct phy_device *phydev, int devad, -+ u32 regnum, u16 mask, u16 cal_val) -+{ -+ int reg_val; -+ int ret; -+ -+ phy_modify_mmd(phydev, devad, regnum, -+ mask, cal_val); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, -+ MTK_PHY_DA_CALIN_FLAG); -+ -+ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_AD_CAL_CLK, reg_val, -+ reg_val & MTK_PHY_DA_CAL_CLK, 500, -+ ANALOG_INTERNAL_OPERATION_MAX_US, false); -+ if (ret) { -+ phydev_err(phydev, "Calibration cycle timeout\n"); -+ return ret; -+ } -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, -+ MTK_PHY_DA_CALIN_FLAG); -+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> -+ MTK_PHY_AD_CAL_COMP_OUT_SHIFT; -+ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); -+ -+ return ret; -+} -+ -+static int rext_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, -+ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, -+ MTK_PHY_RG_BG_RASEL_MASK, buf[1]); -+ -+ return 0; -+} -+ -+static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 rext_cal_val[2]; -+ -+ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); -+ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); -+ rext_fill_result(phydev, rext_cal_val); -+ -+ return 0; -+} -+ -+static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, -+ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, -+ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, -+ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, -+ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); -+ -+ return 0; -+} -+ -+static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 tx_offset_cal_val[4]; -+ -+ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); -+ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); -+ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); -+ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); -+ -+ tx_offset_fill_result(phydev, tx_offset_cal_val); -+ -+ return 0; -+} -+ -+static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ int i; -+ int bias[16] = {}; -+ const int vals_9461[16] = { 7, 1, 4, 7, -+ 7, 1, 4, 7, -+ 7, 1, 4, 7, -+ 7, 1, 4, 7 }; -+ const int vals_9481[16] = { 10, 6, 6, 10, -+ 10, 6, 6, 10, -+ 10, 6, 6, 10, -+ 10, 6, 6, 10 }; -+ switch (phydev->drv->phy_id) { -+ case MTK_GPHY_ID_MT7981: -+ /* We add some calibration to efuse values -+ * due to board level influence. -+ * GBE: +7, TBT: +1, HBT: +4, TST: +7 -+ */ -+ memcpy(bias, (const void *)vals_9461, sizeof(bias)); -+ break; -+ case MTK_GPHY_ID_MT7988: -+ memcpy(bias, (const void *)vals_9481, sizeof(bias)); -+ break; -+ } -+ -+ /* Prevent overflow */ -+ for (i = 0; i < 12; i++) { -+ if (buf[i >> 2] + bias[i] > 63) { -+ buf[i >> 2] = 63; -+ bias[i] = 0; -+ } -+ } -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, -+ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, -+ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, -+ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, -+ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, -+ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, -+ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, -+ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, -+ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, -+ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, -+ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, -+ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, -+ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, -+ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, -+ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, -+ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, -+ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); -+ -+ return 0; -+} -+ -+static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 tx_amp_cal_val[4]; -+ -+ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); -+ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); -+ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); -+ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); -+ tx_amp_fill_result(phydev, tx_amp_cal_val); -+ -+ return 0; -+} -+ -+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, -+ u8 txg_calen_x) -+{ -+ int bias = 0; -+ u16 reg, val; -+ -+ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) -+ bias = -2; -+ -+ val = clamp_val(bias + tx_r50_cal_val, 0, 63); -+ -+ switch (txg_calen_x) { -+ case PAIR_A: -+ reg = MTK_PHY_DA_TX_R50_PAIR_A; -+ break; -+ case PAIR_B: -+ reg = MTK_PHY_DA_TX_R50_PAIR_B; -+ break; -+ case PAIR_C: -+ reg = MTK_PHY_DA_TX_R50_PAIR_C; -+ break; -+ case PAIR_D: -+ reg = MTK_PHY_DA_TX_R50_PAIR_D; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); -+ -+ return 0; -+} -+ -+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, -+ u8 txg_calen_x) -+{ -+ u16 tx_r50_cal_val; -+ -+ switch (txg_calen_x) { -+ case PAIR_A: -+ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); -+ break; -+ case PAIR_B: -+ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); -+ break; -+ case PAIR_C: -+ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); -+ break; -+ case PAIR_D: -+ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); -+ break; -+ default: -+ return -EINVAL; -+ } -+ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); -+ -+ return 0; -+} -+ -+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) -+{ -+ u8 lower_idx, upper_idx, txreserve_val; -+ u8 lower_ret, upper_ret; -+ int ret; -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ANA_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_CAL_CKINV); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_TXVOS_CALEN); -+ -+ switch (rg_txreserve_x) { -+ case PAIR_A: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_A, -+ MTK_PHY_DASN_DAC_IN0_A_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_A, -+ MTK_PHY_DASN_DAC_IN1_A_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ZCALEN_A); -+ break; -+ case PAIR_B: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_B, -+ MTK_PHY_DASN_DAC_IN0_B_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_B, -+ MTK_PHY_DASN_DAC_IN1_B_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_B); -+ break; -+ case PAIR_C: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_C, -+ MTK_PHY_DASN_DAC_IN0_C_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_C, -+ MTK_PHY_DASN_DAC_IN1_C_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_C); -+ break; -+ case PAIR_D: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_D, -+ MTK_PHY_DASN_DAC_IN0_D_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_D, -+ MTK_PHY_DASN_DAC_IN1_D_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_D); -+ break; -+ default: -+ ret = -EINVAL; -+ goto restore; -+ } -+ -+ lower_idx = TXRESERVE_MIN; -+ upper_idx = TXRESERVE_MAX; -+ -+ phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); -+ while ((upper_idx - lower_idx) > 1) { -+ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); -+ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ txreserve_val << 12 | txreserve_val << 8 | -+ txreserve_val << 4 | txreserve_val); -+ if (ret == 1) { -+ upper_idx = txreserve_val; -+ upper_ret = ret; -+ } else if (ret == 0) { -+ lower_idx = txreserve_val; -+ lower_ret = ret; -+ } else { -+ goto restore; -+ } -+ } -+ -+ if (lower_idx == TXRESERVE_MIN) { -+ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ lower_idx << 12 | lower_idx << 8 | -+ lower_idx << 4 | lower_idx); -+ ret = lower_ret; -+ } else if (upper_idx == TXRESERVE_MAX) { -+ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ upper_idx << 12 | upper_idx << 8 | -+ upper_idx << 4 | upper_idx); -+ ret = upper_ret; -+ } -+ if (ret < 0) -+ goto restore; -+ -+ /* We calibrate TX-VCM in different logic. Check upper index and then -+ * lower index. If this calibration is valid, apply lower index's result. -+ */ -+ ret = upper_ret - lower_ret; -+ if (ret == 1) { -+ ret = 0; -+ /* Make sure we use upper_idx in our calibration system */ -+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ upper_idx << 12 | upper_idx << 8 | -+ upper_idx << 4 | upper_idx); -+ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); -+ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && -+ lower_ret == 1) { -+ ret = 0; -+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ lower_idx << 12 | lower_idx << 8 | -+ lower_idx << 4 | lower_idx); -+ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", -+ lower_idx); -+ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && -+ lower_ret == 0) { -+ ret = 0; -+ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", -+ upper_idx); -+ } else { -+ ret = -EINVAL; -+ } -+ -+restore: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ANA_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_TXVOS_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ZCALEN_A); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | -+ MTK_PHY_RG_ZCALEN_D); -+ -+ return ret; -+} -+ -+static void mt798x_phy_common_finetune(struct phy_device *phydev) -+{ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* EnabRandUpdTrig = 1 */ -+ __phy_write(phydev, 0x11, 0x2f00); -+ __phy_write(phydev, 0x12, 0xe); -+ __phy_write(phydev, 0x10, 0x8fb0); -+ -+ /* NormMseLoThresh = 85 */ -+ __phy_write(phydev, 0x11, 0x55a0); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x83aa); -+ -+ /* TrFreeze = 0 */ -+ __phy_write(phydev, 0x11, 0x0); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9686); -+ -+ /* SSTrKp1000Slv = 5 */ -+ __phy_write(phydev, 0x11, 0xbaef); -+ __phy_write(phydev, 0x12, 0x2e); -+ __phy_write(phydev, 0x10, 0x968c); -+ -+ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, -+ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 -+ */ -+ __phy_write(phydev, 0x11, 0xd10a); -+ __phy_write(phydev, 0x12, 0x34); -+ __phy_write(phydev, 0x10, 0x8f82); -+ -+ /* VcoSlicerThreshBitsHigh */ -+ __phy_write(phydev, 0x11, 0x5555); -+ __phy_write(phydev, 0x12, 0x55); -+ __phy_write(phydev, 0x10, 0x8ec0); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, -+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, -+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); -+ -+ /* rg_tr_lpf_cnt_val = 512 */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); -+ -+ /* IIR2 related */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); -+ -+ /* FFE peaking */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, -+ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, -+ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); -+ -+ /* Disable LDO pump */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); -+ /* Adjust LDO output voltage */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); -+} -+ -+static void mt7981_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[8] = { 0x01ce, 0x01c1, -+ 0x020f, 0x0202, -+ 0x03d0, 0x03c0, -+ 0x0013, 0x0005 }; -+ int i, k; -+ -+ /* 100M eye finetune: -+ * Keep middle level of TX MLT3 shapper as default. -+ * Only change TX MLT3 overshoot level here. -+ */ -+ for (k = 0, i = 1; i < 12; i++) { -+ if (i % 3 == 0) -+ continue; -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); -+ } -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ -+ __phy_write(phydev, 0x11, 0xc71); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ -+ /* ResetSyncOffset = 6 */ -+ __phy_write(phydev, 0x11, 0x600); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate = 1 */ -+ __phy_write(phydev, 0x11, 0x4c2a); -+ __phy_write(phydev, 0x12, 0x3e); -+ __phy_write(phydev, 0x10, 0x8fa4); -+ -+ /* FfeUpdGainForce = 4 */ -+ __phy_write(phydev, 0x11, 0x240); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9680); -+ -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt7988_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, -+ 0x020d, 0x0206, 0x0384, 0x03d0, -+ 0x03c6, 0x030a, 0x0011, 0x0005 }; -+ int i; -+ -+ /* Set default MLT3 shaper first */ -+ for (i = 0; i < 12; i++) -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); -+ -+ /* TCT finetune */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); -+ -+ /* Disable TX power saving */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, -+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ -+ __phy_write(phydev, 0x11, 0x671); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ -+ /* ResetSyncOffset = 5 */ -+ __phy_write(phydev, 0x11, 0x500); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate is 1 at default on mt7988 */ -+ -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); -+ /* TxClkOffset = 2 */ -+ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, -+ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt798x_phy_eee(struct phy_device *phydev) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, -+ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | -+ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | -+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, -+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ 0xff)); -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_TESTMUX_ADC_CTRL, -+ MTK_PHY_RG_TXEN_DIG_MASK); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, -+ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | -+ MTK_PHY_LPI_SLV_SEND_TX_EN, -+ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, -+ MTK_PHY_LPI_SEND_LOC_TIMER_MASK | -+ MTK_PHY_LPI_TXPCS_LOC_RCV, -+ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, -+ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, -+ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | -+ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, -+ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, -+ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, -+ 0x33) | -+ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | -+ MTK_PHY_LPI_VCO_EEE_STG0_EN); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, -+ MTK_PHY_EEE_WAKE_MAS_INT_DC | -+ MTK_PHY_EEE_WAKE_SLV_INT_DC); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, -+ MTK_PHY_SMI_DETCNT_MAX_MASK, -+ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | -+ MTK_PHY_SMI_DET_MAX_EN); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, -+ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | -+ MTK_PHY_TREC_UPDATE_ENAB_CLR | -+ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | -+ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* Regsigdet_sel_1000 = 0 */ -+ __phy_write(phydev, 0x11, 0xb); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9690); -+ -+ /* REG_EEE_st2TrKf1000 = 3 */ -+ __phy_write(phydev, 0x11, 0x114f); -+ __phy_write(phydev, 0x12, 0x2); -+ __phy_write(phydev, 0x10, 0x969a); -+ -+ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ -+ __phy_write(phydev, 0x11, 0x3028); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x969e); -+ -+ /* RegEEE_slv_wake_int_timer_tar = 8 */ -+ __phy_write(phydev, 0x11, 0x5010); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96a0); -+ -+ /* RegEEE_trfreeze_timer2 = 586 */ -+ __phy_write(phydev, 0x11, 0x24a); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96a8); -+ -+ /* RegEEE100Stg1_tar = 16 */ -+ __phy_write(phydev, 0x11, 0x3210); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96b8); -+ -+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ -+ __phy_write(phydev, 0x11, 0x1463); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96ca); -+ -+ /* DfeTailEnableVgaThresh1000 = 27 */ -+ __phy_write(phydev, 0x11, 0x36); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8f80); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); -+ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); -+ -+ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, -+ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, -+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); -+} -+ -+static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ u8 start_pair, u8 end_pair) -+{ -+ u8 pair_n; -+ int ret; -+ -+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { -+ /* TX_OFFSET & TX_AMP have no SW calibration. */ -+ switch (cal_item) { -+ case TX_VCM: -+ ret = tx_vcm_cal_sw(phydev, pair_n); -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (ret) -+ return ret; -+ } -+ return 0; -+} -+ -+static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ u8 start_pair, u8 end_pair, u32 *buf) -+{ -+ u8 pair_n; -+ int ret; -+ -+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { -+ /* TX_VCM has no efuse calibration. */ -+ switch (cal_item) { -+ case REXT: -+ ret = rext_cal_efuse(phydev, buf); -+ break; -+ case TX_OFFSET: -+ ret = tx_offset_cal_efuse(phydev, buf); -+ break; -+ case TX_AMP: -+ ret = tx_amp_cal_efuse(phydev, buf); -+ break; -+ case TX_R50: -+ ret = tx_r50_cal_efuse(phydev, buf, pair_n); -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ enum CAL_MODE cal_mode, u8 start_pair, -+ u8 end_pair, u32 *buf) -+{ -+ int ret; -+ -+ switch (cal_mode) { -+ case EFUSE_M: -+ ret = cal_efuse(phydev, cal_item, start_pair, -+ end_pair, buf); -+ break; -+ case SW_M: -+ ret = cal_sw(phydev, cal_item, start_pair, end_pair); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (ret) { -+ phydev_err(phydev, "cal %d failed\n", cal_item); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int mt798x_phy_calibration(struct phy_device *phydev) -+{ -+ int ret = 0; -+ u32 *buf; -+ size_t len; -+ struct nvmem_cell *cell; -+ -+ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); -+ if (IS_ERR(cell)) { -+ if (PTR_ERR(cell) == -EPROBE_DEFER) -+ return PTR_ERR(cell); -+ return 0; -+ } -+ -+ buf = (u32 *)nvmem_cell_read(cell, &len); -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ nvmem_cell_put(cell); -+ -+ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { -+ phydev_err(phydev, "invalid efuse data\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); -+ if (ret) -+ goto out; -+ -+out: -+ kfree(buf); -+ return ret; -+} -+ -+static int mt798x_phy_config_init(struct phy_device *phydev) -+{ -+ switch (phydev->drv->phy_id) { -+ case MTK_GPHY_ID_MT7981: -+ mt7981_phy_finetune(phydev); -+ break; -+ case MTK_GPHY_ID_MT7988: -+ mt7988_phy_finetune(phydev); -+ break; -+ } -+ -+ mt798x_phy_common_finetune(phydev); -+ mt798x_phy_eee(phydev); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ -+static struct phy_driver mtk_socphy_driver[] = { -+ { -+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -+ .name = "MediaTek MT7981 PHY", -+ .config_init = mt798x_phy_config_init, -+ .config_intr = genphy_no_config_intr, -+ .handle_interrupt = genphy_handle_interrupt_no_ack, -+ .probe = mt798x_phy_calibration, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_socphy_read_page, -+ .write_page = mtk_socphy_write_page, -+ }, -+ { -+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), -+ .name = "MediaTek MT7988 PHY", -+ .config_init = mt798x_phy_config_init, -+ .config_intr = genphy_no_config_intr, -+ .handle_interrupt = genphy_handle_interrupt_no_ack, -+ .probe = mt798x_phy_calibration, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_socphy_read_page, -+ .write_page = mtk_socphy_write_page, -+ }, -+}; -+ -+module_phy_driver(mtk_socphy_driver); -+ -+static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { -+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, -+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, -+ { } -+}; -+ -+MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); -+MODULE_AUTHOR("Daniel Golle "); -+MODULE_AUTHOR("SkyLake Huang "); -+MODULE_LICENSE("GPL"); -+ -+MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); ---- a/drivers/net/phy/mediatek-ge.c -+++ b/drivers/net/phy/mediatek-ge.c -@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive - module_phy_driver(mtk_gephy_driver); - - static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { -- { PHY_ID_MATCH_VENDOR(0x03a29400) }, -+ { PHY_ID_MATCH_EXACT(0x03a29441) }, -+ { PHY_ID_MATCH_EXACT(0x03a29412) }, - { } - }; - diff --git a/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch b/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch deleted file mode 100644 index 286ce96a7de7dc..00000000000000 --- a/target/linux/mediatek/patches-6.1/731-v6.5-net-phy-mediatek-ge-soc-support-PHY-LEDs.patch +++ /dev/null @@ -1,524 +0,0 @@ -From c66937b0f8dbb4c6c043663c702b1053fb47fab2 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 14 Aug 2023 02:58:14 +0100 -Subject: [PATCH] net: phy: mediatek-ge-soc: support PHY LEDs - -Implement netdev trigger and primitive bliking offloading as well as -simple set_brigthness function for both PHY LEDs of the in-SoC PHYs -found in MT7981 and MT7988. - -For MT7988, read boottrap register and apply LED polarities accordingly -to get uniform behavior from all LEDs on MT7988. -This requires syscon phandle 'mediatek,pio' present in parenting MDIO bus -which should point to the syscon holding the boottrap register. - -Signed-off-by: Daniel Golle -Reviewed-by: Andrew Lunn -Link: https://lore.kernel.org/r/dc324d48c00cd7350f3a506eaa785324cae97372.1691977904.git.daniel@makrotopia.org -Signed-off-by: Jakub Kicinski ---- - drivers/net/phy/mediatek-ge-soc.c | 435 +++++++++++++++++++++++++++++- - 1 file changed, 426 insertions(+), 9 deletions(-) - ---- a/drivers/net/phy/mediatek-ge-soc.c -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -1,11 +1,14 @@ - // SPDX-License-Identifier: GPL-2.0+ - #include -+#include -+#include - #include - #include - #include - #include - #include - #include -+#include - - #define MTK_GPHY_ID_MT7981 0x03a29461 - #define MTK_GPHY_ID_MT7988 0x03a29481 -@@ -208,9 +211,42 @@ - #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f - #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 - -+/* Registers on MDIO_MMD_VEND2 */ -+#define MTK_PHY_LED0_ON_CTRL 0x24 -+#define MTK_PHY_LED1_ON_CTRL 0x26 -+#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) -+#define MTK_PHY_LED_ON_LINK1000 BIT(0) -+#define MTK_PHY_LED_ON_LINK100 BIT(1) -+#define MTK_PHY_LED_ON_LINK10 BIT(2) -+#define MTK_PHY_LED_ON_LINKDOWN BIT(3) -+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ -+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ -+#define MTK_PHY_LED_ON_FORCE_ON BIT(6) -+#define MTK_PHY_LED_ON_POLARITY BIT(14) -+#define MTK_PHY_LED_ON_ENABLE BIT(15) -+ -+#define MTK_PHY_LED0_BLINK_CTRL 0x25 -+#define MTK_PHY_LED1_BLINK_CTRL 0x27 -+#define MTK_PHY_LED_BLINK_1000TX BIT(0) -+#define MTK_PHY_LED_BLINK_1000RX BIT(1) -+#define MTK_PHY_LED_BLINK_100TX BIT(2) -+#define MTK_PHY_LED_BLINK_100RX BIT(3) -+#define MTK_PHY_LED_BLINK_10TX BIT(4) -+#define MTK_PHY_LED_BLINK_10RX BIT(5) -+#define MTK_PHY_LED_BLINK_COLLISION BIT(6) -+#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) -+#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) -+#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) -+ -+#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) -+ - #define MTK_PHY_RG_BG_RASEL 0x115 - #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) - -+/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ -+#define RG_GPIO_MISC_TPBANK0 0x6f0 -+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) -+ - /* These macro privides efuse parsing for internal phy. */ - #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) - #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -@@ -238,13 +274,6 @@ enum { - PAIR_D, - }; - --enum { -- GPHY_PORT0, -- GPHY_PORT1, -- GPHY_PORT2, -- GPHY_PORT3, --}; -- - enum calibration_mode { - EFUSE_K, - SW_K -@@ -263,6 +292,19 @@ enum CAL_MODE { - SW_M - }; - -+#define MTK_PHY_LED_STATE_FORCE_ON 0 -+#define MTK_PHY_LED_STATE_FORCE_BLINK 1 -+#define MTK_PHY_LED_STATE_NETDEV 2 -+ -+struct mtk_socphy_priv { -+ unsigned long led_state; -+}; -+ -+struct mtk_socphy_shared { -+ u32 boottrap; -+ struct mtk_socphy_priv priv[4]; -+}; -+ - static int mtk_socphy_read_page(struct phy_device *phydev) - { - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -@@ -1073,6 +1115,371 @@ static int mt798x_phy_config_init(struct - return mt798x_phy_calibration(phydev); - } - -+static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, -+ bool on) -+{ -+ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); -+ struct mtk_socphy_priv *priv = phydev->priv; -+ bool changed; -+ -+ if (on) -+ changed = !test_and_set_bit(bit_on, &priv->led_state); -+ else -+ changed = !!test_and_clear_bit(bit_on, &priv->led_state); -+ -+ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + -+ (index ? 16 : 0), &priv->led_state); -+ if (changed) -+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_MASK, -+ on ? MTK_PHY_LED_ON_FORCE_ON : 0); -+ else -+ return 0; -+} -+ -+static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, -+ bool blinking) -+{ -+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); -+ struct mtk_socphy_priv *priv = phydev->priv; -+ bool changed; -+ -+ if (blinking) -+ changed = !test_and_set_bit(bit_blink, &priv->led_state); -+ else -+ changed = !!test_and_clear_bit(bit_blink, &priv->led_state); -+ -+ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV + -+ (index ? 16 : 0), &priv->led_state); -+ if (changed) -+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL, -+ blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0); -+ else -+ return 0; -+} -+ -+static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, -+ unsigned long *delay_on, -+ unsigned long *delay_off) -+{ -+ bool blinking = false; -+ int err = 0; -+ -+ if (index > 1) -+ return -EINVAL; -+ -+ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { -+ blinking = true; -+ *delay_on = 50; -+ *delay_off = 50; -+ } -+ -+ err = mt798x_phy_hw_led_blink_set(phydev, index, blinking); -+ if (err) -+ return err; -+ -+ return mt798x_phy_hw_led_on_set(phydev, index, false); -+} -+ -+static int mt798x_phy_led_brightness_set(struct phy_device *phydev, -+ u8 index, enum led_brightness value) -+{ -+ int err; -+ -+ err = mt798x_phy_hw_led_blink_set(phydev, index, false); -+ if (err) -+ return err; -+ -+ return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF)); -+} -+ -+static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | -+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) | -+ BIT(TRIGGER_NETDEV_LINK) | -+ BIT(TRIGGER_NETDEV_LINK_10) | -+ BIT(TRIGGER_NETDEV_LINK_100) | -+ BIT(TRIGGER_NETDEV_LINK_1000) | -+ BIT(TRIGGER_NETDEV_RX) | -+ BIT(TRIGGER_NETDEV_TX)); -+ -+static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, -+ unsigned long rules) -+{ -+ if (index > 1) -+ return -EINVAL; -+ -+ /* All combinations of the supported triggers are allowed */ -+ if (rules & ~supported_triggers) -+ return -EOPNOTSUPP; -+ -+ return 0; -+}; -+ -+static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, -+ unsigned long *rules) -+{ -+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0); -+ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); -+ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); -+ struct mtk_socphy_priv *priv = phydev->priv; -+ int on, blink; -+ -+ if (index > 1) -+ return -EINVAL; -+ -+ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, -+ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); -+ -+ if (on < 0) -+ return -EIO; -+ -+ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, -+ index ? MTK_PHY_LED1_BLINK_CTRL : -+ MTK_PHY_LED0_BLINK_CTRL); -+ if (blink < 0) -+ return -EIO; -+ -+ if ((on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK10)) || -+ (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | -+ MTK_PHY_LED_BLINK_10RX | MTK_PHY_LED_BLINK_1000TX | -+ MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX))) -+ set_bit(bit_netdev, &priv->led_state); -+ else -+ clear_bit(bit_netdev, &priv->led_state); -+ -+ if (on & MTK_PHY_LED_ON_FORCE_ON) -+ set_bit(bit_on, &priv->led_state); -+ else -+ clear_bit(bit_on, &priv->led_state); -+ -+ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) -+ set_bit(bit_blink, &priv->led_state); -+ else -+ clear_bit(bit_blink, &priv->led_state); -+ -+ if (!rules) -+ return 0; -+ -+ if (on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK10)) -+ *rules |= BIT(TRIGGER_NETDEV_LINK); -+ -+ if (on & MTK_PHY_LED_ON_LINK10) -+ *rules |= BIT(TRIGGER_NETDEV_LINK_10); -+ -+ if (on & MTK_PHY_LED_ON_LINK100) -+ *rules |= BIT(TRIGGER_NETDEV_LINK_100); -+ -+ if (on & MTK_PHY_LED_ON_LINK1000) -+ *rules |= BIT(TRIGGER_NETDEV_LINK_1000); -+ -+ if (on & MTK_PHY_LED_ON_FDX) -+ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX); -+ -+ if (on & MTK_PHY_LED_ON_HDX) -+ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX); -+ -+ if (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | MTK_PHY_LED_BLINK_10RX)) -+ *rules |= BIT(TRIGGER_NETDEV_RX); -+ -+ if (blink & (MTK_PHY_LED_BLINK_1000TX | MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX)) -+ *rules |= BIT(TRIGGER_NETDEV_TX); -+ -+ return 0; -+}; -+ -+static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, -+ unsigned long rules) -+{ -+ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); -+ struct mtk_socphy_priv *priv = phydev->priv; -+ u16 on = 0, blink = 0; -+ int ret; -+ -+ if (index > 1) -+ return -EINVAL; -+ -+ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) -+ on |= MTK_PHY_LED_ON_FDX; -+ -+ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) -+ on |= MTK_PHY_LED_ON_HDX; -+ -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) -+ on |= MTK_PHY_LED_ON_LINK10; -+ -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) -+ on |= MTK_PHY_LED_ON_LINK100; -+ -+ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) -+ on |= MTK_PHY_LED_ON_LINK1000; -+ -+ if (rules & BIT(TRIGGER_NETDEV_RX)) { -+ blink |= MTK_PHY_LED_BLINK_10RX | -+ MTK_PHY_LED_BLINK_100RX | -+ MTK_PHY_LED_BLINK_1000RX; -+ } -+ -+ if (rules & BIT(TRIGGER_NETDEV_TX)) { -+ blink |= MTK_PHY_LED_BLINK_10TX | -+ MTK_PHY_LED_BLINK_100TX | -+ MTK_PHY_LED_BLINK_1000TX; -+ } -+ -+ if (blink || on) -+ set_bit(bit_netdev, &priv->led_state); -+ else -+ clear_bit(bit_netdev, &priv->led_state); -+ -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_ON_CTRL : -+ MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_FDX | -+ MTK_PHY_LED_ON_HDX | -+ MTK_PHY_LED_ON_LINK10 | -+ MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK1000, -+ on); -+ -+ if (ret) -+ return ret; -+ -+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_BLINK_CTRL : -+ MTK_PHY_LED0_BLINK_CTRL, blink); -+}; -+ -+static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) -+{ -+ struct mtk_socphy_shared *priv = phydev->shared->priv; -+ u32 polarities; -+ -+ if (led_num == 0) -+ polarities = ~(priv->boottrap); -+ else -+ polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; -+ -+ if (polarities & BIT(phydev->mdio.addr)) -+ return true; -+ -+ return false; -+} -+ -+static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) -+{ -+ struct pinctrl *pinctrl; -+ int index; -+ -+ /* Setup LED polarity according to bootstrap use of LED pins */ -+ for (index = 0; index < 2; ++index) -+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? -+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, -+ MTK_PHY_LED_ON_POLARITY, -+ mt7988_phy_led_get_polarity(phydev, index) ? -+ MTK_PHY_LED_ON_POLARITY : 0); -+ -+ /* Only now setup pinctrl to avoid bogus blinking */ -+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); -+ if (IS_ERR(pinctrl)) -+ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n"); -+ -+ return 0; -+} -+ -+static int mt7988_phy_probe_shared(struct phy_device *phydev) -+{ -+ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); -+ struct mtk_socphy_shared *shared = phydev->shared->priv; -+ struct regmap *regmap; -+ u32 reg; -+ int ret; -+ -+ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, -+ * LED_C and LED_D respectively. At the same time those pins are used to -+ * bootstrap configuration of the reference clock source (LED_A), -+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). -+ * In practise this is done using a LED and a resistor pulling the pin -+ * either to GND or to VIO. -+ * The detected value at boot time is accessible at run-time using the -+ * TPBANK0 register located in the gpio base of the pinctrl, in order -+ * to read it here it needs to be referenced by a phandle called -+ * 'mediatek,pio' in the MDIO bus hosting the PHY. -+ * The 4 bits in TPBANK0 are kept as package shared data and are used to -+ * set LED polarity for each of the LED0. -+ */ -+ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ -+ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); -+ if (ret) -+ return ret; -+ -+ shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); -+ -+ return 0; -+} -+ -+static void mt798x_phy_leds_state_init(struct phy_device *phydev) -+{ -+ int i; -+ -+ for (i = 0; i < 2; ++i) -+ mt798x_phy_led_hw_control_get(phydev, i, NULL); -+} -+ -+static int mt7988_phy_probe(struct phy_device *phydev) -+{ -+ struct mtk_socphy_shared *shared; -+ struct mtk_socphy_priv *priv; -+ int err; -+ -+ if (phydev->mdio.addr > 3) -+ return -EINVAL; -+ -+ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, -+ sizeof(struct mtk_socphy_shared)); -+ if (err) -+ return err; -+ -+ if (phy_package_probe_once(phydev)) { -+ err = mt7988_phy_probe_shared(phydev); -+ if (err) -+ return err; -+ } -+ -+ shared = phydev->shared->priv; -+ priv = &shared->priv[phydev->mdio.addr]; -+ -+ phydev->priv = priv; -+ -+ mt798x_phy_leds_state_init(phydev); -+ -+ err = mt7988_phy_fix_leds_polarities(phydev); -+ if (err) -+ return err; -+ -+ return mt798x_phy_calibration(phydev); -+} -+ -+static int mt7981_phy_probe(struct phy_device *phydev) -+{ -+ struct mtk_socphy_priv *priv; -+ -+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), -+ GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ phydev->priv = priv; -+ -+ mt798x_phy_leds_state_init(phydev); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ - static struct phy_driver mtk_socphy_driver[] = { - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -@@ -1080,11 +1487,16 @@ static struct phy_driver mtk_socphy_driv - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, -- .probe = mt798x_phy_calibration, -+ .probe = mt7981_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, -+ .led_blink_set = mt798x_phy_led_blink_set, -+ .led_brightness_set = mt798x_phy_led_brightness_set, -+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, -+ .led_hw_control_set = mt798x_phy_led_hw_control_set, -+ .led_hw_control_get = mt798x_phy_led_hw_control_get, - }, - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), -@@ -1092,11 +1504,16 @@ static struct phy_driver mtk_socphy_driv - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, -- .probe = mt798x_phy_calibration, -+ .probe = mt7988_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, - .write_page = mtk_socphy_write_page, -+ .led_blink_set = mt798x_phy_led_blink_set, -+ .led_brightness_set = mt798x_phy_led_brightness_set, -+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported, -+ .led_hw_control_set = mt798x_phy_led_hw_control_set, -+ .led_hw_control_get = mt798x_phy_led_hw_control_get, - }, - }; - diff --git a/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch deleted file mode 100644 index 76d8b0ef008fca..00000000000000 --- a/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch +++ /dev/null @@ -1,63 +0,0 @@ -From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 6 Apr 2023 23:36:50 +0100 -Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink - -MAC drivers using phylink expect SGMII in-band-status to be switched off -when attached to a PHY. Make sure this is the case also for mxl-gpy which -keeps SGMII in-band-status in case of SGMII interface mode is used. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++--- - 1 file changed, 16 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/mxl-gpy.c -+++ b/drivers/net/phy/mxl-gpy.c -@@ -371,8 +371,11 @@ static bool gpy_2500basex_chk(struct phy - - phydev->speed = SPEED_2500; - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -+ -+ if (!phydev->phylink) -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ - return true; - } - -@@ -396,6 +399,14 @@ static int gpy_config_aneg(struct phy_de - u32 adv; - int ret; - -+ /* Disable SGMII auto-negotiation if using phylink */ -+ if (phydev->phylink) { -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ if (ret < 0) -+ return ret; -+ } -+ - if (phydev->autoneg == AUTONEG_DISABLE) { - /* Configure half duplex with genphy_setup_forced, - * because genphy_c45_pma_setup_forced does not support. -@@ -486,6 +497,8 @@ static void gpy_update_interface(struct - switch (phydev->speed) { - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -+ if (phydev->phylink) -+ break; - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, - VSPEC1_SGMII_CTRL_ANEN, 0); - if (ret < 0) -@@ -497,7 +510,7 @@ static void gpy_update_interface(struct - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; -- if (gpy_sgmii_aneg_en(phydev)) -+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev)) - break; - /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed - * if ANEG is disabled (in 2500-BaseX mode). diff --git a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch deleted file mode 100644 index b4c07a4b1f0ad6..00000000000000 --- a/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 28 Feb 2023 17:53:37 +0000 -Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/Kconfig | 7 ++ - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++ - 3 files changed, 226 insertions(+) - create mode 100644 drivers/net/phy/mediatek-2p5ge.c - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -326,6 +326,13 @@ config MEDIATEK_GE_SOC_PHY - present in the SoCs efuse and will dynamically calibrate VCM - (common-mode voltage) during startup. - -+config MEDIATEK_2P5G_PHY -+ tristate "MediaTek 2.5G Ethernet PHY" -+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST -+ default NET_MEDIATEK_SOC -+ help -+ Supports the MediaTek 2.5G Ethernet PHY. -+ - config MICREL_PHY - tristate "Micrel PHYs" - depends on PTP_1588_CLOCK_OPTIONAL ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -79,6 +79,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell - obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o -+obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o - obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o diff --git a/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch b/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch deleted file mode 100644 index 5daa62b6b79230..00000000000000 --- a/target/linux/mediatek/patches-6.1/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch +++ /dev/null @@ -1,270 +0,0 @@ -From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001 -Message-ID: -From: Daniel Golle -Date: Wed, 24 Jan 2024 02:27:04 +0000 -Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK -To: Daniel Golle , - Qingfang Deng , - SkyLake Huang , - Andrew Lunn , - Heiner Kallweit , - Russell King , - David S. Miller , - Eric Dumazet , - Jakub Kicinski , - Paolo Abeni , - Matthias Brugger , - AngeloGioacchino Del Regno , - netdev@vger.kernel.org, - linux-kernel@vger.kernel.org, - linux-arm-kernel@lists.infradead.org, - linux-mediatek@lists.infradead.org - -Sync initialization and calibration routines with MediaTek's reference -driver. Improves compliance and resolves link stability issues with -CH340 IoT devices connected to MT798x built-in PHYs. - -Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs") -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++-------------- - 1 file changed, 81 insertions(+), 66 deletions(-) - ---- a/drivers/net/phy/mediatek-ge-soc.c -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -491,7 +491,7 @@ static int tx_r50_fill_result(struct phy - u16 reg, val; - - if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) -- bias = -2; -+ bias = -1; - - val = clamp_val(bias + tx_r50_cal_val, 0, 63); - -@@ -707,6 +707,11 @@ restore: - static void mt798x_phy_common_finetune(struct phy_device *phydev) - { - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ -+ __phy_write(phydev, 0x11, 0xc71); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ - /* EnabRandUpdTrig = 1 */ - __phy_write(phydev, 0x11, 0x2f00); - __phy_write(phydev, 0x12, 0xe); -@@ -717,15 +722,56 @@ static void mt798x_phy_common_finetune(s - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x83aa); - -- /* TrFreeze = 0 */ -+ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ -+ __phy_write(phydev, 0x11, 0x240); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9680); -+ -+ /* TrFreeze = 0 (mt7988 default) */ - __phy_write(phydev, 0x11, 0x0); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9686); - -+ /* SSTrKp100 = 5 */ -+ /* SSTrKf100 = 6 */ -+ /* SSTrKp1000Mas = 5 */ -+ /* SSTrKf1000Mas = 6 */ - /* SSTrKp1000Slv = 5 */ -+ /* SSTrKf1000Slv = 6 */ - __phy_write(phydev, 0x11, 0xbaef); - __phy_write(phydev, 0x12, 0x2e); - __phy_write(phydev, 0x10, 0x968c); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt7981_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[8] = { 0x01ce, 0x01c1, -+ 0x020f, 0x0202, -+ 0x03d0, 0x03c0, -+ 0x0013, 0x0005 }; -+ int i, k; -+ -+ /* 100M eye finetune: -+ * Keep middle level of TX MLT3 shapper as default. -+ * Only change TX MLT3 overshoot level here. -+ */ -+ for (k = 0, i = 1; i < 12; i++) { -+ if (i % 3 == 0) -+ continue; -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); -+ } -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* ResetSyncOffset = 6 */ -+ __phy_write(phydev, 0x11, 0x600); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate = 1 */ -+ __phy_write(phydev, 0x11, 0x4c2a); -+ __phy_write(phydev, 0x12, 0x3e); -+ __phy_write(phydev, 0x10, 0x8fa4); - - /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, - * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 -@@ -740,7 +786,7 @@ static void mt798x_phy_common_finetune(s - __phy_write(phydev, 0x10, 0x8ec0); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); - -- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ -+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, - MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, - BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); -@@ -773,48 +819,6 @@ static void mt798x_phy_common_finetune(s - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); - } - --static void mt7981_phy_finetune(struct phy_device *phydev) --{ -- u16 val[8] = { 0x01ce, 0x01c1, -- 0x020f, 0x0202, -- 0x03d0, 0x03c0, -- 0x0013, 0x0005 }; -- int i, k; -- -- /* 100M eye finetune: -- * Keep middle level of TX MLT3 shapper as default. -- * Only change TX MLT3 overshoot level here. -- */ -- for (k = 0, i = 1; i < 12; i++) { -- if (i % 3 == 0) -- continue; -- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); -- } -- -- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ -- __phy_write(phydev, 0x11, 0xc71); -- __phy_write(phydev, 0x12, 0xc); -- __phy_write(phydev, 0x10, 0x8fae); -- -- /* ResetSyncOffset = 6 */ -- __phy_write(phydev, 0x11, 0x600); -- __phy_write(phydev, 0x12, 0x0); -- __phy_write(phydev, 0x10, 0x8fc0); -- -- /* VgaDecRate = 1 */ -- __phy_write(phydev, 0x11, 0x4c2a); -- __phy_write(phydev, 0x12, 0x3e); -- __phy_write(phydev, 0x10, 0x8fa4); -- -- /* FfeUpdGainForce = 4 */ -- __phy_write(phydev, 0x11, 0x240); -- __phy_write(phydev, 0x12, 0x0); -- __phy_write(phydev, 0x10, 0x9680); -- -- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); --} -- - static void mt7988_phy_finetune(struct phy_device *phydev) - { - u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, -@@ -829,17 +833,7 @@ static void mt7988_phy_finetune(struct p - /* TCT finetune */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); - -- /* Disable TX power saving */ -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, -- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); -- - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -- -- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ -- __phy_write(phydev, 0x11, 0x671); -- __phy_write(phydev, 0x12, 0xc); -- __phy_write(phydev, 0x10, 0x8fae); -- - /* ResetSyncOffset = 5 */ - __phy_write(phydev, 0x11, 0x500); - __phy_write(phydev, 0x12, 0x0); -@@ -847,13 +841,27 @@ static void mt7988_phy_finetune(struct p - - /* VgaDecRate is 1 at default on mt7988 */ - -- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, -+ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 -+ */ -+ __phy_write(phydev, 0x11, 0xb90a); -+ __phy_write(phydev, 0x12, 0x6f); -+ __phy_write(phydev, 0x10, 0x8f82); -+ -+ /* RemAckCntLimitCtrl = 1 */ -+ __phy_write(phydev, 0x11, 0xfbba); -+ __phy_write(phydev, 0x12, 0xc3); -+ __phy_write(phydev, 0x10, 0x87f8); - -- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); -- /* TxClkOffset = 2 */ -- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, -- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, -+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, -+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); -+ -+ /* rg_tr_lpf_cnt_val = 1023 */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); - } - - static void mt798x_phy_eee(struct phy_device *phydev) -@@ -886,11 +894,11 @@ static void mt798x_phy_eee(struct phy_de - MTK_PHY_LPI_SLV_SEND_TX_EN, - FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); - -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, -- MTK_PHY_LPI_SEND_LOC_TIMER_MASK | -- MTK_PHY_LPI_TXPCS_LOC_RCV, -- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); -+ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, -+ MTK_PHY_LPI_TXPCS_LOC_RCV); - -+ /* This also fixes some IoT issues, such as CH340 */ - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, - MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, - FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | -@@ -924,7 +932,7 @@ static void mt798x_phy_eee(struct phy_de - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x9690); - -- /* REG_EEE_st2TrKf1000 = 3 */ -+ /* REG_EEE_st2TrKf1000 = 2 */ - __phy_write(phydev, 0x11, 0x114f); - __phy_write(phydev, 0x12, 0x2); - __phy_write(phydev, 0x10, 0x969a); -@@ -949,7 +957,7 @@ static void mt798x_phy_eee(struct phy_de - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96b8); - -- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ -+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ - __phy_write(phydev, 0x11, 0x1463); - __phy_write(phydev, 0x12, 0x0); - __phy_write(phydev, 0x10, 0x96ca); -@@ -1461,6 +1469,13 @@ static int mt7988_phy_probe(struct phy_d - if (err) - return err; - -+ /* Disable TX power saving at probing to: -+ * 1. Meet common mode compliance test criteria -+ * 2. Make sure that TX-VCM calibration works fine -+ */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, -+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); -+ - return mt798x_phy_calibration(phydev); - } - diff --git a/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch b/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch deleted file mode 100644 index 51f2a197e9e4b2..00000000000000 --- a/target/linux/mediatek/patches-6.1/735-net-phy-add-Airoha-EN8801SC-PHY.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sat, 23 Mar 2024 20:21:14 +0100 -Subject: [PATCH] net: phy: add Airoha EN8801SC PHY - -Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a -modified version of MTK SDK driver. - -Signed-off-by: Robert Marko ---- - drivers/net/phy/Kconfig | 5 +++++ - drivers/net/phy/Makefile | 1 + - 2 files changed, 6 insertions(+) - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -143,6 +143,11 @@ endif # RTL8366_SMI - - comment "MII PHY device drivers" - -+config AIROHA_EN8801SC_PHY -+ tristate "Airoha EN8801SC Gigabit PHY" -+ help -+ Currently supports the Airoha EN8801SC PHY. -+ - config AIR_EN8811H_PHY - tristate "Airoha EN8811H 2.5 Gigabit PHY" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -47,6 +47,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m) - - obj-$(CONFIG_ADIN_PHY) += adin.o - obj-$(CONFIG_ADIN1100_PHY) += adin1100.o -+obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o - obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o - obj-$(CONFIG_AMD_PHY) += amd.o - obj-$(CONFIG_AQUANTIA_PHY) += aquantia/ diff --git a/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch deleted file mode 100644 index 0c73d520b46295..00000000000000 --- a/target/linux/mediatek/patches-6.1/804-v6.2-pwm-add-mt7986-support.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -329,6 +329,12 @@ static const struct pwm_mediatek_of_data - .has_ck_26m_sel = true, - }; - -+static const struct pwm_mediatek_of_data mt7986_pwm_data = { -+ .num_pwms = 2, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = true, -+}; -+ - static const struct pwm_mediatek_of_data mt8516_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = false, -@@ -342,6 +348,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, - { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, -+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, - { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch b/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch deleted file mode 100644 index 72feecadb1f1f6..00000000000000 --- a/target/linux/mediatek/patches-6.1/805-v6.5-pwm-mediatek-Add-support-for-MT7981.patch +++ /dev/null @@ -1,147 +0,0 @@ -From 967da67a745fb73fd0fc7aa61fd197b76fceb273 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 21 Apr 2023 00:23:21 +0100 -Subject: [PATCH] pwm: mediatek: Add support for MT7981 - -The PWM unit on MT7981 uses different register offsets than previous -MediaTek PWM units. Add support for these new offsets and add support -for PWM on MT7981 which has 3 PWM channels, one of them is typically -used for a temperature controlled fan. -While at it, also reorder pwm_mediatek_of_data entries to restore -alphabetic order. - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Matthias Brugger -Signed-off-by: Thierry Reding ---- - drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++-------- - 1 file changed, 31 insertions(+), 8 deletions(-) - ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data { - unsigned int num_pwms; - bool pwm45_fixup; - bool has_ck_26m_sel; -+ const unsigned int *reg_offset; - }; - - /** -@@ -59,10 +60,14 @@ struct pwm_mediatek_chip { - const struct pwm_mediatek_of_data *soc; - }; - --static const unsigned int pwm_mediatek_reg_offset[] = { -+static const unsigned int mtk_pwm_reg_offset_v1[] = { - 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 - }; - -+static const unsigned int mtk_pwm_reg_offset_v2[] = { -+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 -+}; -+ - static inline struct pwm_mediatek_chip * - to_pwm_mediatek_chip(struct pwm_chip *chip) - { -@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s - unsigned int num, unsigned int offset, - u32 value) - { -- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); -+ writel(value, chip->regs + chip->soc->reg_offset[num] + offset); - } - - static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, -@@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data - .num_pwms = 8, - .pwm45_fixup = false, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt6795_pwm_data = { - .num_pwms = 7, - .pwm45_fixup = false, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7622_pwm_data = { - .num_pwms = 6, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7623_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = true, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7628_pwm_data = { - .num_pwms = 4, - .pwm45_fixup = true, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt7629_pwm_data = { - .num_pwms = 1, - .pwm45_fixup = false, - .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - --static const struct pwm_mediatek_of_data mt8183_pwm_data = { -- .num_pwms = 4, -+static const struct pwm_mediatek_of_data mt7981_pwm_data = { -+ .num_pwms = 3, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v2, - }; - --static const struct pwm_mediatek_of_data mt8365_pwm_data = { -- .num_pwms = 3, -+static const struct pwm_mediatek_of_data mt7986_pwm_data = { -+ .num_pwms = 2, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - --static const struct pwm_mediatek_of_data mt7986_pwm_data = { -- .num_pwms = 2, -+static const struct pwm_mediatek_of_data mt8183_pwm_data = { -+ .num_pwms = 4, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, -+}; -+ -+static const struct pwm_mediatek_of_data mt8365_pwm_data = { -+ .num_pwms = 3, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct pwm_mediatek_of_data mt8516_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = false, - .has_ck_26m_sel = true, -+ .reg_offset = mtk_pwm_reg_offset_v1, - }; - - static const struct of_device_id pwm_mediatek_of_match[] = { -@@ -348,6 +370,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, - { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, -+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, - { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, diff --git a/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch b/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch deleted file mode 100644 index 00543a1bb19027..00000000000000 --- a/target/linux/mediatek/patches-6.1/806-v6.9-pwm-mediatek-add-support-for-MT7988.patch +++ /dev/null @@ -1,44 +0,0 @@ -From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 14 Feb 2024 15:04:54 +0100 -Subject: [PATCH] pwm: mediatek: add support for MT7988 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MT7988 uses new registers layout just like MT7981 but it supports 8 PWM -interfaces. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com -Signed-off-by: Uwe Kleine-König ---- - drivers/pwm/pwm-mediatek.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -342,6 +342,13 @@ static const struct pwm_mediatek_of_data - .reg_offset = mtk_pwm_reg_offset_v1, - }; - -+static const struct pwm_mediatek_of_data mt7988_pwm_data = { -+ .num_pwms = 8, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = false, -+ .reg_offset = mtk_pwm_reg_offset_v2, -+}; -+ - static const struct pwm_mediatek_of_data mt8183_pwm_data = { - .num_pwms = 4, - .pwm45_fixup = false, -@@ -372,6 +379,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, - { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, - { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, -+ { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, - { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch b/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch deleted file mode 100644 index f130fdbc566909..00000000000000 --- a/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch +++ /dev/null @@ -1,129 +0,0 @@ -From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:01:12 +0100 -Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias - functions - -Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo -and mtk_pinconf_bias_get_combo, and make the functions able to support -almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. - -This patch enables pinctrl_moore to support these functions. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++---- - 1 file changed, 42 insertions(+), 7 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-moore.c -+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c -@@ -8,6 +8,7 @@ - * - */ - -+#include - #include - #include "pinctrl-moore.h" - -@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr - { - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); - u32 param = pinconf_to_config_param(*config); -- int val, val2, err, reg, ret = 1; -+ int val, val2, err, pullup, reg, ret = 1; - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -- if (hw->soc->bias_disable_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE) -+ return -EINVAL; -+ } else if (hw->soc->bias_disable_get) { - err = hw->soc->bias_disable_get(hw, desc, &ret); - if (err) - return err; -@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_UP: -- if (hw->soc->bias_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) -+ return -EINVAL; -+ if (!pullup) -+ return -EINVAL; -+ } else if (hw->soc->bias_get) { - err = hw->soc->bias_get(hw, desc, 1, &ret); - if (err) - return err; -@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- if (hw->soc->bias_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) -+ return -EINVAL; -+ if (pullup) -+ return -EINVAL; -+ } else if (hw->soc->bias_get) { - err = hw->soc->bias_get(hw, desc, 0, &ret); - if (err) - return err; -@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -- if (hw->soc->bias_disable_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_disable_set) { - err = hw->soc->bias_disable_set(hw, desc); - if (err) - return err; -@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_UP: -- if (hw->soc->bias_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 1, arg); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_set) { - err = hw->soc->bias_set(hw, desc, 1); - if (err) - return err; -@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- if (hw->soc->bias_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 0, arg); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_set) { - err = hw->soc->bias_set(hw, desc, 0); - if (err) - return err; diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch b/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch deleted file mode 100644 index 694b73a2b1c3b0..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.3-01-thermal-drivers-mtk_thermal-Fix-kernel-doc-function-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From f167da186acf90847e1a6d3716e253825a6218ec Mon Sep 17 00:00:00 2001 -From: Randy Dunlap -Date: Thu, 12 Jan 2023 22:44:49 -0800 -Subject: [PATCH 01/42] thermal/drivers/mtk_thermal: Fix kernel-doc function - name - -Use the correct function name in a kernel-doc comment to prevent -a warning: - -drivers/thermal/mtk_thermal.c:562: warning: expecting prototype for raw_to_mcelsius(). Prototype was for raw_to_mcelsius_v1() instead - -Signed-off-by: Randy Dunlap -Cc: "Rafael J. Wysocki" -Cc: Daniel Lezcano -Cc: Amit Kucheria -Cc: Zhang Rui -Cc: Matthias Brugger -Cc: linux-pm@vger.kernel.org -Cc: linux-arm-kernel@lists.infradead.org -Cc: linux-mediatek@lists.infradead.org -Link: https://lore.kernel.org/r/20230113064449.15061-1-rdunlap@infradead.org -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/mtk_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -550,7 +550,7 @@ static const struct mtk_thermal_data mt8 - }; - - /** -- * raw_to_mcelsius - convert a raw ADC value to mcelsius -+ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius - * @mt: The thermal controller - * @sensno: sensor number - * @raw: raw ADC value diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch b/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch deleted file mode 100644 index aaed9d7e90c34c..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.3-02-thermal-drivers-mtk_thermal-Use-devm_platform_get_an.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 255509232417ee71fd606cb957d44cf6544f0c43 Mon Sep 17 00:00:00 2001 -From: ye xingchen -Date: Wed, 18 Jan 2023 16:37:47 +0800 -Subject: [PATCH 02/42] thermal/drivers/mtk_thermal: Use - devm_platform_get_and_ioremap_resource() - -Convert platform_get_resource(), devm_ioremap_resource() to a single -call to devm_platform_get_and_ioremap_resource(), as this is exactly -what this function does. - -Signed-off-by: ye xingchen -Link: https://lore.kernel.org/r/202301181637472073620@zte.com.cn -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/mtk_thermal.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -990,7 +990,6 @@ static int mtk_thermal_probe(struct plat - int ret, i, ctrl_id; - struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; - struct mtk_thermal *mt; -- struct resource *res; - u64 auxadc_phys_base, apmixed_phys_base; - struct thermal_zone_device *tzdev; - void __iomem *apmixed_base, *auxadc_base; -@@ -1009,8 +1008,7 @@ static int mtk_thermal_probe(struct plat - if (IS_ERR(mt->clk_auxadc)) - return PTR_ERR(mt->clk_auxadc); - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); -+ mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(mt->thermal_base)) - return PTR_ERR(mt->thermal_base); - diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch b/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch deleted file mode 100644 index 215b0fd7dec997..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.3-03-thermal-drivers-mtk-Use-function-pointer-for-raw_to_.patch +++ /dev/null @@ -1,60 +0,0 @@ -From ca86dbd309ba03bef38ae91f037e2030bb671ab7 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 18 Jan 2023 15:40:39 +0000 -Subject: [PATCH 03/42] thermal/drivers/mtk: Use function pointer for - raw_to_mcelsius - -Instead of having if-else logic selecting either raw_to_mcelsius_v1 or -raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function -pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the -probe function. - -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Golle -Reviewed-by: Matthias Brugger -Link: https://lore.kernel.org/r/69c17529e8418da3eec703dde31e1b01e5b0f7e8.1674055882.git.daniel@makrotopia.org -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/mtk_thermal.c | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -292,6 +292,8 @@ struct mtk_thermal { - - const struct mtk_thermal_data *conf; - struct mtk_thermal_bank banks[MAX_NUM_ZONES]; -+ -+ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); - }; - - /* MT8183 thermal sensor data */ -@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature( - for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { - raw = readl(mt->thermal_base + conf->msr[i]); - -- if (mt->conf->version == MTK_THERMAL_V1) { -- temp = raw_to_mcelsius_v1( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- } else { -- temp = raw_to_mcelsius_v2( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- } -+ temp = mt->raw_to_mcelsius( -+ mt, conf->bank_data[bank->id].sensors[i], raw); -+ - - /* - * The first read of a sensor often contains very high bogus -@@ -1073,6 +1071,11 @@ static int mtk_thermal_probe(struct plat - mtk_thermal_release_periodic_ts(mt, auxadc_base); - } - -+ if (mt->conf->version == MTK_THERMAL_V1) -+ mt->raw_to_mcelsius = raw_to_mcelsius_v1; -+ else -+ mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) - for (i = 0; i < mt->conf->num_banks; i++) - mtk_thermal_init_bank(mt, i, apmixed_phys_base, diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch b/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch deleted file mode 100644 index ef2006775a34d4..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.3-04-thermal-drivers-mtk-Add-support-for-MT7986-and-MT798.patch +++ /dev/null @@ -1,236 +0,0 @@ -From aec1d89dccc7cba04fdb3e52dfda328f3302ba17 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 18 Jan 2023 15:40:58 +0000 -Subject: [PATCH 04/42] thermal/drivers/mtk: Add support for MT7986 and MT7981 - -Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. -Brings code to assign values from efuse as well as new function to -convert raw temperature to millidegree celsius, as found in MediaTek's -SDK sources (but cleaned up and de-duplicated) - -[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/2d341fc45266217249586eb4bd3be3ac4ca83a12.1674055882.git.daniel@makrotopia.org -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/mtk_thermal.c | 128 ++++++++++++++++++++++++++++++++-- - 1 file changed, 124 insertions(+), 4 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -150,6 +150,20 @@ - #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) - #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) - -+/* -+ * Layout of the fuses providing the calibration data -+ * These macros can be used for MT7981 and MT7986. -+ */ -+#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) -+#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) -+#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) -+#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) -+#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) -+#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) -+#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) -+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) -+#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) -+ - enum { - VTS1, - VTS2, -@@ -163,6 +177,7 @@ enum { - enum mtk_thermal_version { - MTK_THERMAL_V1 = 1, - MTK_THERMAL_V2, -+ MTK_THERMAL_V3, - }; - - /* MT2701 thermal sensors */ -@@ -245,6 +260,27 @@ enum mtk_thermal_version { - /* The calibration coefficient of sensor */ - #define MT8183_CALIBRATION 153 - -+/* AUXADC channel 11 is used for the temperature sensors */ -+#define MT7986_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT7986 */ -+#define MT7986_NUM_SENSORS 1 -+ -+/* The number of banks in the MT7986 */ -+#define MT7986_NUM_ZONES 1 -+ -+/* The number of sensing points per bank */ -+#define MT7986_NUM_SENSORS_PER_ZONE 1 -+ -+/* MT7986 thermal sensors */ -+#define MT7986_TS1 0 -+ -+/* The number of controller in the MT7986 */ -+#define MT7986_NUM_CONTROLLER 1 -+ -+/* The calibration coefficient of sensor */ -+#define MT7986_CALIBRATION 165 -+ - struct mtk_thermal; - - struct thermal_bank_cfg { -@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762 - static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; - static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; - -+/* MT7986 thermal sensor data */ -+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; -+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; -+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; -+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; -+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; -+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; -+ - /* - * The MT8173 thermal controller has four banks. Each bank can read up to - * four temperature sensors simultaneously. The MT8173 has a total of 5 -@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8 - .version = MTK_THERMAL_V1, - }; - -+/* -+ * MT7986 uses AUXADC Channel 11 for raw data access. -+ */ -+static const struct mtk_thermal_data mt7986_thermal_data = { -+ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT7986_NUM_ZONES, -+ .num_sensors = MT7986_NUM_SENSORS, -+ .vts_index = mt7986_vts_index, -+ .cali_val = MT7986_CALIBRATION, -+ .num_controller = MT7986_NUM_CONTROLLER, -+ .controller_offset = mt7986_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 1, -+ .sensors = mt7986_bank_data, -+ }, -+ }, -+ .msr = mt7986_msr, -+ .adcpnp = mt7986_adcpnp, -+ .sensor_mux_values = mt7986_mux_values, -+ .version = MTK_THERMAL_V3, -+}; -+ - /** - * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius - * @mt: The thermal controller -@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk - return (format_2 - tmp) * 100; - } - -+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) -+{ -+ s32 tmp; -+ -+ if (raw == 0) -+ return 0; -+ -+ raw &= 0xfff; -+ tmp = 100000 * 15 / 16 * 10000; -+ tmp /= 4096 - 512 + mt->adc_ge; -+ tmp /= 1490; -+ tmp *= raw - mt->vts[sensno] - 2900; -+ -+ return mt->degc_cali * 500 - tmp; -+} -+ - /** - * mtk_thermal_get_bank - get bank - * @bank: The bank -@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2( - return 0; - } - -+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) -+{ -+ if (!CALIB_BUF1_VALID_V3(buf[1])) -+ return -EINVAL; -+ -+ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); -+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); -+ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); -+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); -+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); -+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); -+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); -+ -+ if (CALIB_BUF1_ID_V3(buf[1]) == 0) -+ mt->o_slope = 0; -+ -+ return 0; -+} -+ - static int mtk_thermal_get_calibration_data(struct device *dev, - struct mtk_thermal *mt) - { -@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d - - /* Start with default values */ - mt->adc_ge = 512; -+ mt->adc_oe = 512; - for (i = 0; i < mt->conf->num_sensors; i++) - mt->vts[i] = 260; - mt->degc_cali = 40; -@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d - goto out; - } - -- if (mt->conf->version == MTK_THERMAL_V1) -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: - ret = mtk_thermal_extract_efuse_v1(mt, buf); -- else -+ break; -+ case MTK_THERMAL_V2: - ret = mtk_thermal_extract_efuse_v2(mt, buf); -+ break; -+ case MTK_THERMAL_V3: -+ ret = mtk_thermal_extract_efuse_v3(mt, buf); -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } - - if (ret) { - dev_info(dev, "Device not calibrated, using default calibration values\n"); -@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the - .data = (void *)&mt7622_thermal_data, - }, - { -+ .compatible = "mediatek,mt7986-thermal", -+ .data = (void *)&mt7986_thermal_data, -+ }, -+ { - .compatible = "mediatek,mt8183-thermal", - .data = (void *)&mt8183_thermal_data, - }, { -@@ -1066,15 +1184,17 @@ static int mtk_thermal_probe(struct plat - goto err_disable_clk_auxadc; - } - -- if (mt->conf->version == MTK_THERMAL_V2) { -+ if (mt->conf->version != MTK_THERMAL_V1) { - mtk_thermal_turn_on_buffer(apmixed_base); - mtk_thermal_release_periodic_ts(mt, auxadc_base); - } - - if (mt->conf->version == MTK_THERMAL_V1) - mt->raw_to_mcelsius = raw_to_mcelsius_v1; -- else -+ else if (mt->conf->version == MTK_THERMAL_V2) - mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ else -+ mt->raw_to_mcelsius = raw_to_mcelsius_v3; - - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) - for (i = 0; i < mt->conf->num_banks; i++) diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch b/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch deleted file mode 100644 index e102a338cdc344..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.3-05-thermal-drivers-mediatek-Relocate-driver-to-mediatek.patch +++ /dev/null @@ -1,2602 +0,0 @@ -From 5e3aac197a74914ccec2732a89c29d960730d28f Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Thu, 9 Feb 2023 11:56:23 +0100 -Subject: [PATCH 05/42] thermal/drivers/mediatek: Relocate driver to mediatek - folder - -Add MediaTek proprietary folder to upstream more thermal zone and cooler -drivers, relocate the original thermal controller driver to it, and rename it -as "auxadc_thermal.c" to show its purpose more clearly. - -Signed-off-by: Balsam CHIHI -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230209105628.50294-2-bchihi@baylibre.com -Signed-off-by: Daniel Lezcano -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/Kconfig | 14 ++++--------- - drivers/thermal/Makefile | 2 +- - drivers/thermal/mediatek/Kconfig | 21 +++++++++++++++++++ - drivers/thermal/mediatek/Makefile | 1 + - .../auxadc_thermal.c} | 2 +- - 5 files changed, 28 insertions(+), 12 deletions(-) - create mode 100644 drivers/thermal/mediatek/Kconfig - create mode 100644 drivers/thermal/mediatek/Makefile - rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%) - ---- a/drivers/thermal/Kconfig -+++ b/drivers/thermal/Kconfig -@@ -412,16 +412,10 @@ config DA9062_THERMAL - zone. - Compatible with the DA9062 and DA9061 PMICs. - --config MTK_THERMAL -- tristate "Temperature sensor driver for mediatek SoCs" -- depends on ARCH_MEDIATEK || COMPILE_TEST -- depends on HAS_IOMEM -- depends on NVMEM || NVMEM=n -- depends on RESET_CONTROLLER -- default y -- help -- Enable this option if you want to have support for thermal management -- controller present in Mediatek SoCs -+menu "Mediatek thermal drivers" -+depends on ARCH_MEDIATEK || COMPILE_TEST -+source "drivers/thermal/mediatek/Kconfig" -+endmenu - - config AMLOGIC_THERMAL - tristate "Amlogic Thermal Support" ---- a/drivers/thermal/Makefile -+++ b/drivers/thermal/Makefile -@@ -55,7 +55,7 @@ obj-y += st/ - obj-y += qcom/ - obj-y += tegra/ - obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o --obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o -+obj-y += mediatek/ - obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o - obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o - obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o ---- /dev/null -+++ b/drivers/thermal/mediatek/Kconfig -@@ -0,0 +1,21 @@ -+config MTK_THERMAL -+ tristate "MediaTek thermal drivers" -+ depends on THERMAL_OF -+ help -+ This is the option for MediaTek thermal software solutions. -+ Please enable corresponding options to get temperature -+ information from thermal sensors or turn on throttle -+ mechaisms for thermal mitigation. -+ -+if MTK_THERMAL -+ -+config MTK_SOC_THERMAL -+ tristate "AUXADC temperature sensor driver for MediaTek SoCs" -+ depends on HAS_IOMEM -+ help -+ Enable this option if you want to get SoC temperature -+ information for MediaTek platforms. -+ This driver configures thermal controllers to collect -+ temperature via AUXADC interface. -+ -+endif ---- /dev/null -+++ b/drivers/thermal/mediatek/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o ---- a/drivers/thermal/mtk_thermal.c -+++ /dev/null -@@ -1,1254 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-only --/* -- * Copyright (c) 2015 MediaTek Inc. -- * Author: Hanyi Wu -- * Sascha Hauer -- * Dawei Chien -- * Louis Yu -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include -- --#include "thermal_hwmon.h" -- --/* AUXADC Registers */ --#define AUXADC_CON1_SET_V 0x008 --#define AUXADC_CON1_CLR_V 0x00c --#define AUXADC_CON2_V 0x010 --#define AUXADC_DATA(channel) (0x14 + (channel) * 4) -- --#define APMIXED_SYS_TS_CON1 0x604 -- --/* Thermal Controller Registers */ --#define TEMP_MONCTL0 0x000 --#define TEMP_MONCTL1 0x004 --#define TEMP_MONCTL2 0x008 --#define TEMP_MONIDET0 0x014 --#define TEMP_MONIDET1 0x018 --#define TEMP_MSRCTL0 0x038 --#define TEMP_MSRCTL1 0x03c --#define TEMP_AHBPOLL 0x040 --#define TEMP_AHBTO 0x044 --#define TEMP_ADCPNP0 0x048 --#define TEMP_ADCPNP1 0x04c --#define TEMP_ADCPNP2 0x050 --#define TEMP_ADCPNP3 0x0b4 -- --#define TEMP_ADCMUX 0x054 --#define TEMP_ADCEN 0x060 --#define TEMP_PNPMUXADDR 0x064 --#define TEMP_ADCMUXADDR 0x068 --#define TEMP_ADCENADDR 0x074 --#define TEMP_ADCVALIDADDR 0x078 --#define TEMP_ADCVOLTADDR 0x07c --#define TEMP_RDCTRL 0x080 --#define TEMP_ADCVALIDMASK 0x084 --#define TEMP_ADCVOLTAGESHIFT 0x088 --#define TEMP_ADCWRITECTRL 0x08c --#define TEMP_MSR0 0x090 --#define TEMP_MSR1 0x094 --#define TEMP_MSR2 0x098 --#define TEMP_MSR3 0x0B8 -- --#define TEMP_SPARE0 0x0f0 -- --#define TEMP_ADCPNP0_1 0x148 --#define TEMP_ADCPNP1_1 0x14c --#define TEMP_ADCPNP2_1 0x150 --#define TEMP_MSR0_1 0x190 --#define TEMP_MSR1_1 0x194 --#define TEMP_MSR2_1 0x198 --#define TEMP_ADCPNP3_1 0x1b4 --#define TEMP_MSR3_1 0x1B8 -- --#define PTPCORESEL 0x400 -- --#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) -- --#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) --#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) -- --#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) -- --#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) --#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) -- --#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) --#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) -- --/* MT8173 thermal sensors */ --#define MT8173_TS1 0 --#define MT8173_TS2 1 --#define MT8173_TS3 2 --#define MT8173_TS4 3 --#define MT8173_TSABB 4 -- --/* AUXADC channel 11 is used for the temperature sensors */ --#define MT8173_TEMP_AUXADC_CHANNEL 11 -- --/* The total number of temperature sensors in the MT8173 */ --#define MT8173_NUM_SENSORS 5 -- --/* The number of banks in the MT8173 */ --#define MT8173_NUM_ZONES 4 -- --/* The number of sensing points per bank */ --#define MT8173_NUM_SENSORS_PER_ZONE 4 -- --/* The number of controller in the MT8173 */ --#define MT8173_NUM_CONTROLLER 1 -- --/* The calibration coefficient of sensor */ --#define MT8173_CALIBRATION 165 -- --/* -- * Layout of the fuses providing the calibration data -- * These macros could be used for MT8183, MT8173, MT2701, and MT2712. -- * MT8183 has 6 sensors and needs 6 VTS calibration data. -- * MT8173 has 5 sensors and needs 5 VTS calibration data. -- * MT2701 has 3 sensors and needs 3 VTS calibration data. -- * MT2712 has 4 sensors and needs 4 VTS calibration data. -- */ --#define CALIB_BUF0_VALID_V1 BIT(0) --#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff) --#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff) --#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff) --#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff) --#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff) --#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff) --#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff) --#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f) --#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f) --#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1) --#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1) -- --/* -- * Layout of the fuses providing the calibration data -- * These macros could be used for MT7622. -- */ --#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff) --#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff) --#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f) --#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f) --#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff) --#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff) --#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff) --#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) --#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) -- --/* -- * Layout of the fuses providing the calibration data -- * These macros can be used for MT7981 and MT7986. -- */ --#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) --#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) --#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) --#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) --#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) --#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) --#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) --#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) --#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) -- --enum { -- VTS1, -- VTS2, -- VTS3, -- VTS4, -- VTS5, -- VTSABB, -- MAX_NUM_VTS, --}; -- --enum mtk_thermal_version { -- MTK_THERMAL_V1 = 1, -- MTK_THERMAL_V2, -- MTK_THERMAL_V3, --}; -- --/* MT2701 thermal sensors */ --#define MT2701_TS1 0 --#define MT2701_TS2 1 --#define MT2701_TSABB 2 -- --/* AUXADC channel 11 is used for the temperature sensors */ --#define MT2701_TEMP_AUXADC_CHANNEL 11 -- --/* The total number of temperature sensors in the MT2701 */ --#define MT2701_NUM_SENSORS 3 -- --/* The number of sensing points per bank */ --#define MT2701_NUM_SENSORS_PER_ZONE 3 -- --/* The number of controller in the MT2701 */ --#define MT2701_NUM_CONTROLLER 1 -- --/* The calibration coefficient of sensor */ --#define MT2701_CALIBRATION 165 -- --/* MT2712 thermal sensors */ --#define MT2712_TS1 0 --#define MT2712_TS2 1 --#define MT2712_TS3 2 --#define MT2712_TS4 3 -- --/* AUXADC channel 11 is used for the temperature sensors */ --#define MT2712_TEMP_AUXADC_CHANNEL 11 -- --/* The total number of temperature sensors in the MT2712 */ --#define MT2712_NUM_SENSORS 4 -- --/* The number of sensing points per bank */ --#define MT2712_NUM_SENSORS_PER_ZONE 4 -- --/* The number of controller in the MT2712 */ --#define MT2712_NUM_CONTROLLER 1 -- --/* The calibration coefficient of sensor */ --#define MT2712_CALIBRATION 165 -- --#define MT7622_TEMP_AUXADC_CHANNEL 11 --#define MT7622_NUM_SENSORS 1 --#define MT7622_NUM_ZONES 1 --#define MT7622_NUM_SENSORS_PER_ZONE 1 --#define MT7622_TS1 0 --#define MT7622_NUM_CONTROLLER 1 -- --/* The maximum number of banks */ --#define MAX_NUM_ZONES 8 -- --/* The calibration coefficient of sensor */ --#define MT7622_CALIBRATION 165 -- --/* MT8183 thermal sensors */ --#define MT8183_TS1 0 --#define MT8183_TS2 1 --#define MT8183_TS3 2 --#define MT8183_TS4 3 --#define MT8183_TS5 4 --#define MT8183_TSABB 5 -- --/* AUXADC channel is used for the temperature sensors */ --#define MT8183_TEMP_AUXADC_CHANNEL 11 -- --/* The total number of temperature sensors in the MT8183 */ --#define MT8183_NUM_SENSORS 6 -- --/* The number of banks in the MT8183 */ --#define MT8183_NUM_ZONES 1 -- --/* The number of sensing points per bank */ --#define MT8183_NUM_SENSORS_PER_ZONE 6 -- --/* The number of controller in the MT8183 */ --#define MT8183_NUM_CONTROLLER 2 -- --/* The calibration coefficient of sensor */ --#define MT8183_CALIBRATION 153 -- --/* AUXADC channel 11 is used for the temperature sensors */ --#define MT7986_TEMP_AUXADC_CHANNEL 11 -- --/* The total number of temperature sensors in the MT7986 */ --#define MT7986_NUM_SENSORS 1 -- --/* The number of banks in the MT7986 */ --#define MT7986_NUM_ZONES 1 -- --/* The number of sensing points per bank */ --#define MT7986_NUM_SENSORS_PER_ZONE 1 -- --/* MT7986 thermal sensors */ --#define MT7986_TS1 0 -- --/* The number of controller in the MT7986 */ --#define MT7986_NUM_CONTROLLER 1 -- --/* The calibration coefficient of sensor */ --#define MT7986_CALIBRATION 165 -- --struct mtk_thermal; -- --struct thermal_bank_cfg { -- unsigned int num_sensors; -- const int *sensors; --}; -- --struct mtk_thermal_bank { -- struct mtk_thermal *mt; -- int id; --}; -- --struct mtk_thermal_data { -- s32 num_banks; -- s32 num_sensors; -- s32 auxadc_channel; -- const int *vts_index; -- const int *sensor_mux_values; -- const int *msr; -- const int *adcpnp; -- const int cali_val; -- const int num_controller; -- const int *controller_offset; -- bool need_switch_bank; -- struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; -- enum mtk_thermal_version version; --}; -- --struct mtk_thermal { -- struct device *dev; -- void __iomem *thermal_base; -- -- struct clk *clk_peri_therm; -- struct clk *clk_auxadc; -- /* lock: for getting and putting banks */ -- struct mutex lock; -- -- /* Calibration values */ -- s32 adc_ge; -- s32 adc_oe; -- s32 degc_cali; -- s32 o_slope; -- s32 o_slope_sign; -- s32 vts[MAX_NUM_VTS]; -- -- const struct mtk_thermal_data *conf; -- struct mtk_thermal_bank banks[MAX_NUM_ZONES]; -- -- int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); --}; -- --/* MT8183 thermal sensor data */ --static const int mt8183_bank_data[MT8183_NUM_SENSORS] = { -- MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB --}; -- --static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = { -- TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1 --}; -- --static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = { -- TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1, -- TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1 --}; -- --static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 }; --static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100}; -- --static const int mt8183_vts_index[MT8183_NUM_SENSORS] = { -- VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB --}; -- --/* MT8173 thermal sensor data */ --static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { -- { MT8173_TS2, MT8173_TS3 }, -- { MT8173_TS2, MT8173_TS4 }, -- { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, -- { MT8173_TS2 }, --}; -- --static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { -- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 --}; -- --static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { -- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 --}; -- --static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; --static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, }; -- --static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { -- VTS1, VTS2, VTS3, VTS4, VTSABB --}; -- --/* MT2701 thermal sensor data */ --static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { -- MT2701_TS1, MT2701_TS2, MT2701_TSABB --}; -- --static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { -- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 --}; -- --static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { -- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 --}; -- --static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; --static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, }; -- --static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { -- VTS1, VTS2, VTS3 --}; -- --/* MT2712 thermal sensor data */ --static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { -- MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 --}; -- --static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { -- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 --}; -- --static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { -- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 --}; -- --static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; --static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, }; -- --static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { -- VTS1, VTS2, VTS3, VTS4 --}; -- --/* MT7622 thermal sensor data */ --static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; --static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; --static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; --static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; --static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; --static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; -- --/* MT7986 thermal sensor data */ --static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; --static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; --static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; --static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; --static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; --static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; -- --/* -- * The MT8173 thermal controller has four banks. Each bank can read up to -- * four temperature sensors simultaneously. The MT8173 has a total of 5 -- * temperature sensors. We use each bank to measure a certain area of the -- * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple -- * areas, hence is used in different banks. -- * -- * The thermal core only gets the maximum temperature of all banks, so -- * the bank concept wouldn't be necessary here. However, the SVS (Smart -- * Voltage Scaling) unit makes its decisions based on the same bank -- * data, and this indeed needs the temperatures of the individual banks -- * for making better decisions. -- */ --static const struct mtk_thermal_data mt8173_thermal_data = { -- .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, -- .num_banks = MT8173_NUM_ZONES, -- .num_sensors = MT8173_NUM_SENSORS, -- .vts_index = mt8173_vts_index, -- .cali_val = MT8173_CALIBRATION, -- .num_controller = MT8173_NUM_CONTROLLER, -- .controller_offset = mt8173_tc_offset, -- .need_switch_bank = true, -- .bank_data = { -- { -- .num_sensors = 2, -- .sensors = mt8173_bank_data[0], -- }, { -- .num_sensors = 2, -- .sensors = mt8173_bank_data[1], -- }, { -- .num_sensors = 3, -- .sensors = mt8173_bank_data[2], -- }, { -- .num_sensors = 1, -- .sensors = mt8173_bank_data[3], -- }, -- }, -- .msr = mt8173_msr, -- .adcpnp = mt8173_adcpnp, -- .sensor_mux_values = mt8173_mux_values, -- .version = MTK_THERMAL_V1, --}; -- --/* -- * The MT2701 thermal controller has one bank, which can read up to -- * three temperature sensors simultaneously. The MT2701 has a total of 3 -- * temperature sensors. -- * -- * The thermal core only gets the maximum temperature of this one bank, -- * so the bank concept wouldn't be necessary here. However, the SVS (Smart -- * Voltage Scaling) unit makes its decisions based on the same bank -- * data. -- */ --static const struct mtk_thermal_data mt2701_thermal_data = { -- .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, -- .num_banks = 1, -- .num_sensors = MT2701_NUM_SENSORS, -- .vts_index = mt2701_vts_index, -- .cali_val = MT2701_CALIBRATION, -- .num_controller = MT2701_NUM_CONTROLLER, -- .controller_offset = mt2701_tc_offset, -- .need_switch_bank = true, -- .bank_data = { -- { -- .num_sensors = 3, -- .sensors = mt2701_bank_data, -- }, -- }, -- .msr = mt2701_msr, -- .adcpnp = mt2701_adcpnp, -- .sensor_mux_values = mt2701_mux_values, -- .version = MTK_THERMAL_V1, --}; -- --/* -- * The MT2712 thermal controller has one bank, which can read up to -- * four temperature sensors simultaneously. The MT2712 has a total of 4 -- * temperature sensors. -- * -- * The thermal core only gets the maximum temperature of this one bank, -- * so the bank concept wouldn't be necessary here. However, the SVS (Smart -- * Voltage Scaling) unit makes its decisions based on the same bank -- * data. -- */ --static const struct mtk_thermal_data mt2712_thermal_data = { -- .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, -- .num_banks = 1, -- .num_sensors = MT2712_NUM_SENSORS, -- .vts_index = mt2712_vts_index, -- .cali_val = MT2712_CALIBRATION, -- .num_controller = MT2712_NUM_CONTROLLER, -- .controller_offset = mt2712_tc_offset, -- .need_switch_bank = true, -- .bank_data = { -- { -- .num_sensors = 4, -- .sensors = mt2712_bank_data, -- }, -- }, -- .msr = mt2712_msr, -- .adcpnp = mt2712_adcpnp, -- .sensor_mux_values = mt2712_mux_values, -- .version = MTK_THERMAL_V1, --}; -- --/* -- * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data -- * access. -- */ --static const struct mtk_thermal_data mt7622_thermal_data = { -- .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, -- .num_banks = MT7622_NUM_ZONES, -- .num_sensors = MT7622_NUM_SENSORS, -- .vts_index = mt7622_vts_index, -- .cali_val = MT7622_CALIBRATION, -- .num_controller = MT7622_NUM_CONTROLLER, -- .controller_offset = mt7622_tc_offset, -- .need_switch_bank = true, -- .bank_data = { -- { -- .num_sensors = 1, -- .sensors = mt7622_bank_data, -- }, -- }, -- .msr = mt7622_msr, -- .adcpnp = mt7622_adcpnp, -- .sensor_mux_values = mt7622_mux_values, -- .version = MTK_THERMAL_V2, --}; -- --/* -- * The MT8183 thermal controller has one bank for the current SW framework. -- * The MT8183 has a total of 6 temperature sensors. -- * There are two thermal controller to control the six sensor. -- * The first one bind 2 sensor, and the other bind 4 sensors. -- * The thermal core only gets the maximum temperature of all sensor, so -- * the bank concept wouldn't be necessary here. However, the SVS (Smart -- * Voltage Scaling) unit makes its decisions based on the same bank -- * data, and this indeed needs the temperatures of the individual banks -- * for making better decisions. -- */ --static const struct mtk_thermal_data mt8183_thermal_data = { -- .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL, -- .num_banks = MT8183_NUM_ZONES, -- .num_sensors = MT8183_NUM_SENSORS, -- .vts_index = mt8183_vts_index, -- .cali_val = MT8183_CALIBRATION, -- .num_controller = MT8183_NUM_CONTROLLER, -- .controller_offset = mt8183_tc_offset, -- .need_switch_bank = false, -- .bank_data = { -- { -- .num_sensors = 6, -- .sensors = mt8183_bank_data, -- }, -- }, -- -- .msr = mt8183_msr, -- .adcpnp = mt8183_adcpnp, -- .sensor_mux_values = mt8183_mux_values, -- .version = MTK_THERMAL_V1, --}; -- --/* -- * MT7986 uses AUXADC Channel 11 for raw data access. -- */ --static const struct mtk_thermal_data mt7986_thermal_data = { -- .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, -- .num_banks = MT7986_NUM_ZONES, -- .num_sensors = MT7986_NUM_SENSORS, -- .vts_index = mt7986_vts_index, -- .cali_val = MT7986_CALIBRATION, -- .num_controller = MT7986_NUM_CONTROLLER, -- .controller_offset = mt7986_tc_offset, -- .need_switch_bank = true, -- .bank_data = { -- { -- .num_sensors = 1, -- .sensors = mt7986_bank_data, -- }, -- }, -- .msr = mt7986_msr, -- .adcpnp = mt7986_adcpnp, -- .sensor_mux_values = mt7986_mux_values, -- .version = MTK_THERMAL_V3, --}; -- --/** -- * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius -- * @mt: The thermal controller -- * @sensno: sensor number -- * @raw: raw ADC value -- * -- * This converts the raw ADC value to mcelsius using the SoC specific -- * calibration constants -- */ --static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw) --{ -- s32 tmp; -- -- raw &= 0xfff; -- -- tmp = 203450520 << 3; -- tmp /= mt->conf->cali_val + mt->o_slope; -- tmp /= 10000 + mt->adc_ge; -- tmp *= raw - mt->vts[sensno] - 3350; -- tmp >>= 3; -- -- return mt->degc_cali * 500 - tmp; --} -- --static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw) --{ -- s32 format_1; -- s32 format_2; -- s32 g_oe; -- s32 g_gain; -- s32 g_x_roomt; -- s32 tmp; -- -- if (raw == 0) -- return 0; -- -- raw &= 0xfff; -- g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); -- g_oe = mt->adc_oe - 512; -- format_1 = mt->vts[VTS2] + 3105 - g_oe; -- format_2 = (mt->degc_cali * 10) >> 1; -- g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain; -- -- tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; -- tmp = tmp * 10 * 100 / 11; -- -- if (mt->o_slope_sign == 0) -- tmp = tmp / (165 - mt->o_slope); -- else -- tmp = tmp / (165 + mt->o_slope); -- -- return (format_2 - tmp) * 100; --} -- --static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) --{ -- s32 tmp; -- -- if (raw == 0) -- return 0; -- -- raw &= 0xfff; -- tmp = 100000 * 15 / 16 * 10000; -- tmp /= 4096 - 512 + mt->adc_ge; -- tmp /= 1490; -- tmp *= raw - mt->vts[sensno] - 2900; -- -- return mt->degc_cali * 500 - tmp; --} -- --/** -- * mtk_thermal_get_bank - get bank -- * @bank: The bank -- * -- * The bank registers are banked, we have to select a bank in the -- * PTPCORESEL register to access it. -- */ --static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) --{ -- struct mtk_thermal *mt = bank->mt; -- u32 val; -- -- if (mt->conf->need_switch_bank) { -- mutex_lock(&mt->lock); -- -- val = readl(mt->thermal_base + PTPCORESEL); -- val &= ~0xf; -- val |= bank->id; -- writel(val, mt->thermal_base + PTPCORESEL); -- } --} -- --/** -- * mtk_thermal_put_bank - release bank -- * @bank: The bank -- * -- * release a bank previously taken with mtk_thermal_get_bank, -- */ --static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) --{ -- struct mtk_thermal *mt = bank->mt; -- -- if (mt->conf->need_switch_bank) -- mutex_unlock(&mt->lock); --} -- --/** -- * mtk_thermal_bank_temperature - get the temperature of a bank -- * @bank: The bank -- * -- * The temperature of a bank is considered the maximum temperature of -- * the sensors associated to the bank. -- */ --static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) --{ -- struct mtk_thermal *mt = bank->mt; -- const struct mtk_thermal_data *conf = mt->conf; -- int i, temp = INT_MIN, max = INT_MIN; -- u32 raw; -- -- for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { -- raw = readl(mt->thermal_base + conf->msr[i]); -- -- temp = mt->raw_to_mcelsius( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- -- -- /* -- * The first read of a sensor often contains very high bogus -- * temperature value. Filter these out so that the system does -- * not immediately shut down. -- */ -- if (temp > 200000) -- temp = 0; -- -- if (temp > max) -- max = temp; -- } -- -- return max; --} -- --static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) --{ -- struct mtk_thermal *mt = tz->devdata; -- int i; -- int tempmax = INT_MIN; -- -- for (i = 0; i < mt->conf->num_banks; i++) { -- struct mtk_thermal_bank *bank = &mt->banks[i]; -- -- mtk_thermal_get_bank(bank); -- -- tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); -- -- mtk_thermal_put_bank(bank); -- } -- -- *temperature = tempmax; -- -- return 0; --} -- --static const struct thermal_zone_device_ops mtk_thermal_ops = { -- .get_temp = mtk_read_temp, --}; -- --static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, -- u32 apmixed_phys_base, u32 auxadc_phys_base, -- int ctrl_id) --{ -- struct mtk_thermal_bank *bank = &mt->banks[num]; -- const struct mtk_thermal_data *conf = mt->conf; -- int i; -- -- int offset = mt->conf->controller_offset[ctrl_id]; -- void __iomem *controller_base = mt->thermal_base + offset; -- -- bank->id = num; -- bank->mt = mt; -- -- mtk_thermal_get_bank(bank); -- -- /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ -- writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1); -- -- /* -- * filt interval is 1 * 46.540us = 46.54us, -- * sen interval is 429 * 46.540us = 19.96ms -- */ -- writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | -- TEMP_MONCTL2_SENSOR_INTERVAL(429), -- controller_base + TEMP_MONCTL2); -- -- /* poll is set to 10u */ -- writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), -- controller_base + TEMP_AHBPOLL); -- -- /* temperature sampling control, 1 sample */ -- writel(0x0, controller_base + TEMP_MSRCTL0); -- -- /* exceed this polling time, IRQ would be inserted */ -- writel(0xffffffff, controller_base + TEMP_AHBTO); -- -- /* number of interrupts per event, 1 is enough */ -- writel(0x0, controller_base + TEMP_MONIDET0); -- writel(0x0, controller_base + TEMP_MONIDET1); -- -- /* -- * The MT8173 thermal controller does not have its own ADC. Instead it -- * uses AHB bus accesses to control the AUXADC. To do this the thermal -- * controller has to be programmed with the physical addresses of the -- * AUXADC registers and with the various bit positions in the AUXADC. -- * Also the thermal controller controls a mux in the APMIXEDSYS register -- * space. -- */ -- -- /* -- * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) -- * automatically by hw -- */ -- writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); -- -- /* AHB address for auxadc mux selection */ -- writel(auxadc_phys_base + AUXADC_CON1_CLR_V, -- controller_base + TEMP_ADCMUXADDR); -- -- if (mt->conf->version == MTK_THERMAL_V1) { -- /* AHB address for pnp sensor mux selection */ -- writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, -- controller_base + TEMP_PNPMUXADDR); -- } -- -- /* AHB value for auxadc enable */ -- writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); -- -- /* AHB address for auxadc enable (channel 0 immediate mode selected) */ -- writel(auxadc_phys_base + AUXADC_CON1_SET_V, -- controller_base + TEMP_ADCENADDR); -- -- /* AHB address for auxadc valid bit */ -- writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), -- controller_base + TEMP_ADCVALIDADDR); -- -- /* AHB address for auxadc voltage output */ -- writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), -- controller_base + TEMP_ADCVOLTADDR); -- -- /* read valid & voltage are at the same register */ -- writel(0x0, controller_base + TEMP_RDCTRL); -- -- /* indicate where the valid bit is */ -- writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), -- controller_base + TEMP_ADCVALIDMASK); -- -- /* no shift */ -- writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT); -- -- /* enable auxadc mux write transaction */ -- writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, -- controller_base + TEMP_ADCWRITECTRL); -- -- for (i = 0; i < conf->bank_data[num].num_sensors; i++) -- writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], -- mt->thermal_base + conf->adcpnp[i]); -- -- writel((1 << conf->bank_data[num].num_sensors) - 1, -- controller_base + TEMP_MONCTL0); -- -- writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | -- TEMP_ADCWRITECTRL_ADC_MUX_WRITE, -- controller_base + TEMP_ADCWRITECTRL); -- -- mtk_thermal_put_bank(bank); --} -- --static u64 of_get_phys_base(struct device_node *np) --{ -- u64 size64; -- const __be32 *regaddr_p; -- -- regaddr_p = of_get_address(np, 0, &size64, NULL); -- if (!regaddr_p) -- return OF_BAD_ADDR; -- -- return of_translate_address(np, regaddr_p); --} -- --static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) --{ -- int i; -- -- if (!(buf[0] & CALIB_BUF0_VALID_V1)) -- return -EINVAL; -- -- mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); -- -- for (i = 0; i < mt->conf->num_sensors; i++) { -- switch (mt->conf->vts_index[i]) { -- case VTS1: -- mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); -- break; -- case VTS2: -- mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); -- break; -- case VTS3: -- mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); -- break; -- case VTS4: -- mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); -- break; -- case VTS5: -- mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); -- break; -- case VTSABB: -- mt->vts[VTSABB] = -- CALIB_BUF2_VTS_TSABB_V1(buf[2]); -- break; -- default: -- break; -- } -- } -- -- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); -- if (CALIB_BUF1_ID_V1(buf[1]) & -- CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0])) -- mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); -- else -- mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); -- -- return 0; --} -- --static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf) --{ -- if (!CALIB_BUF1_VALID_V2(buf[1])) -- return -EINVAL; -- -- mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); -- mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); -- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); -- mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); -- mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); -- mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); -- mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); -- mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); -- -- return 0; --} -- --static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) --{ -- if (!CALIB_BUF1_VALID_V3(buf[1])) -- return -EINVAL; -- -- mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); -- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); -- mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); -- mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); -- mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); -- mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); -- mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); -- -- if (CALIB_BUF1_ID_V3(buf[1]) == 0) -- mt->o_slope = 0; -- -- return 0; --} -- --static int mtk_thermal_get_calibration_data(struct device *dev, -- struct mtk_thermal *mt) --{ -- struct nvmem_cell *cell; -- u32 *buf; -- size_t len; -- int i, ret = 0; -- -- /* Start with default values */ -- mt->adc_ge = 512; -- mt->adc_oe = 512; -- for (i = 0; i < mt->conf->num_sensors; i++) -- mt->vts[i] = 260; -- mt->degc_cali = 40; -- mt->o_slope = 0; -- -- cell = nvmem_cell_get(dev, "calibration-data"); -- if (IS_ERR(cell)) { -- if (PTR_ERR(cell) == -EPROBE_DEFER) -- return PTR_ERR(cell); -- return 0; -- } -- -- buf = (u32 *)nvmem_cell_read(cell, &len); -- -- nvmem_cell_put(cell); -- -- if (IS_ERR(buf)) -- return PTR_ERR(buf); -- -- if (len < 3 * sizeof(u32)) { -- dev_warn(dev, "invalid calibration data\n"); -- ret = -EINVAL; -- goto out; -- } -- -- switch (mt->conf->version) { -- case MTK_THERMAL_V1: -- ret = mtk_thermal_extract_efuse_v1(mt, buf); -- break; -- case MTK_THERMAL_V2: -- ret = mtk_thermal_extract_efuse_v2(mt, buf); -- break; -- case MTK_THERMAL_V3: -- ret = mtk_thermal_extract_efuse_v3(mt, buf); -- break; -- default: -- ret = -EINVAL; -- break; -- } -- -- if (ret) { -- dev_info(dev, "Device not calibrated, using default calibration values\n"); -- ret = 0; -- } -- --out: -- kfree(buf); -- -- return ret; --} -- --static const struct of_device_id mtk_thermal_of_match[] = { -- { -- .compatible = "mediatek,mt8173-thermal", -- .data = (void *)&mt8173_thermal_data, -- }, -- { -- .compatible = "mediatek,mt2701-thermal", -- .data = (void *)&mt2701_thermal_data, -- }, -- { -- .compatible = "mediatek,mt2712-thermal", -- .data = (void *)&mt2712_thermal_data, -- }, -- { -- .compatible = "mediatek,mt7622-thermal", -- .data = (void *)&mt7622_thermal_data, -- }, -- { -- .compatible = "mediatek,mt7986-thermal", -- .data = (void *)&mt7986_thermal_data, -- }, -- { -- .compatible = "mediatek,mt8183-thermal", -- .data = (void *)&mt8183_thermal_data, -- }, { -- }, --}; --MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); -- --static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) --{ -- int tmp; -- -- tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); -- tmp &= ~(0x37); -- tmp |= 0x1; -- writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); -- udelay(200); --} -- --static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt, -- void __iomem *auxadc_base) --{ -- int tmp; -- -- writel(0x800, auxadc_base + AUXADC_CON1_SET_V); -- writel(0x1, mt->thermal_base + TEMP_MONCTL0); -- tmp = readl(mt->thermal_base + TEMP_MSRCTL1); -- writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); --} -- --static int mtk_thermal_probe(struct platform_device *pdev) --{ -- int ret, i, ctrl_id; -- struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; -- struct mtk_thermal *mt; -- u64 auxadc_phys_base, apmixed_phys_base; -- struct thermal_zone_device *tzdev; -- void __iomem *apmixed_base, *auxadc_base; -- -- mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); -- if (!mt) -- return -ENOMEM; -- -- mt->conf = of_device_get_match_data(&pdev->dev); -- -- mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); -- if (IS_ERR(mt->clk_peri_therm)) -- return PTR_ERR(mt->clk_peri_therm); -- -- mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); -- if (IS_ERR(mt->clk_auxadc)) -- return PTR_ERR(mt->clk_auxadc); -- -- mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); -- if (IS_ERR(mt->thermal_base)) -- return PTR_ERR(mt->thermal_base); -- -- ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); -- if (ret) -- return ret; -- -- mutex_init(&mt->lock); -- -- mt->dev = &pdev->dev; -- -- auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); -- if (!auxadc) { -- dev_err(&pdev->dev, "missing auxadc node\n"); -- return -ENODEV; -- } -- -- auxadc_base = of_iomap(auxadc, 0); -- auxadc_phys_base = of_get_phys_base(auxadc); -- -- of_node_put(auxadc); -- -- if (auxadc_phys_base == OF_BAD_ADDR) { -- dev_err(&pdev->dev, "Can't get auxadc phys address\n"); -- return -EINVAL; -- } -- -- apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); -- if (!apmixedsys) { -- dev_err(&pdev->dev, "missing apmixedsys node\n"); -- return -ENODEV; -- } -- -- apmixed_base = of_iomap(apmixedsys, 0); -- apmixed_phys_base = of_get_phys_base(apmixedsys); -- -- of_node_put(apmixedsys); -- -- if (apmixed_phys_base == OF_BAD_ADDR) { -- dev_err(&pdev->dev, "Can't get auxadc phys address\n"); -- return -EINVAL; -- } -- -- ret = device_reset_optional(&pdev->dev); -- if (ret) -- return ret; -- -- ret = clk_prepare_enable(mt->clk_auxadc); -- if (ret) { -- dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); -- return ret; -- } -- -- ret = clk_prepare_enable(mt->clk_peri_therm); -- if (ret) { -- dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); -- goto err_disable_clk_auxadc; -- } -- -- if (mt->conf->version != MTK_THERMAL_V1) { -- mtk_thermal_turn_on_buffer(apmixed_base); -- mtk_thermal_release_periodic_ts(mt, auxadc_base); -- } -- -- if (mt->conf->version == MTK_THERMAL_V1) -- mt->raw_to_mcelsius = raw_to_mcelsius_v1; -- else if (mt->conf->version == MTK_THERMAL_V2) -- mt->raw_to_mcelsius = raw_to_mcelsius_v2; -- else -- mt->raw_to_mcelsius = raw_to_mcelsius_v3; -- -- for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) -- for (i = 0; i < mt->conf->num_banks; i++) -- mtk_thermal_init_bank(mt, i, apmixed_phys_base, -- auxadc_phys_base, ctrl_id); -- -- platform_set_drvdata(pdev, mt); -- -- tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, -- &mtk_thermal_ops); -- if (IS_ERR(tzdev)) { -- ret = PTR_ERR(tzdev); -- goto err_disable_clk_peri_therm; -- } -- -- ret = devm_thermal_add_hwmon_sysfs(tzdev); -- if (ret) -- dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); -- -- return 0; -- --err_disable_clk_peri_therm: -- clk_disable_unprepare(mt->clk_peri_therm); --err_disable_clk_auxadc: -- clk_disable_unprepare(mt->clk_auxadc); -- -- return ret; --} -- --static int mtk_thermal_remove(struct platform_device *pdev) --{ -- struct mtk_thermal *mt = platform_get_drvdata(pdev); -- -- clk_disable_unprepare(mt->clk_peri_therm); -- clk_disable_unprepare(mt->clk_auxadc); -- -- return 0; --} -- --static struct platform_driver mtk_thermal_driver = { -- .probe = mtk_thermal_probe, -- .remove = mtk_thermal_remove, -- .driver = { -- .name = "mtk-thermal", -- .of_match_table = mtk_thermal_of_match, -- }, --}; -- --module_platform_driver(mtk_thermal_driver); -- --MODULE_AUTHOR("Michael Kao "); --MODULE_AUTHOR("Louis Yu "); --MODULE_AUTHOR("Dawei Chien "); --MODULE_AUTHOR("Sascha Hauer "); --MODULE_AUTHOR("Hanyi Wu "); --MODULE_DESCRIPTION("Mediatek thermal driver"); --MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -0,0 +1,1254 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2015 MediaTek Inc. -+ * Author: Hanyi Wu -+ * Sascha Hauer -+ * Dawei Chien -+ * Louis Yu -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../thermal_hwmon.h" -+ -+/* AUXADC Registers */ -+#define AUXADC_CON1_SET_V 0x008 -+#define AUXADC_CON1_CLR_V 0x00c -+#define AUXADC_CON2_V 0x010 -+#define AUXADC_DATA(channel) (0x14 + (channel) * 4) -+ -+#define APMIXED_SYS_TS_CON1 0x604 -+ -+/* Thermal Controller Registers */ -+#define TEMP_MONCTL0 0x000 -+#define TEMP_MONCTL1 0x004 -+#define TEMP_MONCTL2 0x008 -+#define TEMP_MONIDET0 0x014 -+#define TEMP_MONIDET1 0x018 -+#define TEMP_MSRCTL0 0x038 -+#define TEMP_MSRCTL1 0x03c -+#define TEMP_AHBPOLL 0x040 -+#define TEMP_AHBTO 0x044 -+#define TEMP_ADCPNP0 0x048 -+#define TEMP_ADCPNP1 0x04c -+#define TEMP_ADCPNP2 0x050 -+#define TEMP_ADCPNP3 0x0b4 -+ -+#define TEMP_ADCMUX 0x054 -+#define TEMP_ADCEN 0x060 -+#define TEMP_PNPMUXADDR 0x064 -+#define TEMP_ADCMUXADDR 0x068 -+#define TEMP_ADCENADDR 0x074 -+#define TEMP_ADCVALIDADDR 0x078 -+#define TEMP_ADCVOLTADDR 0x07c -+#define TEMP_RDCTRL 0x080 -+#define TEMP_ADCVALIDMASK 0x084 -+#define TEMP_ADCVOLTAGESHIFT 0x088 -+#define TEMP_ADCWRITECTRL 0x08c -+#define TEMP_MSR0 0x090 -+#define TEMP_MSR1 0x094 -+#define TEMP_MSR2 0x098 -+#define TEMP_MSR3 0x0B8 -+ -+#define TEMP_SPARE0 0x0f0 -+ -+#define TEMP_ADCPNP0_1 0x148 -+#define TEMP_ADCPNP1_1 0x14c -+#define TEMP_ADCPNP2_1 0x150 -+#define TEMP_MSR0_1 0x190 -+#define TEMP_MSR1_1 0x194 -+#define TEMP_MSR2_1 0x198 -+#define TEMP_ADCPNP3_1 0x1b4 -+#define TEMP_MSR3_1 0x1B8 -+ -+#define PTPCORESEL 0x400 -+ -+#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) -+ -+#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) -+#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) -+ -+#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) -+ -+#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) -+#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) -+ -+#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) -+#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) -+ -+/* MT8173 thermal sensors */ -+#define MT8173_TS1 0 -+#define MT8173_TS2 1 -+#define MT8173_TS3 2 -+#define MT8173_TS4 3 -+#define MT8173_TSABB 4 -+ -+/* AUXADC channel 11 is used for the temperature sensors */ -+#define MT8173_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT8173 */ -+#define MT8173_NUM_SENSORS 5 -+ -+/* The number of banks in the MT8173 */ -+#define MT8173_NUM_ZONES 4 -+ -+/* The number of sensing points per bank */ -+#define MT8173_NUM_SENSORS_PER_ZONE 4 -+ -+/* The number of controller in the MT8173 */ -+#define MT8173_NUM_CONTROLLER 1 -+ -+/* The calibration coefficient of sensor */ -+#define MT8173_CALIBRATION 165 -+ -+/* -+ * Layout of the fuses providing the calibration data -+ * These macros could be used for MT8183, MT8173, MT2701, and MT2712. -+ * MT8183 has 6 sensors and needs 6 VTS calibration data. -+ * MT8173 has 5 sensors and needs 5 VTS calibration data. -+ * MT2701 has 3 sensors and needs 3 VTS calibration data. -+ * MT2712 has 4 sensors and needs 4 VTS calibration data. -+ */ -+#define CALIB_BUF0_VALID_V1 BIT(0) -+#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff) -+#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff) -+#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff) -+#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff) -+#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff) -+#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff) -+#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff) -+#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f) -+#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f) -+#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1) -+#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1) -+ -+/* -+ * Layout of the fuses providing the calibration data -+ * These macros could be used for MT7622. -+ */ -+#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff) -+#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff) -+#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f) -+#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f) -+#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff) -+#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff) -+#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff) -+#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) -+#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) -+ -+/* -+ * Layout of the fuses providing the calibration data -+ * These macros can be used for MT7981 and MT7986. -+ */ -+#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) -+#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) -+#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) -+#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) -+#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) -+#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) -+#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) -+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) -+#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) -+ -+enum { -+ VTS1, -+ VTS2, -+ VTS3, -+ VTS4, -+ VTS5, -+ VTSABB, -+ MAX_NUM_VTS, -+}; -+ -+enum mtk_thermal_version { -+ MTK_THERMAL_V1 = 1, -+ MTK_THERMAL_V2, -+ MTK_THERMAL_V3, -+}; -+ -+/* MT2701 thermal sensors */ -+#define MT2701_TS1 0 -+#define MT2701_TS2 1 -+#define MT2701_TSABB 2 -+ -+/* AUXADC channel 11 is used for the temperature sensors */ -+#define MT2701_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT2701 */ -+#define MT2701_NUM_SENSORS 3 -+ -+/* The number of sensing points per bank */ -+#define MT2701_NUM_SENSORS_PER_ZONE 3 -+ -+/* The number of controller in the MT2701 */ -+#define MT2701_NUM_CONTROLLER 1 -+ -+/* The calibration coefficient of sensor */ -+#define MT2701_CALIBRATION 165 -+ -+/* MT2712 thermal sensors */ -+#define MT2712_TS1 0 -+#define MT2712_TS2 1 -+#define MT2712_TS3 2 -+#define MT2712_TS4 3 -+ -+/* AUXADC channel 11 is used for the temperature sensors */ -+#define MT2712_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT2712 */ -+#define MT2712_NUM_SENSORS 4 -+ -+/* The number of sensing points per bank */ -+#define MT2712_NUM_SENSORS_PER_ZONE 4 -+ -+/* The number of controller in the MT2712 */ -+#define MT2712_NUM_CONTROLLER 1 -+ -+/* The calibration coefficient of sensor */ -+#define MT2712_CALIBRATION 165 -+ -+#define MT7622_TEMP_AUXADC_CHANNEL 11 -+#define MT7622_NUM_SENSORS 1 -+#define MT7622_NUM_ZONES 1 -+#define MT7622_NUM_SENSORS_PER_ZONE 1 -+#define MT7622_TS1 0 -+#define MT7622_NUM_CONTROLLER 1 -+ -+/* The maximum number of banks */ -+#define MAX_NUM_ZONES 8 -+ -+/* The calibration coefficient of sensor */ -+#define MT7622_CALIBRATION 165 -+ -+/* MT8183 thermal sensors */ -+#define MT8183_TS1 0 -+#define MT8183_TS2 1 -+#define MT8183_TS3 2 -+#define MT8183_TS4 3 -+#define MT8183_TS5 4 -+#define MT8183_TSABB 5 -+ -+/* AUXADC channel is used for the temperature sensors */ -+#define MT8183_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT8183 */ -+#define MT8183_NUM_SENSORS 6 -+ -+/* The number of banks in the MT8183 */ -+#define MT8183_NUM_ZONES 1 -+ -+/* The number of sensing points per bank */ -+#define MT8183_NUM_SENSORS_PER_ZONE 6 -+ -+/* The number of controller in the MT8183 */ -+#define MT8183_NUM_CONTROLLER 2 -+ -+/* The calibration coefficient of sensor */ -+#define MT8183_CALIBRATION 153 -+ -+/* AUXADC channel 11 is used for the temperature sensors */ -+#define MT7986_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT7986 */ -+#define MT7986_NUM_SENSORS 1 -+ -+/* The number of banks in the MT7986 */ -+#define MT7986_NUM_ZONES 1 -+ -+/* The number of sensing points per bank */ -+#define MT7986_NUM_SENSORS_PER_ZONE 1 -+ -+/* MT7986 thermal sensors */ -+#define MT7986_TS1 0 -+ -+/* The number of controller in the MT7986 */ -+#define MT7986_NUM_CONTROLLER 1 -+ -+/* The calibration coefficient of sensor */ -+#define MT7986_CALIBRATION 165 -+ -+struct mtk_thermal; -+ -+struct thermal_bank_cfg { -+ unsigned int num_sensors; -+ const int *sensors; -+}; -+ -+struct mtk_thermal_bank { -+ struct mtk_thermal *mt; -+ int id; -+}; -+ -+struct mtk_thermal_data { -+ s32 num_banks; -+ s32 num_sensors; -+ s32 auxadc_channel; -+ const int *vts_index; -+ const int *sensor_mux_values; -+ const int *msr; -+ const int *adcpnp; -+ const int cali_val; -+ const int num_controller; -+ const int *controller_offset; -+ bool need_switch_bank; -+ struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; -+ enum mtk_thermal_version version; -+}; -+ -+struct mtk_thermal { -+ struct device *dev; -+ void __iomem *thermal_base; -+ -+ struct clk *clk_peri_therm; -+ struct clk *clk_auxadc; -+ /* lock: for getting and putting banks */ -+ struct mutex lock; -+ -+ /* Calibration values */ -+ s32 adc_ge; -+ s32 adc_oe; -+ s32 degc_cali; -+ s32 o_slope; -+ s32 o_slope_sign; -+ s32 vts[MAX_NUM_VTS]; -+ -+ const struct mtk_thermal_data *conf; -+ struct mtk_thermal_bank banks[MAX_NUM_ZONES]; -+ -+ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); -+}; -+ -+/* MT8183 thermal sensor data */ -+static const int mt8183_bank_data[MT8183_NUM_SENSORS] = { -+ MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB -+}; -+ -+static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = { -+ TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1 -+}; -+ -+static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = { -+ TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1, -+ TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1 -+}; -+ -+static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 }; -+static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100}; -+ -+static const int mt8183_vts_index[MT8183_NUM_SENSORS] = { -+ VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB -+}; -+ -+/* MT8173 thermal sensor data */ -+static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { -+ { MT8173_TS2, MT8173_TS3 }, -+ { MT8173_TS2, MT8173_TS4 }, -+ { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, -+ { MT8173_TS2 }, -+}; -+ -+static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { -+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 -+}; -+ -+static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { -+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 -+}; -+ -+static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; -+static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, }; -+ -+static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { -+ VTS1, VTS2, VTS3, VTS4, VTSABB -+}; -+ -+/* MT2701 thermal sensor data */ -+static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { -+ MT2701_TS1, MT2701_TS2, MT2701_TSABB -+}; -+ -+static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { -+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 -+}; -+ -+static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { -+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 -+}; -+ -+static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; -+static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, }; -+ -+static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { -+ VTS1, VTS2, VTS3 -+}; -+ -+/* MT2712 thermal sensor data */ -+static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { -+ MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 -+}; -+ -+static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { -+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 -+}; -+ -+static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { -+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 -+}; -+ -+static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; -+static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, }; -+ -+static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { -+ VTS1, VTS2, VTS3, VTS4 -+}; -+ -+/* MT7622 thermal sensor data */ -+static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; -+static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; -+static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; -+static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; -+static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; -+static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; -+ -+/* MT7986 thermal sensor data */ -+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; -+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; -+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; -+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; -+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; -+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; -+ -+/* -+ * The MT8173 thermal controller has four banks. Each bank can read up to -+ * four temperature sensors simultaneously. The MT8173 has a total of 5 -+ * temperature sensors. We use each bank to measure a certain area of the -+ * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple -+ * areas, hence is used in different banks. -+ * -+ * The thermal core only gets the maximum temperature of all banks, so -+ * the bank concept wouldn't be necessary here. However, the SVS (Smart -+ * Voltage Scaling) unit makes its decisions based on the same bank -+ * data, and this indeed needs the temperatures of the individual banks -+ * for making better decisions. -+ */ -+static const struct mtk_thermal_data mt8173_thermal_data = { -+ .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT8173_NUM_ZONES, -+ .num_sensors = MT8173_NUM_SENSORS, -+ .vts_index = mt8173_vts_index, -+ .cali_val = MT8173_CALIBRATION, -+ .num_controller = MT8173_NUM_CONTROLLER, -+ .controller_offset = mt8173_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 2, -+ .sensors = mt8173_bank_data[0], -+ }, { -+ .num_sensors = 2, -+ .sensors = mt8173_bank_data[1], -+ }, { -+ .num_sensors = 3, -+ .sensors = mt8173_bank_data[2], -+ }, { -+ .num_sensors = 1, -+ .sensors = mt8173_bank_data[3], -+ }, -+ }, -+ .msr = mt8173_msr, -+ .adcpnp = mt8173_adcpnp, -+ .sensor_mux_values = mt8173_mux_values, -+ .version = MTK_THERMAL_V1, -+}; -+ -+/* -+ * The MT2701 thermal controller has one bank, which can read up to -+ * three temperature sensors simultaneously. The MT2701 has a total of 3 -+ * temperature sensors. -+ * -+ * The thermal core only gets the maximum temperature of this one bank, -+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart -+ * Voltage Scaling) unit makes its decisions based on the same bank -+ * data. -+ */ -+static const struct mtk_thermal_data mt2701_thermal_data = { -+ .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, -+ .num_banks = 1, -+ .num_sensors = MT2701_NUM_SENSORS, -+ .vts_index = mt2701_vts_index, -+ .cali_val = MT2701_CALIBRATION, -+ .num_controller = MT2701_NUM_CONTROLLER, -+ .controller_offset = mt2701_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 3, -+ .sensors = mt2701_bank_data, -+ }, -+ }, -+ .msr = mt2701_msr, -+ .adcpnp = mt2701_adcpnp, -+ .sensor_mux_values = mt2701_mux_values, -+ .version = MTK_THERMAL_V1, -+}; -+ -+/* -+ * The MT2712 thermal controller has one bank, which can read up to -+ * four temperature sensors simultaneously. The MT2712 has a total of 4 -+ * temperature sensors. -+ * -+ * The thermal core only gets the maximum temperature of this one bank, -+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart -+ * Voltage Scaling) unit makes its decisions based on the same bank -+ * data. -+ */ -+static const struct mtk_thermal_data mt2712_thermal_data = { -+ .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, -+ .num_banks = 1, -+ .num_sensors = MT2712_NUM_SENSORS, -+ .vts_index = mt2712_vts_index, -+ .cali_val = MT2712_CALIBRATION, -+ .num_controller = MT2712_NUM_CONTROLLER, -+ .controller_offset = mt2712_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 4, -+ .sensors = mt2712_bank_data, -+ }, -+ }, -+ .msr = mt2712_msr, -+ .adcpnp = mt2712_adcpnp, -+ .sensor_mux_values = mt2712_mux_values, -+ .version = MTK_THERMAL_V1, -+}; -+ -+/* -+ * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data -+ * access. -+ */ -+static const struct mtk_thermal_data mt7622_thermal_data = { -+ .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT7622_NUM_ZONES, -+ .num_sensors = MT7622_NUM_SENSORS, -+ .vts_index = mt7622_vts_index, -+ .cali_val = MT7622_CALIBRATION, -+ .num_controller = MT7622_NUM_CONTROLLER, -+ .controller_offset = mt7622_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 1, -+ .sensors = mt7622_bank_data, -+ }, -+ }, -+ .msr = mt7622_msr, -+ .adcpnp = mt7622_adcpnp, -+ .sensor_mux_values = mt7622_mux_values, -+ .version = MTK_THERMAL_V2, -+}; -+ -+/* -+ * The MT8183 thermal controller has one bank for the current SW framework. -+ * The MT8183 has a total of 6 temperature sensors. -+ * There are two thermal controller to control the six sensor. -+ * The first one bind 2 sensor, and the other bind 4 sensors. -+ * The thermal core only gets the maximum temperature of all sensor, so -+ * the bank concept wouldn't be necessary here. However, the SVS (Smart -+ * Voltage Scaling) unit makes its decisions based on the same bank -+ * data, and this indeed needs the temperatures of the individual banks -+ * for making better decisions. -+ */ -+static const struct mtk_thermal_data mt8183_thermal_data = { -+ .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT8183_NUM_ZONES, -+ .num_sensors = MT8183_NUM_SENSORS, -+ .vts_index = mt8183_vts_index, -+ .cali_val = MT8183_CALIBRATION, -+ .num_controller = MT8183_NUM_CONTROLLER, -+ .controller_offset = mt8183_tc_offset, -+ .need_switch_bank = false, -+ .bank_data = { -+ { -+ .num_sensors = 6, -+ .sensors = mt8183_bank_data, -+ }, -+ }, -+ -+ .msr = mt8183_msr, -+ .adcpnp = mt8183_adcpnp, -+ .sensor_mux_values = mt8183_mux_values, -+ .version = MTK_THERMAL_V1, -+}; -+ -+/* -+ * MT7986 uses AUXADC Channel 11 for raw data access. -+ */ -+static const struct mtk_thermal_data mt7986_thermal_data = { -+ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT7986_NUM_ZONES, -+ .num_sensors = MT7986_NUM_SENSORS, -+ .vts_index = mt7986_vts_index, -+ .cali_val = MT7986_CALIBRATION, -+ .num_controller = MT7986_NUM_CONTROLLER, -+ .controller_offset = mt7986_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 1, -+ .sensors = mt7986_bank_data, -+ }, -+ }, -+ .msr = mt7986_msr, -+ .adcpnp = mt7986_adcpnp, -+ .sensor_mux_values = mt7986_mux_values, -+ .version = MTK_THERMAL_V3, -+}; -+ -+/** -+ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius -+ * @mt: The thermal controller -+ * @sensno: sensor number -+ * @raw: raw ADC value -+ * -+ * This converts the raw ADC value to mcelsius using the SoC specific -+ * calibration constants -+ */ -+static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw) -+{ -+ s32 tmp; -+ -+ raw &= 0xfff; -+ -+ tmp = 203450520 << 3; -+ tmp /= mt->conf->cali_val + mt->o_slope; -+ tmp /= 10000 + mt->adc_ge; -+ tmp *= raw - mt->vts[sensno] - 3350; -+ tmp >>= 3; -+ -+ return mt->degc_cali * 500 - tmp; -+} -+ -+static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw) -+{ -+ s32 format_1; -+ s32 format_2; -+ s32 g_oe; -+ s32 g_gain; -+ s32 g_x_roomt; -+ s32 tmp; -+ -+ if (raw == 0) -+ return 0; -+ -+ raw &= 0xfff; -+ g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); -+ g_oe = mt->adc_oe - 512; -+ format_1 = mt->vts[VTS2] + 3105 - g_oe; -+ format_2 = (mt->degc_cali * 10) >> 1; -+ g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain; -+ -+ tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; -+ tmp = tmp * 10 * 100 / 11; -+ -+ if (mt->o_slope_sign == 0) -+ tmp = tmp / (165 - mt->o_slope); -+ else -+ tmp = tmp / (165 + mt->o_slope); -+ -+ return (format_2 - tmp) * 100; -+} -+ -+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) -+{ -+ s32 tmp; -+ -+ if (raw == 0) -+ return 0; -+ -+ raw &= 0xfff; -+ tmp = 100000 * 15 / 16 * 10000; -+ tmp /= 4096 - 512 + mt->adc_ge; -+ tmp /= 1490; -+ tmp *= raw - mt->vts[sensno] - 2900; -+ -+ return mt->degc_cali * 500 - tmp; -+} -+ -+/** -+ * mtk_thermal_get_bank - get bank -+ * @bank: The bank -+ * -+ * The bank registers are banked, we have to select a bank in the -+ * PTPCORESEL register to access it. -+ */ -+static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) -+{ -+ struct mtk_thermal *mt = bank->mt; -+ u32 val; -+ -+ if (mt->conf->need_switch_bank) { -+ mutex_lock(&mt->lock); -+ -+ val = readl(mt->thermal_base + PTPCORESEL); -+ val &= ~0xf; -+ val |= bank->id; -+ writel(val, mt->thermal_base + PTPCORESEL); -+ } -+} -+ -+/** -+ * mtk_thermal_put_bank - release bank -+ * @bank: The bank -+ * -+ * release a bank previously taken with mtk_thermal_get_bank, -+ */ -+static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) -+{ -+ struct mtk_thermal *mt = bank->mt; -+ -+ if (mt->conf->need_switch_bank) -+ mutex_unlock(&mt->lock); -+} -+ -+/** -+ * mtk_thermal_bank_temperature - get the temperature of a bank -+ * @bank: The bank -+ * -+ * The temperature of a bank is considered the maximum temperature of -+ * the sensors associated to the bank. -+ */ -+static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) -+{ -+ struct mtk_thermal *mt = bank->mt; -+ const struct mtk_thermal_data *conf = mt->conf; -+ int i, temp = INT_MIN, max = INT_MIN; -+ u32 raw; -+ -+ for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { -+ raw = readl(mt->thermal_base + conf->msr[i]); -+ -+ temp = mt->raw_to_mcelsius( -+ mt, conf->bank_data[bank->id].sensors[i], raw); -+ -+ -+ /* -+ * The first read of a sensor often contains very high bogus -+ * temperature value. Filter these out so that the system does -+ * not immediately shut down. -+ */ -+ if (temp > 200000) -+ temp = 0; -+ -+ if (temp > max) -+ max = temp; -+ } -+ -+ return max; -+} -+ -+static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) -+{ -+ struct mtk_thermal *mt = tz->devdata; -+ int i; -+ int tempmax = INT_MIN; -+ -+ for (i = 0; i < mt->conf->num_banks; i++) { -+ struct mtk_thermal_bank *bank = &mt->banks[i]; -+ -+ mtk_thermal_get_bank(bank); -+ -+ tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); -+ -+ mtk_thermal_put_bank(bank); -+ } -+ -+ *temperature = tempmax; -+ -+ return 0; -+} -+ -+static const struct thermal_zone_device_ops mtk_thermal_ops = { -+ .get_temp = mtk_read_temp, -+}; -+ -+static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, -+ u32 apmixed_phys_base, u32 auxadc_phys_base, -+ int ctrl_id) -+{ -+ struct mtk_thermal_bank *bank = &mt->banks[num]; -+ const struct mtk_thermal_data *conf = mt->conf; -+ int i; -+ -+ int offset = mt->conf->controller_offset[ctrl_id]; -+ void __iomem *controller_base = mt->thermal_base + offset; -+ -+ bank->id = num; -+ bank->mt = mt; -+ -+ mtk_thermal_get_bank(bank); -+ -+ /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ -+ writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1); -+ -+ /* -+ * filt interval is 1 * 46.540us = 46.54us, -+ * sen interval is 429 * 46.540us = 19.96ms -+ */ -+ writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | -+ TEMP_MONCTL2_SENSOR_INTERVAL(429), -+ controller_base + TEMP_MONCTL2); -+ -+ /* poll is set to 10u */ -+ writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), -+ controller_base + TEMP_AHBPOLL); -+ -+ /* temperature sampling control, 1 sample */ -+ writel(0x0, controller_base + TEMP_MSRCTL0); -+ -+ /* exceed this polling time, IRQ would be inserted */ -+ writel(0xffffffff, controller_base + TEMP_AHBTO); -+ -+ /* number of interrupts per event, 1 is enough */ -+ writel(0x0, controller_base + TEMP_MONIDET0); -+ writel(0x0, controller_base + TEMP_MONIDET1); -+ -+ /* -+ * The MT8173 thermal controller does not have its own ADC. Instead it -+ * uses AHB bus accesses to control the AUXADC. To do this the thermal -+ * controller has to be programmed with the physical addresses of the -+ * AUXADC registers and with the various bit positions in the AUXADC. -+ * Also the thermal controller controls a mux in the APMIXEDSYS register -+ * space. -+ */ -+ -+ /* -+ * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) -+ * automatically by hw -+ */ -+ writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX); -+ -+ /* AHB address for auxadc mux selection */ -+ writel(auxadc_phys_base + AUXADC_CON1_CLR_V, -+ controller_base + TEMP_ADCMUXADDR); -+ -+ if (mt->conf->version == MTK_THERMAL_V1) { -+ /* AHB address for pnp sensor mux selection */ -+ writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, -+ controller_base + TEMP_PNPMUXADDR); -+ } -+ -+ /* AHB value for auxadc enable */ -+ writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN); -+ -+ /* AHB address for auxadc enable (channel 0 immediate mode selected) */ -+ writel(auxadc_phys_base + AUXADC_CON1_SET_V, -+ controller_base + TEMP_ADCENADDR); -+ -+ /* AHB address for auxadc valid bit */ -+ writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), -+ controller_base + TEMP_ADCVALIDADDR); -+ -+ /* AHB address for auxadc voltage output */ -+ writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), -+ controller_base + TEMP_ADCVOLTADDR); -+ -+ /* read valid & voltage are at the same register */ -+ writel(0x0, controller_base + TEMP_RDCTRL); -+ -+ /* indicate where the valid bit is */ -+ writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), -+ controller_base + TEMP_ADCVALIDMASK); -+ -+ /* no shift */ -+ writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT); -+ -+ /* enable auxadc mux write transaction */ -+ writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, -+ controller_base + TEMP_ADCWRITECTRL); -+ -+ for (i = 0; i < conf->bank_data[num].num_sensors; i++) -+ writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], -+ mt->thermal_base + conf->adcpnp[i]); -+ -+ writel((1 << conf->bank_data[num].num_sensors) - 1, -+ controller_base + TEMP_MONCTL0); -+ -+ writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | -+ TEMP_ADCWRITECTRL_ADC_MUX_WRITE, -+ controller_base + TEMP_ADCWRITECTRL); -+ -+ mtk_thermal_put_bank(bank); -+} -+ -+static u64 of_get_phys_base(struct device_node *np) -+{ -+ u64 size64; -+ const __be32 *regaddr_p; -+ -+ regaddr_p = of_get_address(np, 0, &size64, NULL); -+ if (!regaddr_p) -+ return OF_BAD_ADDR; -+ -+ return of_translate_address(np, regaddr_p); -+} -+ -+static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) -+{ -+ int i; -+ -+ if (!(buf[0] & CALIB_BUF0_VALID_V1)) -+ return -EINVAL; -+ -+ mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); -+ -+ for (i = 0; i < mt->conf->num_sensors; i++) { -+ switch (mt->conf->vts_index[i]) { -+ case VTS1: -+ mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); -+ break; -+ case VTS2: -+ mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); -+ break; -+ case VTS3: -+ mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); -+ break; -+ case VTS4: -+ mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); -+ break; -+ case VTS5: -+ mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); -+ break; -+ case VTSABB: -+ mt->vts[VTSABB] = -+ CALIB_BUF2_VTS_TSABB_V1(buf[2]); -+ break; -+ default: -+ break; -+ } -+ } -+ -+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); -+ if (CALIB_BUF1_ID_V1(buf[1]) & -+ CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0])) -+ mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); -+ else -+ mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); -+ -+ return 0; -+} -+ -+static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf) -+{ -+ if (!CALIB_BUF1_VALID_V2(buf[1])) -+ return -EINVAL; -+ -+ mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); -+ mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); -+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); -+ mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); -+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); -+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); -+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); -+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); -+ -+ return 0; -+} -+ -+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) -+{ -+ if (!CALIB_BUF1_VALID_V3(buf[1])) -+ return -EINVAL; -+ -+ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); -+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); -+ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); -+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); -+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); -+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); -+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); -+ -+ if (CALIB_BUF1_ID_V3(buf[1]) == 0) -+ mt->o_slope = 0; -+ -+ return 0; -+} -+ -+static int mtk_thermal_get_calibration_data(struct device *dev, -+ struct mtk_thermal *mt) -+{ -+ struct nvmem_cell *cell; -+ u32 *buf; -+ size_t len; -+ int i, ret = 0; -+ -+ /* Start with default values */ -+ mt->adc_ge = 512; -+ mt->adc_oe = 512; -+ for (i = 0; i < mt->conf->num_sensors; i++) -+ mt->vts[i] = 260; -+ mt->degc_cali = 40; -+ mt->o_slope = 0; -+ -+ cell = nvmem_cell_get(dev, "calibration-data"); -+ if (IS_ERR(cell)) { -+ if (PTR_ERR(cell) == -EPROBE_DEFER) -+ return PTR_ERR(cell); -+ return 0; -+ } -+ -+ buf = (u32 *)nvmem_cell_read(cell, &len); -+ -+ nvmem_cell_put(cell); -+ -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ -+ if (len < 3 * sizeof(u32)) { -+ dev_warn(dev, "invalid calibration data\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: -+ ret = mtk_thermal_extract_efuse_v1(mt, buf); -+ break; -+ case MTK_THERMAL_V2: -+ ret = mtk_thermal_extract_efuse_v2(mt, buf); -+ break; -+ case MTK_THERMAL_V3: -+ ret = mtk_thermal_extract_efuse_v3(mt, buf); -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ -+ if (ret) { -+ dev_info(dev, "Device not calibrated, using default calibration values\n"); -+ ret = 0; -+ } -+ -+out: -+ kfree(buf); -+ -+ return ret; -+} -+ -+static const struct of_device_id mtk_thermal_of_match[] = { -+ { -+ .compatible = "mediatek,mt8173-thermal", -+ .data = (void *)&mt8173_thermal_data, -+ }, -+ { -+ .compatible = "mediatek,mt2701-thermal", -+ .data = (void *)&mt2701_thermal_data, -+ }, -+ { -+ .compatible = "mediatek,mt2712-thermal", -+ .data = (void *)&mt2712_thermal_data, -+ }, -+ { -+ .compatible = "mediatek,mt7622-thermal", -+ .data = (void *)&mt7622_thermal_data, -+ }, -+ { -+ .compatible = "mediatek,mt7986-thermal", -+ .data = (void *)&mt7986_thermal_data, -+ }, -+ { -+ .compatible = "mediatek,mt8183-thermal", -+ .data = (void *)&mt8183_thermal_data, -+ }, { -+ }, -+}; -+MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); -+ -+static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) -+{ -+ int tmp; -+ -+ tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); -+ tmp &= ~(0x37); -+ tmp |= 0x1; -+ writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); -+ udelay(200); -+} -+ -+static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt, -+ void __iomem *auxadc_base) -+{ -+ int tmp; -+ -+ writel(0x800, auxadc_base + AUXADC_CON1_SET_V); -+ writel(0x1, mt->thermal_base + TEMP_MONCTL0); -+ tmp = readl(mt->thermal_base + TEMP_MSRCTL1); -+ writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1); -+} -+ -+static int mtk_thermal_probe(struct platform_device *pdev) -+{ -+ int ret, i, ctrl_id; -+ struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; -+ struct mtk_thermal *mt; -+ u64 auxadc_phys_base, apmixed_phys_base; -+ struct thermal_zone_device *tzdev; -+ void __iomem *apmixed_base, *auxadc_base; -+ -+ mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); -+ if (!mt) -+ return -ENOMEM; -+ -+ mt->conf = of_device_get_match_data(&pdev->dev); -+ -+ mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); -+ if (IS_ERR(mt->clk_peri_therm)) -+ return PTR_ERR(mt->clk_peri_therm); -+ -+ mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); -+ if (IS_ERR(mt->clk_auxadc)) -+ return PTR_ERR(mt->clk_auxadc); -+ -+ mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); -+ if (IS_ERR(mt->thermal_base)) -+ return PTR_ERR(mt->thermal_base); -+ -+ ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); -+ if (ret) -+ return ret; -+ -+ mutex_init(&mt->lock); -+ -+ mt->dev = &pdev->dev; -+ -+ auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); -+ if (!auxadc) { -+ dev_err(&pdev->dev, "missing auxadc node\n"); -+ return -ENODEV; -+ } -+ -+ auxadc_base = of_iomap(auxadc, 0); -+ auxadc_phys_base = of_get_phys_base(auxadc); -+ -+ of_node_put(auxadc); -+ -+ if (auxadc_phys_base == OF_BAD_ADDR) { -+ dev_err(&pdev->dev, "Can't get auxadc phys address\n"); -+ return -EINVAL; -+ } -+ -+ apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); -+ if (!apmixedsys) { -+ dev_err(&pdev->dev, "missing apmixedsys node\n"); -+ return -ENODEV; -+ } -+ -+ apmixed_base = of_iomap(apmixedsys, 0); -+ apmixed_phys_base = of_get_phys_base(apmixedsys); -+ -+ of_node_put(apmixedsys); -+ -+ if (apmixed_phys_base == OF_BAD_ADDR) { -+ dev_err(&pdev->dev, "Can't get auxadc phys address\n"); -+ return -EINVAL; -+ } -+ -+ ret = device_reset_optional(&pdev->dev); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(mt->clk_auxadc); -+ if (ret) { -+ dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(mt->clk_peri_therm); -+ if (ret) { -+ dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); -+ goto err_disable_clk_auxadc; -+ } -+ -+ if (mt->conf->version != MTK_THERMAL_V1) { -+ mtk_thermal_turn_on_buffer(apmixed_base); -+ mtk_thermal_release_periodic_ts(mt, auxadc_base); -+ } -+ -+ if (mt->conf->version == MTK_THERMAL_V1) -+ mt->raw_to_mcelsius = raw_to_mcelsius_v1; -+ else if (mt->conf->version == MTK_THERMAL_V2) -+ mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ else -+ mt->raw_to_mcelsius = raw_to_mcelsius_v3; -+ -+ for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) -+ for (i = 0; i < mt->conf->num_banks; i++) -+ mtk_thermal_init_bank(mt, i, apmixed_phys_base, -+ auxadc_phys_base, ctrl_id); -+ -+ platform_set_drvdata(pdev, mt); -+ -+ tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, -+ &mtk_thermal_ops); -+ if (IS_ERR(tzdev)) { -+ ret = PTR_ERR(tzdev); -+ goto err_disable_clk_peri_therm; -+ } -+ -+ ret = devm_thermal_add_hwmon_sysfs(tzdev); -+ if (ret) -+ dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); -+ -+ return 0; -+ -+err_disable_clk_peri_therm: -+ clk_disable_unprepare(mt->clk_peri_therm); -+err_disable_clk_auxadc: -+ clk_disable_unprepare(mt->clk_auxadc); -+ -+ return ret; -+} -+ -+static int mtk_thermal_remove(struct platform_device *pdev) -+{ -+ struct mtk_thermal *mt = platform_get_drvdata(pdev); -+ -+ clk_disable_unprepare(mt->clk_peri_therm); -+ clk_disable_unprepare(mt->clk_auxadc); -+ -+ return 0; -+} -+ -+static struct platform_driver mtk_thermal_driver = { -+ .probe = mtk_thermal_probe, -+ .remove = mtk_thermal_remove, -+ .driver = { -+ .name = "mtk-thermal", -+ .of_match_table = mtk_thermal_of_match, -+ }, -+}; -+ -+module_platform_driver(mtk_thermal_driver); -+ -+MODULE_AUTHOR("Michael Kao "); -+MODULE_AUTHOR("Louis Yu "); -+MODULE_AUTHOR("Dawei Chien "); -+MODULE_AUTHOR("Sascha Hauer "); -+MODULE_AUTHOR("Hanyi Wu "); -+MODULE_DESCRIPTION("Mediatek thermal driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch b/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch deleted file mode 100644 index 2ae3734e409665..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.3-06-thermal-drivers-mediatek-Add-the-Low-Voltage-Thermal.patch +++ /dev/null @@ -1,1298 +0,0 @@ -From 325fadf27b21f7d79843c3cc282b7f3e6620ad3d Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Thu, 9 Feb 2023 11:56:26 +0100 -Subject: [PATCH 06/42] thermal/drivers/mediatek: Add the Low Voltage Thermal - Sensor driver - -The Low Voltage Thermal Sensor (LVTS) is a multiple sensors, multi -controllers contained in a thermal domain. - -A thermal domains can be the MCU or the AP. - -Each thermal domains contain up to seven controllers, each thermal -controller handle up to four thermal sensors. - -The LVTS has two Finite State Machines (FSM), one to handle the -functionin temperatures range like hot or cold temperature and another -one to handle monitoring trip point. The FSM notifies via interrupts -when a trip point is crossed. - -The interrupt is managed at the thermal controller level, so when an -interrupt occurs, the driver has to find out which sensor triggered -such an interrupt. - -The sampling of the thermal can be filtered or immediate. For the -former, the LVTS measures several points and applies a low pass -filter. - -Signed-off-by: Balsam CHIHI -Reviewed-by: AngeloGioacchino Del Regno - -On MT8195 Tomato Chromebook: - -Tested-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230209105628.50294-5-bchihi@baylibre.com -Signed-off-by: Daniel Lezcano -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/mediatek/Kconfig | 16 + - drivers/thermal/mediatek/Makefile | 1 + - drivers/thermal/mediatek/lvts_thermal.c | 1224 +++++++++++++++++++++++ - 3 files changed, 1241 insertions(+) - create mode 100644 drivers/thermal/mediatek/lvts_thermal.c - ---- a/drivers/thermal/mediatek/Kconfig -+++ b/drivers/thermal/mediatek/Kconfig -@@ -18,4 +18,20 @@ config MTK_SOC_THERMAL - This driver configures thermal controllers to collect - temperature via AUXADC interface. - -+config MTK_LVTS_THERMAL -+ tristate "LVTS Thermal Driver for MediaTek SoCs" -+ depends on HAS_IOMEM -+ help -+ Enable this option if you want to get SoC temperature -+ information for supported MediaTek platforms. -+ This driver configures LVTS (Low Voltage Thermal Sensor) -+ thermal controllers to collect temperatures via ASIF -+ (Analog Serial Interface). -+ -+config MTK_LVTS_THERMAL_DEBUGFS -+ bool "LVTS thermal debugfs" -+ depends on MTK_LVTS_THERMAL && DEBUG_FS -+ help -+ Enable this option to debug the internals of the device driver. -+ - endif ---- a/drivers/thermal/mediatek/Makefile -+++ b/drivers/thermal/mediatek/Makefile -@@ -1 +1,2 @@ - obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o -+obj-$(CONFIG_MTK_LVTS_THERMAL) += lvts_thermal.o ---- /dev/null -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -0,0 +1,1224 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Balsam CHIHI -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define LVTS_MONCTL0(__base) (__base + 0x0000) -+#define LVTS_MONCTL1(__base) (__base + 0x0004) -+#define LVTS_MONCTL2(__base) (__base + 0x0008) -+#define LVTS_MONINT(__base) (__base + 0x000C) -+#define LVTS_MONINTSTS(__base) (__base + 0x0010) -+#define LVTS_MONIDET0(__base) (__base + 0x0014) -+#define LVTS_MONIDET1(__base) (__base + 0x0018) -+#define LVTS_MONIDET2(__base) (__base + 0x001C) -+#define LVTS_MONIDET3(__base) (__base + 0x0020) -+#define LVTS_H2NTHRE(__base) (__base + 0x0024) -+#define LVTS_HTHRE(__base) (__base + 0x0028) -+#define LVTS_OFFSETH(__base) (__base + 0x0030) -+#define LVTS_OFFSETL(__base) (__base + 0x0034) -+#define LVTS_MSRCTL0(__base) (__base + 0x0038) -+#define LVTS_MSRCTL1(__base) (__base + 0x003C) -+#define LVTS_TSSEL(__base) (__base + 0x0040) -+#define LVTS_CALSCALE(__base) (__base + 0x0048) -+#define LVTS_ID(__base) (__base + 0x004C) -+#define LVTS_CONFIG(__base) (__base + 0x0050) -+#define LVTS_EDATA00(__base) (__base + 0x0054) -+#define LVTS_EDATA01(__base) (__base + 0x0058) -+#define LVTS_EDATA02(__base) (__base + 0x005C) -+#define LVTS_EDATA03(__base) (__base + 0x0060) -+#define LVTS_MSR0(__base) (__base + 0x0090) -+#define LVTS_MSR1(__base) (__base + 0x0094) -+#define LVTS_MSR2(__base) (__base + 0x0098) -+#define LVTS_MSR3(__base) (__base + 0x009C) -+#define LVTS_IMMD0(__base) (__base + 0x00A0) -+#define LVTS_IMMD1(__base) (__base + 0x00A4) -+#define LVTS_IMMD2(__base) (__base + 0x00A8) -+#define LVTS_IMMD3(__base) (__base + 0x00AC) -+#define LVTS_PROTCTL(__base) (__base + 0x00C0) -+#define LVTS_PROTTA(__base) (__base + 0x00C4) -+#define LVTS_PROTTB(__base) (__base + 0x00C8) -+#define LVTS_PROTTC(__base) (__base + 0x00CC) -+#define LVTS_CLKEN(__base) (__base + 0x00E4) -+ -+#define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38)) -+#define LVTS_GROUP_INTERVAL 1 -+#define LVTS_FILTER_INTERVAL 1 -+#define LVTS_SENSOR_INTERVAL 1 -+#define LVTS_HW_FILTER 0x2 -+#define LVTS_TSSEL_CONF 0x13121110 -+#define LVTS_CALSCALE_CONF 0x300 -+#define LVTS_MONINT_CONF 0x9FBF7BDE -+ -+#define LVTS_INT_SENSOR0 0x0009001F -+#define LVTS_INT_SENSOR1 0X000881F0 -+#define LVTS_INT_SENSOR2 0x00247C00 -+#define LVTS_INT_SENSOR3 0x1FC00000 -+ -+#define LVTS_SENSOR_MAX 4 -+#define LVTS_GOLDEN_TEMP_MAX 62 -+#define LVTS_GOLDEN_TEMP_DEFAULT 50 -+#define LVTS_COEFF_A -250460 -+#define LVTS_COEFF_B 250460 -+ -+#define LVTS_MSR_IMMEDIATE_MODE 0 -+#define LVTS_MSR_FILTERED_MODE 1 -+ -+#define LVTS_HW_SHUTDOWN_MT8195 105000 -+ -+static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; -+static int coeff_b = LVTS_COEFF_B; -+ -+struct lvts_sensor_data { -+ int dt_id; -+}; -+ -+struct lvts_ctrl_data { -+ struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; -+ int cal_offset[LVTS_SENSOR_MAX]; -+ int hw_tshut_temp; -+ int num_lvts_sensor; -+ int offset; -+ int mode; -+}; -+ -+struct lvts_data { -+ const struct lvts_ctrl_data *lvts_ctrl; -+ int num_lvts_ctrl; -+}; -+ -+struct lvts_sensor { -+ struct thermal_zone_device *tz; -+ void __iomem *msr; -+ void __iomem *base; -+ int id; -+ int dt_id; -+}; -+ -+struct lvts_ctrl { -+ struct lvts_sensor sensors[LVTS_SENSOR_MAX]; -+ u32 calibration[LVTS_SENSOR_MAX]; -+ u32 hw_tshut_raw_temp; -+ int num_lvts_sensor; -+ int mode; -+ void __iomem *base; -+}; -+ -+struct lvts_domain { -+ struct lvts_ctrl *lvts_ctrl; -+ struct reset_control *reset; -+ struct clk *clk; -+ int num_lvts_ctrl; -+ void __iomem *base; -+ size_t calib_len; -+ u8 *calib; -+#ifdef CONFIG_DEBUG_FS -+ struct dentry *dom_dentry; -+#endif -+}; -+ -+#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS -+ -+#define LVTS_DEBUG_FS_REGS(__reg) \ -+{ \ -+ .name = __stringify(__reg), \ -+ .offset = __reg(0), \ -+} -+ -+static const struct debugfs_reg32 lvts_regs[] = { -+ LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), -+ LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), -+ LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), -+ LVTS_DEBUG_FS_REGS(LVTS_MONINT), -+ LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), -+ LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), -+ LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), -+ LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), -+ LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), -+ LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), -+ LVTS_DEBUG_FS_REGS(LVTS_HTHRE), -+ LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), -+ LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), -+ LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), -+ LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), -+ LVTS_DEBUG_FS_REGS(LVTS_TSSEL), -+ LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), -+ LVTS_DEBUG_FS_REGS(LVTS_ID), -+ LVTS_DEBUG_FS_REGS(LVTS_CONFIG), -+ LVTS_DEBUG_FS_REGS(LVTS_EDATA00), -+ LVTS_DEBUG_FS_REGS(LVTS_EDATA01), -+ LVTS_DEBUG_FS_REGS(LVTS_EDATA02), -+ LVTS_DEBUG_FS_REGS(LVTS_EDATA03), -+ LVTS_DEBUG_FS_REGS(LVTS_MSR0), -+ LVTS_DEBUG_FS_REGS(LVTS_MSR1), -+ LVTS_DEBUG_FS_REGS(LVTS_MSR2), -+ LVTS_DEBUG_FS_REGS(LVTS_MSR3), -+ LVTS_DEBUG_FS_REGS(LVTS_IMMD0), -+ LVTS_DEBUG_FS_REGS(LVTS_IMMD1), -+ LVTS_DEBUG_FS_REGS(LVTS_IMMD2), -+ LVTS_DEBUG_FS_REGS(LVTS_IMMD3), -+ LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), -+ LVTS_DEBUG_FS_REGS(LVTS_PROTTA), -+ LVTS_DEBUG_FS_REGS(LVTS_PROTTB), -+ LVTS_DEBUG_FS_REGS(LVTS_PROTTC), -+ LVTS_DEBUG_FS_REGS(LVTS_CLKEN), -+}; -+ -+static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) -+{ -+ struct debugfs_regset32 *regset; -+ struct lvts_ctrl *lvts_ctrl; -+ struct dentry *dentry; -+ char name[64]; -+ int i; -+ -+ lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); -+ if (!lvts_td->dom_dentry) -+ return 0; -+ -+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { -+ -+ lvts_ctrl = &lvts_td->lvts_ctrl[i]; -+ -+ sprintf(name, "controller%d", i); -+ dentry = debugfs_create_dir(name, lvts_td->dom_dentry); -+ if (!dentry) -+ continue; -+ -+ regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); -+ if (!regset) -+ continue; -+ -+ regset->base = lvts_ctrl->base; -+ regset->regs = lvts_regs; -+ regset->nregs = ARRAY_SIZE(lvts_regs); -+ -+ debugfs_create_regset32("registers", 0400, dentry, regset); -+ } -+ -+ return 0; -+} -+ -+static void lvts_debugfs_exit(struct lvts_domain *lvts_td) -+{ -+ debugfs_remove_recursive(lvts_td->dom_dentry); -+} -+ -+#else -+ -+static inline int lvts_debugfs_init(struct device *dev, -+ struct lvts_domain *lvts_td) -+{ -+ return 0; -+} -+ -+static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } -+ -+#endif -+ -+static int lvts_raw_to_temp(u32 raw_temp) -+{ -+ int temperature; -+ -+ temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; -+ temperature += coeff_b; -+ -+ return temperature; -+} -+ -+static u32 lvts_temp_to_raw(int temperature) -+{ -+ u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; -+ -+ raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); -+ -+ return raw_temp; -+} -+ -+static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) -+{ -+ struct lvts_sensor *lvts_sensor = tz->devdata; -+ void __iomem *msr = lvts_sensor->msr; -+ u32 value; -+ -+ /* -+ * Measurement registers: -+ * -+ * LVTS_MSR[0-3] / LVTS_IMMD[0-3] -+ * -+ * Bits: -+ * -+ * 32-17: Unused -+ * 16 : Valid temperature -+ * 15-0 : Raw temperature -+ */ -+ value = readl(msr); -+ -+ /* -+ * As the thermal zone temperature will read before the -+ * hardware sensor is fully initialized, we have to check the -+ * validity of the temperature returned when reading the -+ * measurement register. The thermal controller will set the -+ * valid bit temperature only when it is totally initialized. -+ * -+ * Otherwise, we may end up with garbage values out of the -+ * functionning temperature and directly jump to a system -+ * shutdown. -+ */ -+ if (!(value & BIT(16))) -+ return -EAGAIN; -+ -+ *temp = lvts_raw_to_temp(value & 0xFFFF); -+ -+ return 0; -+} -+ -+static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) -+{ -+ struct lvts_sensor *lvts_sensor = tz->devdata; -+ void __iomem *base = lvts_sensor->base; -+ u32 raw_low = lvts_temp_to_raw(low); -+ u32 raw_high = lvts_temp_to_raw(high); -+ -+ /* -+ * Hot to normal temperature threshold -+ * -+ * LVTS_H2NTHRE -+ * -+ * Bits: -+ * -+ * 14-0 : Raw temperature for threshold -+ */ -+ if (low != -INT_MAX) { -+ dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low); -+ writel(raw_low, LVTS_H2NTHRE(base)); -+ } -+ -+ /* -+ * Hot temperature threshold -+ * -+ * LVTS_HTHRE -+ * -+ * Bits: -+ * -+ * 14-0 : Raw temperature for threshold -+ */ -+ dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high); -+ writel(raw_high, LVTS_HTHRE(base)); -+ -+ return 0; -+} -+ -+static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) -+{ -+ irqreturn_t iret = IRQ_NONE; -+ u32 value; -+ u32 masks[] = { -+ LVTS_INT_SENSOR0, -+ LVTS_INT_SENSOR1, -+ LVTS_INT_SENSOR2, -+ LVTS_INT_SENSOR3 -+ }; -+ int i; -+ -+ /* -+ * Interrupt monitoring status -+ * -+ * LVTS_MONINTST -+ * -+ * Bits: -+ * -+ * 31 : Interrupt for stage 3 -+ * 30 : Interrupt for stage 2 -+ * 29 : Interrupt for state 1 -+ * 28 : Interrupt using filter on sensor 3 -+ * -+ * 27 : Interrupt using immediate on sensor 3 -+ * 26 : Interrupt normal to hot on sensor 3 -+ * 25 : Interrupt high offset on sensor 3 -+ * 24 : Interrupt low offset on sensor 3 -+ * -+ * 23 : Interrupt hot threshold on sensor 3 -+ * 22 : Interrupt cold threshold on sensor 3 -+ * 21 : Interrupt using filter on sensor 2 -+ * 20 : Interrupt using filter on sensor 1 -+ * -+ * 19 : Interrupt using filter on sensor 0 -+ * 18 : Interrupt using immediate on sensor 2 -+ * 17 : Interrupt using immediate on sensor 1 -+ * 16 : Interrupt using immediate on sensor 0 -+ * -+ * 15 : Interrupt device access timeout interrupt -+ * 14 : Interrupt normal to hot on sensor 2 -+ * 13 : Interrupt high offset interrupt on sensor 2 -+ * 12 : Interrupt low offset interrupt on sensor 2 -+ * -+ * 11 : Interrupt hot threshold on sensor 2 -+ * 10 : Interrupt cold threshold on sensor 2 -+ * 9 : Interrupt normal to hot on sensor 1 -+ * 8 : Interrupt high offset interrupt on sensor 1 -+ * -+ * 7 : Interrupt low offset interrupt on sensor 1 -+ * 6 : Interrupt hot threshold on sensor 1 -+ * 5 : Interrupt cold threshold on sensor 1 -+ * 4 : Interrupt normal to hot on sensor 0 -+ * -+ * 3 : Interrupt high offset interrupt on sensor 0 -+ * 2 : Interrupt low offset interrupt on sensor 0 -+ * 1 : Interrupt hot threshold on sensor 0 -+ * 0 : Interrupt cold threshold on sensor 0 -+ * -+ * We are interested in the sensor(s) responsible of the -+ * interrupt event. We update the thermal framework with the -+ * thermal zone associated with the sensor. The framework will -+ * take care of the rest whatever the kind of interrupt, we -+ * are only interested in which sensor raised the interrupt. -+ * -+ * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 -+ * => 0x1FC00000 -+ * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 -+ * => 0x00247C00 -+ * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000 -+ * => 0X000881F0 -+ * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 -+ * => 0x0009001F -+ */ -+ value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); -+ -+ /* -+ * Let's figure out which sensors raised the interrupt -+ * -+ * NOTE: the masks array must be ordered with the index -+ * corresponding to the sensor id eg. index=0, mask for -+ * sensor0. -+ */ -+ for (i = 0; i < ARRAY_SIZE(masks); i++) { -+ -+ if (!(value & masks[i])) -+ continue; -+ -+ thermal_zone_device_update(lvts_ctrl->sensors[i].tz, -+ THERMAL_TRIP_VIOLATED); -+ iret = IRQ_HANDLED; -+ } -+ -+ /* -+ * Write back to clear the interrupt status (W1C) -+ */ -+ writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); -+ -+ return iret; -+} -+ -+/* -+ * Temperature interrupt handler. Even if the driver supports more -+ * interrupt modes, we use the interrupt when the temperature crosses -+ * the hot threshold the way up and the way down (modulo the -+ * hysteresis). -+ * -+ * Each thermal domain has a couple of interrupts, one for hardware -+ * reset and another one for all the thermal events happening on the -+ * different sensors. -+ * -+ * The interrupt is configured for thermal events when crossing the -+ * hot temperature limit. At each interrupt, we check in every -+ * controller if there is an interrupt pending. -+ */ -+static irqreturn_t lvts_irq_handler(int irq, void *data) -+{ -+ struct lvts_domain *lvts_td = data; -+ irqreturn_t aux, iret = IRQ_NONE; -+ int i; -+ -+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { -+ -+ aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl); -+ if (aux != IRQ_HANDLED) -+ continue; -+ -+ iret = IRQ_HANDLED; -+ } -+ -+ return iret; -+} -+ -+static struct thermal_zone_device_ops lvts_ops = { -+ .get_temp = lvts_get_temp, -+ .set_trips = lvts_set_trips, -+}; -+ -+static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, -+ const struct lvts_ctrl_data *lvts_ctrl_data) -+{ -+ struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; -+ void __iomem *msr_regs[] = { -+ LVTS_MSR0(lvts_ctrl->base), -+ LVTS_MSR1(lvts_ctrl->base), -+ LVTS_MSR2(lvts_ctrl->base), -+ LVTS_MSR3(lvts_ctrl->base) -+ }; -+ -+ void __iomem *imm_regs[] = { -+ LVTS_IMMD0(lvts_ctrl->base), -+ LVTS_IMMD1(lvts_ctrl->base), -+ LVTS_IMMD2(lvts_ctrl->base), -+ LVTS_IMMD3(lvts_ctrl->base) -+ }; -+ -+ int i; -+ -+ for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { -+ -+ int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; -+ -+ /* -+ * At this point, we don't know which id matches which -+ * sensor. Let's set arbitrally the id from the index. -+ */ -+ lvts_sensor[i].id = i; -+ -+ /* -+ * The thermal zone registration will set the trip -+ * point interrupt in the thermal controller -+ * register. But this one will be reset in the -+ * initialization after. So we need to post pone the -+ * thermal zone creation after the controller is -+ * setup. For this reason, we store the device tree -+ * node id from the data in the sensor structure -+ */ -+ lvts_sensor[i].dt_id = dt_id; -+ -+ /* -+ * We assign the base address of the thermal -+ * controller as a back pointer. So it will be -+ * accessible from the different thermal framework ops -+ * as we pass the lvts_sensor pointer as thermal zone -+ * private data. -+ */ -+ lvts_sensor[i].base = lvts_ctrl->base; -+ -+ /* -+ * Each sensor has its own register address to read from. -+ */ -+ lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? -+ imm_regs[i] : msr_regs[i]; -+ }; -+ -+ lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; -+ -+ return 0; -+} -+ -+/* -+ * The efuse blob values follows the sensor enumeration per thermal -+ * controller. The decoding of the stream is as follow: -+ * -+ * <--?-> <----big0 ???---> <-sensor0-> <-0-> -+ * ------------------------------------------ -+ * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 | -+ * ------------------------------------------ -+ * -+ * <--sensor1--><-0-> <----big1 ???---> <-sen -+ * ------------------------------------------ -+ * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | -+ * ------------------------------------------ -+ * -+ * sor0-> <-0-> <-sensor1-> <-0-> .......... -+ * ------------------------------------------ -+ * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | -+ * ------------------------------------------ -+ * -+ * And so on ... -+ * -+ * The data description gives the offset of the calibration data in -+ * this bytes stream for each sensor. -+ * -+ * Each thermal controller can handle up to 4 sensors max, we don't -+ * care if there are less as the array of calibration is sized to 4 -+ * anyway. The unused sensor slot will be zeroed. -+ */ -+static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, -+ const struct lvts_ctrl_data *lvts_ctrl_data, -+ u8 *efuse_calibration) -+{ -+ int i; -+ -+ for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) -+ memcpy(&lvts_ctrl->calibration[i], -+ efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); -+ -+ return 0; -+} -+ -+/* -+ * The efuse bytes stream can be split into different chunk of -+ * nvmems. This function reads and concatenate those into a single -+ * buffer so it can be read sequentially when initializing the -+ * calibration data. -+ */ -+static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, -+ const struct lvts_data *lvts_data) -+{ -+ struct device_node *np = dev_of_node(dev); -+ struct nvmem_cell *cell; -+ struct property *prop; -+ const char *cell_name; -+ -+ of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { -+ size_t len; -+ u8 *efuse; -+ -+ cell = of_nvmem_cell_get(np, cell_name); -+ if (IS_ERR(cell)) { -+ dev_err(dev, "Failed to get cell '%s'\n", cell_name); -+ return PTR_ERR(cell); -+ } -+ -+ efuse = nvmem_cell_read(cell, &len); -+ -+ nvmem_cell_put(cell); -+ -+ if (IS_ERR(efuse)) { -+ dev_err(dev, "Failed to read cell '%s'\n", cell_name); -+ return PTR_ERR(efuse); -+ } -+ -+ lvts_td->calib = devm_krealloc(dev, lvts_td->calib, -+ lvts_td->calib_len + len, GFP_KERNEL); -+ if (!lvts_td->calib) -+ return -ENOMEM; -+ -+ memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); -+ -+ lvts_td->calib_len += len; -+ -+ kfree(efuse); -+ } -+ -+ return 0; -+} -+ -+static int lvts_golden_temp_init(struct device *dev, u32 *value) -+{ -+ u32 gt; -+ -+ gt = (*value) >> 24; -+ -+ if (gt && gt < LVTS_GOLDEN_TEMP_MAX) -+ golden_temp = gt; -+ -+ coeff_b = golden_temp * 500 + LVTS_COEFF_B; -+ -+ return 0; -+} -+ -+static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, -+ const struct lvts_data *lvts_data) -+{ -+ size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; -+ struct lvts_ctrl *lvts_ctrl; -+ int i, ret; -+ -+ /* -+ * Create the calibration bytes stream from efuse data -+ */ -+ ret = lvts_calibration_read(dev, lvts_td, lvts_data); -+ if (ret) -+ return ret; -+ -+ /* -+ * The golden temp information is contained in the first chunk -+ * of efuse data. -+ */ -+ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); -+ if (ret) -+ return ret; -+ -+ lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); -+ if (!lvts_ctrl) -+ return -ENOMEM; -+ -+ for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { -+ -+ lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; -+ -+ ret = lvts_sensor_init(dev, &lvts_ctrl[i], -+ &lvts_data->lvts_ctrl[i]); -+ if (ret) -+ return ret; -+ -+ ret = lvts_calibration_init(dev, &lvts_ctrl[i], -+ &lvts_data->lvts_ctrl[i], -+ lvts_td->calib); -+ if (ret) -+ return ret; -+ -+ /* -+ * The mode the ctrl will use to read the temperature -+ * (filtered or immediate) -+ */ -+ lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; -+ -+ /* -+ * The temperature to raw temperature must be done -+ * after initializing the calibration. -+ */ -+ lvts_ctrl[i].hw_tshut_raw_temp = -+ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); -+ } -+ -+ /* -+ * We no longer need the efuse bytes stream, let's free it -+ */ -+ devm_kfree(dev, lvts_td->calib); -+ -+ lvts_td->lvts_ctrl = lvts_ctrl; -+ lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; -+ -+ return 0; -+} -+ -+/* -+ * At this point the configuration register is the only place in the -+ * driver where we write multiple values. Per hardware constraint, -+ * each write in the configuration register must be separated by a -+ * delay of 2 us. -+ */ -+static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) -+{ -+ int i; -+ -+ /* -+ * Configuration register -+ */ -+ for (i = 0; i < nr_cmds; i++) { -+ writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); -+ usleep_range(2, 4); -+ } -+} -+ -+static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) -+{ -+ /* -+ * LVTS_PROTCTL : Thermal Protection Sensor Selection -+ * -+ * Bits: -+ * -+ * 19-18 : Sensor to base the protection on -+ * 17-16 : Strategy: -+ * 00 : Average of 4 sensors -+ * 01 : Max of 4 sensors -+ * 10 : Selected sensor with bits 19-18 -+ * 11 : Reserved -+ */ -+ writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); -+ -+ /* -+ * LVTS_PROTTA : Stage 1 temperature threshold -+ * LVTS_PROTTB : Stage 2 temperature threshold -+ * LVTS_PROTTC : Stage 3 temperature threshold -+ * -+ * Bits: -+ * -+ * 14-0: Raw temperature threshold -+ * -+ * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); -+ * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); -+ */ -+ writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); -+ -+ /* -+ * LVTS_MONINT : Interrupt configuration register -+ * -+ * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS -+ * register, except we set the bits to enable the interrupt. -+ */ -+ writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); -+ -+ return 0; -+} -+ -+static int lvts_domain_reset(struct device *dev, struct reset_control *reset) -+{ -+ int ret; -+ -+ ret = reset_control_assert(reset); -+ if (ret) -+ return ret; -+ -+ return reset_control_deassert(reset); -+} -+ -+/* -+ * Enable or disable the clocks of a specified thermal controller -+ */ -+static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) -+{ -+ /* -+ * LVTS_CLKEN : Internal LVTS clock -+ * -+ * Bits: -+ * -+ * 0 : enable / disable clock -+ */ -+ writel(enable, LVTS_CLKEN(lvts_ctrl->base)); -+ -+ return 0; -+} -+ -+static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) -+{ -+ u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; -+ -+ lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); -+ -+ /* -+ * LVTS_ID : Get ID and status of the thermal controller -+ * -+ * Bits: -+ * -+ * 0-5 : thermal controller id -+ * 7 : thermal controller connection is valid -+ */ -+ id = readl(LVTS_ID(lvts_ctrl->base)); -+ if (!(id & BIT(7))) -+ return -EIO; -+ -+ return 0; -+} -+ -+static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) -+{ -+ /* -+ * Write device mask: 0xC1030000 -+ */ -+ u32 cmds[] = { -+ 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, -+ 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, -+ 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, -+ 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 -+ }; -+ -+ lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); -+ -+ return 0; -+} -+ -+static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) -+{ -+ int i; -+ void __iomem *lvts_edata[] = { -+ LVTS_EDATA00(lvts_ctrl->base), -+ LVTS_EDATA01(lvts_ctrl->base), -+ LVTS_EDATA02(lvts_ctrl->base), -+ LVTS_EDATA03(lvts_ctrl->base) -+ }; -+ -+ /* -+ * LVTS_EDATA0X : Efuse calibration reference value for sensor X -+ * -+ * Bits: -+ * -+ * 20-0 : Efuse value for normalization data -+ */ -+ for (i = 0; i < LVTS_SENSOR_MAX; i++) -+ writel(lvts_ctrl->calibration[i], lvts_edata[i]); -+ -+ return 0; -+} -+ -+static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) -+{ -+ u32 value; -+ -+ /* -+ * LVTS_TSSEL : Sensing point index numbering -+ * -+ * Bits: -+ * -+ * 31-24: ADC Sense 3 -+ * 23-16: ADC Sense 2 -+ * 15-8 : ADC Sense 1 -+ * 7-0 : ADC Sense 0 -+ */ -+ value = LVTS_TSSEL_CONF; -+ writel(value, LVTS_TSSEL(lvts_ctrl->base)); -+ -+ /* -+ * LVTS_CALSCALE : ADC voltage round -+ */ -+ value = 0x300; -+ value = LVTS_CALSCALE_CONF; -+ -+ /* -+ * LVTS_MSRCTL0 : Sensor filtering strategy -+ * -+ * Filters: -+ * -+ * 000 : One sample -+ * 001 : Avg 2 samples -+ * 010 : 4 samples, drop min and max, avg 2 samples -+ * 011 : 6 samples, drop min and max, avg 4 samples -+ * 100 : 10 samples, drop min and max, avg 8 samples -+ * 101 : 18 samples, drop min and max, avg 16 samples -+ * -+ * Bits: -+ * -+ * 0-2 : Sensor0 filter -+ * 3-5 : Sensor1 filter -+ * 6-8 : Sensor2 filter -+ * 9-11 : Sensor3 filter -+ */ -+ value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | -+ LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; -+ writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); -+ -+ /* -+ * LVTS_MSRCTL1 : Measurement control -+ * -+ * Bits: -+ * -+ * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 -+ * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 -+ * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 -+ * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 -+ * -+ * That configuration will ignore the filtering and the delays -+ * introduced below in MONCTL1 and MONCTL2 -+ */ -+ if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { -+ value = BIT(9) | BIT(6) | BIT(5) | BIT(4); -+ writel(value, LVTS_MSRCTL1(lvts_ctrl->base)); -+ } -+ -+ /* -+ * LVTS_MONCTL1 : Period unit and group interval configuration -+ * -+ * The clock source of LVTS thermal controller is 26MHz. -+ * -+ * The period unit is a time base for all the interval delays -+ * specified in the registers. By default we use 12. The time -+ * conversion is done by multiplying by 256 and 1/26.10^6 -+ * -+ * An interval delay multiplied by the period unit gives the -+ * duration in seconds. -+ * -+ * - Filter interval delay is a delay between two samples of -+ * the same sensor. -+ * -+ * - Sensor interval delay is a delay between two samples of -+ * different sensors. -+ * -+ * - Group interval delay is a delay between different rounds. -+ * -+ * For example: -+ * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, -+ * and two sensors, TS1 and TS2, are in a LVTS thermal controller -+ * and then -+ * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us -+ * Filter interval delay = 1 * Period unit = 118.149us -+ * Sensor interval delay = 2 * Period unit = 236.298us -+ * Group interval delay = 1 * Period unit = 118.149us -+ * -+ * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... -+ * <--> Filter interval delay -+ * <--> Sensor interval delay -+ * <--> Group interval delay -+ * Bits: -+ * 29 - 20 : Group interval -+ * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) -+ * or an interrupt everytime the hot threshold is crossed (0) -+ * 9 - 0 : Period unit -+ * -+ */ -+ value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; -+ writel(value, LVTS_MONCTL1(lvts_ctrl->base)); -+ -+ /* -+ * LVTS_MONCTL2 : Filtering and sensor interval -+ * -+ * Bits: -+ * -+ * 25-16 : Interval unit in PERIOD_UNIT between sample on -+ * the same sensor, filter interval -+ * 9-0 : Interval unit in PERIOD_UNIT between each sensor -+ * -+ */ -+ value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; -+ writel(value, LVTS_MONCTL2(lvts_ctrl->base)); -+ -+ return lvts_irq_init(lvts_ctrl); -+} -+ -+static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) -+{ -+ struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; -+ struct thermal_zone_device *tz; -+ u32 sensor_map = 0; -+ int i; -+ -+ for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { -+ -+ int dt_id = lvts_sensors[i].dt_id; -+ -+ tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], -+ &lvts_ops); -+ if (IS_ERR(tz)) { -+ /* -+ * This thermal zone is not described in the -+ * device tree. It is not an error from the -+ * thermal OF code POV, we just continue. -+ */ -+ if (PTR_ERR(tz) == -ENODEV) -+ continue; -+ -+ return PTR_ERR(tz); -+ } -+ -+ /* -+ * The thermal zone pointer will be needed in the -+ * interrupt handler, we store it in the sensor -+ * structure. The thermal domain structure will be -+ * passed to the interrupt handler private data as the -+ * interrupt is shared for all the controller -+ * belonging to the thermal domain. -+ */ -+ lvts_sensors[i].tz = tz; -+ -+ /* -+ * This sensor was correctly associated with a thermal -+ * zone, let's set the corresponding bit in the sensor -+ * map, so we can enable the temperature monitoring in -+ * the hardware thermal controller. -+ */ -+ sensor_map |= BIT(i); -+ } -+ -+ /* -+ * Bits: -+ * 9: Single point access flow -+ * 0-3: Enable sensing point 0-3 -+ * -+ * The initialization of the thermal zones give us -+ * which sensor point to enable. If any thermal zone -+ * was not described in the device tree, it won't be -+ * enabled here in the sensor map. -+ */ -+ writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); -+ -+ return 0; -+} -+ -+static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, -+ const struct lvts_data *lvts_data) -+{ -+ struct lvts_ctrl *lvts_ctrl; -+ int i, ret; -+ -+ ret = lvts_ctrl_init(dev, lvts_td, lvts_data); -+ if (ret) -+ return ret; -+ -+ ret = lvts_domain_reset(dev, lvts_td->reset); -+ if (ret) { -+ dev_dbg(dev, "Failed to reset domain"); -+ return ret; -+ } -+ -+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { -+ -+ lvts_ctrl = &lvts_td->lvts_ctrl[i]; -+ -+ /* -+ * Initialization steps: -+ * -+ * - Enable the clock -+ * - Connect to the LVTS -+ * - Initialize the LVTS -+ * - Prepare the calibration data -+ * - Select monitored sensors -+ * [ Configure sampling ] -+ * [ Configure the interrupt ] -+ * - Start measurement -+ */ -+ ret = lvts_ctrl_set_enable(lvts_ctrl, true); -+ if (ret) { -+ dev_dbg(dev, "Failed to enable LVTS clock"); -+ return ret; -+ } -+ -+ ret = lvts_ctrl_connect(dev, lvts_ctrl); -+ if (ret) { -+ dev_dbg(dev, "Failed to connect to LVTS controller"); -+ return ret; -+ } -+ -+ ret = lvts_ctrl_initialize(dev, lvts_ctrl); -+ if (ret) { -+ dev_dbg(dev, "Failed to initialize controller"); -+ return ret; -+ } -+ -+ ret = lvts_ctrl_calibrate(dev, lvts_ctrl); -+ if (ret) { -+ dev_dbg(dev, "Failed to calibrate controller"); -+ return ret; -+ } -+ -+ ret = lvts_ctrl_configure(dev, lvts_ctrl); -+ if (ret) { -+ dev_dbg(dev, "Failed to configure controller"); -+ return ret; -+ } -+ -+ ret = lvts_ctrl_start(dev, lvts_ctrl); -+ if (ret) { -+ dev_dbg(dev, "Failed to start controller"); -+ return ret; -+ } -+ } -+ -+ return lvts_debugfs_init(dev, lvts_td); -+} -+ -+static int lvts_probe(struct platform_device *pdev) -+{ -+ const struct lvts_data *lvts_data; -+ struct lvts_domain *lvts_td; -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ int irq, ret; -+ -+ lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); -+ if (!lvts_td) -+ return -ENOMEM; -+ -+ lvts_data = of_device_get_match_data(dev); -+ -+ lvts_td->clk = devm_clk_get_enabled(dev, NULL); -+ if (IS_ERR(lvts_td->clk)) -+ return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); -+ -+ res = platform_get_mem_or_io(pdev, 0); -+ if (!res) -+ return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); -+ -+ lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); -+ if (IS_ERR(lvts_td->base)) -+ return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); -+ -+ lvts_td->reset = devm_reset_control_get_by_index(dev, 0); -+ if (IS_ERR(lvts_td->reset)) -+ return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return dev_err_probe(dev, irq, "No irq resource\n"); -+ -+ ret = lvts_domain_init(dev, lvts_td, lvts_data); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); -+ -+ /* -+ * At this point the LVTS is initialized and enabled. We can -+ * safely enable the interrupt. -+ */ -+ ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, -+ IRQF_ONESHOT, dev_name(dev), lvts_td); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to request interrupt\n"); -+ -+ platform_set_drvdata(pdev, lvts_td); -+ -+ return 0; -+} -+ -+static int lvts_remove(struct platform_device *pdev) -+{ -+ struct lvts_domain *lvts_td; -+ int i; -+ -+ lvts_td = platform_get_drvdata(pdev); -+ -+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) -+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); -+ -+ lvts_debugfs_exit(lvts_td); -+ -+ return 0; -+} -+ -+static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = { -+ { -+ .cal_offset = { 0x04, 0x07 }, -+ .lvts_sensor = { -+ { .dt_id = MT8195_MCU_BIG_CPU0 }, -+ { .dt_id = MT8195_MCU_BIG_CPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x0, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, -+ }, -+ { -+ .cal_offset = { 0x0d, 0x10 }, -+ .lvts_sensor = { -+ { .dt_id = MT8195_MCU_BIG_CPU2 }, -+ { .dt_id = MT8195_MCU_BIG_CPU3 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x100, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, -+ }, -+ { -+ .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, -+ .lvts_sensor = { -+ { .dt_id = MT8195_MCU_LITTLE_CPU0 }, -+ { .dt_id = MT8195_MCU_LITTLE_CPU1 }, -+ { .dt_id = MT8195_MCU_LITTLE_CPU2 }, -+ { .dt_id = MT8195_MCU_LITTLE_CPU3 } -+ }, -+ .num_lvts_sensor = 4, -+ .offset = 0x200, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, -+ } -+}; -+ -+static const struct lvts_data mt8195_lvts_mcu_data = { -+ .lvts_ctrl = mt8195_lvts_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl), -+}; -+ -+static const struct of_device_id lvts_of_match[] = { -+ { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, lvts_of_match); -+ -+static struct platform_driver lvts_driver = { -+ .probe = lvts_probe, -+ .remove = lvts_remove, -+ .driver = { -+ .name = "mtk-lvts-thermal", -+ .of_match_table = lvts_of_match, -+ }, -+}; -+module_platform_driver(lvts_driver); -+ -+MODULE_AUTHOR("Balsam CHIHI "); -+MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch deleted file mode 100644 index b6a5f64090111f..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-07-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch +++ /dev/null @@ -1,186 +0,0 @@ -From 498e2f7a6e69dcbca24715de2b4b97569fdfeff4 Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Thu, 9 Feb 2023 11:56:24 +0100 -Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controllers - -Add LVTS thermal controllers dt-binding definition for mt8192 and mt8195. - -Signed-off-by: Balsam CHIHI -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20230209105628.50294-3-bchihi@baylibre.com -Signed-off-by: Daniel Lezcano -Signed-off-by: Rafael J. Wysocki ---- - .../thermal/mediatek,lvts-thermal.yaml | 142 ++++++++++++++++++ - .../thermal/mediatek,lvts-thermal.h | 19 +++ - 2 files changed, 161 insertions(+) - create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml - create mode 100644 include/dt-bindings/thermal/mediatek,lvts-thermal.h - ---- /dev/null -+++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml -@@ -0,0 +1,142 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek SoC Low Voltage Thermal Sensor (LVTS) -+ -+maintainers: -+ - Balsam CHIHI -+ -+description: | -+ LVTS is a thermal management architecture composed of three subsystems, -+ a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU), -+ a Converter - Low Voltage Thermal Sensor converter (LVTS), and -+ a Digital controller (LVTS_CTRL). -+ -+properties: -+ compatible: -+ enum: -+ - mediatek,mt8192-lvts-ap -+ - mediatek,mt8192-lvts-mcu -+ - mediatek,mt8195-lvts-ap -+ - mediatek,mt8195-lvts-mcu -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 1 -+ -+ resets: -+ maxItems: 1 -+ description: LVTS reset for clearing temporary data on AP/MCU. -+ -+ nvmem-cells: -+ minItems: 1 -+ items: -+ - description: Calibration eFuse data 1 for LVTS -+ - description: Calibration eFuse data 2 for LVTS -+ -+ nvmem-cell-names: -+ minItems: 1 -+ items: -+ - const: lvts-calib-data-1 -+ - const: lvts-calib-data-2 -+ -+ "#thermal-sensor-cells": -+ const: 1 -+ -+allOf: -+ - $ref: thermal-sensor.yaml# -+ -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - mediatek,mt8192-lvts-ap -+ - mediatek,mt8192-lvts-mcu -+ then: -+ properties: -+ nvmem-cells: -+ maxItems: 1 -+ -+ nvmem-cell-names: -+ maxItems: 1 -+ -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - mediatek,mt8195-lvts-ap -+ - mediatek,mt8195-lvts-mcu -+ then: -+ properties: -+ nvmem-cells: -+ minItems: 2 -+ -+ nvmem-cell-names: -+ minItems: 2 -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - resets -+ - nvmem-cells -+ - nvmem-cell-names -+ - "#thermal-sensor-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ lvts_mcu: thermal-sensor@11278000 { -+ compatible = "mediatek,mt8195-lvts-mcu"; -+ reg = <0 0x11278000 0 0x1000>; -+ interrupts = ; -+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; -+ resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; -+ nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; -+ nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; -+ #thermal-sensor-cells = <1>; -+ }; -+ }; -+ -+ thermal_zones: thermal-zones { -+ cpu0-thermal { -+ polling-delay = <1000>; -+ polling-delay-passive = <250>; -+ thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; -+ -+ trips { -+ cpu0_alert: trip-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu0_crit: trip-crit { -+ temperature = <100000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; ---- /dev/null -+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h -@@ -0,0 +1,19 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2023 MediaTek Inc. -+ * Author: Balsam CHIHI -+ */ -+ -+#ifndef __MEDIATEK_LVTS_DT_H -+#define __MEDIATEK_LVTS_DT_H -+ -+#define MT8195_MCU_BIG_CPU0 0 -+#define MT8195_MCU_BIG_CPU1 1 -+#define MT8195_MCU_BIG_CPU2 2 -+#define MT8195_MCU_BIG_CPU3 3 -+#define MT8195_MCU_LITTLE_CPU0 4 -+#define MT8195_MCU_LITTLE_CPU1 5 -+#define MT8195_MCU_LITTLE_CPU2 6 -+#define MT8195_MCU_LITTLE_CPU3 7 -+ -+#endif /* __MEDIATEK_LVTS_DT_H */ diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch deleted file mode 100644 index efb0d8b64fb3ba..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-08-dt-bindings-thermal-mediatek-Add-AP-domain-to-LVTS-t.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 05aaa7fdb0736262e224369b9b9f1410320fc71b Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 7 Mar 2023 16:45:21 +0100 -Subject: [PATCH] dt-bindings: thermal: mediatek: Add AP domain to LVTS thermal - controllers for mt8195 - -Add AP Domain to LVTS thermal controllers dt-binding definition for mt8195. - -Signed-off-by: Balsam CHIHI -Acked-by: Rob Herring -Reviewed-by: AngeloGioacchino Del Regno -Tested-by: Chen-Yu Tsai -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230307154524.118541-2-bchihi@baylibre.com ---- - include/dt-bindings/thermal/mediatek,lvts-thermal.h | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h -+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h -@@ -16,4 +16,14 @@ - #define MT8195_MCU_LITTLE_CPU2 6 - #define MT8195_MCU_LITTLE_CPU3 7 - -+#define MT8195_AP_VPU0 8 -+#define MT8195_AP_VPU1 9 -+#define MT8195_AP_GPU0 10 -+#define MT8195_AP_GPU1 11 -+#define MT8195_AP_VDEC 12 -+#define MT8195_AP_IMG 13 -+#define MT8195_AP_INFRA 14 -+#define MT8195_AP_CAM0 15 -+#define MT8195_AP_CAM1 16 -+ - #endif /* __MEDIATEK_LVTS_DT_H */ diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch deleted file mode 100644 index c68969321e5a51..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-09-thermal-core-Add-a-thermal-zone-devdata-accessor.patch +++ /dev/null @@ -1,65 +0,0 @@ -From a6ff3c0021468721b96e84892a8cae24bde8d65f Mon Sep 17 00:00:00 2001 -From: Daniel Lezcano -Date: Wed, 1 Mar 2023 21:14:29 +0100 -Subject: [PATCH] thermal/core: Add a thermal zone 'devdata' accessor - -The thermal zone device structure is exposed to the different drivers -and obviously they access the internals while that should be -restricted to the core thermal code. - -In order to self-encapsulate the thermal core code, we need to prevent -the drivers accessing directly the thermal zone structure and provide -accessor functions to deal with. - -Provide an accessor to the 'devdata' structure and make use of it in -the different drivers. - -No functional changes intended. - -Signed-off-by: Daniel Lezcano -Acked-by: Rafael J. Wysocki -Acked-by: Mark Brown -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/thermal_core.c | 6 ++++++ - include/linux/thermal.h | 7 +++++++ - 2 files changed, 13 insertions(+) - ---- a/drivers/thermal/thermal_core.c -+++ b/drivers/thermal/thermal_core.c -@@ -1346,6 +1346,12 @@ struct thermal_zone_device *thermal_zone - } - EXPORT_SYMBOL_GPL(thermal_zone_device_register); - -+void *thermal_zone_device_priv(struct thermal_zone_device *tzd) -+{ -+ return tzd->devdata; -+} -+EXPORT_SYMBOL_GPL(thermal_zone_device_priv); -+ - /** - * thermal_zone_device_unregister - removes the registered thermal zone device - * @tz: the thermal zone device to remove ---- a/include/linux/thermal.h -+++ b/include/linux/thermal.h -@@ -346,6 +346,8 @@ thermal_zone_device_register_with_trips( - void *, struct thermal_zone_device_ops *, - struct thermal_zone_params *, int, int); - -+void *thermal_zone_device_priv(struct thermal_zone_device *tzd); -+ - int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int, - struct thermal_cooling_device *, - unsigned long, unsigned long, -@@ -417,6 +419,11 @@ static inline int thermal_zone_get_offse - struct thermal_zone_device *tz) - { return -ENODEV; } - -+static inline void *thermal_zone_device_priv(struct thermal_zone_device *tz) -+{ -+ return NULL; -+} -+ - static inline int thermal_zone_device_enable(struct thermal_zone_device *tz) - { return -ENODEV; } - diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch deleted file mode 100644 index 66d3c9e302891f..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-10-thermal-core-Add-thermal_zone_device-structure-type-.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 072e35c98806100182c0a7263cf4cba09ce43463 Mon Sep 17 00:00:00 2001 -From: Daniel Lezcano -Date: Wed, 1 Mar 2023 21:14:38 +0100 -Subject: [PATCH] thermal/core: Add thermal_zone_device structure 'type' - accessor - -The thermal zone device structure is exposed via the exported -thermal.h header. This structure should stay private the thermal core -code. In order to encapsulate the structure, let's add an accessor to -get the 'type' of the thermal zone. - -Signed-off-by: Daniel Lezcano -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/thermal_core.c | 6 ++++++ - include/linux/thermal.h | 6 ++++++ - 2 files changed, 12 insertions(+) - ---- a/drivers/thermal/thermal_core.c -+++ b/drivers/thermal/thermal_core.c -@@ -1352,6 +1352,12 @@ void *thermal_zone_device_priv(struct th - } - EXPORT_SYMBOL_GPL(thermal_zone_device_priv); - -+const char *thermal_zone_device_type(struct thermal_zone_device *tzd) -+{ -+ return tzd->type; -+} -+EXPORT_SYMBOL_GPL(thermal_zone_device_type); -+ - /** - * thermal_zone_device_unregister - removes the registered thermal zone device - * @tz: the thermal zone device to remove ---- a/include/linux/thermal.h -+++ b/include/linux/thermal.h -@@ -347,6 +347,7 @@ thermal_zone_device_register_with_trips( - struct thermal_zone_params *, int, int); - - void *thermal_zone_device_priv(struct thermal_zone_device *tzd); -+const char *thermal_zone_device_type(struct thermal_zone_device *tzd); - - int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int, - struct thermal_cooling_device *, -@@ -423,6 +424,11 @@ static inline void *thermal_zone_device_ - { - return NULL; - } -+ -+static inline const char *thermal_zone_device_type(struct thermal_zone_device *tzd) -+{ -+ return NULL; -+} - - static inline int thermal_zone_device_enable(struct thermal_zone_device *tz) - { return -ENODEV; } diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch b/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch deleted file mode 100644 index 57bc910d3e3cc4..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-11-thermal-core-Use-the-thermal-zone-devdata-accessor-i.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 7d78bab533eb9aa0e5240e25a204e8f416723ed6 Mon Sep 17 00:00:00 2001 -From: Daniel Lezcano -Date: Wed, 1 Mar 2023 21:14:30 +0100 -Subject: [PATCH 07/42] thermal/core: Use the thermal zone 'devdata' accessor - in thermal located drivers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The thermal zone device structure is exposed to the different drivers -and obviously they access the internals while that should be -restricted to the core thermal code. - -In order to self-encapsulate the thermal core code, we need to prevent -the drivers accessing directly the thermal zone structure and provide -accessor functions to deal with. - -Use the devdata accessor introduced in the previous patch. - -No functional changes intended. - -[skipped drivers not relevant for mediatek target] - -Signed-off-by: Daniel Lezcano -Reviewed-by: Niklas Söderlund #R-Car -Acked-by: Mark Brown -Reviewed-by: AngeloGioacchino Del Regno #MediaTek auxadc and lvts -Reviewed-by: Balsam CHIHI #Mediatek lvts -Reviewed-by: Adam Ward #da9062 -Reviewed-by: Baolin Wang #spread -Acked-by: Jernej Skrabec #sun8i_thermal -Acked-by: Rafael J. Wysocki -Acked-by: Florian Fainelli #Broadcom -Reviewed-by: Dhruva Gole # K3 bandgap -Acked-by: Linus Walleij -Acked-by: Heiko Stuebner #rockchip -Reviewed-by: Kunihiko Hayashi #uniphier -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/mediatek/auxadc_thermal.c | 2 +- - drivers/thermal/mediatek/lvts_thermal.c | 4 ++-- - 43 files changed, 71 insertions(+), 73 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -763,7 +763,7 @@ static int mtk_thermal_bank_temperature( - - static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) - { -- struct mtk_thermal *mt = tz->devdata; -+ struct mtk_thermal *mt = thermal_zone_device_priv(tz); - int i; - int tempmax = INT_MIN; - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -252,7 +252,7 @@ static u32 lvts_temp_to_raw(int temperat - - static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) - { -- struct lvts_sensor *lvts_sensor = tz->devdata; -+ struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); - void __iomem *msr = lvts_sensor->msr; - u32 value; - -@@ -290,7 +290,7 @@ static int lvts_get_temp(struct thermal_ - - static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) - { -- struct lvts_sensor *lvts_sensor = tz->devdata; -+ struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); - void __iomem *base = lvts_sensor->base; - u32 raw_low = lvts_temp_to_raw(low); - u32 raw_high = lvts_temp_to_raw(high); diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch b/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch deleted file mode 100644 index 647b3b0eca11a4..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-12-thermal-hwmon-Use-the-right-device-for-devm_thermal_.patch +++ /dev/null @@ -1,201 +0,0 @@ -From cc9c60e9cfeeac45d63361fa8c085c43c4bdfe3a Mon Sep 17 00:00:00 2001 -From: Daniel Lezcano -Date: Wed, 1 Mar 2023 21:14:36 +0100 -Subject: [PATCH 08/42] thermal/hwmon: Use the right device for - devm_thermal_add_hwmon_sysfs() - -The devres variant of thermal_add_hwmon_sysfs() only takes the thermal -zone structure pointer as parameter. - -Actually, it uses the tz->device to add it in the devres list. - -It is preferable to use the device registering the thermal zone -instead of the thermal zone device itself. That prevents the driver -accessing the thermal zone structure internals and it is from my POV -more correct regarding how devm_ is used. - -[skipped imx thermal which did not apply cleanly and irrelevant on -mediatek target] - -Signed-off-by: Daniel Lezcano -Acked-by: Martin Blumenstingl #amlogic_thermal -Acked-by: Jernej Skrabec #sun8i_thermal -Reviewed-by: AngeloGioacchino Del Regno #MediaTek auxadc -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/amlogic_thermal.c | 2 +- - drivers/thermal/imx_sc_thermal.c | 2 +- - drivers/thermal/k3_bandgap.c | 2 +- - drivers/thermal/mediatek/auxadc_thermal.c | 2 +- - drivers/thermal/qcom/qcom-spmi-adc-tm5.c | 2 +- - drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 2 +- - drivers/thermal/qcom/tsens.c | 2 +- - drivers/thermal/qoriq_thermal.c | 2 +- - drivers/thermal/sun8i_thermal.c | 2 +- - drivers/thermal/tegra/tegra30-tsensor.c | 2 +- - drivers/thermal/thermal_hwmon.c | 4 ++-- - drivers/thermal/thermal_hwmon.h | 4 ++-- - drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +- - 13 files changed, 15 insertions(+), 15 deletions(-) - ---- a/drivers/thermal/amlogic_thermal.c -+++ b/drivers/thermal/amlogic_thermal.c -@@ -286,7 +286,7 @@ static int amlogic_thermal_probe(struct - return ret; - } - -- if (devm_thermal_add_hwmon_sysfs(pdata->tzd)) -+ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, pdata->tzd)) - dev_warn(&pdev->dev, "Failed to add hwmon sysfs attributes\n"); - - ret = amlogic_thermal_initialize(pdata); ---- a/drivers/thermal/imx_sc_thermal.c -+++ b/drivers/thermal/imx_sc_thermal.c -@@ -120,7 +120,7 @@ static int imx_sc_thermal_probe(struct p - return ret; - } - -- if (devm_thermal_add_hwmon_sysfs(sensor->tzd)) -+ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, sensor->tzd)) - dev_warn(&pdev->dev, "failed to add hwmon sysfs attributes\n"); - } - ---- a/drivers/thermal/k3_bandgap.c -+++ b/drivers/thermal/k3_bandgap.c -@@ -222,7 +222,7 @@ static int k3_bandgap_probe(struct platf - goto err_alloc; - } - -- if (devm_thermal_add_hwmon_sysfs(data[id].tzd)) -+ if (devm_thermal_add_hwmon_sysfs(dev, data[id].tzd)) - dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); - } - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -1210,7 +1210,7 @@ static int mtk_thermal_probe(struct plat - goto err_disable_clk_peri_therm; - } - -- ret = devm_thermal_add_hwmon_sysfs(tzdev); -+ ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev); - if (ret) - dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); - ---- a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c -+++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c -@@ -688,7 +688,7 @@ static int adc_tm5_register_tzd(struct a - return PTR_ERR(tzd); - } - adc_tm->channels[i].tzd = tzd; -- if (devm_thermal_add_hwmon_sysfs(tzd)) -+ if (devm_thermal_add_hwmon_sysfs(adc_tm->dev, tzd)) - dev_warn(adc_tm->dev, - "Failed to add hwmon sysfs attributes\n"); - } ---- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c -+++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c -@@ -460,7 +460,7 @@ static int qpnp_tm_probe(struct platform - return ret; - } - -- if (devm_thermal_add_hwmon_sysfs(chip->tz_dev)) -+ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, chip->tz_dev)) - dev_warn(&pdev->dev, - "Failed to add hwmon sysfs attributes\n"); - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -1056,7 +1056,7 @@ static int tsens_register(struct tsens_p - if (priv->ops->enable) - priv->ops->enable(priv, i); - -- if (devm_thermal_add_hwmon_sysfs(tzd)) -+ if (devm_thermal_add_hwmon_sysfs(priv->dev, tzd)) - dev_warn(priv->dev, - "Failed to add hwmon sysfs attributes\n"); - } ---- a/drivers/thermal/qoriq_thermal.c -+++ b/drivers/thermal/qoriq_thermal.c -@@ -158,7 +158,7 @@ static int qoriq_tmu_register_tmu_zone(s - return ret; - } - -- if (devm_thermal_add_hwmon_sysfs(tzd)) -+ if (devm_thermal_add_hwmon_sysfs(dev, tzd)) - dev_warn(dev, - "Failed to add hwmon sysfs attributes\n"); - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -468,7 +468,7 @@ static int sun8i_ths_register(struct ths - if (IS_ERR(tmdev->sensor[i].tzd)) - return PTR_ERR(tmdev->sensor[i].tzd); - -- if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd)) -+ if (devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd)) - dev_warn(tmdev->dev, - "Failed to add hwmon sysfs attributes\n"); - } ---- a/drivers/thermal/tegra/tegra30-tsensor.c -+++ b/drivers/thermal/tegra/tegra30-tsensor.c -@@ -530,7 +530,7 @@ static int tegra_tsensor_register_channe - return 0; - } - -- if (devm_thermal_add_hwmon_sysfs(tsc->tzd)) -+ if (devm_thermal_add_hwmon_sysfs(ts->dev, tsc->tzd)) - dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n"); - - return 0; ---- a/drivers/thermal/thermal_hwmon.c -+++ b/drivers/thermal/thermal_hwmon.c -@@ -255,7 +255,7 @@ static void devm_thermal_hwmon_release(s - thermal_remove_hwmon_sysfs(*(struct thermal_zone_device **)res); - } - --int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz) -+int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz) - { - struct thermal_zone_device **ptr; - int ret; -@@ -272,7 +272,7 @@ int devm_thermal_add_hwmon_sysfs(struct - } - - *ptr = tz; -- devres_add(&tz->device, ptr); -+ devres_add(dev, ptr); - - return ret; - } ---- a/drivers/thermal/thermal_hwmon.h -+++ b/drivers/thermal/thermal_hwmon.h -@@ -17,7 +17,7 @@ - - #ifdef CONFIG_THERMAL_HWMON - int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz); --int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz); -+int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz); - void thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz); - #else - static inline int -@@ -27,7 +27,7 @@ thermal_add_hwmon_sysfs(struct thermal_z - } - - static inline int --devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz) -+devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz) - { - return 0; - } ---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c -+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c -@@ -182,7 +182,7 @@ int ti_thermal_expose_sensor(struct ti_b - ti_bandgap_set_sensor_data(bgp, id, data); - ti_bandgap_write_update_interval(bgp, data->sensor_id, interval); - -- if (devm_thermal_add_hwmon_sysfs(data->ti_thermal)) -+ if (devm_thermal_add_hwmon_sysfs(bgp->dev, data->ti_thermal)) - dev_warn(bgp->dev, "failed to add hwmon sysfs attributes\n"); - - return 0; diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch b/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch deleted file mode 100644 index 9dedc2cb685279..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-13-thermal-Don-t-use-device-internal-thermal-zone-struc.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 5a72b8e4bac753e4dc74dc0a1335d120f63df97a Mon Sep 17 00:00:00 2001 -From: Daniel Lezcano -Date: Wed, 1 Mar 2023 21:14:37 +0100 -Subject: [PATCH 09/42] thermal: Don't use 'device' internal thermal zone - structure field - -Some drivers are directly using the thermal zone's 'device' structure -field. - -Use the driver device pointer instead of the thermal zone device when -it is available. - -Remove the traces when they are duplicate with the traces in the core -code. - -[again skipped imx_thermal.c] - -Cc: Jean Delvare -Cc: Guenter Roeck -Signed-off-by: Daniel Lezcano -Reviewed-by: Balsam CHIHI #Mediatek LVTS -Reviewed-by: AngeloGioacchino Del Regno #MediaTek LVTS -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/mediatek/lvts_thermal.c | 4 ++-- - drivers/thermal/thermal_hwmon.c | 4 ++-- - drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +- - 3 files changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -305,7 +305,7 @@ static int lvts_set_trips(struct thermal - * 14-0 : Raw temperature for threshold - */ - if (low != -INT_MAX) { -- dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low); -+ pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low); - writel(raw_low, LVTS_H2NTHRE(base)); - } - -@@ -318,7 +318,7 @@ static int lvts_set_trips(struct thermal - * - * 14-0 : Raw temperature for threshold - */ -- dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high); -+ pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high); - writel(raw_high, LVTS_HTHRE(base)); - - return 0; ---- a/drivers/thermal/thermal_hwmon.c -+++ b/drivers/thermal/thermal_hwmon.c -@@ -220,14 +220,14 @@ void thermal_remove_hwmon_sysfs(struct t - hwmon = thermal_hwmon_lookup_by_type(tz); - if (unlikely(!hwmon)) { - /* Should never happen... */ -- dev_dbg(&tz->device, "hwmon device lookup failed!\n"); -+ dev_dbg(hwmon->device, "hwmon device lookup failed!\n"); - return; - } - - temp = thermal_hwmon_lookup_temp(hwmon, tz); - if (unlikely(!temp)) { - /* Should never happen... */ -- dev_dbg(&tz->device, "temperature input lookup failed!\n"); -+ dev_dbg(hwmon->device, "temperature input lookup failed!\n"); - return; - } - ---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c -+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c -@@ -43,7 +43,7 @@ static void ti_thermal_work(struct work_ - - thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED); - -- dev_dbg(&data->ti_thermal->device, "updated thermal zone %s\n", -+ dev_dbg(data->bgp->dev, "updated thermal zone %s\n", - data->ti_thermal->type); - } - diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch b/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch deleted file mode 100644 index 8cec9aba97729c..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-14-thermal-Use-thermal_zone_device_type-accessor.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 66b3a292d3fc749e8ec7ac5278a17e8a5757ecbc Mon Sep 17 00:00:00 2001 -From: Daniel Lezcano -Date: Wed, 1 Mar 2023 21:14:41 +0100 -Subject: [PATCH 10/42] thermal: Use thermal_zone_device_type() accessor - -Replace the accesses to 'tz->type' by its accessor version in order to -self-encapsulate the thermal_zone_device structure. - -Signed-off-by: Daniel Lezcano -Reviewed-by: Ido Schimmel #mlxsw -Reviewed-by: AngeloGioacchino Del Regno #MediaTek LVTS -Signed-off-by: Rafael J. Wysocki ---- - drivers/net/ethernet/mellanox/mlxsw/core_thermal.c | 2 +- - drivers/thermal/mediatek/lvts_thermal.c | 6 ++++-- - drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +- - 3 files changed, 6 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c -+++ b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c -@@ -168,7 +168,7 @@ mlxsw_thermal_module_trips_update(struct - - if (crit_temp > emerg_temp) { - dev_warn(dev, "%s : Critical threshold %d is above emergency threshold %d\n", -- tz->tzdev->type, crit_temp, emerg_temp); -+ thermal_zone_device_type(tz->tzdev), crit_temp, emerg_temp); - return 0; - } - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -305,7 +305,8 @@ static int lvts_set_trips(struct thermal - * 14-0 : Raw temperature for threshold - */ - if (low != -INT_MAX) { -- pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low); -+ pr_debug("%s: Setting low limit temperature interrupt: %d\n", -+ thermal_zone_device_type(tz), low); - writel(raw_low, LVTS_H2NTHRE(base)); - } - -@@ -318,7 +319,8 @@ static int lvts_set_trips(struct thermal - * - * 14-0 : Raw temperature for threshold - */ -- pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high); -+ pr_debug("%s: Setting high limit temperature interrupt: %d\n", -+ thermal_zone_device_type(tz), high); - writel(raw_high, LVTS_HTHRE(base)); - - return 0; ---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c -+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c -@@ -44,7 +44,7 @@ static void ti_thermal_work(struct work_ - thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED); - - dev_dbg(data->bgp->dev, "updated thermal zone %s\n", -- data->ti_thermal->type); -+ thermal_zone_device_type(data->ti_thermal)); - } - - /** diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch deleted file mode 100644 index 68f41fdd168d98..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-15-thermal-drivers-mediatek-Control-buffer-enablement-t.patch +++ /dev/null @@ -1,81 +0,0 @@ -From f6658c1c4ae98477d6be00495226c0617354fe76 Mon Sep 17 00:00:00 2001 -From: Markus Schneider-Pargmann -Date: Fri, 27 Jan 2023 16:44:43 +0100 -Subject: [PATCH 11/42] thermal/drivers/mediatek: Control buffer enablement - tweaks - -Add logic in order to be able to turn on the control buffer on MT8365. -This change now allows to have control buffer support for MTK_THERMAL_V1, -and it allows to define the register offset, and mask used to enable it. - -Signed-off-by: Markus Schneider-Pargmann -Signed-off-by: Fabien Parent -Signed-off-by: Amjad Ouled-Ameur -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-2-55a1ae14af74@baylibre.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/mediatek/auxadc_thermal.c | 28 +++++++++++++++-------- - 1 file changed, 19 insertions(+), 9 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -307,6 +307,9 @@ struct mtk_thermal_data { - bool need_switch_bank; - struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; - enum mtk_thermal_version version; -+ u32 apmixed_buffer_ctl_reg; -+ u32 apmixed_buffer_ctl_mask; -+ u32 apmixed_buffer_ctl_set; - }; - - struct mtk_thermal { -@@ -560,6 +563,9 @@ static const struct mtk_thermal_data mt7 - .adcpnp = mt7622_adcpnp, - .sensor_mux_values = mt7622_mux_values, - .version = MTK_THERMAL_V2, -+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, -+ .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), -+ .apmixed_buffer_ctl_set = BIT(0), - }; - - /* -@@ -1079,14 +1085,18 @@ static const struct of_device_id mtk_the - }; - MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); - --static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base) -+static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, -+ void __iomem *apmixed_base) - { -- int tmp; -+ u32 tmp; -+ -+ if (!mt->conf->apmixed_buffer_ctl_reg) -+ return; - -- tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1); -- tmp &= ~(0x37); -- tmp |= 0x1; -- writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1); -+ tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg); -+ tmp &= mt->conf->apmixed_buffer_ctl_mask; -+ tmp |= mt->conf->apmixed_buffer_ctl_set; -+ writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg); - udelay(200); - } - -@@ -1184,10 +1194,10 @@ static int mtk_thermal_probe(struct plat - goto err_disable_clk_auxadc; - } - -- if (mt->conf->version != MTK_THERMAL_V1) { -- mtk_thermal_turn_on_buffer(apmixed_base); -+ mtk_thermal_turn_on_buffer(mt, apmixed_base); -+ -+ if (mt->conf->version != MTK_THERMAL_V2) - mtk_thermal_release_periodic_ts(mt, auxadc_base); -- } - - if (mt->conf->version == MTK_THERMAL_V1) - mt->raw_to_mcelsius = raw_to_mcelsius_v1; diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch b/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch deleted file mode 100644 index 285c6f6a7b3aa0..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-16-thermal-drivers-mediatek-Add-support-for-MT8365-SoC.patch +++ /dev/null @@ -1,123 +0,0 @@ -From c4eff784465f88218dc5eb51320320464db83d3f Mon Sep 17 00:00:00 2001 -From: Fabien Parent -Date: Fri, 27 Jan 2023 16:44:44 +0100 -Subject: [PATCH 12/42] thermal/drivers/mediatek: Add support for MT8365 SoC - -MT8365 is similar to the other SoCs supported by the driver. It has only -one bank and 3 actual sensors that can be multiplexed. There is another -one sensor that does not have usable data. - -Signed-off-by: Fabien Parent -Signed-off-by: Amjad Ouled-Ameur -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-3-55a1ae14af74@baylibre.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/mediatek/auxadc_thermal.c | 68 +++++++++++++++++++++++ - 1 file changed, 68 insertions(+) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -31,6 +31,7 @@ - #define AUXADC_CON2_V 0x010 - #define AUXADC_DATA(channel) (0x14 + (channel) * 4) - -+#define APMIXED_SYS_TS_CON0 0x600 - #define APMIXED_SYS_TS_CON1 0x604 - - /* Thermal Controller Registers */ -@@ -281,6 +282,17 @@ enum mtk_thermal_version { - /* The calibration coefficient of sensor */ - #define MT7986_CALIBRATION 165 - -+/* MT8365 */ -+#define MT8365_TEMP_AUXADC_CHANNEL 11 -+#define MT8365_CALIBRATION 164 -+#define MT8365_NUM_CONTROLLER 1 -+#define MT8365_NUM_BANKS 1 -+#define MT8365_NUM_SENSORS 3 -+#define MT8365_NUM_SENSORS_PER_ZONE 3 -+#define MT8365_TS1 0 -+#define MT8365_TS2 1 -+#define MT8365_TS3 2 -+ - struct mtk_thermal; - - struct thermal_bank_cfg { -@@ -435,6 +447,24 @@ static const int mt7986_mux_values[MT798 - static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; - static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; - -+/* MT8365 thermal sensor data */ -+static const int mt8365_bank_data[MT8365_NUM_SENSORS] = { -+ MT8365_TS1, MT8365_TS2, MT8365_TS3 -+}; -+ -+static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = { -+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 -+}; -+ -+static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = { -+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 -+}; -+ -+static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 }; -+static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 }; -+ -+static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 }; -+ - /* - * The MT8173 thermal controller has four banks. Each bank can read up to - * four temperature sensors simultaneously. The MT8173 has a total of 5 -@@ -510,6 +540,40 @@ static const struct mtk_thermal_data mt2 - }; - - /* -+ * The MT8365 thermal controller has one bank, which can read up to -+ * four temperature sensors simultaneously. The MT8365 has a total of 3 -+ * temperature sensors. -+ * -+ * The thermal core only gets the maximum temperature of this one bank, -+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart -+ * Voltage Scaling) unit makes its decisions based on the same bank -+ * data. -+ */ -+static const struct mtk_thermal_data mt8365_thermal_data = { -+ .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT8365_NUM_BANKS, -+ .num_sensors = MT8365_NUM_SENSORS, -+ .vts_index = mt8365_vts_index, -+ .cali_val = MT8365_CALIBRATION, -+ .num_controller = MT8365_NUM_CONTROLLER, -+ .controller_offset = mt8365_tc_offset, -+ .need_switch_bank = false, -+ .bank_data = { -+ { -+ .num_sensors = MT8365_NUM_SENSORS, -+ .sensors = mt8365_bank_data -+ }, -+ }, -+ .msr = mt8365_msr, -+ .adcpnp = mt8365_adcpnp, -+ .sensor_mux_values = mt8365_mux_values, -+ .version = MTK_THERMAL_V1, -+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0, -+ .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28), -+ .apmixed_buffer_ctl_set = 0, -+}; -+ -+/* - * The MT2712 thermal controller has one bank, which can read up to - * four temperature sensors simultaneously. The MT2712 has a total of 4 - * temperature sensors. -@@ -1080,6 +1144,10 @@ static const struct of_device_id mtk_the - { - .compatible = "mediatek,mt8183-thermal", - .data = (void *)&mt8183_thermal_data, -+ }, -+ { -+ .compatible = "mediatek,mt8365-thermal", -+ .data = (void *)&mt8365_thermal_data, - }, { - }, - }; diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch b/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch deleted file mode 100644 index 5c99aa80c1ed72..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-17-thermal-drivers-mediatek-Add-delay-after-thermal-ban.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 4eead70db74922bc61e9d0b4591524369a335751 Mon Sep 17 00:00:00 2001 -From: Amjad Ouled-Ameur -Date: Fri, 27 Jan 2023 16:44:46 +0100 -Subject: [PATCH 13/42] thermal/drivers/mediatek: Add delay after thermal banks - initialization - -Thermal sensor reads performed immediately after thermal bank -initialization returns bogus values. This is currently tackled by returning -0 if the temperature is bogus (exceeding 200000). - -Instead, add a delay between the bank init and the thermal zone device -register to properly fix this. - -Signed-off-by: Michael Kao -Signed-off-by: Hsin-Yi Wang -Signed-off-by: Amjad Ouled-Ameur -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-5-55a1ae14af74@baylibre.com -Signed-off-by: Daniel Lezcano ---- - drivers/thermal/mediatek/auxadc_thermal.c | 11 +++-------- - 1 file changed, 3 insertions(+), 8 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -816,14 +816,6 @@ static int mtk_thermal_bank_temperature( - mt, conf->bank_data[bank->id].sensors[i], raw); - - -- /* -- * The first read of a sensor often contains very high bogus -- * temperature value. Filter these out so that the system does -- * not immediately shut down. -- */ -- if (temp > 200000) -- temp = 0; -- - if (temp > max) - max = temp; - } -@@ -1281,6 +1273,9 @@ static int mtk_thermal_probe(struct plat - - platform_set_drvdata(pdev, mt); - -+ /* Delay for thermal banks to be ready */ -+ msleep(30); -+ - tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, - &mtk_thermal_ops); - if (IS_ERR(tzdev)) { diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch b/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch deleted file mode 100644 index 734f5c1e770ede..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-18-thermal-drivers-mediatek-lvts_thermal-Fix-sensor-1-i.patch +++ /dev/null @@ -1,46 +0,0 @@ -From ad9dc9e92367803a4f9576aea0dab110d03fc510 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Tue, 28 Mar 2023 11:10:17 +0800 -Subject: [PATCH 14/42] thermal/drivers/mediatek/lvts_thermal: Fix sensor 1 - interrupt status bitmask - -The binary representation for sensor 1 interrupt status was incorrectly -assembled, when compared to the full table given in the same comment -section. The conversion into hex was also incorrect, leading to -incorrect interrupt status bitmask for sensor 1. This would cause the -driver to incorrectly identify changes for sensor 1, when in fact it -was sensor 0, or a sensor access time out. - -Fix the binary and hex representations in the comments, and the actual -bitmask macro. - -Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") -Signed-off-by: Chen-Yu Tsai -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230328031017.1360976-1-wenst@chromium.org ---- - drivers/thermal/mediatek/lvts_thermal.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -66,7 +66,7 @@ - #define LVTS_MONINT_CONF 0x9FBF7BDE - - #define LVTS_INT_SENSOR0 0x0009001F --#define LVTS_INT_SENSOR1 0X000881F0 -+#define LVTS_INT_SENSOR1 0x001203E0 - #define LVTS_INT_SENSOR2 0x00247C00 - #define LVTS_INT_SENSOR3 0x1FC00000 - -@@ -395,8 +395,8 @@ static irqreturn_t lvts_ctrl_irq_handler - * => 0x1FC00000 - * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 - * => 0x00247C00 -- * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000 -- * => 0X000881F0 -+ * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 -+ * => 0X001203E0 - * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 - * => 0x0009001F - */ diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch deleted file mode 100644 index d09c2055a3ef87..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-19-thermal-drivers-mediatek-lvts_thermal-Add-AP-domain-.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 9aad43ad3285fc21158fb416830a6156a9a31fa5 Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 7 Mar 2023 16:45:22 +0100 -Subject: [PATCH 15/42] thermal/drivers/mediatek/lvts_thermal: Add AP domain - for mt8195 - -Add MT8195 AP Domain support to LVTS Driver. - -Take the opportunity to update the comments to show calibration data -information related to the new domain. - -[dlezcano]: Massaged a bit the changelog - -Signed-off-by: Balsam CHIHI -Tested-by: Chen-Yu Tsai -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 94 +++++++++++++++++++------ - 1 file changed, 74 insertions(+), 20 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -530,29 +530,33 @@ static int lvts_sensor_init(struct devic - * The efuse blob values follows the sensor enumeration per thermal - * controller. The decoding of the stream is as follow: - * -- * <--?-> <----big0 ???---> <-sensor0-> <-0-> -- * ------------------------------------------ -- * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 | -- * ------------------------------------------ -+ * stream index map for MCU Domain : - * -- * <--sensor1--><-0-> <----big1 ???---> <-sen -- * ------------------------------------------ -- * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | -- * ------------------------------------------ -+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> -+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 - * -- * sor0-> <-0-> <-sensor1-> <-0-> .......... -- * ------------------------------------------ -- * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | -- * ------------------------------------------ -+ * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> -+ * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 - * -- * And so on ... -+ * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> -+ * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 -+ * -+ * stream index map for AP Domain : -+ * -+ * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> -+ * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A -+ * -+ * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> -+ * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 -+ * -+ * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> -+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F -+ * -+ * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> -+ * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 - * - * The data description gives the offset of the calibration data in - * this bytes stream for each sensor. -- * -- * Each thermal controller can handle up to 4 sensors max, we don't -- * care if there are less as the array of calibration is sized to 4 -- * anyway. The unused sensor slot will be zeroed. - */ - static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, - const struct lvts_ctrl_data *lvts_ctrl_data, -@@ -1165,7 +1169,7 @@ static int lvts_remove(struct platform_d - return 0; - } - --static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = { -+static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { - { - .cal_offset = { 0x04, 0x07 }, - .lvts_sensor = { -@@ -1200,13 +1204,63 @@ static const struct lvts_ctrl_data mt819 - } - }; - -+static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { -+ { -+ .cal_offset = { 0x25, 0x28 }, -+ .lvts_sensor = { -+ { .dt_id = MT8195_AP_VPU0 }, -+ { .dt_id = MT8195_AP_VPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x0, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, -+ }, -+ { -+ .cal_offset = { 0x2e, 0x31 }, -+ .lvts_sensor = { -+ { .dt_id = MT8195_AP_GPU0 }, -+ { .dt_id = MT8195_AP_GPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x100, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, -+ }, -+ { -+ .cal_offset = { 0x37, 0x3a, 0x3d }, -+ .lvts_sensor = { -+ { .dt_id = MT8195_AP_VDEC }, -+ { .dt_id = MT8195_AP_IMG }, -+ { .dt_id = MT8195_AP_INFRA }, -+ }, -+ .num_lvts_sensor = 3, -+ .offset = 0x200, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, -+ }, -+ { -+ .cal_offset = { 0x43, 0x46 }, -+ .lvts_sensor = { -+ { .dt_id = MT8195_AP_CAM0 }, -+ { .dt_id = MT8195_AP_CAM1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x300, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, -+ } -+}; -+ - static const struct lvts_data mt8195_lvts_mcu_data = { -- .lvts_ctrl = mt8195_lvts_data_ctrl, -- .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl), -+ .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), -+}; -+ -+static const struct lvts_data mt8195_lvts_ap_data = { -+ .lvts_ctrl = mt8195_lvts_ap_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), - }; - - static const struct of_device_id lvts_of_match[] = { - { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, -+ { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, - {}, - }; - MODULE_DEVICE_TABLE(of, lvts_of_match); diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch b/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch deleted file mode 100644 index a48ea3742bb16e..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-20-Revert-thermal-drivers-mediatek-Add-delay-after-ther.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 7105a86760bd9e4d107075cefc75016b693a5542 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Wed, 19 Apr 2023 08:11:45 +0200 -Subject: [PATCH 16/42] Revert "thermal/drivers/mediatek: Add delay after - thermal banks initialization" - -Some more testing revealed that this commit introduces a regression on some -MT8173 Chromebooks and at least on one MT6795 Sony Xperia M5 smartphone due -to the delay being apparently variable and machine specific. - -Another solution would be to delay for a bit more (~70ms) but this is not -feasible for two reasons: first of all, we're adding an even bigger delay -in a probe function; second, some machines need less, some may need even -more, making the msleep at probe solution highly suboptimal. - -This reverts commit 10debf8c2da8011c8009dd4b3f6d0ab85891c81b. - -Fixes: 10debf8c2da8 ("thermal/drivers/mediatek: Add delay after thermal banks initialization") -Reported-by: "kernelci.org bot" -Signed-off-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230419061146.22246-2-angelogioacchino.delregno@collabora.com ---- - drivers/thermal/mediatek/auxadc_thermal.c | 11 ++++++++--- - 1 file changed, 8 insertions(+), 3 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -816,6 +816,14 @@ static int mtk_thermal_bank_temperature( - mt, conf->bank_data[bank->id].sensors[i], raw); - - -+ /* -+ * The first read of a sensor often contains very high bogus -+ * temperature value. Filter these out so that the system does -+ * not immediately shut down. -+ */ -+ if (temp > 200000) -+ temp = 0; -+ - if (temp > max) - max = temp; - } -@@ -1273,9 +1281,6 @@ static int mtk_thermal_probe(struct plat - - platform_set_drvdata(pdev, mt); - -- /* Delay for thermal banks to be ready */ -- msleep(30); -- - tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, - &mtk_thermal_ops); - if (IS_ERR(tzdev)) { diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch b/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch deleted file mode 100644 index aae87af5d1cc42..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-21-thermal-drivers-mediatek-Add-temperature-constraints.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 681b652c9dfc4037d4a55b2733e091a4e1a5de18 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Wed, 19 Apr 2023 08:11:46 +0200 -Subject: [PATCH 17/42] thermal/drivers/mediatek: Add temperature constraints - to validate read -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The AUXADC thermal v1 allows reading temperature range between -20°C to -150°C and any value out of this range is invalid. - -Add new definitions for MT8173_TEMP_{MIN_MAX} and a new small helper -mtk_thermal_temp_is_valid() to check if new readings are in range: if -not, we tell to the API that the reading is invalid by returning -THERMAL_TEMP_INVALID. - -It was chosen to introduce the helper function because, even though this -temperature range is realistically ok for all, it comes from a downstream -kernel driver for version 1, but here we also support v2 and v3 which may -may have wider constraints. - -Signed-off-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230419061146.22246-3-angelogioacchino.delregno@collabora.com ---- - drivers/thermal/mediatek/auxadc_thermal.c | 24 +++++++++++++++++------ - 1 file changed, 18 insertions(+), 6 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -116,6 +116,10 @@ - /* The calibration coefficient of sensor */ - #define MT8173_CALIBRATION 165 - -+/* Valid temperatures range */ -+#define MT8173_TEMP_MIN -20000 -+#define MT8173_TEMP_MAX 150000 -+ - /* - * Layout of the fuses providing the calibration data - * These macros could be used for MT8183, MT8173, MT2701, and MT2712. -@@ -689,6 +693,11 @@ static const struct mtk_thermal_data mt7 - .version = MTK_THERMAL_V3, - }; - -+static bool mtk_thermal_temp_is_valid(int temp) -+{ -+ return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX); -+} -+ - /** - * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius - * @mt: The thermal controller -@@ -815,14 +824,17 @@ static int mtk_thermal_bank_temperature( - temp = mt->raw_to_mcelsius( - mt, conf->bank_data[bank->id].sensors[i], raw); - -- - /* -- * The first read of a sensor often contains very high bogus -- * temperature value. Filter these out so that the system does -- * not immediately shut down. -+ * Depending on the filt/sen intervals and ADC polling time, -+ * we may need up to 60 milliseconds after initialization: this -+ * will result in the first reading containing an out of range -+ * temperature value. -+ * Validate the reading to both address the aforementioned issue -+ * and to eventually avoid bogus readings during runtime in the -+ * event that the AUXADC gets unstable due to high EMI, etc. - */ -- if (temp > 200000) -- temp = 0; -+ if (!mtk_thermal_temp_is_valid(temp)) -+ temp = THERMAL_TEMP_INVALID; - - if (temp > max) - max = temp; diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch deleted file mode 100644 index 782684aacc6839..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-22-thermal-drivers-mediatek-Use-devm_of_iomap-to-avoid-.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 458fa1d508de3f17e49d974a0158d9aeff273a58 Mon Sep 17 00:00:00 2001 -From: Kang Chen -Date: Wed, 19 Apr 2023 10:07:48 +0800 -Subject: [PATCH 18/42] thermal/drivers/mediatek: Use devm_of_iomap to avoid - resource leak in mtk_thermal_probe - -Smatch reports: -1. mtk_thermal_probe() warn: 'apmixed_base' from of_iomap() not released. -2. mtk_thermal_probe() warn: 'auxadc_base' from of_iomap() not released. - -The original code forgets to release iomap resource when handling errors, -fix it by switch to devm_of_iomap. - -Fixes: 89945047b166 ("thermal: mediatek: Add tsensor support for V2 thermal system") -Signed-off-by: Kang Chen -Reviewed-by: Dongliang Mu -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230419020749.621257-1-void0red@hust.edu.cn ---- - drivers/thermal/mediatek/auxadc_thermal.c | 14 ++++++++++++-- - 1 file changed, 12 insertions(+), 2 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -1232,7 +1232,12 @@ static int mtk_thermal_probe(struct plat - return -ENODEV; - } - -- auxadc_base = of_iomap(auxadc, 0); -+ auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL); -+ if (IS_ERR(auxadc_base)) { -+ of_node_put(auxadc); -+ return PTR_ERR(auxadc_base); -+ } -+ - auxadc_phys_base = of_get_phys_base(auxadc); - - of_node_put(auxadc); -@@ -1248,7 +1253,12 @@ static int mtk_thermal_probe(struct plat - return -ENODEV; - } - -- apmixed_base = of_iomap(apmixedsys, 0); -+ apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL); -+ if (IS_ERR(apmixed_base)) { -+ of_node_put(apmixedsys); -+ return PTR_ERR(apmixed_base); -+ } -+ - apmixed_phys_base = of_get_phys_base(apmixedsys); - - of_node_put(apmixedsys); diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch b/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch deleted file mode 100644 index d7896dbd60a7a5..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-23-thermal-drivers-mediatek-Change-clk_prepare_enable-t.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 227d1856924ec00a4f5bdf5afcf77bc7f3f04e86 Mon Sep 17 00:00:00 2001 -From: Kang Chen -Date: Wed, 19 Apr 2023 10:07:49 +0800 -Subject: [PATCH 19/42] thermal/drivers/mediatek: Change clk_prepare_enable to - devm_clk_get_enabled in mtk_thermal_probe - -Use devm_clk_get_enabled to do automatic resource management. -Meanwhile, remove error handling labels in the probe function and -the whole remove function. - -Signed-off-by: Kang Chen -Reviewed-by: Dongliang Mu -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230419020749.621257-2-void0red@hust.edu.cn ---- - drivers/thermal/mediatek/auxadc_thermal.c | 44 +++++------------------ - 1 file changed, 9 insertions(+), 35 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -1206,14 +1206,6 @@ static int mtk_thermal_probe(struct plat - - mt->conf = of_device_get_match_data(&pdev->dev); - -- mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); -- if (IS_ERR(mt->clk_peri_therm)) -- return PTR_ERR(mt->clk_peri_therm); -- -- mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); -- if (IS_ERR(mt->clk_auxadc)) -- return PTR_ERR(mt->clk_auxadc); -- - mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(mt->thermal_base)) - return PTR_ERR(mt->thermal_base); -@@ -1272,16 +1264,18 @@ static int mtk_thermal_probe(struct plat - if (ret) - return ret; - -- ret = clk_prepare_enable(mt->clk_auxadc); -- if (ret) { -+ mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc"); -+ if (IS_ERR(mt->clk_auxadc)) { -+ ret = PTR_ERR(mt->clk_auxadc); - dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); - return ret; - } - -- ret = clk_prepare_enable(mt->clk_peri_therm); -- if (ret) { -+ mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm"); -+ if (IS_ERR(mt->clk_peri_therm)) { -+ ret = PTR_ERR(mt->clk_peri_therm); - dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); -- goto err_disable_clk_auxadc; -+ return ret; - } - - mtk_thermal_turn_on_buffer(mt, apmixed_base); -@@ -1305,38 +1299,18 @@ static int mtk_thermal_probe(struct plat - - tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, - &mtk_thermal_ops); -- if (IS_ERR(tzdev)) { -- ret = PTR_ERR(tzdev); -- goto err_disable_clk_peri_therm; -- } -+ if (IS_ERR(tzdev)) -+ return PTR_ERR(tzdev); - - ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev); - if (ret) - dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs"); - - return 0; -- --err_disable_clk_peri_therm: -- clk_disable_unprepare(mt->clk_peri_therm); --err_disable_clk_auxadc: -- clk_disable_unprepare(mt->clk_auxadc); -- -- return ret; --} -- --static int mtk_thermal_remove(struct platform_device *pdev) --{ -- struct mtk_thermal *mt = platform_get_drvdata(pdev); -- -- clk_disable_unprepare(mt->clk_peri_therm); -- clk_disable_unprepare(mt->clk_auxadc); -- -- return 0; - } - - static struct platform_driver mtk_thermal_driver = { - .probe = mtk_thermal_probe, -- .remove = mtk_thermal_remove, - .driver = { - .name = "mtk-thermal", - .of_match_table = mtk_thermal_of_match, diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch b/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch deleted file mode 100644 index fd18a5365c0ab8..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-24-thermal-drivers-mediatek-Use-of_address_to_resource.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 655fe2533ac05323a07c19ba079bf2064e7741af Mon Sep 17 00:00:00 2001 -From: Rob Herring -Date: Sun, 19 Mar 2023 11:32:31 -0500 -Subject: [PATCH 20/42] thermal/drivers/mediatek: Use of_address_to_resource() - -Replace of_get_address() and of_translate_address() calls with single -call to of_address_to_resource(). - -Signed-off-by: Rob Herring -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230319163231.226738-1-robh@kernel.org ---- - drivers/thermal/mediatek/auxadc_thermal.c | 8 +++----- - 1 file changed, 3 insertions(+), 5 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -979,14 +979,12 @@ static void mtk_thermal_init_bank(struct - - static u64 of_get_phys_base(struct device_node *np) - { -- u64 size64; -- const __be32 *regaddr_p; -+ struct resource res; - -- regaddr_p = of_get_address(np, 0, &size64, NULL); -- if (!regaddr_p) -+ if (of_address_to_resource(np, 0, &res)) - return OF_BAD_ADDR; - -- return of_translate_address(np, regaddr_p); -+ return res.start; - } - - static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf) diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch b/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch deleted file mode 100644 index c3ff17d5173e5c..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-25-Revert-thermal-drivers-mediatek-Use-devm_of_iomap-to.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 2c380d07215e6fce3ac66cc5af059bc2c2a69f7a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= -Date: Thu, 25 May 2023 14:18:11 +0200 -Subject: [PATCH 21/42] Revert "thermal/drivers/mediatek: Use devm_of_iomap to - avoid resource leak in mtk_thermal_probe" -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This reverts commit f05c7b7d9ea9477fcc388476c6f4ade8c66d2d26. - -That change was causing a regression in the generic-adc-thermal-probed -bootrr test as reported in the kernelci-results list [1]. -A proper rework will take longer, so revert it for now. - -[1] https://groups.io/g/kernelci-results/message/42660 - -Fixes: f05c7b7d9ea9 ("thermal/drivers/mediatek: Use devm_of_iomap to avoid resource leak in mtk_thermal_probe") -Signed-off-by: Ricardo Cañuelo -Suggested-by: AngeloGioacchino Del Regno -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230525121811.3360268-1-ricardo.canuelo@collabora.com ---- - drivers/thermal/mediatek/auxadc_thermal.c | 14 ++------------ - 1 file changed, 2 insertions(+), 12 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -1222,12 +1222,7 @@ static int mtk_thermal_probe(struct plat - return -ENODEV; - } - -- auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL); -- if (IS_ERR(auxadc_base)) { -- of_node_put(auxadc); -- return PTR_ERR(auxadc_base); -- } -- -+ auxadc_base = of_iomap(auxadc, 0); - auxadc_phys_base = of_get_phys_base(auxadc); - - of_node_put(auxadc); -@@ -1243,12 +1238,7 @@ static int mtk_thermal_probe(struct plat - return -ENODEV; - } - -- apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL); -- if (IS_ERR(apmixed_base)) { -- of_node_put(apmixedsys); -- return PTR_ERR(apmixed_base); -- } -- -+ apmixed_base = of_iomap(apmixedsys, 0); - apmixed_phys_base = of_get_phys_base(apmixedsys); - - of_node_put(apmixedsys); diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch b/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch deleted file mode 100644 index c4456529c1c4e1..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-26-thermal-drivers-mediatek-lvts_thermal-Register-therm.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 496f4b08981d8a788ad5a2073fa1c65a2af1862b Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Tue, 13 Jun 2023 17:13:16 +0800 -Subject: [PATCH 22/42] thermal/drivers/mediatek/lvts_thermal: Register thermal - zones as hwmon sensors - -Register thermal zones as hwmon sensors to let userspace read -temperatures using standard hwmon interface. - -Signed-off-by: Chen-Yu Tsai -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230613091317.1691247-1-wenst@chromium.org ---- - drivers/thermal/mediatek/lvts_thermal.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -19,6 +19,8 @@ - #include - #include - -+#include "../thermal_hwmon.h" -+ - #define LVTS_MONCTL0(__base) (__base + 0x0000) - #define LVTS_MONCTL1(__base) (__base + 0x0004) - #define LVTS_MONCTL2(__base) (__base + 0x0008) -@@ -996,6 +998,9 @@ static int lvts_ctrl_start(struct device - return PTR_ERR(tz); - } - -+ if (devm_thermal_add_hwmon_sysfs(dev, tz)) -+ dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id); -+ - /* - * The thermal zone pointer will be needed in the - * interrupt handler, we store it in the sensor diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch b/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch deleted file mode 100644 index 22e7a954edec82..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-27-thermal-drivers-mediatek-lvts_thermal-Remove-redunda.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 885b9768ce2a66ed5d250822aed53d5114c895da Mon Sep 17 00:00:00 2001 -From: Yangtao Li -Date: Tue, 20 Jun 2023 17:07:31 +0800 -Subject: [PATCH 23/42] thermal/drivers/mediatek/lvts_thermal: Remove redundant - msg in lvts_ctrl_start() - -The upper-layer devm_thermal_add_hwmon_sysfs() function can directly -print error information. - -Signed-off-by: Yangtao Li -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230620090732.50025-10-frank.li@vivo.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -998,8 +998,7 @@ static int lvts_ctrl_start(struct device - return PTR_ERR(tz); - } - -- if (devm_thermal_add_hwmon_sysfs(dev, tz)) -- dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id); -+ devm_thermal_add_hwmon_sysfs(dev, tz); - - /* - * The thermal zone pointer will be needed in the diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch deleted file mode 100644 index bc67727423d0f8..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-29-thermal-drivers-mediatek-lvts_thermal-Handle-IRQ-on-.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 27b389d9f62c2174f95fe4002b11e77d4cb3ce80 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= - -Date: Thu, 6 Jul 2023 11:37:32 -0400 -Subject: [PATCH 25/42] thermal/drivers/mediatek/lvts_thermal: Handle IRQ on - all controllers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There is a single IRQ handler for each LVTS thermal domain, and it is -supposed to check each of its underlying controllers for the origin of -the interrupt and clear its status. However due to a typo, only the -first controller was ever being handled, which resulted in the interrupt -never being cleared when it happened on the other controllers. Add the -missing index so interrupts are handled for all controllers. - -Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") -Reviewed-by: Matthias Brugger -Reviewed-by: AngeloGioacchino Del Regno -Tested-by: Chen-Yu Tsai -Signed-off-by: Nícolas F. R. A. Prado -Reviewed-by: Alexandre Mergnat -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230706153823.201943-2-nfraprado@collabora.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -451,7 +451,7 @@ static irqreturn_t lvts_irq_handler(int - - for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { - -- aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl); -+ aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); - if (aux != IRQ_HANDLED) - continue; - diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch deleted file mode 100644 index 51d119c05b85e9..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-30-thermal-drivers-mediatek-lvts_thermal-Honor-sensors-.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 6d827142643ee10c13ff9a1d90f38fb399aa9fff Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= - -Date: Thu, 6 Jul 2023 11:37:33 -0400 -Subject: [PATCH 26/42] thermal/drivers/mediatek/lvts_thermal: Honor sensors in - immediate mode -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Each controller can be configured to operate on immediate or filtered -mode. On filtered mode, the sensors are enabled by setting the -corresponding bits in MONCTL0, while on immediate mode, by setting -MSRCTL1. - -Previously, the code would set MSRCTL1 for all four sensors when -configured to immediate mode, but given that the controller might not -have all four sensors connected, this would cause interrupts to trigger -for non-existent sensors. Fix this by handling the MSRCTL1 register -analogously to the MONCTL0: only enable the sensors that were declared. - -Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") -Reviewed-by: AngeloGioacchino Del Regno -Tested-by: Chen-Yu Tsai -Signed-off-by: Nícolas F. R. A. Prado -Reviewed-by: Alexandre Mergnat -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230706153823.201943-3-nfraprado@collabora.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 57 ++++++++++++++----------- - 1 file changed, 33 insertions(+), 24 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -897,24 +897,6 @@ static int lvts_ctrl_configure(struct de - writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); - - /* -- * LVTS_MSRCTL1 : Measurement control -- * -- * Bits: -- * -- * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 -- * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 -- * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 -- * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 -- * -- * That configuration will ignore the filtering and the delays -- * introduced below in MONCTL1 and MONCTL2 -- */ -- if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { -- value = BIT(9) | BIT(6) | BIT(5) | BIT(4); -- writel(value, LVTS_MSRCTL1(lvts_ctrl->base)); -- } -- -- /* - * LVTS_MONCTL1 : Period unit and group interval configuration - * - * The clock source of LVTS thermal controller is 26MHz. -@@ -979,6 +961,15 @@ static int lvts_ctrl_start(struct device - struct thermal_zone_device *tz; - u32 sensor_map = 0; - int i; -+ /* -+ * Bitmaps to enable each sensor on immediate and filtered modes, as -+ * described in MSRCTL1 and MONCTL0 registers below, respectively. -+ */ -+ u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; -+ u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; -+ -+ u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? -+ sensor_imm_bitmap : sensor_filt_bitmap; - - for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { - -@@ -1016,20 +1007,38 @@ static int lvts_ctrl_start(struct device - * map, so we can enable the temperature monitoring in - * the hardware thermal controller. - */ -- sensor_map |= BIT(i); -+ sensor_map |= sensor_bitmap[i]; - } - - /* -- * Bits: -- * 9: Single point access flow -- * 0-3: Enable sensing point 0-3 -- * - * The initialization of the thermal zones give us - * which sensor point to enable. If any thermal zone - * was not described in the device tree, it won't be - * enabled here in the sensor map. - */ -- writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); -+ if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { -+ /* -+ * LVTS_MSRCTL1 : Measurement control -+ * -+ * Bits: -+ * -+ * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 -+ * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 -+ * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 -+ * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 -+ * -+ * That configuration will ignore the filtering and the delays -+ * introduced in MONCTL1 and MONCTL2 -+ */ -+ writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); -+ } else { -+ /* -+ * Bits: -+ * 9: Single point access flow -+ * 0-3: Enable sensing point 0-3 -+ */ -+ writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); -+ } - - return 0; - } diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch b/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch deleted file mode 100644 index bfbadee3503107..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-31-thermal-drivers-mediatek-lvts_thermal-Use-offset-thr.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 93bb11dd19bdcc1fc97c7ceababd0db9fde128ad Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= - -Date: Thu, 6 Jul 2023 11:37:34 -0400 -Subject: [PATCH 27/42] thermal/drivers/mediatek/lvts_thermal: Use offset - threshold for IRQ -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There are two kinds of temperature monitoring interrupts available: -* High Offset, Low Offset -* Hot, Hot to normal, Cold - -The code currently uses the hot/h2n/cold interrupts, however in a way -that doesn't work: the cold threshold is left uninitialized, which -prevents the other thresholds from ever triggering, and the h2n -interrupt is used as the lower threshold, which prevents the hot -interrupt from triggering again after the thresholds are updated by the -thermal framework, since a hot interrupt can only trigger again after -the hot to normal interrupt has been triggered. - -But better yet than addressing those issues, is to use the high/low -offset interrupts instead. This way only two thresholds need to be -managed, which have a simpler state machine, making them a better match -to the thermal framework's high and low thresholds. - -Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") -Signed-off-by: Nícolas F. R. A. Prado -Reviewed-by: Alexandre Mergnat -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230706153823.201943-4-nfraprado@collabora.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -298,9 +298,9 @@ static int lvts_set_trips(struct thermal - u32 raw_high = lvts_temp_to_raw(high); - - /* -- * Hot to normal temperature threshold -+ * Low offset temperature threshold - * -- * LVTS_H2NTHRE -+ * LVTS_OFFSETL - * - * Bits: - * -@@ -309,13 +309,13 @@ static int lvts_set_trips(struct thermal - if (low != -INT_MAX) { - pr_debug("%s: Setting low limit temperature interrupt: %d\n", - thermal_zone_device_type(tz), low); -- writel(raw_low, LVTS_H2NTHRE(base)); -+ writel(raw_low, LVTS_OFFSETL(base)); - } - - /* -- * Hot temperature threshold -+ * High offset temperature threshold - * -- * LVTS_HTHRE -+ * LVTS_OFFSETH - * - * Bits: - * -@@ -323,7 +323,7 @@ static int lvts_set_trips(struct thermal - */ - pr_debug("%s: Setting high limit temperature interrupt: %d\n", - thermal_zone_device_type(tz), high); -- writel(raw_high, LVTS_HTHRE(base)); -+ writel(raw_high, LVTS_OFFSETH(base)); - - return 0; - } diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch b/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch deleted file mode 100644 index 1c35d0ad1996a4..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-32-thermal-drivers-mediatek-lvts_thermal-Disable-undesi.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 8f8cab9d3e90acf1db278ef44ad05f10aefb973f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= - -Date: Thu, 6 Jul 2023 11:37:35 -0400 -Subject: [PATCH 28/42] thermal/drivers/mediatek/lvts_thermal: Disable - undesired interrupts -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Out of the many interrupts supported by the hardware, the only ones of -interest to the driver currently are: -* The temperature went over the high offset threshold, for any of the - sensors -* The temperature went below the low offset threshold, for any of the - sensors -* The temperature went over the stage3 threshold - -These are the only thresholds configured by the driver through the -OFFSETH, OFFSETL, and PROTTC registers, respectively. - -The current interrupt mask in LVTS_MONINT_CONF, enables many more -interrupts, including data ready on sensors for both filtered and -immediate mode. These are not only not handled by the driver, but they -are also triggered too often, causing unneeded overhead. Disable these -unnecessary interrupts. - -The meaning of each bit can be seen in the comment describing -LVTS_MONINTST in the IRQ handler. - -Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") -Signed-off-by: Nícolas F. R. A. Prado -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Alexandre Mergnat -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230706153823.201943-5-nfraprado@collabora.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -65,7 +65,7 @@ - #define LVTS_HW_FILTER 0x2 - #define LVTS_TSSEL_CONF 0x13121110 - #define LVTS_CALSCALE_CONF 0x300 --#define LVTS_MONINT_CONF 0x9FBF7BDE -+#define LVTS_MONINT_CONF 0x8300318C - - #define LVTS_INT_SENSOR0 0x0009001F - #define LVTS_INT_SENSOR1 0x001203E0 diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch b/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch deleted file mode 100644 index 60942fdb895dd9..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-33-thermal-drivers-mediatek-lvts_thermal-Don-t-leave-th.patch +++ /dev/null @@ -1,70 +0,0 @@ -From bd1ccf9408e6155564530af5e09b53ae497fe332 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= - -Date: Thu, 6 Jul 2023 11:37:36 -0400 -Subject: [PATCH 29/42] thermal/drivers/mediatek/lvts_thermal: Don't leave - threshold zeroed -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The thermal framework might leave the low threshold unset if there -aren't any lower trip points. This leaves the register zeroed, which -translates to a very high temperature for the low threshold. The -interrupt for this threshold is then immediately triggered, and the -state machine gets stuck, preventing any other temperature monitoring -interrupts to ever trigger. - -(The same happens by not setting the Cold or Hot to Normal thresholds -when using those) - -Set the unused threshold to a valid low value. This value was chosen so -that for any valid golden temperature read from the efuse, when the -value is converted to raw and back again to milliCelsius, the result -doesn't underflow. - -Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") -Signed-off-by: Nícolas F. R. A. Prado -Reviewed-by: Alexandre Mergnat -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230706153823.201943-6-nfraprado@collabora.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -83,6 +83,8 @@ - - #define LVTS_HW_SHUTDOWN_MT8195 105000 - -+#define LVTS_MINIMUM_THRESHOLD 20000 -+ - static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; - static int coeff_b = LVTS_COEFF_B; - -@@ -294,7 +296,7 @@ static int lvts_set_trips(struct thermal - { - struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); - void __iomem *base = lvts_sensor->base; -- u32 raw_low = lvts_temp_to_raw(low); -+ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); - u32 raw_high = lvts_temp_to_raw(high); - - /* -@@ -306,11 +308,9 @@ static int lvts_set_trips(struct thermal - * - * 14-0 : Raw temperature for threshold - */ -- if (low != -INT_MAX) { -- pr_debug("%s: Setting low limit temperature interrupt: %d\n", -- thermal_zone_device_type(tz), low); -- writel(raw_low, LVTS_OFFSETL(base)); -- } -+ pr_debug("%s: Setting low limit temperature interrupt: %d\n", -+ thermal_zone_device_type(tz), low); -+ writel(raw_low, LVTS_OFFSETL(base)); - - /* - * High offset temperature threshold diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch b/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch deleted file mode 100644 index e99aa0cdfd9b61..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-34-thermal-drivers-mediatek-lvts_thermal-Manage-thresho.patch +++ /dev/null @@ -1,156 +0,0 @@ -From d4dd09968cab3249e6148e1c3fccb51824edb411 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= - -Date: Thu, 6 Jul 2023 11:37:37 -0400 -Subject: [PATCH 30/42] thermal/drivers/mediatek/lvts_thermal: Manage threshold - between sensors -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Each LVTS thermal controller can have up to four sensors, each capable -of triggering its own interrupt when its measured temperature crosses -the configured threshold. The threshold for each sensor is handled -separately by the thermal framework, since each one is registered with -its own thermal zone and trips. However, the temperature thresholds are -configured on the controller, and therefore are shared between all -sensors on that controller. - -When the temperature measured by the sensors is different enough to -cause the thermal framework to configure different thresholds for each -one, interrupts start triggering on sensors outside the last threshold -configured. - -To address the issue, track the thresholds required by each sensor and -only actually set the highest one in the hardware, and disable -interrupts for all sensors outside the current configured range. - -Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver") -Signed-off-by: Nícolas F. R. A. Prado -Reviewed-by: Alexandre Mergnat -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230706153823.201943-7-nfraprado@collabora.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 69 +++++++++++++++++++++++++ - 1 file changed, 69 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -67,6 +67,11 @@ - #define LVTS_CALSCALE_CONF 0x300 - #define LVTS_MONINT_CONF 0x8300318C - -+#define LVTS_MONINT_OFFSET_SENSOR0 0xC -+#define LVTS_MONINT_OFFSET_SENSOR1 0x180 -+#define LVTS_MONINT_OFFSET_SENSOR2 0x3000 -+#define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 -+ - #define LVTS_INT_SENSOR0 0x0009001F - #define LVTS_INT_SENSOR1 0x001203E0 - #define LVTS_INT_SENSOR2 0x00247C00 -@@ -112,6 +117,8 @@ struct lvts_sensor { - void __iomem *base; - int id; - int dt_id; -+ int low_thresh; -+ int high_thresh; - }; - - struct lvts_ctrl { -@@ -121,6 +128,8 @@ struct lvts_ctrl { - int num_lvts_sensor; - int mode; - void __iomem *base; -+ int low_thresh; -+ int high_thresh; - }; - - struct lvts_domain { -@@ -292,12 +301,66 @@ static int lvts_get_temp(struct thermal_ - return 0; - } - -+static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) -+{ -+ u32 masks[] = { -+ LVTS_MONINT_OFFSET_SENSOR0, -+ LVTS_MONINT_OFFSET_SENSOR1, -+ LVTS_MONINT_OFFSET_SENSOR2, -+ LVTS_MONINT_OFFSET_SENSOR3, -+ }; -+ u32 value = 0; -+ int i; -+ -+ value = readl(LVTS_MONINT(lvts_ctrl->base)); -+ -+ for (i = 0; i < ARRAY_SIZE(masks); i++) { -+ if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh -+ && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) -+ value |= masks[i]; -+ else -+ value &= ~masks[i]; -+ } -+ -+ writel(value, LVTS_MONINT(lvts_ctrl->base)); -+} -+ -+static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) -+{ -+ int i; -+ -+ if (high > lvts_ctrl->high_thresh) -+ return true; -+ -+ for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) -+ if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh -+ && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) -+ return false; -+ -+ return true; -+} -+ - static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) - { - struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); -+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]); - void __iomem *base = lvts_sensor->base; - u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); - u32 raw_high = lvts_temp_to_raw(high); -+ bool should_update_thresh; -+ -+ lvts_sensor->low_thresh = low; -+ lvts_sensor->high_thresh = high; -+ -+ should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); -+ if (should_update_thresh) { -+ lvts_ctrl->high_thresh = high; -+ lvts_ctrl->low_thresh = low; -+ } -+ lvts_update_irq_mask(lvts_ctrl); -+ -+ if (!should_update_thresh) -+ return 0; - - /* - * Low offset temperature threshold -@@ -521,6 +584,9 @@ static int lvts_sensor_init(struct devic - */ - lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? - imm_regs[i] : msr_regs[i]; -+ -+ lvts_sensor[i].low_thresh = INT_MIN; -+ lvts_sensor[i].high_thresh = INT_MIN; - }; - - lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; -@@ -688,6 +754,9 @@ static int lvts_ctrl_init(struct device - */ - lvts_ctrl[i].hw_tshut_raw_temp = - lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); -+ -+ lvts_ctrl[i].low_thresh = INT_MIN; -+ lvts_ctrl[i].high_thresh = INT_MIN; - } - - /* diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch b/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch deleted file mode 100644 index 9ce3eeb74b53c8..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-35-thermal-drivers-mediatek-lvts-Fix-parameter-check-in.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 5af4904adc8b840987000724977c13c706d3b7d8 Mon Sep 17 00:00:00 2001 -From: Minjie Du -Date: Thu, 13 Jul 2023 12:24:12 +0800 -Subject: [PATCH 31/42] thermal/drivers/mediatek/lvts: Fix parameter check in - lvts_debugfs_init() - -The documentation says "If an error occurs, ERR_PTR(-ERROR) will be -returned" but the current code checks against a NULL pointer returned. - -Fix this by checking if IS_ERR(). - -Signed-off-by: Minjie Du -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230713042413.2519-1-duminjie@vivo.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -201,7 +201,7 @@ static int lvts_debugfs_init(struct devi - int i; - - lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); -- if (!lvts_td->dom_dentry) -+ if (IS_ERR(lvts_td->dom_dentry)) - return 0; - - for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch b/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch deleted file mode 100644 index 4841054917577c..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-36-thermal-drivers-mediatek-Clean-up-redundant-dev_err_.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 6186be80317d1dbda34d35c06c084a083938f2d3 Mon Sep 17 00:00:00 2001 -From: Chen Jiahao -Date: Wed, 2 Aug 2023 17:45:27 +0800 -Subject: [PATCH 32/42] thermal/drivers/mediatek: Clean up redundant - dev_err_probe() - -Referring to platform_get_irq()'s definition, the return value has -already been checked if ret < 0, and printed via dev_err_probe(). -Calling dev_err_probe() one more time outside platform_get_irq() -is obviously redundant. - -Removing dev_err_probe() outside platform_get_irq() to clean up -above problem. - -Signed-off-by: Chen Jiahao -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230802094527.988842-1-chenjiahao16@huawei.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -1216,7 +1216,7 @@ static int lvts_probe(struct platform_de - - irq = platform_get_irq(pdev, 0); - if (irq < 0) -- return dev_err_probe(dev, irq, "No irq resource\n"); -+ return irq; - - ret = lvts_domain_init(dev, lvts_td, lvts_data); - if (ret) diff --git a/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch b/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch deleted file mode 100644 index c88bf984fa7952..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.4-37-thermal-drivers-mediatek-lvts_thermal-Make-readings-.patch +++ /dev/null @@ -1,95 +0,0 @@ -From c2ab54ab0425388e65901a7af2fbf69ead968708 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= - -Date: Thu, 13 Jul 2023 11:42:37 -0400 -Subject: [PATCH 33/42] thermal/drivers/mediatek/lvts_thermal: Make readings - valid in filtered mode -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Currently, when a controller is configured to use filtered mode, thermal -readings are valid only about 30% of the time. - -Upon testing, it was noticed that lowering any of the interval settings -resulted in an improved rate of valid data. The same was observed when -decreasing the number of samples for each sensor (which also results in -quicker measurements). - -Retrying the read with a timeout longer than the time it takes to -resample (about 344us with these settings and 4 sensors) also improves -the rate. - -Lower all timing settings to the minimum, configure the filtering to -single sample, and poll the measurement register for at least one period -to improve the data validity on filtered mode. With these changes in -place, out of 100000 reads, a single one failed, ie 99.999% of the data -was valid. - -Reviewed-by: Chen-Yu Tsai -Tested-by: Chen-Yu Tsai -Signed-off-by: Nícolas F. R. A. Prado -Reviewed-by: Alexandre Mergnat -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230713154743.611870-1-nfraprado@collabora.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 19 ++++++++++++------- - 1 file changed, 12 insertions(+), 7 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -58,11 +58,11 @@ - #define LVTS_PROTTC(__base) (__base + 0x00CC) - #define LVTS_CLKEN(__base) (__base + 0x00E4) - --#define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38)) --#define LVTS_GROUP_INTERVAL 1 --#define LVTS_FILTER_INTERVAL 1 --#define LVTS_SENSOR_INTERVAL 1 --#define LVTS_HW_FILTER 0x2 -+#define LVTS_PERIOD_UNIT 0 -+#define LVTS_GROUP_INTERVAL 0 -+#define LVTS_FILTER_INTERVAL 0 -+#define LVTS_SENSOR_INTERVAL 0 -+#define LVTS_HW_FILTER 0x0 - #define LVTS_TSSEL_CONF 0x13121110 - #define LVTS_CALSCALE_CONF 0x300 - #define LVTS_MONINT_CONF 0x8300318C -@@ -86,6 +86,9 @@ - #define LVTS_MSR_IMMEDIATE_MODE 0 - #define LVTS_MSR_FILTERED_MODE 1 - -+#define LVTS_MSR_READ_TIMEOUT_US 400 -+#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) -+ - #define LVTS_HW_SHUTDOWN_MT8195 105000 - - #define LVTS_MINIMUM_THRESHOLD 20000 -@@ -268,6 +271,7 @@ static int lvts_get_temp(struct thermal_ - struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); - void __iomem *msr = lvts_sensor->msr; - u32 value; -+ int rc; - - /* - * Measurement registers: -@@ -280,7 +284,8 @@ static int lvts_get_temp(struct thermal_ - * 16 : Valid temperature - * 15-0 : Raw temperature - */ -- value = readl(msr); -+ rc = readl_poll_timeout(msr, value, value & BIT(16), -+ LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); - - /* - * As the thermal zone temperature will read before the -@@ -293,7 +298,7 @@ static int lvts_get_temp(struct thermal_ - * functionning temperature and directly jump to a system - * shutdown. - */ -- if (!(value & BIT(16))) -+ if (rc) - return -EAGAIN; - - *temp = lvts_raw_to_temp(value & 0xFFFF); diff --git a/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch b/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch deleted file mode 100644 index 994461cdb161bc..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.6-38-thermal-drivers-mediatek-auxadc_thermal-Removed-call.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c864ff9de3b225b43bb8e08dedb223632323e059 Mon Sep 17 00:00:00 2001 -From: Andrei Coardos -Date: Fri, 11 Aug 2023 22:28:47 +0300 -Subject: [PATCH 34/42] thermal/drivers/mediatek/auxadc_thermal: Removed call - to platform_set_drvdata() - -This function call was found to be unnecessary as there is no equivalent -platform_get_drvdata() call to access the private data of the driver. Also, -the private data is defined in this driver, so there is no risk of it being -accessed outside of this driver file. - -Signed-off-by: Andrei Coardos -Reviewed-by: Alexandru Ardelean -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230811192847.3838-1-aboutphysycs@gmail.com ---- - drivers/thermal/mediatek/auxadc_thermal.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -1283,8 +1283,6 @@ static int mtk_thermal_probe(struct plat - mtk_thermal_init_bank(mt, i, apmixed_phys_base, - auxadc_phys_base, ctrl_id); - -- platform_set_drvdata(pdev, mt); -- - tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt, - &mtk_thermal_ops); - if (IS_ERR(tzdev)) diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch b/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch deleted file mode 100644 index b3bfa37458c8b9..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-39-thermal-lvts-Convert-to-platform-remove-callback-ret.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Wed, 27 Sep 2023 21:37:23 +0200 -Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback - returning void -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The .remove() callback for a platform driver returns an int which makes -many driver authors wrongly assume it's possible to do error handling by -returning an error code. However the value returned is ignored (apart -from emitting a warning) and this typically results in resource leaks. - -To improve here there is a quest to make the remove callback return -void. In the first step of this quest all drivers are converted to -.remove_new(), which already returns void. Eventually after all drivers -are converted, .remove_new() will be renamed to .remove(). - -Trivially convert this driver from always returning zero in the remove -callback to the void returning variant. - -Signed-off-by: Uwe Kleine-König -Acked-by: Daniel Lezcano -Signed-off-by: Rafael J. Wysocki ---- - drivers/thermal/mediatek/lvts_thermal.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -1241,7 +1241,7 @@ static int lvts_probe(struct platform_de - return 0; - } - --static int lvts_remove(struct platform_device *pdev) -+static void lvts_remove(struct platform_device *pdev) - { - struct lvts_domain *lvts_td; - int i; -@@ -1252,8 +1252,6 @@ static int lvts_remove(struct platform_d - lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); - - lvts_debugfs_exit(lvts_td); -- -- return 0; - } - - static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { -@@ -1354,7 +1352,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match); - - static struct platform_driver lvts_driver = { - .probe = lvts_probe, -- .remove = lvts_remove, -+ .remove_new = lvts_remove, - .driver = { - .name = "mtk-lvts-thermal", - .of_match_table = lvts_of_match, diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch b/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch deleted file mode 100644 index 16a32f564bf352..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-40-thermal-drivers-mediatek-lvts_thermal-Make-coeff-con.patch +++ /dev/null @@ -1,198 +0,0 @@ -From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 22 Sep 2023 07:50:19 +0200 -Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff - configurable - -The upcoming mt7988 has different temperature coefficients so we -cannot use constants in the functions lvts_golden_temp_init, -lvts_golden_temp_init and lvts_raw_to_temp anymore. - -Add a field in the lvts_ctrl pointing to the lvts_data which now -contains the soc-specific temperature coefficents. - -To make the code better readable, rename static int coeff_b to -golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Tested-by: Daniel Golle -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de ---- - drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++--------- - 1 file changed, 34 insertions(+), 17 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -80,8 +80,8 @@ - #define LVTS_SENSOR_MAX 4 - #define LVTS_GOLDEN_TEMP_MAX 62 - #define LVTS_GOLDEN_TEMP_DEFAULT 50 --#define LVTS_COEFF_A -250460 --#define LVTS_COEFF_B 250460 -+#define LVTS_COEFF_A_MT8195 -250460 -+#define LVTS_COEFF_B_MT8195 250460 - - #define LVTS_MSR_IMMEDIATE_MODE 0 - #define LVTS_MSR_FILTERED_MODE 1 -@@ -94,7 +94,7 @@ - #define LVTS_MINIMUM_THRESHOLD 20000 - - static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; --static int coeff_b = LVTS_COEFF_B; -+static int golden_temp_offset; - - struct lvts_sensor_data { - int dt_id; -@@ -112,6 +112,8 @@ struct lvts_ctrl_data { - struct lvts_data { - const struct lvts_ctrl_data *lvts_ctrl; - int num_lvts_ctrl; -+ int temp_factor; -+ int temp_offset; - }; - - struct lvts_sensor { -@@ -126,6 +128,7 @@ struct lvts_sensor { - - struct lvts_ctrl { - struct lvts_sensor sensors[LVTS_SENSOR_MAX]; -+ const struct lvts_data *lvts_data; - u32 calibration[LVTS_SENSOR_MAX]; - u32 hw_tshut_raw_temp; - int num_lvts_sensor; -@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt - - #endif - --static int lvts_raw_to_temp(u32 raw_temp) -+static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) - { - int temperature; - -- temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; -- temperature += coeff_b; -+ temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; -+ temperature += golden_temp_offset; - - return temperature; - } - --static u32 lvts_temp_to_raw(int temperature) -+static u32 lvts_temp_to_raw(int temperature, int temp_factor) - { -- u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; -+ u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; - -- raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); -+ raw_temp = div_s64(raw_temp, -temp_factor); - - return raw_temp; - } -@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat - static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) - { - struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); -+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, -+ sensors[lvts_sensor->id]); -+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; - void __iomem *msr = lvts_sensor->msr; - u32 value; - int rc; -@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_ - if (rc) - return -EAGAIN; - -- *temp = lvts_raw_to_temp(value & 0xFFFF); -+ *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); - - return 0; - } -@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st - static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) - { - struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); -- struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]); -+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, -+ sensors[lvts_sensor->id]); -+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; - void __iomem *base = lvts_sensor->base; -- u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); -- u32 raw_high = lvts_temp_to_raw(high); -+ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, -+ lvts_data->temp_factor); -+ u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); - bool should_update_thresh; - - lvts_sensor->low_thresh = low; -@@ -692,7 +701,7 @@ static int lvts_calibration_read(struct - return 0; - } - --static int lvts_golden_temp_init(struct device *dev, u32 *value) -+static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset) - { - u32 gt; - -@@ -701,7 +710,7 @@ static int lvts_golden_temp_init(struct - if (gt && gt < LVTS_GOLDEN_TEMP_MAX) - golden_temp = gt; - -- coeff_b = golden_temp * 500 + LVTS_COEFF_B; -+ golden_temp_offset = golden_temp * 500 + temp_offset; - - return 0; - } -@@ -724,7 +733,7 @@ static int lvts_ctrl_init(struct device - * The golden temp information is contained in the first chunk - * of efuse data. - */ -- ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); -+ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset); - if (ret) - return ret; - -@@ -735,6 +744,7 @@ static int lvts_ctrl_init(struct device - for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { - - lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; -+ lvts_ctrl[i].lvts_data = lvts_data; - - ret = lvts_sensor_init(dev, &lvts_ctrl[i], - &lvts_data->lvts_ctrl[i]); -@@ -758,7 +768,8 @@ static int lvts_ctrl_init(struct device - * after initializing the calibration. - */ - lvts_ctrl[i].hw_tshut_raw_temp = -- lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); -+ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp, -+ lvts_data->temp_factor); - - lvts_ctrl[i].low_thresh = INT_MIN; - lvts_ctrl[i].high_thresh = INT_MIN; -@@ -1223,6 +1234,8 @@ static int lvts_probe(struct platform_de - if (irq < 0) - return irq; - -+ golden_temp_offset = lvts_data->temp_offset; -+ - ret = lvts_domain_init(dev, lvts_td, lvts_data); - if (ret) - return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); -@@ -1336,11 +1349,15 @@ static const struct lvts_ctrl_data mt819 - static const struct lvts_data mt8195_lvts_mcu_data = { - .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), -+ .temp_factor = LVTS_COEFF_A_MT8195, -+ .temp_offset = LVTS_COEFF_B_MT8195, - }; - - static const struct lvts_data mt8195_lvts_ap_data = { - .lvts_ctrl = mt8195_lvts_ap_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), -+ .temp_factor = LVTS_COEFF_A_MT8195, -+ .temp_offset = LVTS_COEFF_B_MT8195, - }; - - static const struct of_device_id lvts_of_match[] = { diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch b/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch deleted file mode 100644 index 1c2146f43f91e5..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-41-dt-bindings-thermal-mediatek-Add-LVTS-thermal-sensor.patch +++ /dev/null @@ -1,35 +0,0 @@ -From be2cc09bd5b46f13629d4fcdeac7ad1b18bb1a0b Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 22 Sep 2023 07:50:18 +0200 -Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal sensors for - mt7988 - -Add sensor constants for MT7988. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Acked-by: Conor Dooley -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de ---- - include/dt-bindings/thermal/mediatek,lvts-thermal.h | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h -+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h -@@ -7,6 +7,15 @@ - #ifndef __MEDIATEK_LVTS_DT_H - #define __MEDIATEK_LVTS_DT_H - -+#define MT7988_CPU_0 0 -+#define MT7988_CPU_1 1 -+#define MT7988_ETH2P5G_0 2 -+#define MT7988_ETH2P5G_1 3 -+#define MT7988_TOPS_0 4 -+#define MT7988_TOPS_1 5 -+#define MT7988_ETHWARP_0 6 -+#define MT7988_ETHWARP_1 7 -+ - #define MT8195_MCU_BIG_CPU0 0 - #define MT8195_MCU_BIG_CPU1 1 - #define MT8195_MCU_BIG_CPU2 2 diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch b/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch deleted file mode 100644 index 97c803a820bbe8..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-42-thermal-drivers-mediatek-lvts_thermal-Add-mt7988-sup.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 22 Sep 2023 07:50:20 +0200 -Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988 - support - -Add Support for Mediatek Filogic 880/MT7988 LVTS. - -Signed-off-by: Frank Wunderlich -Tested-by: Daniel Golle -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de ---- - drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -82,6 +82,8 @@ - #define LVTS_GOLDEN_TEMP_DEFAULT 50 - #define LVTS_COEFF_A_MT8195 -250460 - #define LVTS_COEFF_B_MT8195 250460 -+#define LVTS_COEFF_A_MT7988 -204650 -+#define LVTS_COEFF_B_MT7988 204650 - - #define LVTS_MSR_IMMEDIATE_MODE 0 - #define LVTS_MSR_FILTERED_MODE 1 -@@ -89,6 +91,7 @@ - #define LVTS_MSR_READ_TIMEOUT_US 400 - #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) - -+#define LVTS_HW_SHUTDOWN_MT7988 105000 - #define LVTS_HW_SHUTDOWN_MT8195 105000 - - #define LVTS_MINIMUM_THRESHOLD 20000 -@@ -1267,6 +1270,33 @@ static void lvts_remove(struct platform_ - lvts_debugfs_exit(lvts_td); - } - -+static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { -+ { -+ .cal_offset = { 0x00, 0x04, 0x08, 0x0c }, -+ .lvts_sensor = { -+ { .dt_id = MT7988_CPU_0 }, -+ { .dt_id = MT7988_CPU_1 }, -+ { .dt_id = MT7988_ETH2P5G_0 }, -+ { .dt_id = MT7988_ETH2P5G_1 } -+ }, -+ .num_lvts_sensor = 4, -+ .offset = 0x0, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, -+ }, -+ { -+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, -+ .lvts_sensor = { -+ { .dt_id = MT7988_TOPS_0}, -+ { .dt_id = MT7988_TOPS_1}, -+ { .dt_id = MT7988_ETHWARP_0}, -+ { .dt_id = MT7988_ETHWARP_1} -+ }, -+ .num_lvts_sensor = 4, -+ .offset = 0x100, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, -+ } -+}; -+ - static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { - { - .cal_offset = { 0x04, 0x07 }, -@@ -1346,6 +1376,13 @@ static const struct lvts_ctrl_data mt819 - } - }; - -+static const struct lvts_data mt7988_lvts_ap_data = { -+ .lvts_ctrl = mt7988_lvts_ap_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), -+ .temp_factor = LVTS_COEFF_A_MT7988, -+ .temp_offset = LVTS_COEFF_B_MT7988, -+}; -+ - static const struct lvts_data mt8195_lvts_mcu_data = { - .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), -@@ -1361,6 +1398,7 @@ static const struct lvts_data mt8195_lvt - }; - - static const struct of_device_id lvts_of_match[] = { -+ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, - { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, - { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, - {}, diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch b/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch deleted file mode 100644 index 5b212a2a372ea4..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-43-thermal-drivers-mediatek-lvts_thermal-Fix-error-chec.patch +++ /dev/null @@ -1,30 +0,0 @@ -From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001 -From: Minjie Du -Date: Thu, 21 Sep 2023 17:10:50 +0800 -Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check - in lvts_debugfs_init() - -debugfs_create_dir() function returns an error value embedded in -the pointer (PTR_ERR). Evaluate the return value using IS_ERR -rather than checking for NULL. - -Signed-off-by: Minjie Du -Reviewed-by: Alexandre Mergnat -Reviewed-by: Chen-Yu Tsai -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi - - sprintf(name, "controller%d", i); - dentry = debugfs_create_dir(name, lvts_td->dom_dentry); -- if (!dentry) -+ if (IS_ERR(dentry)) - continue; - - regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch b/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch deleted file mode 100644 index 88f383c4aecc5b..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch +++ /dev/null @@ -1,33 +0,0 @@ -From e6f43063f2fe9f08b34797bc6d223f7d63b01910 Mon Sep 17 00:00:00 2001 -From: Markus Schneider-Pargmann -Date: Mon, 18 Sep 2023 12:07:06 +0200 -Subject: [PATCH 39/42] thermal/drivers/mediatek: Fix probe for THERMAL_V2 - -Fix the probe function to call mtk_thermal_release_periodic_ts for -everything != MTK_THERMAL_V1. This was accidentally changed from V1 -to V2 in the original patch. - -Reported-by: Frank Wunderlich -Closes: https://lore.kernel.org/lkml/B0B3775B-B8D1-4284-814F-4F41EC22F532@public-files.de/ -Reported-by: Daniel Lezcano -Closes: https://lore.kernel.org/lkml/07a569b9-e691-64ea-dd65-3b49842af33d@linaro.org/ -Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks") -Signed-off-by: Markus Schneider-Pargmann -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20230918100706.1229239-1-msp@baylibre.com ---- - drivers/thermal/mediatek/auxadc_thermal.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -1268,7 +1268,7 @@ static int mtk_thermal_probe(struct plat - - mtk_thermal_turn_on_buffer(mt, apmixed_base); - -- if (mt->conf->version != MTK_THERMAL_V2) -+ if (mt->conf->version != MTK_THERMAL_V1) - mtk_thermal_release_periodic_ts(mt, auxadc_base); - - if (mt->conf->version == MTK_THERMAL_V1) diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch b/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch deleted file mode 100644 index 7b4b124b561fcc..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-45-thermal-drivers-mediatek-lvts_thermal-Add-suspend-an.patch +++ /dev/null @@ -1,83 +0,0 @@ -From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 17 Oct 2023 21:05:42 +0200 -Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and - resume -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add suspend and resume support to LVTS driver. - -Signed-off-by: Balsam CHIHI -[bero@baylibre.com: suspend/resume in noirq phase] -Co-developed-by: Bernhard Rosenkränzer -Signed-off-by: Bernhard Rosenkränzer -Reviewed-by: Matthias Brugger -Reviewed-by: Alexandre Mergnat -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -1297,6 +1297,38 @@ static const struct lvts_ctrl_data mt798 - } - }; - -+static int lvts_suspend(struct device *dev) -+{ -+ struct lvts_domain *lvts_td; -+ int i; -+ -+ lvts_td = dev_get_drvdata(dev); -+ -+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) -+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); -+ -+ clk_disable_unprepare(lvts_td->clk); -+ -+ return 0; -+} -+ -+static int lvts_resume(struct device *dev) -+{ -+ struct lvts_domain *lvts_td; -+ int i, ret; -+ -+ lvts_td = dev_get_drvdata(dev); -+ -+ ret = clk_prepare_enable(lvts_td->clk); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) -+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); -+ -+ return 0; -+} -+ - static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { - { - .cal_offset = { 0x04, 0x07 }, -@@ -1405,12 +1437,17 @@ static const struct of_device_id lvts_of - }; - MODULE_DEVICE_TABLE(of, lvts_of_match); - -+static const struct dev_pm_ops lvts_pm_ops = { -+ NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) -+}; -+ - static struct platform_driver lvts_driver = { - .probe = lvts_probe, - .remove_new = lvts_remove, - .driver = { - .name = "mtk-lvts-thermal", - .of_match_table = lvts_of_match, -+ .pm = &lvts_pm_ops, - }, - }; - module_platform_driver(lvts_driver); diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch b/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch deleted file mode 100644 index c278168610f5e8..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-46-dt-bindings-thermal-mediatek-Add-LVTS-thermal-contro.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 0bb4937b58ab712f158588376dbac97f8e9df68e Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 17 Oct 2023 21:05:41 +0200 -Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controller - definition for mt8192 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add LVTS thermal controller definition for MT8192. - -Signed-off-by: Balsam CHIHI -Reviewed-by: AngeloGioacchino Del Regno -Acked-by: Krzysztof Kozlowski -Signed-off-by: Bernhard Rosenkränzer -Reviewed-by: Matthias Brugger -Reviewed-by: Alexandre Mergnat -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com ---- - .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h -+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h -@@ -35,4 +35,23 @@ - #define MT8195_AP_CAM0 15 - #define MT8195_AP_CAM1 16 - -+#define MT8192_MCU_BIG_CPU0 0 -+#define MT8192_MCU_BIG_CPU1 1 -+#define MT8192_MCU_BIG_CPU2 2 -+#define MT8192_MCU_BIG_CPU3 3 -+#define MT8192_MCU_LITTLE_CPU0 4 -+#define MT8192_MCU_LITTLE_CPU1 5 -+#define MT8192_MCU_LITTLE_CPU2 6 -+#define MT8192_MCU_LITTLE_CPU3 7 -+ -+#define MT8192_AP_VPU0 8 -+#define MT8192_AP_VPU1 9 -+#define MT8192_AP_GPU0 10 -+#define MT8192_AP_GPU1 11 -+#define MT8192_AP_INFRA 12 -+#define MT8192_AP_CAM 13 -+#define MT8192_AP_MD0 14 -+#define MT8192_AP_MD1 15 -+#define MT8192_AP_MD2 16 -+ - #endif /* __MEDIATEK_LVTS_DT_H */ diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch b/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch deleted file mode 100644 index 6d68a6cd5799c6..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-47-thermal-drivers-mediatek-lvts_thermal-Add-mt8192-sup.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 17 Oct 2023 21:05:43 +0200 -Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192 - support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add LVTS Driver support for MT8192. - -Co-developed-by: Nícolas F. R. A. Prado -Signed-off-by: Nícolas F. R. A. Prado -Signed-off-by: Balsam CHIHI -Reviewed-by: Nícolas F. R. A. Prado -[bero@baylibre.com: cosmetic changes, rebase] -Signed-off-by: Bernhard Rosenkränzer -Reviewed-by: Matthias Brugger -Reviewed-by: Alexandre Mergnat -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++ - 1 file changed, 95 insertions(+) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -92,6 +92,7 @@ - #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) - - #define LVTS_HW_SHUTDOWN_MT7988 105000 -+#define LVTS_HW_SHUTDOWN_MT8192 105000 - #define LVTS_HW_SHUTDOWN_MT8195 105000 - - #define LVTS_MINIMUM_THRESHOLD 20000 -@@ -1329,6 +1330,88 @@ static int lvts_resume(struct device *de - return 0; - } - -+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { -+ { -+ .cal_offset = { 0x04, 0x08 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_MCU_BIG_CPU0 }, -+ { .dt_id = MT8192_MCU_BIG_CPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x0, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ .mode = LVTS_MSR_FILTERED_MODE, -+ }, -+ { -+ .cal_offset = { 0x0c, 0x10 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_MCU_BIG_CPU2 }, -+ { .dt_id = MT8192_MCU_BIG_CPU3 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x100, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ .mode = LVTS_MSR_FILTERED_MODE, -+ }, -+ { -+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_MCU_LITTLE_CPU0 }, -+ { .dt_id = MT8192_MCU_LITTLE_CPU1 }, -+ { .dt_id = MT8192_MCU_LITTLE_CPU2 }, -+ { .dt_id = MT8192_MCU_LITTLE_CPU3 } -+ }, -+ .num_lvts_sensor = 4, -+ .offset = 0x200, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ .mode = LVTS_MSR_FILTERED_MODE, -+ } -+}; -+ -+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { -+ { -+ .cal_offset = { 0x24, 0x28 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_AP_VPU0 }, -+ { .dt_id = MT8192_AP_VPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x0, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ }, -+ { -+ .cal_offset = { 0x2c, 0x30 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_AP_GPU0 }, -+ { .dt_id = MT8192_AP_GPU1 } -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x100, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ }, -+ { -+ .cal_offset = { 0x34, 0x38 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_AP_INFRA }, -+ { .dt_id = MT8192_AP_CAM }, -+ }, -+ .num_lvts_sensor = 2, -+ .offset = 0x200, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ }, -+ { -+ .cal_offset = { 0x3c, 0x40, 0x44 }, -+ .lvts_sensor = { -+ { .dt_id = MT8192_AP_MD0 }, -+ { .dt_id = MT8192_AP_MD1 }, -+ { .dt_id = MT8192_AP_MD2 } -+ }, -+ .num_lvts_sensor = 3, -+ .offset = 0x300, -+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, -+ } -+}; -+ - static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { - { - .cal_offset = { 0x04, 0x07 }, -@@ -1415,6 +1498,16 @@ static const struct lvts_data mt7988_lvt - .temp_offset = LVTS_COEFF_B_MT7988, - }; - -+static const struct lvts_data mt8192_lvts_mcu_data = { -+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), -+}; -+ -+static const struct lvts_data mt8192_lvts_ap_data = { -+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl, -+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), -+}; -+ - static const struct lvts_data mt8195_lvts_mcu_data = { - .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, - .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), -@@ -1431,6 +1524,8 @@ static const struct lvts_data mt8195_lvt - - static const struct of_device_id lvts_of_match[] = { - { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, -+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, -+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, - { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, - { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, - {}, diff --git a/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch b/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch deleted file mode 100644 index c20c0b5f2e3dfe..00000000000000 --- a/target/linux/mediatek/patches-6.1/830-v6.7-48-thermal-drivers-mediatek-lvts_thermal-Update-calibra.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001 -From: Balsam CHIHI -Date: Tue, 17 Oct 2023 21:05:45 +0200 -Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update - calibration data documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Update LVTS calibration data documentation for mt8192 and mt8195. - -Signed-off-by: Balsam CHIHI -Reviewed-by: Nícolas F. R. A. Prado -[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado ] -Signed-off-by: Bernhard Rosenkränzer -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Alexandre Mergnat -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com ---- - drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++-- - 1 file changed, 29 insertions(+), 2 deletions(-) - ---- a/drivers/thermal/mediatek/lvts_thermal.c -+++ b/drivers/thermal/mediatek/lvts_thermal.c -@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic - * The efuse blob values follows the sensor enumeration per thermal - * controller. The decoding of the stream is as follow: - * -- * stream index map for MCU Domain : -+ * MT8192 : -+ * Stream index map for MCU Domain mt8192 : -+ * -+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> -+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B -+ * -+ * <-----sensor#2-----> <-----sensor#3-----> -+ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 -+ * -+ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> -+ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 -+ * -+ * Stream index map for AP Domain mt8192 : -+ * -+ * <-----sensor#0-----> <-----sensor#1-----> -+ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B -+ * -+ * <-----sensor#2-----> <-----sensor#3-----> -+ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 -+ * -+ * <-----sensor#4-----> <-----sensor#5-----> -+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B -+ * -+ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> -+ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 -+ * -+ * MT8195 : -+ * Stream index map for MCU Domain mt8195 : - * - * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> - * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 -@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic - * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> - * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 - * -- * stream index map for AP Domain : -+ * Stream index map for AP Domain mt8195 : - * - * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> - * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A diff --git a/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch b/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch deleted file mode 100644 index fc173646e053f7..00000000000000 --- a/target/linux/mediatek/patches-6.1/831-thermal-drivers-mediatek-Fix-control-buffer-enablement-on-MT7896.patch +++ /dev/null @@ -1,59 +0,0 @@ -From patchwork Thu Sep 7 11:20:18 2023 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Frank Wunderlich -X-Patchwork-Id: 13376356 -From: Frank Wunderlich -To: linux-mediatek@lists.infradead.org -Subject: [PATCH] thermal/drivers/mediatek: Fix control buffer enablement on - MT7896 -Date: Thu, 7 Sep 2023 13:20:18 +0200 -Message-Id: <20230907112018.52811-1-linux@fw-web.de> -X-Mailer: git-send-email 2.34.1 -MIME-Version: 1.0 -X-Mail-ID: e7eeb8e1-00de-41f6-a5df-ce2e9164136e -X-BeenThere: linux-mediatek@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -Cc: Daniel Lezcano , - "Rafael J. Wysocki" , linux-pm@vger.kernel.org, - Amit Kucheria , Daniel Golle , - stable@vger.kernel.org, linux-kernel@vger.kernel.org, - Matthias Brugger , Zhang Rui , - linux-arm-kernel@lists.infradead.org, - AngeloGioacchino Del Regno -Sender: "Linux-mediatek" - -From: Frank Wunderlich - -Reading thermal sensor on mt7986 devices returns invalid temperature: - -bpi-r3 ~ # cat /sys/class/thermal/thermal_zone0/temp - -274000 - -Fix this by adding missing members in mtk_thermal_data struct which were -used in mtk_thermal_turn_on_buffer after commit 33140e668b10. - -Cc: stable@vger.kernel.org -Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks") -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Markus Schneider-Pargmann ---- - drivers/thermal/mediatek/auxadc_thermal.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/thermal/mediatek/auxadc_thermal.c -+++ b/drivers/thermal/mediatek/auxadc_thermal.c -@@ -691,6 +691,9 @@ static const struct mtk_thermal_data mt7 - .adcpnp = mt7986_adcpnp, - .sensor_mux_values = mt7986_mux_values, - .version = MTK_THERMAL_V3, -+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, -+ .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), -+ .apmixed_buffer_ctl_set = BIT(0), - }; - - static bool mtk_thermal_temp_is_valid(int temp) diff --git a/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch b/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch deleted file mode 100644 index 4c398c59f93551..00000000000000 --- a/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 9 Oct 2022 12:16:31 +0200 -Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support - -Add i2c support for MT7986 SoC. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt7986_compat = { -+ .quirks = &mt7622_i2c_quirks, -+ .regs = mt_i2c_regs_v1, -+ .pmic_i2c = 0, -+ .dcm = 1, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 0, -+ .dma_sync = 1, -+ .ltiming_adjust = 0, -+ .max_dma_support = 32, -+}; -+ - static const struct mtk_i2c_compatible mt8173_compat = { - .regs = mt_i2c_regs_v1, - .pmic_i2c = 0, -@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, - { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, diff --git a/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch b/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch deleted file mode 100644 index 18c66cdac52910..00000000000000 --- a/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001 -From: ye xingchen -Date: Thu, 19 Jan 2023 17:19:58 +0800 -Subject: [PATCH 13/16] i2c: mt65xx: Use - devm_platform_get_and_ioremap_resource() - -Convert platform_get_resource(), devm_ioremap_resource() to a single -call to devm_platform_get_and_ioremap_resource(), as this is exactly -what this function does. - -Signed-off-by: ye xingchen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform - { - int ret = 0; - struct mtk_i2c *i2c; -- struct resource *res; - int i, irq, speed_clk; - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) - return -ENOMEM; - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- i2c->base = devm_ioremap_resource(&pdev->dev, res); -+ i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(i2c->base)) - return PTR_ERR(i2c->base); - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -- i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); -+ i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(i2c->pdmabase)) - return PTR_ERR(i2c->pdmabase); - diff --git a/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch b/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch deleted file mode 100644 index d000d535226f42..00000000000000 --- a/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Sat, 11 Mar 2023 12:16:54 +0100 -Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The driver can match only via the DT table so the table should be always -used and the of_match_ptr does not have any sense (this also allows ACPI -matching via PRP0001, even though it might not be relevant here). - - drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=] - -Signed-off-by: Krzysztof Kozlowski -Reviewed-by: Guenter Roeck -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr - .driver = { - .name = I2C_DRV_NAME, - .pm = &mtk_i2c_pm, -- .of_match_table = of_match_ptr(mtk_i2c_of_match), -+ .of_match_table = mtk_i2c_of_match, - }, - }; - diff --git a/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch b/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch deleted file mode 100644 index e0973741e29d68..00000000000000 --- a/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch +++ /dev/null @@ -1,47 +0,0 @@ -From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 10 Apr 2023 17:19:38 +0100 -Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC - -Add support for the I2C units found in the MediaTek MT7981 and MT7988 -SoCs. Just like other recent MediaTek I2C units that also uses v3 -register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being -0x94 instead of 0x4). - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Alexandre Mergnat -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt7981_compat = { -+ .regs = mt_i2c_regs_v3, -+ .pmic_i2c = 0, -+ .dcm = 0, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 1, -+ .ltiming_adjust = 1, -+ .max_dma_support = 33 -+}; -+ - static const struct mtk_i2c_compatible mt7986_compat = { - .quirks = &mt7622_i2c_quirks, - .regs = mt_i2c_regs_v1, -@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat }, - { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, - { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, diff --git a/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch b/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch deleted file mode 100644 index 69cc155d8d2307..00000000000000 --- a/target/linux/mediatek/patches-6.1/855-i2c-mt65xx-allow-optional-pmic-clock.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sat, 26 Aug 2023 21:56:51 +0100 -Subject: [PATCH] i2c: mt65xx: allow optional pmic clock - -Using the I2C host controller on the MT7981 SoC requires 4 clocks to -be enabled. One of them, the pmic clk, is only enabled in case -'mediatek,have-pmic' is also set which has other consequences which -are not desired in this case. - -Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty -is not present and the bus is not used to connect to a pmic, but may -still require to enable the pmic clock. - -Signed-off-by: Daniel Golle ---- - drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform - if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) - return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk); - -+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic"); -+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { -+ dev_err(&pdev->dev, "cannot get pmic clock\n"); -+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); -+ } -+ - if (i2c->have_pmic) { -- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic"); -- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { -+ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) { - dev_err(&pdev->dev, "cannot get pmic clock\n"); -- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); -+ return -ENODEV; - } - speed_clk = I2C_MT65XX_CLK_PMIC; - } else { -- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL; - speed_clk = I2C_MT65XX_CLK_MAIN; - } - diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch b/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch deleted file mode 100644 index 9607eec821082b..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.6-01-ASoC-mediatek-mt7986-add-common-header.patch +++ /dev/null @@ -1,269 +0,0 @@ -From d35469096915f2551ed1d26da1ab12ff500fc963 Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 17 Aug 2023 18:13:33 +0800 -Subject: [PATCH 1/9] ASoC: mediatek: mt7986: add common header - -Add header files for register definition and structure. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/mt7986/mt7986-afe-common.h | 49 +++++ - sound/soc/mediatek/mt7986/mt7986-reg.h | 196 ++++++++++++++++++ - 2 files changed, 245 insertions(+) - create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-common.h - create mode 100644 sound/soc/mediatek/mt7986/mt7986-reg.h - ---- /dev/null -+++ b/sound/soc/mediatek/mt7986/mt7986-afe-common.h -@@ -0,0 +1,49 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * mt7986-afe-common.h -- MediaTek 7986 audio driver definitions -+ * -+ * Copyright (c) 2023 MediaTek Inc. -+ * Authors: Vic Wu -+ * Maso Huang -+ */ -+ -+#ifndef _MT_7986_AFE_COMMON_H_ -+#define _MT_7986_AFE_COMMON_H_ -+ -+#include -+#include -+#include -+#include -+#include "../common/mtk-base-afe.h" -+ -+enum { -+ MT7986_MEMIF_DL1, -+ MT7986_MEMIF_VUL12, -+ MT7986_MEMIF_NUM, -+ MT7986_DAI_ETDM = MT7986_MEMIF_NUM, -+ MT7986_DAI_NUM, -+}; -+ -+enum { -+ MT7986_IRQ_0, -+ MT7986_IRQ_1, -+ MT7986_IRQ_2, -+ MT7986_IRQ_NUM, -+}; -+ -+struct mt7986_afe_private { -+ struct clk_bulk_data *clks; -+ int num_clks; -+ -+ int pm_runtime_bypass_reg_ctl; -+ -+ /* dai */ -+ void *dai_priv[MT7986_DAI_NUM]; -+}; -+ -+unsigned int mt7986_afe_rate_transform(struct device *dev, -+ unsigned int rate); -+ -+/* dai register */ -+int mt7986_dai_etdm_register(struct mtk_base_afe *afe); -+#endif ---- /dev/null -+++ b/sound/soc/mediatek/mt7986/mt7986-reg.h -@@ -0,0 +1,196 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * mt7986-reg.h -- MediaTek 7986 audio driver reg definition -+ * -+ * Copyright (c) 2023 MediaTek Inc. -+ * Authors: Vic Wu -+ * Maso Huang -+ */ -+ -+#ifndef _MT7986_REG_H_ -+#define _MT7986_REG_H_ -+ -+#define AUDIO_TOP_CON2 0x0008 -+#define AUDIO_TOP_CON4 0x0010 -+#define AUDIO_ENGEN_CON0 0x0014 -+#define AFE_IRQ_MCU_EN 0x0100 -+#define AFE_IRQ_MCU_STATUS 0x0120 -+#define AFE_IRQ_MCU_CLR 0x0128 -+#define AFE_IRQ0_MCU_CFG0 0x0140 -+#define AFE_IRQ0_MCU_CFG1 0x0144 -+#define AFE_IRQ1_MCU_CFG0 0x0148 -+#define AFE_IRQ1_MCU_CFG1 0x014c -+#define AFE_IRQ2_MCU_CFG0 0x0150 -+#define AFE_IRQ2_MCU_CFG1 0x0154 -+#define ETDM_IN5_CON0 0x13f0 -+#define ETDM_IN5_CON1 0x13f4 -+#define ETDM_IN5_CON2 0x13f8 -+#define ETDM_IN5_CON3 0x13fc -+#define ETDM_IN5_CON4 0x1400 -+#define ETDM_OUT5_CON0 0x1570 -+#define ETDM_OUT5_CON4 0x1580 -+#define ETDM_OUT5_CON5 0x1584 -+#define ETDM_4_7_COWORK_CON0 0x15e0 -+#define ETDM_4_7_COWORK_CON1 0x15e4 -+#define AFE_CONN018_1 0x1b44 -+#define AFE_CONN018_4 0x1b50 -+#define AFE_CONN019_1 0x1b64 -+#define AFE_CONN019_4 0x1b70 -+#define AFE_CONN124_1 0x2884 -+#define AFE_CONN124_4 0x2890 -+#define AFE_CONN125_1 0x28a4 -+#define AFE_CONN125_4 0x28b0 -+#define AFE_CONN_RS_0 0x3920 -+#define AFE_CONN_RS_3 0x392c -+#define AFE_CONN_16BIT_0 0x3960 -+#define AFE_CONN_16BIT_3 0x396c -+#define AFE_CONN_24BIT_0 0x3980 -+#define AFE_CONN_24BIT_3 0x398c -+#define AFE_MEMIF_CON0 0x3d98 -+#define AFE_MEMIF_RD_MON 0x3da0 -+#define AFE_MEMIF_WR_MON 0x3da4 -+#define AFE_DL0_BASE_MSB 0x3e40 -+#define AFE_DL0_BASE 0x3e44 -+#define AFE_DL0_CUR_MSB 0x3e48 -+#define AFE_DL0_CUR 0x3e4c -+#define AFE_DL0_END_MSB 0x3e50 -+#define AFE_DL0_END 0x3e54 -+#define AFE_DL0_RCH_MON 0x3e58 -+#define AFE_DL0_LCH_MON 0x3e5c -+#define AFE_DL0_CON0 0x3e60 -+#define AFE_VUL0_BASE_MSB 0x4220 -+#define AFE_VUL0_BASE 0x4224 -+#define AFE_VUL0_CUR_MSB 0x4228 -+#define AFE_VUL0_CUR 0x422c -+#define AFE_VUL0_END_MSB 0x4230 -+#define AFE_VUL0_END 0x4234 -+#define AFE_VUL0_CON0 0x4238 -+ -+#define AFE_MAX_REGISTER AFE_VUL0_CON0 -+#define AFE_IRQ_STATUS_BITS 0x7 -+#define AFE_IRQ_CNT_SHIFT 0 -+#define AFE_IRQ_CNT_MASK 0xffffff -+ -+/* AUDIO_TOP_CON2 */ -+#define CLK_OUT5_PDN BIT(14) -+#define CLK_OUT5_PDN_MASK BIT(14) -+#define CLK_IN5_PDN BIT(7) -+#define CLK_IN5_PDN_MASK BIT(7) -+ -+/* AUDIO_TOP_CON4 */ -+#define PDN_APLL_TUNER2 BIT(12) -+#define PDN_APLL_TUNER2_MASK BIT(12) -+ -+/* AUDIO_ENGEN_CON0 */ -+#define AUD_APLL2_EN BIT(3) -+#define AUD_APLL2_EN_MASK BIT(3) -+#define AUD_26M_EN BIT(0) -+#define AUD_26M_EN_MASK BIT(0) -+ -+/* AFE_DL0_CON0 */ -+#define DL0_ON_SFT 28 -+#define DL0_ON_MASK 0x1 -+#define DL0_ON_MASK_SFT BIT(28) -+#define DL0_MINLEN_SFT 20 -+#define DL0_MINLEN_MASK 0xf -+#define DL0_MINLEN_MASK_SFT (0xf << 20) -+#define DL0_MODE_SFT 8 -+#define DL0_MODE_MASK 0x1f -+#define DL0_MODE_MASK_SFT (0x1f << 8) -+#define DL0_PBUF_SIZE_SFT 5 -+#define DL0_PBUF_SIZE_MASK 0x3 -+#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5) -+#define DL0_MONO_SFT 4 -+#define DL0_MONO_MASK 0x1 -+#define DL0_MONO_MASK_SFT BIT(4) -+#define DL0_HALIGN_SFT 2 -+#define DL0_HALIGN_MASK 0x1 -+#define DL0_HALIGN_MASK_SFT BIT(2) -+#define DL0_HD_MODE_SFT 0 -+#define DL0_HD_MODE_MASK 0x3 -+#define DL0_HD_MODE_MASK_SFT (0x3 << 0) -+ -+/* AFE_VUL0_CON0 */ -+#define VUL0_ON_SFT 28 -+#define VUL0_ON_MASK 0x1 -+#define VUL0_ON_MASK_SFT BIT(28) -+#define VUL0_MODE_SFT 8 -+#define VUL0_MODE_MASK 0x1f -+#define VUL0_MODE_MASK_SFT (0x1f << 8) -+#define VUL0_MONO_SFT 4 -+#define VUL0_MONO_MASK 0x1 -+#define VUL0_MONO_MASK_SFT BIT(4) -+#define VUL0_HALIGN_SFT 2 -+#define VUL0_HALIGN_MASK 0x1 -+#define VUL0_HALIGN_MASK_SFT BIT(2) -+#define VUL0_HD_MODE_SFT 0 -+#define VUL0_HD_MODE_MASK 0x3 -+#define VUL0_HD_MODE_MASK_SFT (0x3 << 0) -+ -+/* AFE_IRQ_MCU_CON */ -+#define IRQ_MCU_MODE_SFT 4 -+#define IRQ_MCU_MODE_MASK 0x1f -+#define IRQ_MCU_MODE_MASK_SFT (0x1f << 4) -+#define IRQ_MCU_ON_SFT 0 -+#define IRQ_MCU_ON_MASK 0x1 -+#define IRQ_MCU_ON_MASK_SFT BIT(0) -+#define IRQ0_MCU_CLR_SFT 0 -+#define IRQ0_MCU_CLR_MASK 0x1 -+#define IRQ0_MCU_CLR_MASK_SFT BIT(0) -+#define IRQ1_MCU_CLR_SFT 1 -+#define IRQ1_MCU_CLR_MASK 0x1 -+#define IRQ1_MCU_CLR_MASK_SFT BIT(1) -+#define IRQ2_MCU_CLR_SFT 2 -+#define IRQ2_MCU_CLR_MASK 0x1 -+#define IRQ2_MCU_CLR_MASK_SFT BIT(2) -+ -+/* ETDM_IN5_CON2 */ -+#define IN_CLK_SRC(x) ((x) << 10) -+#define IN_CLK_SRC_SFT 10 -+#define IN_CLK_SRC_MASK GENMASK(12, 10) -+ -+/* ETDM_IN5_CON3 */ -+#define IN_SEL_FS(x) ((x) << 26) -+#define IN_SEL_FS_SFT 26 -+#define IN_SEL_FS_MASK GENMASK(30, 26) -+ -+/* ETDM_IN5_CON4 */ -+#define IN_RELATCH(x) ((x) << 20) -+#define IN_RELATCH_SFT 20 -+#define IN_RELATCH_MASK GENMASK(24, 20) -+#define IN_CLK_INV BIT(18) -+#define IN_CLK_INV_MASK BIT(18) -+ -+/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */ -+#define RELATCH_SRC_MASK GENMASK(30, 28) -+#define ETDM_CH_NUM_MASK GENMASK(27, 23) -+#define ETDM_WRD_LEN_MASK GENMASK(20, 16) -+#define ETDM_BIT_LEN_MASK GENMASK(15, 11) -+#define ETDM_FMT_MASK GENMASK(8, 6) -+#define ETDM_SYNC BIT(1) -+#define ETDM_SYNC_MASK BIT(1) -+#define ETDM_EN BIT(0) -+#define ETDM_EN_MASK BIT(0) -+ -+/* ETDM_OUT5_CON4 */ -+#define OUT_RELATCH(x) ((x) << 24) -+#define OUT_RELATCH_SFT 24 -+#define OUT_RELATCH_MASK GENMASK(28, 24) -+#define OUT_CLK_SRC(x) ((x) << 6) -+#define OUT_CLK_SRC_SFT 6 -+#define OUT_CLK_SRC_MASK GENMASK(8, 6) -+#define OUT_SEL_FS(x) (x) -+#define OUT_SEL_FS_SFT 0 -+#define OUT_SEL_FS_MASK GENMASK(4, 0) -+ -+/* ETDM_OUT5_CON5 */ -+#define ETDM_CLK_DIV BIT(12) -+#define ETDM_CLK_DIV_MASK BIT(12) -+#define OUT_CLK_INV BIT(9) -+#define OUT_CLK_INV_MASK BIT(9) -+ -+/* ETDM_4_7_COWORK_CON0 */ -+#define OUT_SEL(x) ((x) << 12) -+#define OUT_SEL_SFT 12 -+#define OUT_SEL_MASK GENMASK(15, 12) -+#endif diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch b/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch deleted file mode 100644 index f22add580fe012..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.6-02-ASoC-mediatek-mt7986-support-etdm-in-platform-driver.patch +++ /dev/null @@ -1,430 +0,0 @@ -From 948a288897015fb3ee63b3f720b396b590c17fd7 Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 17 Aug 2023 18:13:34 +0800 -Subject: [PATCH 2/9] ASoC: mediatek: mt7986: support etdm in platform driver - -Add mt7986 etdm dai driver support. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230817101338.18782-3-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 411 ++++++++++++++++++++ - 1 file changed, 411 insertions(+) - create mode 100644 sound/soc/mediatek/mt7986/mt7986-dai-etdm.c - ---- /dev/null -+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c -@@ -0,0 +1,411 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * MediaTek ALSA SoC Audio DAI eTDM Control -+ * -+ * Copyright (c) 2023 MediaTek Inc. -+ * Authors: Vic Wu -+ * Maso Huang -+ */ -+ -+#include -+#include -+#include -+#include -+#include "mt7986-afe-common.h" -+#include "mt7986-reg.h" -+ -+#define HOPPING_CLK 0 -+#define APLL_CLK 1 -+#define MTK_DAI_ETDM_FORMAT_I2S 0 -+#define MTK_DAI_ETDM_FORMAT_DSPA 4 -+#define MTK_DAI_ETDM_FORMAT_DSPB 5 -+ -+enum { -+ MTK_ETDM_RATE_8K = 0, -+ MTK_ETDM_RATE_12K = 1, -+ MTK_ETDM_RATE_16K = 2, -+ MTK_ETDM_RATE_24K = 3, -+ MTK_ETDM_RATE_32K = 4, -+ MTK_ETDM_RATE_48K = 5, -+ MTK_ETDM_RATE_96K = 7, -+ MTK_ETDM_RATE_192K = 9, -+ MTK_ETDM_RATE_11K = 16, -+ MTK_ETDM_RATE_22K = 17, -+ MTK_ETDM_RATE_44K = 18, -+ MTK_ETDM_RATE_88K = 19, -+ MTK_ETDM_RATE_176K = 20, -+}; -+ -+struct mtk_dai_etdm_priv { -+ bool bck_inv; -+ bool lrck_inv; -+ bool slave_mode; -+ unsigned int format; -+}; -+ -+static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate) -+{ -+ switch (rate) { -+ case 8000: -+ return MTK_ETDM_RATE_8K; -+ case 11025: -+ return MTK_ETDM_RATE_11K; -+ case 12000: -+ return MTK_ETDM_RATE_12K; -+ case 16000: -+ return MTK_ETDM_RATE_16K; -+ case 22050: -+ return MTK_ETDM_RATE_22K; -+ case 24000: -+ return MTK_ETDM_RATE_24K; -+ case 32000: -+ return MTK_ETDM_RATE_32K; -+ case 44100: -+ return MTK_ETDM_RATE_44K; -+ case 48000: -+ return MTK_ETDM_RATE_48K; -+ case 88200: -+ return MTK_ETDM_RATE_88K; -+ case 96000: -+ return MTK_ETDM_RATE_96K; -+ case 176400: -+ return MTK_ETDM_RATE_176K; -+ case 192000: -+ return MTK_ETDM_RATE_192K; -+ default: -+ dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n", -+ __func__, rate, MTK_ETDM_RATE_48K); -+ return MTK_ETDM_RATE_48K; -+ } -+} -+ -+static int get_etdm_wlen(unsigned int bitwidth) -+{ -+ return bitwidth <= 16 ? 16 : 32; -+} -+ -+/* dai component */ -+/* interconnection */ -+ -+static const struct snd_kcontrol_new o124_mix[] = { -+ SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0), -+}; -+ -+static const struct snd_kcontrol_new o125_mix[] = { -+ SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0), -+}; -+ -+static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { -+ -+ /* DL */ -+ SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0), -+ SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0), -+ /* UL */ -+ SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)), -+ SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)), -+}; -+ -+static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { -+ {"I150", NULL, "ETDM Capture"}, -+ {"I151", NULL, "ETDM Capture"}, -+ {"ETDM Playback", NULL, "O124"}, -+ {"ETDM Playback", NULL, "O125"}, -+ {"O124", "I032_Switch", "I032"}, -+ {"O125", "I033_Switch", "I033"}, -+}; -+ -+/* dai ops */ -+static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); -+ struct mt7986_afe_private *afe_priv = afe->platform_priv; -+ int ret; -+ -+ ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks); -+ if (ret) -+ return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n"); -+ -+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0); -+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0); -+ -+ return 0; -+} -+ -+static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); -+ struct mt7986_afe_private *afe_priv = afe->platform_priv; -+ -+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, -+ CLK_OUT5_PDN); -+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, -+ CLK_IN5_PDN); -+ -+ clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks); -+} -+ -+static unsigned int get_etdm_ch_fixup(unsigned int channels) -+{ -+ if (channels > 16) -+ return 24; -+ else if (channels > 8) -+ return 16; -+ else if (channels > 4) -+ return 8; -+ else if (channels > 2) -+ return 4; -+ else -+ return 2; -+} -+ -+static int mtk_dai_etdm_config(struct mtk_base_afe *afe, -+ struct snd_pcm_hw_params *params, -+ struct snd_soc_dai *dai, -+ int stream) -+{ -+ struct mt7986_afe_private *afe_priv = afe->platform_priv; -+ struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; -+ unsigned int rate = params_rate(params); -+ unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate); -+ unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate); -+ unsigned int channels = params_channels(params); -+ unsigned int bit_width = params_width(params); -+ unsigned int wlen = get_etdm_wlen(bit_width); -+ unsigned int val = 0; -+ unsigned int mask = 0; -+ -+ dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n", -+ __func__, stream, rate, bit_width); -+ -+ /* CON0 */ -+ mask |= ETDM_BIT_LEN_MASK; -+ val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1); -+ mask |= ETDM_WRD_LEN_MASK; -+ val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1); -+ mask |= ETDM_FMT_MASK; -+ val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format); -+ mask |= ETDM_CH_NUM_MASK; -+ val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1); -+ mask |= RELATCH_SRC_MASK; -+ val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK); -+ -+ switch (stream) { -+ case SNDRV_PCM_STREAM_PLAYBACK: -+ /* set ETDM_OUT5_CON0 */ -+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val); -+ -+ /* set ETDM_OUT5_CON4 */ -+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, -+ OUT_RELATCH_MASK, OUT_RELATCH(afe_rate)); -+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, -+ OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK)); -+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4, -+ OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate)); -+ -+ /* set ETDM_OUT5_CON5 */ -+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON5, -+ ETDM_CLK_DIV_MASK, ETDM_CLK_DIV); -+ break; -+ case SNDRV_PCM_STREAM_CAPTURE: -+ /* set ETDM_IN5_CON0 */ -+ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val); -+ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, -+ ETDM_SYNC_MASK, ETDM_SYNC); -+ -+ /* set ETDM_IN5_CON2 */ -+ regmap_update_bits(afe->regmap, ETDM_IN5_CON2, -+ IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK)); -+ -+ /* set ETDM_IN5_CON3 */ -+ regmap_update_bits(afe->regmap, ETDM_IN5_CON3, -+ IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate)); -+ -+ /* set ETDM_IN5_CON4 */ -+ regmap_update_bits(afe->regmap, ETDM_IN5_CON4, -+ IN_RELATCH_MASK, IN_RELATCH(afe_rate)); -+ break; -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, -+ struct snd_soc_dai *dai) -+{ -+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); -+ -+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); -+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); -+ -+ return 0; -+} -+ -+static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, -+ struct snd_soc_dai *dai) -+{ -+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); -+ -+ dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); -+ switch (cmd) { -+ case SNDRV_PCM_TRIGGER_START: -+ case SNDRV_PCM_TRIGGER_RESUME: -+ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK, -+ ETDM_EN); -+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK, -+ ETDM_EN); -+ break; -+ case SNDRV_PCM_TRIGGER_STOP: -+ case SNDRV_PCM_TRIGGER_SUSPEND: -+ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK, -+ 0); -+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK, -+ 0); -+ break; -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) -+{ -+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); -+ struct mt7986_afe_private *afe_priv = afe->platform_priv; -+ struct mtk_dai_etdm_priv *etdm_data; -+ void *priv_data; -+ -+ switch (dai->id) { -+ case MT7986_DAI_ETDM: -+ break; -+ default: -+ dev_warn(afe->dev, "%s(), id %d not support\n", -+ __func__, dai->id); -+ return -EINVAL; -+ } -+ -+ priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv), -+ GFP_KERNEL); -+ if (!priv_data) -+ return -ENOMEM; -+ -+ afe_priv->dai_priv[dai->id] = priv_data; -+ etdm_data = afe_priv->dai_priv[dai->id]; -+ -+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_I2S: -+ etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; -+ break; -+ case SND_SOC_DAIFMT_DSP_A: -+ etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; -+ break; -+ case SND_SOC_DAIFMT_DSP_B: -+ etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_NB_NF: -+ etdm_data->bck_inv = false; -+ etdm_data->lrck_inv = false; -+ break; -+ case SND_SOC_DAIFMT_NB_IF: -+ etdm_data->bck_inv = false; -+ etdm_data->lrck_inv = true; -+ break; -+ case SND_SOC_DAIFMT_IB_NF: -+ etdm_data->bck_inv = true; -+ etdm_data->lrck_inv = false; -+ break; -+ case SND_SOC_DAIFMT_IB_IF: -+ etdm_data->bck_inv = true; -+ etdm_data->lrck_inv = true; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBM_CFM: -+ etdm_data->slave_mode = true; -+ break; -+ case SND_SOC_DAIFMT_CBS_CFS: -+ etdm_data->slave_mode = false; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { -+ .startup = mtk_dai_etdm_startup, -+ .shutdown = mtk_dai_etdm_shutdown, -+ .hw_params = mtk_dai_etdm_hw_params, -+ .trigger = mtk_dai_etdm_trigger, -+ .set_fmt = mtk_dai_etdm_set_fmt, -+}; -+ -+/* dai driver */ -+#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\ -+ SNDRV_PCM_RATE_88200 |\ -+ SNDRV_PCM_RATE_96000 |\ -+ SNDRV_PCM_RATE_176400 |\ -+ SNDRV_PCM_RATE_192000) -+ -+#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ -+ SNDRV_PCM_FMTBIT_S24_LE |\ -+ SNDRV_PCM_FMTBIT_S32_LE) -+ -+static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { -+ { -+ .name = "ETDM", -+ .id = MT7986_DAI_ETDM, -+ .capture = { -+ .stream_name = "ETDM Capture", -+ .channels_min = 1, -+ .channels_max = 2, -+ .rates = MTK_ETDM_RATES, -+ .formats = MTK_ETDM_FORMATS, -+ }, -+ .playback = { -+ .stream_name = "ETDM Playback", -+ .channels_min = 1, -+ .channels_max = 2, -+ .rates = MTK_ETDM_RATES, -+ .formats = MTK_ETDM_FORMATS, -+ }, -+ .ops = &mtk_dai_etdm_ops, -+ .symmetric_rate = 1, -+ .symmetric_sample_bits = 1, -+ }, -+}; -+ -+int mt7986_dai_etdm_register(struct mtk_base_afe *afe) -+{ -+ struct mtk_base_afe_dai *dai; -+ -+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); -+ if (!dai) -+ return -ENOMEM; -+ -+ list_add(&dai->list, &afe->sub_dais); -+ -+ dai->dai_drivers = mtk_dai_etdm_driver; -+ dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); -+ -+ dai->dapm_widgets = mtk_dai_etdm_widgets; -+ dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); -+ dai->dapm_routes = mtk_dai_etdm_routes; -+ dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); -+ -+ return 0; -+} diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch b/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch deleted file mode 100644 index b899b963d203b8..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.6-03-ASoC-mediatek-mt7986-add-platform-driver.patch +++ /dev/null @@ -1,685 +0,0 @@ -From fc7776dee86bc07d22820a904760a95f49a2f12e Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 17 Aug 2023 18:13:35 +0800 -Subject: [PATCH 3/9] ASoC: mediatek: mt7986: add platform driver - -Add mt7986 platform driver. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230817101338.18782-4-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/Kconfig | 10 + - sound/soc/mediatek/Makefile | 1 + - sound/soc/mediatek/mt7986/Makefile | 8 + - sound/soc/mediatek/mt7986/mt7986-afe-pcm.c | 622 +++++++++++++++++++++ - 4 files changed, 641 insertions(+) - create mode 100644 sound/soc/mediatek/mt7986/Makefile - create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-pcm.c - ---- a/sound/soc/mediatek/Kconfig -+++ b/sound/soc/mediatek/Kconfig -@@ -54,6 +54,16 @@ config SND_SOC_MT6797_MT6351 - Select Y if you have such device. - If unsure select "N". - -+config SND_SOC_MT7986 -+ tristate "ASoC support for Mediatek MT7986 chip" -+ depends on ARCH_MEDIATEK -+ select SND_SOC_MEDIATEK -+ help -+ This adds ASoC platform driver support for MediaTek MT7986 chip -+ that can be used with other codecs. -+ Select Y if you have such device. -+ If unsure select "N". -+ - config SND_SOC_MT8173 - tristate "ASoC support for Mediatek MT8173 chip" - depends on ARCH_MEDIATEK ---- a/sound/soc/mediatek/Makefile -+++ b/sound/soc/mediatek/Makefile -@@ -2,6 +2,7 @@ - obj-$(CONFIG_SND_SOC_MEDIATEK) += common/ - obj-$(CONFIG_SND_SOC_MT2701) += mt2701/ - obj-$(CONFIG_SND_SOC_MT6797) += mt6797/ -+obj-$(CONFIG_SND_SOC_MT7986) += mt7986/ - obj-$(CONFIG_SND_SOC_MT8173) += mt8173/ - obj-$(CONFIG_SND_SOC_MT8183) += mt8183/ - obj-$(CONFIG_SND_SOC_MT8186) += mt8186/ ---- /dev/null -+++ b/sound/soc/mediatek/mt7986/Makefile -@@ -0,0 +1,8 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+# platform driver -+snd-soc-mt7986-afe-objs := \ -+ mt7986-afe-pcm.o \ -+ mt7986-dai-etdm.o -+ -+obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o ---- /dev/null -+++ b/sound/soc/mediatek/mt7986/mt7986-afe-pcm.c -@@ -0,0 +1,622 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * MediaTek ALSA SoC AFE platform driver for MT7986 -+ * -+ * Copyright (c) 2023 MediaTek Inc. -+ * Authors: Vic Wu -+ * Maso Huang -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mt7986-afe-common.h" -+#include "mt7986-reg.h" -+#include "../common/mtk-afe-platform-driver.h" -+#include "../common/mtk-afe-fe-dai.h" -+ -+enum { -+ MTK_AFE_RATE_8K = 0, -+ MTK_AFE_RATE_11K = 1, -+ MTK_AFE_RATE_12K = 2, -+ MTK_AFE_RATE_16K = 4, -+ MTK_AFE_RATE_22K = 5, -+ MTK_AFE_RATE_24K = 6, -+ MTK_AFE_RATE_32K = 8, -+ MTK_AFE_RATE_44K = 9, -+ MTK_AFE_RATE_48K = 10, -+ MTK_AFE_RATE_88K = 13, -+ MTK_AFE_RATE_96K = 14, -+ MTK_AFE_RATE_176K = 17, -+ MTK_AFE_RATE_192K = 18, -+}; -+ -+enum { -+ CLK_INFRA_AUD_BUS_CK = 0, -+ CLK_INFRA_AUD_26M_CK, -+ CLK_INFRA_AUD_L_CK, -+ CLK_INFRA_AUD_AUD_CK, -+ CLK_INFRA_AUD_EG2_CK, -+ CLK_NUM -+}; -+ -+static const char *aud_clks[CLK_NUM] = { -+ [CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck", -+ [CLK_INFRA_AUD_26M_CK] = "aud_26m_ck", -+ [CLK_INFRA_AUD_L_CK] = "aud_l_ck", -+ [CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck", -+ [CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck", -+}; -+ -+unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate) -+{ -+ switch (rate) { -+ case 8000: -+ return MTK_AFE_RATE_8K; -+ case 11025: -+ return MTK_AFE_RATE_11K; -+ case 12000: -+ return MTK_AFE_RATE_12K; -+ case 16000: -+ return MTK_AFE_RATE_16K; -+ case 22050: -+ return MTK_AFE_RATE_22K; -+ case 24000: -+ return MTK_AFE_RATE_24K; -+ case 32000: -+ return MTK_AFE_RATE_32K; -+ case 44100: -+ return MTK_AFE_RATE_44K; -+ case 48000: -+ return MTK_AFE_RATE_48K; -+ case 88200: -+ return MTK_AFE_RATE_88K; -+ case 96000: -+ return MTK_AFE_RATE_96K; -+ case 176400: -+ return MTK_AFE_RATE_176K; -+ case 192000: -+ return MTK_AFE_RATE_192K; -+ default: -+ dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n", -+ __func__, rate, MTK_AFE_RATE_48K); -+ return MTK_AFE_RATE_48K; -+ } -+} -+ -+static const struct snd_pcm_hardware mt7986_afe_hardware = { -+ .info = SNDRV_PCM_INFO_MMAP | -+ SNDRV_PCM_INFO_INTERLEAVED | -+ SNDRV_PCM_INFO_MMAP_VALID, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE | -+ SNDRV_PCM_FMTBIT_S24_LE | -+ SNDRV_PCM_FMTBIT_S32_LE, -+ .period_bytes_min = 256, -+ .period_bytes_max = 4 * 48 * 1024, -+ .periods_min = 2, -+ .periods_max = 256, -+ .buffer_bytes_max = 8 * 48 * 1024, -+ .fifo_size = 0, -+}; -+ -+static int mt7986_memif_fs(struct snd_pcm_substream *substream, -+ unsigned int rate) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); -+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); -+ -+ return mt7986_afe_rate_transform(afe->dev, rate); -+} -+ -+static int mt7986_irq_fs(struct snd_pcm_substream *substream, -+ unsigned int rate) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); -+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); -+ -+ return mt7986_afe_rate_transform(afe->dev, rate); -+} -+ -+#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ -+ SNDRV_PCM_RATE_88200 |\ -+ SNDRV_PCM_RATE_96000 |\ -+ SNDRV_PCM_RATE_176400 |\ -+ SNDRV_PCM_RATE_192000) -+ -+#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ -+ SNDRV_PCM_FMTBIT_S24_LE |\ -+ SNDRV_PCM_FMTBIT_S32_LE) -+ -+static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = { -+ /* FE DAIs: memory intefaces to CPU */ -+ { -+ .name = "DL1", -+ .id = MT7986_MEMIF_DL1, -+ .playback = { -+ .stream_name = "DL1", -+ .channels_min = 1, -+ .channels_max = 2, -+ .rates = MTK_PCM_RATES, -+ .formats = MTK_PCM_FORMATS, -+ }, -+ .ops = &mtk_afe_fe_ops, -+ }, -+ { -+ .name = "UL1", -+ .id = MT7986_MEMIF_VUL12, -+ .capture = { -+ .stream_name = "UL1", -+ .channels_min = 1, -+ .channels_max = 2, -+ .rates = MTK_PCM_RATES, -+ .formats = MTK_PCM_FORMATS, -+ }, -+ .ops = &mtk_afe_fe_ops, -+ }, -+}; -+ -+static const struct snd_kcontrol_new o018_mix[] = { -+ SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0), -+}; -+ -+static const struct snd_kcontrol_new o019_mix[] = { -+ SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0), -+}; -+ -+static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = { -+ /* DL */ -+ SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0), -+ SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0), -+ -+ /* UL */ -+ SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0, -+ o018_mix, ARRAY_SIZE(o018_mix)), -+ SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0, -+ o019_mix, ARRAY_SIZE(o019_mix)), -+}; -+ -+static const struct snd_soc_dapm_route mt7986_memif_routes[] = { -+ {"I032", NULL, "DL1"}, -+ {"I033", NULL, "DL1"}, -+ {"UL1", NULL, "O018"}, -+ {"UL1", NULL, "O019"}, -+ {"O018", "I150_Switch", "I150"}, -+ {"O019", "I151_Switch", "I151"}, -+}; -+ -+static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = { -+ .name = "mt7986-afe-pcm-dai", -+}; -+ -+static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = { -+ [MT7986_MEMIF_DL1] = { -+ .name = "DL1", -+ .id = MT7986_MEMIF_DL1, -+ .reg_ofs_base = AFE_DL0_BASE, -+ .reg_ofs_cur = AFE_DL0_CUR, -+ .reg_ofs_end = AFE_DL0_END, -+ .reg_ofs_base_msb = AFE_DL0_BASE_MSB, -+ .reg_ofs_cur_msb = AFE_DL0_CUR_MSB, -+ .reg_ofs_end_msb = AFE_DL0_END_MSB, -+ .fs_reg = AFE_DL0_CON0, -+ .fs_shift = DL0_MODE_SFT, -+ .fs_maskbit = DL0_MODE_MASK, -+ .mono_reg = AFE_DL0_CON0, -+ .mono_shift = DL0_MONO_SFT, -+ .enable_reg = AFE_DL0_CON0, -+ .enable_shift = DL0_ON_SFT, -+ .hd_reg = AFE_DL0_CON0, -+ .hd_shift = DL0_HD_MODE_SFT, -+ .hd_align_reg = AFE_DL0_CON0, -+ .hd_align_mshift = DL0_HALIGN_SFT, -+ .pbuf_reg = AFE_DL0_CON0, -+ .pbuf_shift = DL0_PBUF_SIZE_SFT, -+ .minlen_reg = AFE_DL0_CON0, -+ .minlen_shift = DL0_MINLEN_SFT, -+ }, -+ [MT7986_MEMIF_VUL12] = { -+ .name = "VUL12", -+ .id = MT7986_MEMIF_VUL12, -+ .reg_ofs_base = AFE_VUL0_BASE, -+ .reg_ofs_cur = AFE_VUL0_CUR, -+ .reg_ofs_end = AFE_VUL0_END, -+ .reg_ofs_base_msb = AFE_VUL0_BASE_MSB, -+ .reg_ofs_cur_msb = AFE_VUL0_CUR_MSB, -+ .reg_ofs_end_msb = AFE_VUL0_END_MSB, -+ .fs_reg = AFE_VUL0_CON0, -+ .fs_shift = VUL0_MODE_SFT, -+ .fs_maskbit = VUL0_MODE_MASK, -+ .mono_reg = AFE_VUL0_CON0, -+ .mono_shift = VUL0_MONO_SFT, -+ .enable_reg = AFE_VUL0_CON0, -+ .enable_shift = VUL0_ON_SFT, -+ .hd_reg = AFE_VUL0_CON0, -+ .hd_shift = VUL0_HD_MODE_SFT, -+ .hd_align_reg = AFE_VUL0_CON0, -+ .hd_align_mshift = VUL0_HALIGN_SFT, -+ }, -+}; -+ -+static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = { -+ [MT7986_IRQ_0] = { -+ .id = MT7986_IRQ_0, -+ .irq_cnt_reg = AFE_IRQ0_MCU_CFG1, -+ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, -+ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, -+ .irq_fs_reg = AFE_IRQ0_MCU_CFG0, -+ .irq_fs_shift = IRQ_MCU_MODE_SFT, -+ .irq_fs_maskbit = IRQ_MCU_MODE_MASK, -+ .irq_en_reg = AFE_IRQ0_MCU_CFG0, -+ .irq_en_shift = IRQ_MCU_ON_SFT, -+ .irq_clr_reg = AFE_IRQ_MCU_CLR, -+ .irq_clr_shift = IRQ0_MCU_CLR_SFT, -+ }, -+ [MT7986_IRQ_1] = { -+ .id = MT7986_IRQ_1, -+ .irq_cnt_reg = AFE_IRQ1_MCU_CFG1, -+ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, -+ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, -+ .irq_fs_reg = AFE_IRQ1_MCU_CFG0, -+ .irq_fs_shift = IRQ_MCU_MODE_SFT, -+ .irq_fs_maskbit = IRQ_MCU_MODE_MASK, -+ .irq_en_reg = AFE_IRQ1_MCU_CFG0, -+ .irq_en_shift = IRQ_MCU_ON_SFT, -+ .irq_clr_reg = AFE_IRQ_MCU_CLR, -+ .irq_clr_shift = IRQ1_MCU_CLR_SFT, -+ }, -+ [MT7986_IRQ_2] = { -+ .id = MT7986_IRQ_2, -+ .irq_cnt_reg = AFE_IRQ2_MCU_CFG1, -+ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, -+ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, -+ .irq_fs_reg = AFE_IRQ2_MCU_CFG0, -+ .irq_fs_shift = IRQ_MCU_MODE_SFT, -+ .irq_fs_maskbit = IRQ_MCU_MODE_MASK, -+ .irq_en_reg = AFE_IRQ2_MCU_CFG0, -+ .irq_en_shift = IRQ_MCU_ON_SFT, -+ .irq_clr_reg = AFE_IRQ_MCU_CLR, -+ .irq_clr_shift = IRQ2_MCU_CLR_SFT, -+ }, -+}; -+ -+static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ /* -+ * Those auto-gen regs are read-only, so put it as volatile because -+ * volatile registers cannot be cached, which means that they cannot -+ * be set when power is off -+ */ -+ -+ switch (reg) { -+ case AFE_DL0_CUR_MSB: -+ case AFE_DL0_CUR: -+ case AFE_DL0_RCH_MON: -+ case AFE_DL0_LCH_MON: -+ case AFE_VUL0_CUR_MSB: -+ case AFE_VUL0_CUR: -+ case AFE_IRQ_MCU_STATUS: -+ case AFE_MEMIF_RD_MON: -+ case AFE_MEMIF_WR_MON: -+ return true; -+ default: -+ return false; -+ }; -+} -+ -+static const struct regmap_config mt7986_afe_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .volatile_reg = mt7986_is_volatile_reg, -+ .max_register = AFE_MAX_REGISTER, -+ .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1), -+}; -+ -+static int mt7986_init_clock(struct mtk_base_afe *afe) -+{ -+ struct mt7986_afe_private *afe_priv = afe->platform_priv; -+ int ret, i; -+ -+ afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM, -+ sizeof(*afe_priv->clks), GFP_KERNEL); -+ if (!afe_priv->clks) -+ return -ENOMEM; -+ afe_priv->num_clks = CLK_NUM; -+ -+ for (i = 0; i < afe_priv->num_clks; i++) -+ afe_priv->clks[i].id = aud_clks[i]; -+ -+ ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks); -+ if (ret) -+ return dev_err_probe(afe->dev, ret, "Failed to get clocks\n"); -+ -+ return 0; -+} -+ -+static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev) -+{ -+ struct mtk_base_afe *afe = dev; -+ struct mtk_base_afe_irq *irq; -+ u32 mcu_en, status, status_mcu; -+ int i, ret; -+ irqreturn_t irq_ret = IRQ_HANDLED; -+ -+ /* get irq that is sent to MCU */ -+ regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); -+ -+ ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); -+ /* only care IRQ which is sent to MCU */ -+ status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS; -+ -+ if (ret || status_mcu == 0) { -+ dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", -+ __func__, ret, status, mcu_en); -+ -+ irq_ret = IRQ_NONE; -+ goto err_irq; -+ } -+ -+ for (i = 0; i < MT7986_MEMIF_NUM; i++) { -+ struct mtk_base_afe_memif *memif = &afe->memif[i]; -+ -+ if (!memif->substream) -+ continue; -+ -+ if (memif->irq_usage < 0) -+ continue; -+ -+ irq = &afe->irqs[memif->irq_usage]; -+ -+ if (status_mcu & (1 << irq->irq_data->irq_en_shift)) -+ snd_pcm_period_elapsed(memif->substream); -+ } -+ -+err_irq: -+ /* clear irq */ -+ regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu); -+ -+ return irq_ret; -+} -+ -+static int mt7986_afe_runtime_suspend(struct device *dev) -+{ -+ struct mtk_base_afe *afe = dev_get_drvdata(dev); -+ struct mt7986_afe_private *afe_priv = afe->platform_priv; -+ -+ if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) -+ goto skip_regmap; -+ -+ /* disable clk*/ -+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff); -+ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0); -+ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0); -+ -+ /* make sure all irq status are cleared, twice intended */ -+ regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff); -+ -+skip_regmap: -+ clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks); -+ -+ return 0; -+} -+ -+static int mt7986_afe_runtime_resume(struct device *dev) -+{ -+ struct mtk_base_afe *afe = dev_get_drvdata(dev); -+ struct mt7986_afe_private *afe_priv = afe->platform_priv; -+ int ret; -+ -+ ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks); -+ if (ret) -+ return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n"); -+ -+ if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) -+ return 0; -+ -+ /* enable clk*/ -+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0); -+ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, -+ AUD_APLL2_EN); -+ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, -+ AUD_26M_EN); -+ -+ return 0; -+} -+ -+static int mt7986_afe_component_probe(struct snd_soc_component *component) -+{ -+ return mtk_afe_add_sub_dai_control(component); -+} -+ -+static const struct snd_soc_component_driver mt7986_afe_component = { -+ .name = AFE_PCM_NAME, -+ .probe = mt7986_afe_component_probe, -+ .pointer = mtk_afe_pcm_pointer, -+ .pcm_construct = mtk_afe_pcm_new, -+}; -+ -+static int mt7986_dai_memif_register(struct mtk_base_afe *afe) -+{ -+ struct mtk_base_afe_dai *dai; -+ -+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); -+ if (!dai) -+ return -ENOMEM; -+ -+ list_add(&dai->list, &afe->sub_dais); -+ -+ dai->dai_drivers = mt7986_memif_dai_driver; -+ dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver); -+ -+ dai->dapm_widgets = mt7986_memif_widgets; -+ dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets); -+ dai->dapm_routes = mt7986_memif_routes; -+ dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes); -+ -+ return 0; -+} -+ -+typedef int (*dai_register_cb)(struct mtk_base_afe *); -+static const dai_register_cb dai_register_cbs[] = { -+ mt7986_dai_etdm_register, -+ mt7986_dai_memif_register, -+}; -+ -+static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev) -+{ -+ struct mtk_base_afe *afe; -+ struct mt7986_afe_private *afe_priv; -+ struct device *dev; -+ int i, irq_id, ret; -+ -+ afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); -+ if (!afe) -+ return -ENOMEM; -+ platform_set_drvdata(pdev, afe); -+ -+ afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), -+ GFP_KERNEL); -+ if (!afe->platform_priv) -+ return -ENOMEM; -+ -+ afe_priv = afe->platform_priv; -+ afe->dev = &pdev->dev; -+ dev = afe->dev; -+ -+ afe->base_addr = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(afe->base_addr)) -+ return PTR_ERR(afe->base_addr); -+ -+ /* initial audio related clock */ -+ ret = mt7986_init_clock(afe); -+ if (ret) -+ return dev_err_probe(dev, ret, "Cannot initialize clocks\n"); -+ -+ ret = devm_pm_runtime_enable(dev); -+ if (ret) -+ return ret; -+ -+ /* enable clock for regcache get default value from hw */ -+ afe_priv->pm_runtime_bypass_reg_ctl = true; -+ pm_runtime_get_sync(&pdev->dev); -+ -+ afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, -+ &mt7986_afe_regmap_config); -+ -+ pm_runtime_put_sync(&pdev->dev); -+ if (IS_ERR(afe->regmap)) -+ return PTR_ERR(afe->regmap); -+ -+ afe_priv->pm_runtime_bypass_reg_ctl = false; -+ -+ /* init memif */ -+ afe->memif_size = MT7986_MEMIF_NUM; -+ afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), -+ GFP_KERNEL); -+ if (!afe->memif) -+ return -ENOMEM; -+ -+ for (i = 0; i < afe->memif_size; i++) { -+ afe->memif[i].data = &memif_data[i]; -+ afe->memif[i].irq_usage = -1; -+ } -+ -+ mutex_init(&afe->irq_alloc_lock); -+ -+ /* irq initialize */ -+ afe->irqs_size = MT7986_IRQ_NUM; -+ afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), -+ GFP_KERNEL); -+ if (!afe->irqs) -+ return -ENOMEM; -+ -+ for (i = 0; i < afe->irqs_size; i++) -+ afe->irqs[i].irq_data = &irq_data[i]; -+ -+ /* request irq */ -+ irq_id = platform_get_irq(pdev, 0); -+ if (irq_id < 0) { -+ ret = irq_id; -+ return dev_err_probe(dev, ret, "No irq found\n"); -+ } -+ ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler, -+ IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n"); -+ -+ /* init sub_dais */ -+ INIT_LIST_HEAD(&afe->sub_dais); -+ -+ for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { -+ ret = dai_register_cbs[i](afe); -+ if (ret) -+ return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i); -+ } -+ -+ /* init dai_driver and component_driver */ -+ ret = mtk_afe_combine_sub_dai(afe); -+ if (ret) -+ return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n"); -+ -+ afe->mtk_afe_hardware = &mt7986_afe_hardware; -+ afe->memif_fs = mt7986_memif_fs; -+ afe->irq_fs = mt7986_irq_fs; -+ -+ afe->runtime_resume = mt7986_afe_runtime_resume; -+ afe->runtime_suspend = mt7986_afe_runtime_suspend; -+ -+ /* register component */ -+ ret = devm_snd_soc_register_component(&pdev->dev, -+ &mt7986_afe_component, -+ NULL, 0); -+ if (ret) -+ return dev_err_probe(dev, ret, "Cannot register AFE component\n"); -+ -+ ret = devm_snd_soc_register_component(afe->dev, -+ &mt7986_afe_pcm_dai_component, -+ afe->dai_drivers, -+ afe->num_dai_drivers); -+ if (ret) -+ return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n"); -+ -+ return 0; -+} -+ -+static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev) -+{ -+ pm_runtime_disable(&pdev->dev); -+ if (!pm_runtime_status_suspended(&pdev->dev)) -+ mt7986_afe_runtime_suspend(&pdev->dev); -+} -+ -+static const struct of_device_id mt7986_afe_pcm_dt_match[] = { -+ { .compatible = "mediatek,mt7986-afe" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match); -+ -+static const struct dev_pm_ops mt7986_afe_pm_ops = { -+ SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend, -+ mt7986_afe_runtime_resume, NULL) -+}; -+ -+static struct platform_driver mt7986_afe_pcm_driver = { -+ .driver = { -+ .name = "mt7986-audio", -+ .of_match_table = mt7986_afe_pcm_dt_match, -+ .pm = &mt7986_afe_pm_ops, -+ }, -+ .probe = mt7986_afe_pcm_dev_probe, -+ .remove_new = mt7986_afe_pcm_dev_remove, -+}; -+module_platform_driver(mt7986_afe_pcm_driver); -+ -+MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986"); -+MODULE_AUTHOR("Vic Wu "); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch b/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch deleted file mode 100644 index dd354c04e3d318..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.6-04-ASoC-mediatek-mt7986-add-machine-driver-with-wm8960.patch +++ /dev/null @@ -1,243 +0,0 @@ -From ddf6abc1c78072f8ccad59166be95f0ca5af8ca4 Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 17 Aug 2023 18:13:36 +0800 -Subject: [PATCH 4/9] ASoC: mediatek: mt7986: add machine driver with wm8960 - -Add support for mt7986 board with wm8960. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230817101338.18782-5-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/Kconfig | 10 ++ - sound/soc/mediatek/mt7986/Makefile | 1 + - sound/soc/mediatek/mt7986/mt7986-wm8960.c | 196 ++++++++++++++++++++++ - 3 files changed, 207 insertions(+) - create mode 100644 sound/soc/mediatek/mt7986/mt7986-wm8960.c - ---- a/sound/soc/mediatek/Kconfig -+++ b/sound/soc/mediatek/Kconfig -@@ -64,6 +64,16 @@ config SND_SOC_MT7986 - Select Y if you have such device. - If unsure select "N". - -+config SND_SOC_MT7986_WM8960 -+ tristate "ASoc Audio driver for MT7986 with WM8960 codec" -+ depends on SND_SOC_MT7986 && I2C -+ select SND_SOC_WM8960 -+ help -+ This adds support for ASoC machine driver for MediaTek MT7986 -+ boards with the WM8960 codecs. -+ Select Y if you have such device. -+ If unsure select "N". -+ - config SND_SOC_MT8173 - tristate "ASoC support for Mediatek MT8173 chip" - depends on ARCH_MEDIATEK ---- a/sound/soc/mediatek/mt7986/Makefile -+++ b/sound/soc/mediatek/mt7986/Makefile -@@ -6,3 +6,4 @@ snd-soc-mt7986-afe-objs := \ - mt7986-dai-etdm.o - - obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o -+obj-$(CONFIG_SND_SOC_MT7986_WM8960) += mt7986-wm8960.o ---- /dev/null -+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c -@@ -0,0 +1,196 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * mt7986-wm8960.c -- MT7986-WM8960 ALSA SoC machine driver -+ * -+ * Copyright (c) 2023 MediaTek Inc. -+ * Authors: Vic Wu -+ * Maso Huang -+ */ -+ -+#include -+#include -+ -+#include "mt7986-afe-common.h" -+ -+struct mt7986_wm8960_priv { -+ struct device_node *platform_node; -+ struct device_node *codec_node; -+}; -+ -+static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = { -+ SND_SOC_DAPM_HP("Headphone", NULL), -+ SND_SOC_DAPM_MIC("AMIC", NULL), -+}; -+ -+static const struct snd_kcontrol_new mt7986_wm8960_controls[] = { -+ SOC_DAPM_PIN_SWITCH("Headphone"), -+ SOC_DAPM_PIN_SWITCH("AMIC"), -+}; -+ -+SND_SOC_DAILINK_DEFS(playback, -+ DAILINK_COMP_ARRAY(COMP_CPU("DL1")), -+ DAILINK_COMP_ARRAY(COMP_DUMMY()), -+ DAILINK_COMP_ARRAY(COMP_EMPTY())); -+ -+SND_SOC_DAILINK_DEFS(capture, -+ DAILINK_COMP_ARRAY(COMP_CPU("UL1")), -+ DAILINK_COMP_ARRAY(COMP_DUMMY()), -+ DAILINK_COMP_ARRAY(COMP_EMPTY())); -+ -+SND_SOC_DAILINK_DEFS(codec, -+ DAILINK_COMP_ARRAY(COMP_CPU("ETDM")), -+ DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8960-hifi")), -+ DAILINK_COMP_ARRAY(COMP_EMPTY())); -+ -+static struct snd_soc_dai_link mt7986_wm8960_dai_links[] = { -+ /* FE */ -+ { -+ .name = "wm8960-playback", -+ .stream_name = "wm8960-playback", -+ .trigger = {SND_SOC_DPCM_TRIGGER_POST, -+ SND_SOC_DPCM_TRIGGER_POST}, -+ .dynamic = 1, -+ .dpcm_playback = 1, -+ SND_SOC_DAILINK_REG(playback), -+ }, -+ { -+ .name = "wm8960-capture", -+ .stream_name = "wm8960-capture", -+ .trigger = {SND_SOC_DPCM_TRIGGER_POST, -+ SND_SOC_DPCM_TRIGGER_POST}, -+ .dynamic = 1, -+ .dpcm_capture = 1, -+ SND_SOC_DAILINK_REG(capture), -+ }, -+ /* BE */ -+ { -+ .name = "wm8960-codec", -+ .no_pcm = 1, -+ .dai_fmt = SND_SOC_DAIFMT_I2S | -+ SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBS_CFS | -+ SND_SOC_DAIFMT_GATED, -+ .dpcm_playback = 1, -+ .dpcm_capture = 1, -+ SND_SOC_DAILINK_REG(codec), -+ }, -+}; -+ -+static struct snd_soc_card mt7986_wm8960_card = { -+ .name = "mt7986-wm8960", -+ .owner = THIS_MODULE, -+ .dai_link = mt7986_wm8960_dai_links, -+ .num_links = ARRAY_SIZE(mt7986_wm8960_dai_links), -+ .controls = mt7986_wm8960_controls, -+ .num_controls = ARRAY_SIZE(mt7986_wm8960_controls), -+ .dapm_widgets = mt7986_wm8960_widgets, -+ .num_dapm_widgets = ARRAY_SIZE(mt7986_wm8960_widgets), -+}; -+ -+static int mt7986_wm8960_machine_probe(struct platform_device *pdev) -+{ -+ struct snd_soc_card *card = &mt7986_wm8960_card; -+ struct snd_soc_dai_link *dai_link; -+ struct device_node *platform, *codec; -+ struct mt7986_wm8960_priv *priv; -+ int ret, i; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ platform = of_get_child_by_name(pdev->dev.of_node, "platform"); -+ -+ if (platform) { -+ priv->platform_node = of_parse_phandle(platform, "sound-dai", 0); -+ of_node_put(platform); -+ -+ if (!priv->platform_node) { -+ dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n"); -+ return -EINVAL; -+ } -+ } else { -+ dev_err(&pdev->dev, "Property 'platform' missing or invalid\n"); -+ return -EINVAL; -+ } -+ -+ for_each_card_prelinks(card, i, dai_link) { -+ if (dai_link->platforms->name) -+ continue; -+ dai_link->platforms->of_node = priv->platform_node; -+ } -+ -+ card->dev = &pdev->dev; -+ -+ codec = of_get_child_by_name(pdev->dev.of_node, "codec"); -+ -+ if (codec) { -+ priv->codec_node = of_parse_phandle(codec, "sound-dai", 0); -+ of_node_put(codec); -+ -+ if (!priv->codec_node) { -+ of_node_put(priv->platform_node); -+ dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n"); -+ return -EINVAL; -+ } -+ } else { -+ of_node_put(priv->platform_node); -+ dev_err(&pdev->dev, "Property 'codec' missing or invalid\n"); -+ return -EINVAL; -+ } -+ -+ for_each_card_prelinks(card, i, dai_link) { -+ if (dai_link->codecs->name) -+ continue; -+ dai_link->codecs->of_node = priv->codec_node; -+ } -+ -+ ret = snd_soc_of_parse_audio_routing(card, "audio-routing"); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to parse audio-routing: %d\n", ret); -+ goto err_of_node_put; -+ } -+ -+ ret = devm_snd_soc_register_card(&pdev->dev, card); -+ if (ret) { -+ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret); -+ goto err_of_node_put; -+ } -+ -+err_of_node_put: -+ of_node_put(priv->codec_node); -+ of_node_put(priv->platform_node); -+ return ret; -+} -+ -+static void mt7986_wm8960_machine_remove(struct platform_device *pdev) -+{ -+ struct snd_soc_card *card = platform_get_drvdata(pdev); -+ struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card); -+ -+ of_node_put(priv->codec_node); -+ of_node_put(priv->platform_node); -+} -+ -+static const struct of_device_id mt7986_wm8960_machine_dt_match[] = { -+ {.compatible = "mediatek,mt7986-wm8960-sound"}, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, mt7986_wm8960_machine_dt_match); -+ -+static struct platform_driver mt7986_wm8960_machine = { -+ .driver = { -+ .name = "mt7986-wm8960", -+ .of_match_table = mt7986_wm8960_machine_dt_match, -+ }, -+ .probe = mt7986_wm8960_machine_probe, -+ .remove_new = mt7986_wm8960_machine_remove, -+}; -+ -+module_platform_driver(mt7986_wm8960_machine); -+ -+/* Module information */ -+MODULE_DESCRIPTION("MT7986 WM8960 ALSA SoC machine driver"); -+MODULE_AUTHOR("Vic Wu "); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("mt7986 wm8960 soc card"); diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch b/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch deleted file mode 100644 index 8cf0b5464a964b..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.6-05-ASoC-dt-bindings-mediatek-mt7986-wm8960-add-mt7986-w.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 72469f950b629e57e60fbcbefed45e083619b986 Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 17 Aug 2023 18:13:37 +0800 -Subject: [PATCH 5/9] ASoC: dt-bindings: mediatek,mt7986-wm8960: add - mt7986-wm8960 document - -Add document for mt7986 board with wm8960. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230817101338.18782-6-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - .../sound/mediatek,mt7986-wm8960.yaml | 67 +++++++++++++++++++ - 1 file changed, 67 insertions(+) - create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml -@@ -0,0 +1,67 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-wm8960.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MT7986 sound card with WM8960 codec -+ -+maintainers: -+ - Maso Huang -+ -+allOf: -+ - $ref: sound-card-common.yaml# -+ -+properties: -+ compatible: -+ const: mediatek,mt7986-wm8960-sound -+ -+ platform: -+ type: object -+ additionalProperties: false -+ properties: -+ sound-dai: -+ description: The phandle of MT7986 platform. -+ maxItems: 1 -+ required: -+ - sound-dai -+ -+ codec: -+ type: object -+ additionalProperties: false -+ properties: -+ sound-dai: -+ description: The phandle of wm8960 codec. -+ maxItems: 1 -+ required: -+ - sound-dai -+ -+unevaluatedProperties: false -+ -+required: -+ - compatible -+ - audio-routing -+ - platform -+ - codec -+ -+examples: -+ - | -+ sound { -+ compatible = "mediatek,mt7986-wm8960-sound"; -+ model = "mt7986-wm8960"; -+ audio-routing = -+ "Headphone", "HP_L", -+ "Headphone", "HP_R", -+ "LINPUT1", "AMIC", -+ "RINPUT1", "AMIC"; -+ -+ platform { -+ sound-dai = <&afe>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+ -+... diff --git a/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch b/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch deleted file mode 100644 index 236d6a217c50cb..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.6-06-ASoC-dt-bindings-mediatek-mt7986-afe-add-audio-afe-d.patch +++ /dev/null @@ -1,180 +0,0 @@ -From d16202eb38585adbc16e32d11188dbc2127015de Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 17 Aug 2023 18:13:38 +0800 -Subject: [PATCH 6/9] ASoC: dt-bindings: mediatek,mt7986-afe: add audio afe - document - -Add mt7986 audio afe document. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230817101338.18782-7-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - .../bindings/sound/mediatek,mt7986-afe.yaml | 160 ++++++++++++++++++ - 1 file changed, 160 insertions(+) - create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml -@@ -0,0 +1,160 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek AFE PCM controller for MT7986 -+ -+maintainers: -+ - Maso Huang -+ -+properties: -+ compatible: -+ oneOf: -+ - const: mediatek,mt7986-afe -+ - items: -+ - enum: -+ - mediatek,mt7981-afe -+ - mediatek,mt7988-afe -+ - const: mediatek,mt7986-afe -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 5 -+ items: -+ - description: audio bus clock -+ - description: audio 26M clock -+ - description: audio intbus clock -+ - description: audio hopping clock -+ - description: audio pll clock -+ - description: mux for pcm_mck -+ - description: audio i2s/pcm mck -+ -+ clock-names: -+ minItems: 5 -+ items: -+ - const: bus_ck -+ - const: 26m_ck -+ - const: l_ck -+ - const: aud_ck -+ - const: eg2_ck -+ - const: sel -+ - const: i2s_m -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ -+allOf: -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: mediatek,mt7986-afe -+ then: -+ properties: -+ clocks: -+ items: -+ - description: audio bus clock -+ - description: audio 26M clock -+ - description: audio intbus clock -+ - description: audio hopping clock -+ - description: audio pll clock -+ clock-names: -+ items: -+ - const: bus_ck -+ - const: 26m_ck -+ - const: l_ck -+ - const: aud_ck -+ - const: eg2_ck -+ -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: mediatek,mt7981-afe -+ then: -+ properties: -+ clocks: -+ items: -+ - description: audio bus clock -+ - description: audio 26M clock -+ - description: audio intbus clock -+ - description: audio hopping clock -+ - description: audio pll clock -+ - description: mux for pcm_mck -+ clock-names: -+ items: -+ - const: bus_ck -+ - const: 26m_ck -+ - const: l_ck -+ - const: aud_ck -+ - const: eg2_ck -+ - const: sel -+ -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: mediatek,mt7988-afe -+ then: -+ properties: -+ clocks: -+ items: -+ - description: audio bus clock -+ - description: audio 26M clock -+ - description: audio intbus clock -+ - description: audio hopping clock -+ - description: audio pll clock -+ - description: mux for pcm_mck -+ - description: audio i2s/pcm mck -+ clock-names: -+ items: -+ - const: bus_ck -+ - const: 26m_ck -+ - const: l_ck -+ - const: aud_ck -+ - const: eg2_ck -+ - const: sel -+ - const: i2s_m -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ -+ afe@11210000 { -+ compatible = "mediatek,mt7986-afe"; -+ reg = <0x11210000 0x9000>; -+ interrupts = ; -+ clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>, -+ <&infracfg_ao CLK_INFRA_AUD_26M_CK>, -+ <&infracfg_ao CLK_INFRA_AUD_L_CK>, -+ <&infracfg_ao CLK_INFRA_AUD_AUD_CK>, -+ <&infracfg_ao CLK_INFRA_AUD_EG2_CK>; -+ clock-names = "bus_ck", -+ "26m_ck", -+ "l_ck", -+ "aud_ck", -+ "eg2_ck"; -+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>, -+ <&topckgen CLK_TOP_AUD_L_SEL>, -+ <&topckgen CLK_TOP_A_TUNER_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>, -+ <&apmixedsys CLK_APMIXED_APLL2>, -+ <&topckgen CLK_TOP_APLL2_D4>; -+ }; -+ -+... diff --git a/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch b/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch deleted file mode 100644 index 413db8233f0517..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.7-07-ASoC-mediatek-mt7986-drop-the-remove-callback-of-mt7.patch +++ /dev/null @@ -1,42 +0,0 @@ -From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Tue, 24 Oct 2023 11:50:17 +0800 -Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of - mt7986_wm8960 - -Drop the remove callback of mt7986_wm8960. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ---------- - 1 file changed, 10 deletions(-) - ---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c -+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c -@@ -163,15 +163,6 @@ err_of_node_put: - return ret; - } - --static void mt7986_wm8960_machine_remove(struct platform_device *pdev) --{ -- struct snd_soc_card *card = platform_get_drvdata(pdev); -- struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card); -- -- of_node_put(priv->codec_node); -- of_node_put(priv->platform_node); --} -- - static const struct of_device_id mt7986_wm8960_machine_dt_match[] = { - {.compatible = "mediatek,mt7986-wm8960-sound"}, - { /* sentinel */ } -@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8 - .of_match_table = mt7986_wm8960_machine_dt_match, - }, - .probe = mt7986_wm8960_machine_probe, -- .remove_new = mt7986_wm8960_machine_remove, - }; - - module_platform_driver(mt7986_wm8960_machine); diff --git a/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch b/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch deleted file mode 100644 index 5c596fc49c9b58..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.7-08-ASoC-mediatek-mt7986-remove-the-mt7986_wm8960_priv-s.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Tue, 24 Oct 2023 11:50:18 +0800 -Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv - structure - -Remove the mt7986_wm8960_priv structure. - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++-------------- - 1 file changed, 12 insertions(+), 21 deletions(-) - ---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c -+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c -@@ -12,11 +12,6 @@ - - #include "mt7986-afe-common.h" - --struct mt7986_wm8960_priv { -- struct device_node *platform_node; -- struct device_node *codec_node; --}; -- - static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = { - SND_SOC_DAPM_HP("Headphone", NULL), - SND_SOC_DAPM_MIC("AMIC", NULL), -@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s - struct snd_soc_card *card = &mt7986_wm8960_card; - struct snd_soc_dai_link *dai_link; - struct device_node *platform, *codec; -- struct mt7986_wm8960_priv *priv; -+ struct device_node *platform_dai_node, *codec_dai_node; - int ret, i; - -- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -- if (!priv) -- return -ENOMEM; -+ card->dev = &pdev->dev; - - platform = of_get_child_by_name(pdev->dev.of_node, "platform"); - - if (platform) { -- priv->platform_node = of_parse_phandle(platform, "sound-dai", 0); -+ platform_dai_node = of_parse_phandle(platform, "sound-dai", 0); - of_node_put(platform); - -- if (!priv->platform_node) { -+ if (!platform_dai_node) { - dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n"); - return -EINVAL; - } -@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s - for_each_card_prelinks(card, i, dai_link) { - if (dai_link->platforms->name) - continue; -- dai_link->platforms->of_node = priv->platform_node; -+ dai_link->platforms->of_node = platform_dai_node; - } - -- card->dev = &pdev->dev; -- - codec = of_get_child_by_name(pdev->dev.of_node, "codec"); - - if (codec) { -- priv->codec_node = of_parse_phandle(codec, "sound-dai", 0); -+ codec_dai_node = of_parse_phandle(codec, "sound-dai", 0); - of_node_put(codec); - -- if (!priv->codec_node) { -- of_node_put(priv->platform_node); -+ if (!codec_dai_node) { -+ of_node_put(platform_dai_node); - dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n"); - return -EINVAL; - } - } else { -- of_node_put(priv->platform_node); -+ of_node_put(platform_dai_node); - dev_err(&pdev->dev, "Property 'codec' missing or invalid\n"); - return -EINVAL; - } -@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s - for_each_card_prelinks(card, i, dai_link) { - if (dai_link->codecs->name) - continue; -- dai_link->codecs->of_node = priv->codec_node; -+ dai_link->codecs->of_node = codec_dai_node; - } - - ret = snd_soc_of_parse_audio_routing(card, "audio-routing"); -@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s - } - - err_of_node_put: -- of_node_put(priv->codec_node); -- of_node_put(priv->platform_node); -+ of_node_put(platform_dai_node); -+ of_node_put(codec_dai_node); - return ret; - } - diff --git a/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch b/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch deleted file mode 100644 index d4128deabcc4ce..00000000000000 --- a/target/linux/mediatek/patches-6.1/860-v6.7-09-ASoC-mediatek-mt7986-add-sample-rate-checker.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Tue, 24 Oct 2023 11:50:19 +0800 -Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker - -mt7986 only supports 8/12/16/24/32/48/96/192 kHz - -Signed-off-by: Maso Huang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com -Signed-off-by: Mark Brown ---- - sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++---- - 1 file changed, 19 insertions(+), 4 deletions(-) - ---- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c -+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c -@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) - { -+ unsigned int rate = params_rate(params); - struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); - -- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); -- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); -- -- return 0; -+ switch (rate) { -+ case 8000: -+ case 12000: -+ case 16000: -+ case 24000: -+ case 32000: -+ case 48000: -+ case 96000: -+ case 192000: -+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK); -+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE); -+ return 0; -+ default: -+ dev_err(afe->dev, -+ "Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n", -+ rate); -+ return -EINVAL; -+ } - } - - static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, diff --git a/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch b/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch deleted file mode 100644 index a40c249257c513..00000000000000 --- a/target/linux/mediatek/patches-6.1/861-pending-10-ASoC-mediatek-mt7986-silence-error-in-case-of-EPROBE.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 10 Dec 2023 22:41:39 +0000 -Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of - -EPROBE_DEFER - -If probe is defered no error should be printed. Mute it. - -Signed-off-by: Daniel Golle ---- - sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c -+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c -@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s - - ret = devm_snd_soc_register_card(&pdev->dev, card); - if (ret) { -- dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret); -+ if (ret != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret); -+ - goto err_of_node_put; - } - diff --git a/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch b/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch deleted file mode 100644 index e40dca2a7de43e..00000000000000 --- a/target/linux/mediatek/patches-6.1/862-arm64-dts-mt7986-add-afe.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 7 Sep 2023 10:54:37 +0800 -Subject: [PATCH] arm64: dts: mt7986: add afe - ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++ - 1 files changed, 23 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -249,6 +249,28 @@ - status = "disabled"; - }; - -+ afe: audio-controller@11210000 { -+ compatible = "mediatek,mt7986-afe"; -+ reg = <0 0x11210000 0 0x9000>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, -+ <&infracfg CLK_INFRA_AUD_26M_CK>, -+ <&infracfg CLK_INFRA_AUD_L_CK>, -+ <&infracfg CLK_INFRA_AUD_AUD_CK>, -+ <&infracfg CLK_INFRA_AUD_EG2_CK>; -+ clock-names = "aud_bus_ck", -+ "aud_26m_ck", -+ "aud_l_ck", -+ "aud_aud_ck", -+ "aud_eg2_ck"; -+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>, -+ <&topckgen CLK_TOP_AUD_L_SEL>, -+ <&topckgen CLK_TOP_A_TUNER_SEL>; -+ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>, -+ <&apmixedsys CLK_APMIXED_APLL2>, -+ <&topckgen CLK_TOP_APLL2_D4>; -+ }; -+ - pwm: pwm@10048000 { - compatible = "mediatek,mt7986-pwm"; - reg = <0 0x10048000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch b/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch deleted file mode 100644 index 15e30dec56cf42..00000000000000 --- a/target/linux/mediatek/patches-6.1/863-arm64-dts-mt7986-add-sound-wm8960.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001 -From: Maso Huang -Date: Thu, 7 Sep 2023 10:54:37 +0800 -Subject: [PATCH] arm64: dts: mt7986: add sound wm8960 - ---- - .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 39 +++++++++++++++++++ - 1 files changed, 39 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts -@@ -4,6 +4,35 @@ - - / { - compatible = "mediatek,mt7986a-rfb-snand"; -+ -+ sound_wm8960 { -+ compatible = "mediatek,mt7986-wm8960-sound"; -+ audio-routing = "Headphone", "HP_L", -+ "Headphone", "HP_R", -+ "LINPUT1", "AMIC", -+ "RINPUT1", "AMIC"; -+ -+ status = "okay"; -+ -+ platform { -+ sound-dai = <&afe>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c_pins>; -+ status = "okay"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ }; - }; - - &spi0 { -@@ -50,3 +79,13 @@ - &wifi { - mediatek,mtd-eeprom = <&factory 0>; - }; -+ -+&pio { -+ i2c_pins: i2c-pins-3-4 { -+ mux { -+ function = "i2c"; -+ groups = "i2c"; -+ }; -+ }; -+}; -+ diff --git a/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch b/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch deleted file mode 100644 index bddcd4bb0c0746..00000000000000 --- a/target/linux/mediatek/patches-6.1/864-arm64-dts-mt7986-add-sound-overlay-for-bpi-r3.patch +++ /dev/null @@ -1,75 +0,0 @@ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso -@@ -0,0 +1,62 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 MediaTek Inc. -+ * Author: Maso Huang -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ sound_wm8960 { -+ compatible = "mediatek,mt7986-wm8960-sound"; -+ audio-routing = "Headphone", "HP_L", -+ "Headphone", "HP_R", -+ "LINPUT1", "AMIC", -+ "RINPUT1", "AMIC"; -+ -+ status = "okay"; -+ -+ platform { -+ sound-dai = <&afe>; -+ }; -+ -+ codec { -+ sound-dai = <&wm8960>; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2c0>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c_pins>; -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ wm8960: wm8960@1a { -+ compatible = "wlf,wm8960"; -+ reg = <0x1a>; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&pio>; -+ __overlay__ { -+ i2c_pins: i2c-pins-3-4 { -+ mux { -+ function = "i2c"; -+ groups = "i2c"; -+ }; -+ }; -+ }; -+ }; -+}; ---- a/arch/arm64/boot/dts/mediatek/Makefile -+++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-respeaker-2mics.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb diff --git a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch deleted file mode 100644 index 87a937be054eaf..00000000000000 --- a/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ /dev/null @@ -1,65 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -313,7 +313,7 @@ - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ -- asm_sel { -+ asmsel: asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&sata>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&sata_phy>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch deleted file mode 100644 index bfca4b63894b50..00000000000000 --- a/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch +++ /dev/null @@ -1,54 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config CMDLINE - string "Default kernel command string" - default "" ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha - if (p != NULL && l > 0) - strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - handle_cmdline: - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -2240,6 +2240,14 @@ config CMDLINE_FORCE - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config EFI_STUB - bool - diff --git a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch deleted file mode 100644 index d1f6a96720b8eb..00000000000000 --- a/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -640,5 +640,28 @@ - }; - - &wmac { -+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x44000020 0x0 0x10002000 -+ 0x4400 0x4000000 0x0 0x0 -+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 -+ 0x41c4 0x26000000 0xc0c52600 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0xc6c6 -+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 -+ 0x83838382 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x84002e00 0x90000087 0x8a000000 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0xb000009 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x7707>; -+ - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch b/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch deleted file mode 100644 index 014342aad5bc14..00000000000000 --- a/target/linux/mediatek/patches-6.1/911-dts-mt7622-bpi-r64-add-rootdisk.patch +++ /dev/null @@ -1,103 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -32,6 +32,9 @@ - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; -+ rootdisk-emmc = <&emmc_rootfs>; -+ rootdisk-sd = <&sd_rootfs>; -+ rootdisk-snfi = <&ubi_rootfs>; - }; - - cpus { -@@ -234,6 +237,26 @@ - assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; - non-removable; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ block { -+ compatible = "block-device"; -+ partitions { -+ block-partition-env { -+ partname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-layout"; -+ }; -+ }; -+ emmc_rootfs: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+ }; - }; - - &mmc1 { -@@ -250,6 +273,26 @@ - vqmmc-supply = <®_3p3v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; -+ -+ card@0 { -+ compatible = "mmc-card"; -+ reg = <0>; -+ -+ block { -+ compatible = "block-device"; -+ partitions { -+ block-partition-env { -+ partname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-layout"; -+ }; -+ }; -+ sd_rootfs: block-partition-production { -+ partname = "production"; -+ }; -+ }; -+ }; -+ }; - }; - - &nandc { -@@ -284,14 +327,29 @@ - }; - - partition@80000 { -- label = "fip"; -- reg = <0x80000 0x200000>; -- read-only; -- }; -- -- ubi: partition@280000 { - label = "ubi"; -- reg = <0x280000 0x7d80000>; -+ reg = <0x80000 0x7f80000>; -+ compatible = "linux,ubi"; -+ -+ volumes { -+ ubi-volume-ubootenv { -+ volname = "ubootenv"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool-layout"; -+ }; -+ }; -+ -+ ubi-volume-ubootenv2 { -+ volname = "ubootenv2"; -+ nvmem-layout { -+ compatible = "u-boot,env-redundant-bool-layout"; -+ }; -+ }; -+ -+ ubi_rootfs: ubi-volume-fit { -+ volname = "fit"; -+ }; -+ }; - }; - }; - }; diff --git a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch b/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch deleted file mode 100644 index 3d05bf7679b8f7..00000000000000 --- a/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -1227,8 +1227,15 @@ static int mtk_spi_probe(struct platform - if (ret < 0) - return dev_err_probe(dev, ret, "failed to enable hclk\n"); - -+ ret = clk_prepare_enable(mdata->sel_clk); -+ if (ret < 0) { -+ clk_disable_unprepare(mdata->spi_hclk); -+ return dev_err_probe(dev, ret, "failed to enable sel_clk\n"); -+ } -+ - ret = clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { -+ clk_disable_unprepare(mdata->sel_clk); - clk_disable_unprepare(mdata->spi_hclk); - return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); - } diff --git a/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch deleted file mode 100644 index 30be53518ac19c..00000000000000 --- a/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001 -Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 16:40:31 +0100 -Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename - mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region - -This is a preliminary patch to move wed ilm/dlm and cpuboot properties in -dedicated dts nodes. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -234,8 +234,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we - } - - static int --mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index, -- struct mtk_wed_wo_memory_region *region) -+mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index, -+ struct mtk_wed_wo_memory_region *region) - { - struct reserved_mem *rmem; - struct device_node *np; -@@ -321,7 +321,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - if (index < 0) - continue; - -- ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]); -+ ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]); - if (ret) - return ret; - } diff --git a/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch deleted file mode 100644 index da61f1c0502f33..00000000000000 --- a/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001 -Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 16:32:41 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++---------- - 1 file changed, 11 insertions(+), 10 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -121,12 +121,6 @@ - reg = <0 0x151f8000 0 0x2000>; - no-map; - }; -- -- wo_boot: wo-boot@15194000 { -- reg = <0 0x15194000 0 0x1000>; -- no-map; -- }; -- - }; - - timer { -@@ -541,10 +535,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wed1: wed@15011000 { -@@ -554,10 +549,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wo_ccif0: syscon@151a5000 { -@@ -574,6 +570,11 @@ - interrupts = ; - }; - -+ wo_cpuboot: syscon@15194000 { -+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; -+ reg = <0 0x15194000 0 0x1000>; -+ }; -+ - eth: ethernet@15100000 { - compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; diff --git a/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch deleted file mode 100644 index b4bea2087b3d80..00000000000000 --- a/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch +++ /dev/null @@ -1,81 +0,0 @@ -From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 18:13:04 +0100 -Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a - dedicated dts node - -Since the cpuboot memory region is not part of the RAM SoC, move cpuboot -in a deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where cpuboot was -defined as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +- - 2 files changed, 30 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -34,12 +34,23 @@ static struct mtk_wed_wo_memory_region m - - static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg) - { -- return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); -+ u32 val; -+ -+ if (!wo->boot_regmap) -+ return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); -+ -+ if (regmap_read(wo->boot_regmap, reg, &val)) -+ val = ~0; -+ -+ return val; - } - - static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val) - { -- writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); -+ if (wo->boot_regmap) -+ regmap_write(wo->boot_regmap, reg, val); -+ else -+ writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg); - } - - static struct sk_buff * -@@ -313,6 +324,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - u32 val, boot_cr; - int ret, i; - -+ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, -+ "mediatek,wo-cpuboot"); -+ - /* load firmware region metadata */ - for (i = 0; i < ARRAY_SIZE(mem_region); i++) { - int index = of_property_match_string(wo->hw->node, -@@ -321,6 +335,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - if (index < 0) - continue; - -+ if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap)) -+ continue; -+ - ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]); - if (ret) - return ret; ---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h -+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h -@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue { - struct mtk_wed_wo { - struct mtk_wed_hw *hw; - -+ struct regmap *boot_regmap; - struct mtk_wed_wo_queue q_tx; - struct mtk_wed_wo_queue q_rx; - diff --git a/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch deleted file mode 100644 index b4ba5b0d2df4be..00000000000000 --- a/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,86 +0,0 @@ -From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001 -Message-Id: -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 18:51:47 +0100 -Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts - node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where ilm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++--- - 1 file changed, 49 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -316,6 +316,39 @@ next: - } - - static int -+mtk_wed_mcu_load_ilm(struct mtk_wed_wo *wo) -+{ -+ struct mtk_wed_wo_memory_region *ilm_region; -+ struct resource res; -+ struct device_node *np; -+ int ret; -+ -+ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0); -+ if (!np) -+ return 0; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ ilm_region = &mem_region[MTK_WED_WO_REGION_ILM]; -+ ilm_region->phy_addr = res.start; -+ ilm_region->size = resource_size(&res); -+ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start, -+ resource_size(&res)); -+ -+ if (!IS_ERR(ilm_region->addr)) -+ return 0; -+ -+ ret = PTR_ERR(ilm_region->addr); -+ ilm_region->addr = NULL; -+ -+ return ret; -+} -+ -+static int - mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo) - { - const struct mtk_wed_fw_trailer *trailer; -@@ -324,14 +357,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - u32 val, boot_cr; - int ret, i; - -+ mtk_wed_mcu_load_ilm(wo); - wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, - "mediatek,wo-cpuboot"); - - /* load firmware region metadata */ - for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- int index = of_property_match_string(wo->hw->node, -- "memory-region-names", -- mem_region[i].name); -+ int index; -+ -+ if (mem_region[i].addr) -+ continue; -+ -+ index = of_property_match_string(wo->hw->node, -+ "memory-region-names", -+ mem_region[i].name); - if (index < 0) - continue; - diff --git a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch deleted file mode 100644 index c92fcd43cee97b..00000000000000 --- a/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: -References: -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:45:16 +0100 -Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts - node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where dlm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_wed.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device - struct device_node *np; - int index; - -+ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0); -+ if (np) { -+ struct resource res; -+ int ret; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ dev->rro.miod_phys = res.start; -+ goto out; -+ } -+ -+ /* For backward compatibility, we need to check if DLM -+ * node is defined through reserved memory property. -+ */ - index = of_property_match_string(dev->hw->node, "memory-region-names", - "wo-dlm"); - if (index < 0) -@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device - return -ENODEV; - - dev->rro.miod_phys = rmem->base; -+out: - dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; - - return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring, diff --git a/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch deleted file mode 100644 index 2f1becd1b8912a..00000000000000 --- a/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001 -Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:10:56 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------ - 1 file changed, 16 insertions(+), 18 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -97,16 +97,6 @@ - no-map; - }; - -- wo_ilm0: wo-ilm@151e0000 { -- reg = <0 0x151e0000 0 0x8000>; -- no-map; -- }; -- -- wo_ilm1: wo-ilm@151f0000 { -- reg = <0 0x151f0000 0 0x8000>; -- no-map; -- }; -- - wo_data: wo-data@4fd80000 { - reg = <0 0x4fd80000 0 0x240000>; - no-map; -@@ -534,11 +524,10 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -548,11 +537,10 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-ilm = <&wo_ilm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -570,6 +558,16 @@ - interrupts = ; - }; - -+ wo_ilm0: syscon@151e0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151e0000 0 0x8000>; -+ }; -+ -+ wo_ilm1: syscon@151f0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151f0000 0 0x8000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch deleted file mode 100644 index 5b52a4934e2634..00000000000000 --- a/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001 -Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:53:30 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++----------- - 1 file changed, 16 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -101,16 +101,6 @@ - reg = <0 0x4fd80000 0 0x240000>; - no-map; - }; -- -- wo_dlm0: wo-dlm@151e8000 { -- reg = <0 0x151e8000 0 0x2000>; -- no-map; -- }; -- -- wo_dlm1: wo-dlm@151f8000 { -- reg = <0 0x151f8000 0 0x2000>; -- no-map; -- }; - }; - - timer { -@@ -524,10 +514,11 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; -+ mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -537,10 +528,11 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; - mediatek,wo-ilm = <&wo_ilm1>; -+ mediatek,wo-dlm = <&wo_dlm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -568,6 +560,16 @@ - reg = <0 0x151f0000 0 0x8000>; - }; - -+ wo_dlm0: syscon@151e8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151e8000 0 0x2000>; -+ }; -+ -+ wo_dlm1: syscon@151f8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151f8000 0 0x2000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; diff --git a/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch b/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch deleted file mode 100644 index 8b86c5042972d2..00000000000000 --- a/target/linux/mediatek/patches-6.1/950-smartrg-i2c-led-driver.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- - drivers/leds/Kconfig | 10 ++++++++++ - drivers/leds/Makefile | 1 + - 2 files changed, 11 insertions(+) - ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -874,6 +874,16 @@ source "drivers/leds/flash/Kconfig" - comment "RGB LED drivers" - source "drivers/leds/rgb/Kconfig" - -+config LEDS_SMARTRG_LED -+ tristate "LED support for Adtran SmartRG" -+ depends on LEDS_CLASS && I2C && OF -+ help -+ This option enables support for the Adtran SmartRG platform -+ system LED driver. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called leds-smartrg-system. -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o - obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o - obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o - obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o -+obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o - obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o - obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o - obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o diff --git a/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch b/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch deleted file mode 100644 index 71cb3006ab8da0..00000000000000 --- a/target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch +++ /dev/null @@ -1,599 +0,0 @@ -From: Lorenzo Bianconi -Date: Thu, 2 Nov 2023 16:47:07 +0100 -Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields - in mtk_soc_data struct - -Split tx and rx fields in mtk_soc_data struct. This is a preliminary -patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang -if the device receives a corrupted packet. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++-------- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +-- - 2 files changed, 139 insertions(+), 100 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1264,7 +1264,7 @@ static int mtk_init_fq_dma(struct mtk_et - eth->scratch_ring = eth->sram_base; - else - eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, -- cnt * soc->txrx.txd_size, -+ cnt * soc->tx.desc_size, - ð->phy_scratch_ring, - GFP_KERNEL); - if (unlikely(!eth->scratch_ring)) -@@ -1280,16 +1280,16 @@ static int mtk_init_fq_dma(struct mtk_et - if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) - return -ENOMEM; - -- phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); -+ phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1); - - for (i = 0; i < cnt; i++) { - struct mtk_tx_dma_v2 *txd; - -- txd = eth->scratch_ring + i * soc->txrx.txd_size; -+ txd = eth->scratch_ring + i * soc->tx.desc_size; - txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; - if (i < cnt - 1) - txd->txd2 = eth->phy_scratch_ring + -- (i + 1) * soc->txrx.txd_size; -+ (i + 1) * soc->tx.desc_size; - - txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); - txd->txd4 = 0; -@@ -1538,7 +1538,7 @@ static int mtk_tx_map(struct sk_buff *sk - if (itxd == ring->last_free) - return -ENOMEM; - -- itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); -+ itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); - memset(itx_buf, 0, sizeof(*itx_buf)); - - txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, -@@ -1579,7 +1579,7 @@ static int mtk_tx_map(struct sk_buff *sk - - memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); - txd_info.size = min_t(unsigned int, frag_size, -- soc->txrx.dma_max_len); -+ soc->tx.dma_max_len); - txd_info.qid = queue; - txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && - !(frag_size - txd_info.size); -@@ -1592,7 +1592,7 @@ static int mtk_tx_map(struct sk_buff *sk - mtk_tx_set_dma_desc(dev, txd, &txd_info); - - tx_buf = mtk_desc_to_tx_buf(ring, txd, -- soc->txrx.txd_size); -+ soc->tx.desc_size); - if (new_desc) - memset(tx_buf, 0, sizeof(*tx_buf)); - tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; -@@ -1635,7 +1635,7 @@ static int mtk_tx_map(struct sk_buff *sk - } else { - int next_idx; - -- next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), -+ next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size), - ring->dma_size); - mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); - } -@@ -1644,7 +1644,7 @@ static int mtk_tx_map(struct sk_buff *sk - - err_dma: - do { -- tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); -+ tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size); - - /* unmap dma */ - mtk_tx_unmap(eth, tx_buf, NULL, false); -@@ -1669,7 +1669,7 @@ static int mtk_cal_txd_req(struct mtk_et - for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { - frag = &skb_shinfo(skb)->frags[i]; - nfrags += DIV_ROUND_UP(skb_frag_size(frag), -- eth->soc->txrx.dma_max_len); -+ eth->soc->tx.dma_max_len); - } - } else { - nfrags += skb_shinfo(skb)->nr_frags; -@@ -1810,7 +1810,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri - - ring = ð->rx_ring[i]; - idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); -- rxd = ring->dma + idx * eth->soc->txrx.rxd_size; -+ rxd = ring->dma + idx * eth->soc->rx.desc_size; - if (rxd->rxd2 & RX_DMA_DONE) { - ring->calc_idx_update = true; - return ring; -@@ -1978,7 +1978,7 @@ static int mtk_xdp_submit_frame(struct m - } - htxd = txd; - -- tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); -+ tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size); - memset(tx_buf, 0, sizeof(*tx_buf)); - htx_buf = tx_buf; - -@@ -1997,7 +1997,7 @@ static int mtk_xdp_submit_frame(struct m - goto unmap; - - tx_buf = mtk_desc_to_tx_buf(ring, txd, -- soc->txrx.txd_size); -+ soc->tx.desc_size); - memset(tx_buf, 0, sizeof(*tx_buf)); - n_desc++; - } -@@ -2035,7 +2035,7 @@ static int mtk_xdp_submit_frame(struct m - } else { - int idx; - -- idx = txd_to_idx(ring, txd, soc->txrx.txd_size); -+ idx = txd_to_idx(ring, txd, soc->tx.desc_size); - mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), - MT7628_TX_CTX_IDX0); - } -@@ -2046,7 +2046,7 @@ static int mtk_xdp_submit_frame(struct m - - unmap: - while (htxd != txd) { -- tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); -+ tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size); - mtk_tx_unmap(eth, tx_buf, NULL, false); - - htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; -@@ -2177,7 +2177,7 @@ static int mtk_poll_rx(struct napi_struc - goto rx_done; - - idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); -- rxd = ring->dma + idx * eth->soc->txrx.rxd_size; -+ rxd = ring->dma + idx * eth->soc->rx.desc_size; - data = ring->data[idx]; - - if (!mtk_rx_get_desc(eth, &trxd, rxd)) -@@ -2312,7 +2312,7 @@ static int mtk_poll_rx(struct napi_struc - rxdcsum = &trxd.rxd4; - } - -- if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) -+ if (*rxdcsum & eth->soc->rx.dma_l4_valid) - skb->ip_summed = CHECKSUM_UNNECESSARY; - else - skb_checksum_none_assert(skb); -@@ -2436,7 +2436,7 @@ static int mtk_poll_tx_qdma(struct mtk_e - break; - - tx_buf = mtk_desc_to_tx_buf(ring, desc, -- eth->soc->txrx.txd_size); -+ eth->soc->tx.desc_size); - if (!tx_buf->data) - break; - -@@ -2487,7 +2487,7 @@ static int mtk_poll_tx_pdma(struct mtk_e - } - mtk_tx_unmap(eth, tx_buf, &bq, true); - -- desc = ring->dma + cpu * eth->soc->txrx.txd_size; -+ desc = ring->dma + cpu * eth->soc->tx.desc_size; - ring->last_free = desc; - atomic_inc(&ring->free_count); - -@@ -2577,7 +2577,7 @@ static int mtk_napi_rx(struct napi_struc - do { - int rx_done; - -- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, -+ mtk_w32(eth, eth->soc->rx.irq_done_mask, - reg_map->pdma.irq_status); - rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); - rx_done_total += rx_done; -@@ -2593,10 +2593,10 @@ static int mtk_napi_rx(struct napi_struc - return budget; - - } while (mtk_r32(eth, reg_map->pdma.irq_status) & -- eth->soc->txrx.rx_irq_done_mask); -+ eth->soc->rx.irq_done_mask); - - if (napi_complete_done(napi, rx_done_total)) -- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); -+ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); - - return rx_done_total; - } -@@ -2605,7 +2605,7 @@ static int mtk_tx_alloc(struct mtk_eth * - { - const struct mtk_soc_data *soc = eth->soc; - struct mtk_tx_ring *ring = ð->tx_ring; -- int i, sz = soc->txrx.txd_size; -+ int i, sz = soc->tx.desc_size; - struct mtk_tx_dma_v2 *txd; - int ring_size; - u32 ofs, val; -@@ -2728,14 +2728,14 @@ static void mtk_tx_clean(struct mtk_eth - } - if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) { - dma_free_coherent(eth->dma_dev, -- ring->dma_size * soc->txrx.txd_size, -+ ring->dma_size * soc->tx.desc_size, - ring->dma, ring->phys); - ring->dma = NULL; - } - - if (ring->dma_pdma) { - dma_free_coherent(eth->dma_dev, -- ring->dma_size * soc->txrx.txd_size, -+ ring->dma_size * soc->tx.desc_size, - ring->dma_pdma, ring->phys_pdma); - ring->dma_pdma = NULL; - } -@@ -2790,15 +2790,15 @@ static int mtk_rx_alloc(struct mtk_eth * - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) || - rx_flag != MTK_RX_FLAGS_NORMAL) { - ring->dma = dma_alloc_coherent(eth->dma_dev, -- rx_dma_size * eth->soc->txrx.rxd_size, -- &ring->phys, GFP_KERNEL); -+ rx_dma_size * eth->soc->rx.desc_size, -+ &ring->phys, GFP_KERNEL); - } else { - struct mtk_tx_ring *tx_ring = ð->tx_ring; - - ring->dma = tx_ring->dma + tx_ring_size * -- eth->soc->txrx.txd_size * (ring_no + 1); -+ eth->soc->tx.desc_size * (ring_no + 1); - ring->phys = tx_ring->phys + tx_ring_size * -- eth->soc->txrx.txd_size * (ring_no + 1); -+ eth->soc->tx.desc_size * (ring_no + 1); - } - - if (!ring->dma) -@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth * - dma_addr_t dma_addr; - void *data; - -- rxd = ring->dma + i * eth->soc->txrx.rxd_size; -+ rxd = ring->dma + i * eth->soc->rx.desc_size; - if (ring->page_pool) { - data = mtk_page_pool_get_buff(ring->page_pool, - &dma_addr, GFP_KERNEL); -@@ -2900,7 +2900,7 @@ static void mtk_rx_clean(struct mtk_eth - if (!ring->data[i]) - continue; - -- rxd = ring->dma + i * eth->soc->txrx.rxd_size; -+ rxd = ring->dma + i * eth->soc->rx.desc_size; - if (!rxd->rxd1) - continue; - -@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth - - if (!in_sram && ring->dma) { - dma_free_coherent(eth->dma_dev, -- ring->dma_size * eth->soc->txrx.rxd_size, -+ ring->dma_size * eth->soc->rx.desc_size, - ring->dma, ring->phys); - ring->dma = NULL; - } -@@ -3280,7 +3280,7 @@ static void mtk_dma_free(struct mtk_eth - netdev_reset_queue(eth->netdev[i]); - if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) { - dma_free_coherent(eth->dma_dev, -- MTK_QDMA_RING_SIZE * soc->txrx.txd_size, -+ MTK_QDMA_RING_SIZE * soc->tx.desc_size, - eth->scratch_ring, eth->phy_scratch_ring); - eth->scratch_ring = NULL; - eth->phy_scratch_ring = 0; -@@ -3330,7 +3330,7 @@ static irqreturn_t mtk_handle_irq_rx(int - - eth->rx_events++; - if (likely(napi_schedule_prep(ð->rx_napi))) { -- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); -+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); - __napi_schedule(ð->rx_napi); - } - -@@ -3356,9 +3356,9 @@ static irqreturn_t mtk_handle_irq(int ir - const struct mtk_reg_map *reg_map = eth->soc->reg_map; - - if (mtk_r32(eth, reg_map->pdma.irq_mask) & -- eth->soc->txrx.rx_irq_done_mask) { -+ eth->soc->rx.irq_done_mask) { - if (mtk_r32(eth, reg_map->pdma.irq_status) & -- eth->soc->txrx.rx_irq_done_mask) -+ eth->soc->rx.irq_done_mask) - mtk_handle_irq_rx(irq, _eth); - } - if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { -@@ -3376,10 +3376,10 @@ static void mtk_poll_controller(struct n - struct mtk_eth *eth = mac->hw; - - mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); -- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); -+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); - mtk_handle_irq_rx(eth->irq[2], dev); - mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); -- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); -+ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask); - } - #endif - -@@ -3545,7 +3545,7 @@ static int mtk_open(struct net_device *d - napi_enable(ð->tx_napi); - napi_enable(ð->rx_napi); - mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); -- mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); -+ mtk_rx_irq_enable(eth, soc->rx.irq_done_mask); - refcount_set(ð->dma_refcnt, 1); - } - else -@@ -3628,7 +3628,7 @@ static int mtk_stop(struct net_device *d - mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); - - mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); -- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); -+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask); - napi_disable(ð->tx_napi); - napi_disable(ð->rx_napi); - -@@ -4107,9 +4107,9 @@ static int mtk_hw_init(struct mtk_eth *e - - /* FE int grouping */ - mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); -- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); -+ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4); - mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); -- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); -+ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4); - mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); - - if (mtk_is_netsys_v3_or_greater(eth)) { -@@ -5270,11 +5270,15 @@ static const struct mtk_soc_data mt2701_ - .required_clks = MT7623_CLKS_BITMAP, - .required_pctl = true, - .version = 1, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), -- .rx_irq_done_mask = MTK_RX_DONE_INT, -- .rx_dma_l4_valid = RX_DMA_L4_VALID, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN, -+ .dma_len_offset = 16, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma), -+ .irq_done_mask = MTK_RX_DONE_INT, -+ .dma_l4_valid = RX_DMA_L4_VALID, - .dma_max_len = MTK_TX_DMA_BUF_LEN, - .dma_len_offset = 16, - }, -@@ -5290,11 +5294,15 @@ static const struct mtk_soc_data mt7621_ - .offload_version = 1, - .hash_offset = 2, - .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), -- .rx_irq_done_mask = MTK_RX_DONE_INT, -- .rx_dma_l4_valid = RX_DMA_L4_VALID, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN, -+ .dma_len_offset = 16, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma), -+ .irq_done_mask = MTK_RX_DONE_INT, -+ .dma_l4_valid = RX_DMA_L4_VALID, - .dma_max_len = MTK_TX_DMA_BUF_LEN, - .dma_len_offset = 16, - }, -@@ -5312,11 +5320,15 @@ static const struct mtk_soc_data mt7622_ - .hash_offset = 2, - .has_accounting = true, - .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), -- .rx_irq_done_mask = MTK_RX_DONE_INT, -- .rx_dma_l4_valid = RX_DMA_L4_VALID, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN, -+ .dma_len_offset = 16, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma), -+ .irq_done_mask = MTK_RX_DONE_INT, -+ .dma_l4_valid = RX_DMA_L4_VALID, - .dma_max_len = MTK_TX_DMA_BUF_LEN, - .dma_len_offset = 16, - }, -@@ -5333,11 +5345,15 @@ static const struct mtk_soc_data mt7623_ - .hash_offset = 2, - .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, - .disable_pll_modes = true, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), -- .rx_irq_done_mask = MTK_RX_DONE_INT, -- .rx_dma_l4_valid = RX_DMA_L4_VALID, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN, -+ .dma_len_offset = 16, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma), -+ .irq_done_mask = MTK_RX_DONE_INT, -+ .dma_l4_valid = RX_DMA_L4_VALID, - .dma_max_len = MTK_TX_DMA_BUF_LEN, - .dma_len_offset = 16, - }, -@@ -5352,11 +5368,15 @@ static const struct mtk_soc_data mt7629_ - .required_pctl = false, - .has_accounting = true, - .version = 1, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), -- .rx_irq_done_mask = MTK_RX_DONE_INT, -- .rx_dma_l4_valid = RX_DMA_L4_VALID, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN, -+ .dma_len_offset = 16, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma), -+ .irq_done_mask = MTK_RX_DONE_INT, -+ .dma_l4_valid = RX_DMA_L4_VALID, - .dma_max_len = MTK_TX_DMA_BUF_LEN, - .dma_len_offset = 16, - }, -@@ -5374,11 +5394,15 @@ static const struct mtk_soc_data mt7981_ - .hash_offset = 4, - .has_accounting = true, - .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma_v2), -- .rxd_size = sizeof(struct mtk_rx_dma_v2), -- .rx_irq_done_mask = MTK_RX_DONE_INT_V2, -- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma_v2), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -+ .dma_len_offset = 8, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma_v2), -+ .irq_done_mask = MTK_RX_DONE_INT_V2, -+ .dma_l4_valid = RX_DMA_L4_VALID_V2, - .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, - .dma_len_offset = 8, - }, -@@ -5396,11 +5420,15 @@ static const struct mtk_soc_data mt7986_ - .hash_offset = 4, - .has_accounting = true, - .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma_v2), -- .rxd_size = sizeof(struct mtk_rx_dma_v2), -- .rx_irq_done_mask = MTK_RX_DONE_INT_V2, -- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma_v2), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -+ .dma_len_offset = 8, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma_v2), -+ .irq_done_mask = MTK_RX_DONE_INT_V2, -+ .dma_l4_valid = RX_DMA_L4_VALID_V2, - .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, - .dma_len_offset = 8, - }, -@@ -5418,11 +5446,15 @@ static const struct mtk_soc_data mt7988_ - .hash_offset = 4, - .has_accounting = true, - .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma_v2), -- .rxd_size = sizeof(struct mtk_rx_dma_v2), -- .rx_irq_done_mask = MTK_RX_DONE_INT_V2, -- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma_v2), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -+ .dma_len_offset = 8, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma_v2), -+ .irq_done_mask = MTK_RX_DONE_INT_V2, -+ .dma_l4_valid = RX_DMA_L4_VALID_V2, - .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, - .dma_len_offset = 8, - }, -@@ -5435,11 +5467,15 @@ static const struct mtk_soc_data rt5350_ - .required_clks = MT7628_CLKS_BITMAP, - .required_pctl = false, - .version = 1, -- .txrx = { -- .txd_size = sizeof(struct mtk_tx_dma), -- .rxd_size = sizeof(struct mtk_rx_dma), -- .rx_irq_done_mask = MTK_RX_DONE_INT, -- .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, -+ .tx = { -+ .desc_size = sizeof(struct mtk_tx_dma), -+ .dma_max_len = MTK_TX_DMA_BUF_LEN, -+ .dma_len_offset = 16, -+ }, -+ .rx = { -+ .desc_size = sizeof(struct mtk_rx_dma), -+ .irq_done_mask = MTK_RX_DONE_INT, -+ .dma_l4_valid = RX_DMA_L4_VALID_PDMA, - .dma_max_len = MTK_TX_DMA_BUF_LEN, - .dma_len_offset = 16, - }, ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -327,8 +327,8 @@ - /* QDMA descriptor txd3 */ - #define TX_DMA_OWNER_CPU BIT(31) - #define TX_DMA_LS0 BIT(30) --#define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) --#define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len) -+#define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset) -+#define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len) - #define TX_DMA_SWC BIT(14) - #define TX_DMA_PQID GENMASK(3, 0) - #define TX_DMA_ADDR64_MASK GENMASK(3, 0) -@@ -348,8 +348,8 @@ - /* QDMA descriptor rxd2 */ - #define RX_DMA_DONE BIT(31) - #define RX_DMA_LSO BIT(30) --#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset) --#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len) -+#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset) -+#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len) - #define RX_DMA_VTAG BIT(15) - #define RX_DMA_ADDR64_MASK GENMASK(3, 0) - #if IS_ENABLED(CONFIG_64BIT) -@@ -1209,10 +1209,9 @@ struct mtk_reg_map { - * @foe_entry_size Foe table entry size. - * @has_accounting Bool indicating support for accounting of - * offloaded flows. -- * @txd_size Tx DMA descriptor size. -- * @rxd_size Rx DMA descriptor size. -- * @rx_irq_done_mask Rx irq done register mask. -- * @rx_dma_l4_valid Rx DMA valid register mask. -+ * @desc_size Tx/Rx DMA descriptor size. -+ * @irq_done_mask Rx irq done register mask. -+ * @dma_l4_valid Rx DMA valid register mask. - * @dma_max_len Max DMA tx/rx buffer length. - * @dma_len_offset Tx/Rx DMA length field offset. - */ -@@ -1230,13 +1229,17 @@ struct mtk_soc_data { - bool has_accounting; - bool disable_pll_modes; - struct { -- u32 txd_size; -- u32 rxd_size; -- u32 rx_irq_done_mask; -- u32 rx_dma_l4_valid; -+ u32 desc_size; - u32 dma_max_len; - u32 dma_len_offset; -- } txrx; -+ } tx; -+ struct { -+ u32 desc_size; -+ u32 irq_done_mask; -+ u32 dma_l4_valid; -+ u32 dma_max_len; -+ u32 dma_len_offset; -+ } rx; - }; - - #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) diff --git a/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch b/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch deleted file mode 100644 index 8b7d5c0a1c904a..00000000000000 --- a/target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch +++ /dev/null @@ -1,123 +0,0 @@ -From: Daniel Golle -Date: Tue, 10 Oct 2023 21:06:43 +0200 -Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of - ADMAv2 on MT7981 and MT7986 - -ADMA is plagued by RX hangs which can't easily detected and happen upon -receival of a corrupted package. -Use QDMA just like on netsys v1 which is also still present and usable, and -doesn't suffer from that problem. - -Co-developed-by: Lorenzo Bianconi -Signed-off-by: Lorenzo Bianconi -Signed-off-by: Daniel Golle ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++----------- - 1 file changed, 23 insertions(+), 23 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r - .tx_irq_mask = 0x461c, - .tx_irq_status = 0x4618, - .pdma = { -- .rx_ptr = 0x6100, -- .rx_cnt_cfg = 0x6104, -- .pcrx_ptr = 0x6108, -- .glo_cfg = 0x6204, -- .rst_idx = 0x6208, -- .delay_irq = 0x620c, -- .irq_status = 0x6220, -- .irq_mask = 0x6228, -- .adma_rx_dbg0 = 0x6238, -- .int_grp = 0x6250, -+ .rx_ptr = 0x4100, -+ .rx_cnt_cfg = 0x4104, -+ .pcrx_ptr = 0x4108, -+ .glo_cfg = 0x4204, -+ .rst_idx = 0x4208, -+ .delay_irq = 0x420c, -+ .irq_status = 0x4220, -+ .irq_mask = 0x4228, -+ .adma_rx_dbg0 = 0x4238, -+ .int_grp = 0x4250, - }, - .qdma = { - .qtx_cfg = 0x4400, -@@ -1232,7 +1232,7 @@ static bool mtk_rx_get_desc(struct mtk_e - rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); - rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); - rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); -- if (mtk_is_netsys_v2_or_greater(eth)) { -+ if (mtk_is_netsys_v3_or_greater(eth)) { - rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); - rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); - } -@@ -2184,7 +2184,7 @@ static int mtk_poll_rx(struct napi_struc - break; - - /* find out which mac the packet come from. values start at 1 */ -- if (mtk_is_netsys_v2_or_greater(eth)) { -+ if (mtk_is_netsys_v3_or_greater(eth)) { - u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); - - switch (val) { -@@ -2296,7 +2296,7 @@ static int mtk_poll_rx(struct napi_struc - skb->dev = netdev; - bytes += skb->len; - -- if (mtk_is_netsys_v2_or_greater(eth)) { -+ if (mtk_is_netsys_v3_or_greater(eth)) { - reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); - hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; - if (hash != MTK_RXD5_FOE_ENTRY) -@@ -2846,7 +2846,7 @@ static int mtk_rx_alloc(struct mtk_eth * - - rxd->rxd3 = 0; - rxd->rxd4 = 0; -- if (mtk_is_netsys_v2_or_greater(eth)) { -+ if (mtk_is_netsys_v3_or_greater(eth)) { - rxd->rxd5 = 0; - rxd->rxd6 = 0; - rxd->rxd7 = 0; -@@ -4053,7 +4053,7 @@ static int mtk_hw_init(struct mtk_eth *e - else - mtk_hw_reset(eth); - -- if (mtk_is_netsys_v2_or_greater(eth)) { -+ if (mtk_is_netsys_v3_or_greater(eth)) { - /* Set FE to PDMAv2 if necessary */ - val = mtk_r32(eth, MTK_FE_GLO_MISC); - mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); -@@ -5400,11 +5400,11 @@ static const struct mtk_soc_data mt7981_ - .dma_len_offset = 8, - }, - .rx = { -- .desc_size = sizeof(struct mtk_rx_dma_v2), -- .irq_done_mask = MTK_RX_DONE_INT_V2, -+ .desc_size = sizeof(struct mtk_rx_dma), -+ .irq_done_mask = MTK_RX_DONE_INT, - .dma_l4_valid = RX_DMA_L4_VALID_V2, -- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -- .dma_len_offset = 8, -+ .dma_max_len = MTK_TX_DMA_BUF_LEN, -+ .dma_len_offset = 16, - }, - }; - -@@ -5426,11 +5426,11 @@ static const struct mtk_soc_data mt7986_ - .dma_len_offset = 8, - }, - .rx = { -- .desc_size = sizeof(struct mtk_rx_dma_v2), -- .irq_done_mask = MTK_RX_DONE_INT_V2, -+ .desc_size = sizeof(struct mtk_rx_dma), -+ .irq_done_mask = MTK_RX_DONE_INT, - .dma_l4_valid = RX_DMA_L4_VALID_V2, -- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, -- .dma_len_offset = 8, -+ .dma_max_len = MTK_TX_DMA_BUF_LEN, -+ .dma_len_offset = 16, - }, - }; - diff --git a/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch b/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch deleted file mode 100644 index 11b52d07ab3481..00000000000000 --- a/target/linux/mediatek/patches-6.1/963-net-ethernet-mtk_eth_soc-fix-WED-wifi-reset.patch +++ /dev/null @@ -1,49 +0,0 @@ -From: Felix Fietkau -Date: Thu, 18 Jan 2024 12:51:32 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset - -The WLAN + WED reset sequence relies on being able to receive interrupts from -the card, in order to synchronize individual steps with the firmware. -When WED is stopped, leave interrupts running and rely on the driver turning -off unwanted ones. -WED DMA also needs to be disabled before resetting. - -Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop") -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_wed.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -1071,13 +1071,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic - static void - mtk_wed_stop(struct mtk_wed_device *dev) - { -+ mtk_wed_dma_disable(dev); - mtk_wed_set_ext_int(dev, false); - - wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0); - wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0); - wdma_w32(dev, MTK_WDMA_INT_MASK, 0); - wdma_w32(dev, MTK_WDMA_INT_GRP2, 0); -- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0); - - if (!mtk_wed_get_rx_capa(dev)) - return; -@@ -1090,7 +1090,6 @@ static void - mtk_wed_deinit(struct mtk_wed_device *dev) - { - mtk_wed_stop(dev); -- mtk_wed_dma_disable(dev); - - wed_clr(dev, MTK_WED_CTRL, - MTK_WED_CTRL_WDMA_INT_AGENT_EN | -@@ -2621,9 +2620,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d - static void - mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask) - { -- if (!dev->running) -- return; -- - mtk_wed_set_ext_int(dev, !!mask); - wed_w32(dev, MTK_WED_INT_MASK, mask); - } diff --git a/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch index 7ab735af4c7cc6..ec6cef800a000d 100644 --- a/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch +++ b/target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch @@ -258,7 +258,7 @@ Signed-off-by: Michael Gray static int kernel_init(void *); extern void init_IRQ(void); -@@ -994,6 +998,18 @@ asmlinkage __visible void __init __no_sa +@@ -996,6 +1000,18 @@ asmlinkage __visible void __init __no_sa page_alloc_init(); pr_notice("Kernel command line: %s\n", saved_command_line); diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts index 5364daad454741..23e89a9ae42d31 100644 --- a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts +++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax880.dts @@ -193,6 +193,7 @@ }; partition@480000 { + compatible = "u-boot,env"; label = "0:appsblenv"; reg = <0x480000 0x10000>; }; diff --git a/target/linux/ramips/Makefile b/target/linux/ramips/Makefile index fec2a2b1f83c58..1429fdd65593bf 100644 --- a/target/linux/ramips/Makefile +++ b/target/linux/ramips/Makefile @@ -10,8 +10,7 @@ BOARDNAME:=MediaTek Ralink MIPS SUBTARGETS:=mt7620 mt7621 mt76x8 rt288x rt305x rt3883 FEATURES:=squashfs gpio -KERNEL_PATCHVER:=6.1 -KERNEL_TESTING_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.6 define Target/Description Build firmware images for Ralink RT288x/RT3xxx based boards. diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 086719a43d4bb7..54fe13123db134 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -474,6 +474,36 @@ #interrupt-cells = <1>; interrupts = ; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupts = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupts = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + interrupts = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + interrupts = <3>; + }; + + ethphy4: ethernet-phy@4 { + reg = <4>; + interrupts = <4>; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; @@ -482,30 +512,35 @@ status = "disabled"; reg = <0>; label = "lan0"; + phy-handle = <ðphy0>; }; port@1 { status = "disabled"; reg = <1>; label = "lan1"; + phy-handle = <ðphy1>; }; port@2 { status = "disabled"; reg = <2>; label = "lan2"; + phy-handle = <ðphy2>; }; port@3 { status = "disabled"; reg = <3>; label = "lan3"; + phy-handle = <ðphy3>; }; port@4 { status = "disabled"; reg = <4>; label = "lan4"; + phy-handle = <ðphy4>; }; port@6 { diff --git a/target/linux/ramips/dts/mt7621_adslr_g7.dts b/target/linux/ramips/dts/mt7621_adslr_g7.dts index 6ca9eccd2d788e..2dea282bf5b160 100644 --- a/target/linux/ramips/dts/mt7621_adslr_g7.dts +++ b/target/linux/ramips/dts/mt7621_adslr_g7.dts @@ -136,10 +136,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts b/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts index 4f942f160203e9..f2f5719af21b31 100644 --- a/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts +++ b/target/linux/ramips/dts/mt7621_afoundry_ew1200.dts @@ -155,10 +155,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts b/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts index 85fda96ce5c606..c0e208d33dae50 100644 --- a/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts +++ b/target/linux/ramips/dts/mt7621_alfa-network_ax1800rm.dts @@ -176,10 +176,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts b/target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts index 07e0d23788d7f6..6280a643a9b6b7 100644 --- a/target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts +++ b/target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts @@ -13,10 +13,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts b/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts index 48506907ebf8dc..4a5194c3639194 100644 --- a/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts +++ b/target/linux/ramips/dts/mt7621_arcadyan_we420223-99.dts @@ -203,10 +203,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &pcie { diff --git a/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi b/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi index 78627b2157ec6d..ec9da152ce32cd 100644 --- a/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi +++ b/target/linux/ramips/dts/mt7621_arcadyan_wg4xx223.dtsi @@ -185,10 +185,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi b/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi index edfdc9b173f037..2f0308268882cb 100644 --- a/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi +++ b/target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi @@ -111,10 +111,8 @@ status = "okay"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &gmac0 { diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts b/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts index 4915f8125e8380..d5b46b14eeb5cc 100644 --- a/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts +++ b/target/linux/ramips/dts/mt7621_asus_rt-ac57u-v1.dts @@ -170,10 +170,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi b/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi index 5bccddec0b6ff4..bee8afdc90f44f 100644 --- a/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi +++ b/target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi @@ -166,10 +166,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts b/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts index faf58e0187b639..76645987b23b10 100644 --- a/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts +++ b/target/linux/ramips/dts/mt7621_asus_rt-ax53u.dts @@ -183,10 +183,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts b/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts index 7bb375cb298637..972b3d5bd89a3c 100644 --- a/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts +++ b/target/linux/ramips/dts/mt7621_asus_rt-ax54.dts @@ -157,10 +157,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts b/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts index b18bd113dad9b4..d73dfe94215641 100644 --- a/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts +++ b/target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts @@ -182,10 +182,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts b/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts index 12ff04ed28d299..e2fa019d073efa 100644 --- a/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts +++ b/target/linux/ramips/dts/mt7621_beeline_smartbox-giga.dts @@ -216,10 +216,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts b/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts index 84ec15b872076d..56080ff917b609 100644 --- a/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts +++ b/target/linux/ramips/dts/mt7621_beeline_smartbox-turbo-plus.dts @@ -209,10 +209,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_belkin_rt1800.dts b/target/linux/ramips/dts/mt7621_belkin_rt1800.dts index 25fc335c56a651..be519abf6e8f73 100644 --- a/target/linux/ramips/dts/mt7621_belkin_rt1800.dts +++ b/target/linux/ramips/dts/mt7621_belkin_rt1800.dts @@ -162,10 +162,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts index c065997ea1eb19..7b1cc64b5094bc 100644 --- a/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts +++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts @@ -174,10 +174,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts index 66b47d2fa027db..fa90fba3d55759 100644 --- a/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts +++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts @@ -199,10 +199,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts b/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts index e3b165c640534f..00b21658366308 100644 --- a/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts +++ b/target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts @@ -208,10 +208,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_cudy_m1800.dts b/target/linux/ramips/dts/mt7621_cudy_m1800.dts index 12f5ce3ec92d3b..1aa58210062f28 100644 --- a/target/linux/ramips/dts/mt7621_cudy_m1800.dts +++ b/target/linux/ramips/dts/mt7621_cudy_m1800.dts @@ -66,10 +66,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &pcie { diff --git a/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts b/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts index 9d5701a7cca82d..265b48143ecaf7 100644 --- a/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts +++ b/target/linux/ramips/dts/mt7621_cudy_wr1300-v1.dts @@ -193,10 +193,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi b/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi index 55da73dcdab12b..da62648bc9e5b8 100644 --- a/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi +++ b/target/linux/ramips/dts/mt7621_cudy_wr1300-v2v3.dtsi @@ -153,10 +153,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_cudy_wr2100.dts b/target/linux/ramips/dts/mt7621_cudy_wr2100.dts index 5b21cff130567f..827855126772b4 100644 --- a/target/linux/ramips/dts/mt7621_cudy_wr2100.dts +++ b/target/linux/ramips/dts/mt7621_cudy_wr2100.dts @@ -208,10 +208,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_cudy_x6.dtsi b/target/linux/ramips/dts/mt7621_cudy_x6.dtsi index 81a34e9302eff0..0542640f13f81c 100644 --- a/target/linux/ramips/dts/mt7621_cudy_x6.dtsi +++ b/target/linux/ramips/dts/mt7621_cudy_x6.dtsi @@ -116,10 +116,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts b/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts index 90a5c196fc710f..cf924cffb6142d 100644 --- a/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts +++ b/target/linux/ramips/dts/mt7621_dlink_covr-x1860-a1.dts @@ -184,10 +184,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts index 7e5809ed3a3f01..7bc3a3f186cde5 100644 --- a/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts +++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts @@ -187,10 +187,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts index 434a6d9f1a506d..9d476749595671 100644 --- a/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts +++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts @@ -203,10 +203,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts index a3753f37d4315a..25d2768d23942f 100644 --- a/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts +++ b/target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts @@ -120,10 +120,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts b/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts index 8939e523fedbbe..589669c36a1e32 100644 --- a/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts +++ b/target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts @@ -144,10 +144,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi b/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi index 11d673dc871915..0f5b4f0d90d938 100644 --- a/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi +++ b/target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi @@ -110,10 +110,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi b/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi index 57652fb278bd25..d5adb8728cebc7 100644 --- a/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi +++ b/target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi @@ -188,10 +188,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi b/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi index d7309dbdfea768..8e7652cac7ea3e 100644 --- a/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi +++ b/target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi @@ -151,10 +151,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts b/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts index bbc135ad83a971..503ec40b50fa55 100644 --- a/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts +++ b/target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts @@ -85,10 +85,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi b/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi index 418b0cfa9a7b72..cdb94dcdc1b516 100644 --- a/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi +++ b/target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk.dtsi @@ -124,10 +124,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi b/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi index dae247f4ceaac8..4b61b9faf29f79 100644 --- a/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi +++ b/target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi @@ -94,10 +94,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_etisalat_s3.dts b/target/linux/ramips/dts/mt7621_etisalat_s3.dts index 2fb3aedaff3dda..60452a63f430a7 100644 --- a/target/linux/ramips/dts/mt7621_etisalat_s3.dts +++ b/target/linux/ramips/dts/mt7621_etisalat_s3.dts @@ -209,10 +209,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts b/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts index 9030c051f1e71b..a017baa1ba04ed 100644 --- a/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts +++ b/target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts @@ -144,10 +144,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts b/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts index 849074111be043..e4b254ebce8401 100644 --- a/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts +++ b/target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts @@ -145,10 +145,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts b/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts index 7ef7201faf7a5a..2710aa6f3edbce 100644 --- a/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts +++ b/target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts @@ -116,10 +116,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi b/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi index 88148c6759a2d2..1520aaf5b10da8 100644 --- a/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi +++ b/target/linux/ramips/dts/mt7621_h3c_tx180x.dtsi @@ -58,10 +58,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &nand { diff --git a/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi b/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi index 53c59123979d52..dd7b72707e10ea 100644 --- a/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi +++ b/target/linux/ramips/dts/mt7621_haier-sim_wr1800k.dtsi @@ -73,10 +73,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &nand { diff --git a/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts b/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts index cae9f717b1eaf0..195a12b7d16c24 100644 --- a/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts +++ b/target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts @@ -77,10 +77,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts b/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts index 1bf66401378678..5a8f32d7236fe6 100644 --- a/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts +++ b/target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts @@ -153,10 +153,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts b/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts index a7610070de21c3..e7641394516985 100644 --- a/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts +++ b/target/linux/ramips/dts/mt7621_huasifei_ws1208v2.dts @@ -169,10 +169,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_humax_e10.dts b/target/linux/ramips/dts/mt7621_humax_e10.dts index dfa91ad43a72e3..39eac32d538f4e 100644 --- a/target/linux/ramips/dts/mt7621_humax_e10.dts +++ b/target/linux/ramips/dts/mt7621_humax_e10.dts @@ -169,10 +169,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts index 4f84302417622c..9e64077e0ce3a9 100644 --- a/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts +++ b/target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts @@ -174,10 +174,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts index 4543f45a9fee40..86d8a93da614fe 100644 --- a/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts +++ b/target/linux/ramips/dts/mt7621_iodata_wn-deax1800gr.dts @@ -186,10 +186,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts index 9de7297405d9e6..bcb7e576786d0e 100644 --- a/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts +++ b/target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts @@ -170,10 +170,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts b/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts index b055afc3adb927..519c52065be442 100644 --- a/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts +++ b/target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts @@ -160,10 +160,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi b/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi index b3063a333edc19..07187d8bfed213 100644 --- a/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi +++ b/target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi @@ -161,10 +161,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts b/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts index 790668cc410d64..e322e4efdbb387 100644 --- a/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts +++ b/target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts @@ -153,10 +153,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts b/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts index e8c7f12d01efa1..bfb62071994064 100644 --- a/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts +++ b/target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts @@ -130,10 +130,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts b/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts index 6990d31e391903..7c46635fb5e7b9 100644 --- a/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts +++ b/target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts @@ -134,10 +134,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iptime_a3004t.dts b/target/linux/ramips/dts/mt7621_iptime_a3004t.dts index a96e89b3f30daf..7b2465c14fa52f 100644 --- a/target/linux/ramips/dts/mt7621_iptime_a3004t.dts +++ b/target/linux/ramips/dts/mt7621_iptime_a3004t.dts @@ -135,10 +135,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi b/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi index 848891056a3181..6bfdffefb7c8e9 100644 --- a/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi +++ b/target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi @@ -152,10 +152,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iptime_a8004t.dts b/target/linux/ramips/dts/mt7621_iptime_a8004t.dts index 249904da6a37e6..7f28d7af3fb5f8 100644 --- a/target/linux/ramips/dts/mt7621_iptime_a8004t.dts +++ b/target/linux/ramips/dts/mt7621_iptime_a8004t.dts @@ -138,10 +138,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts b/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts index 88067a4fa5476c..8263c062dd5378 100644 --- a/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts +++ b/target/linux/ramips/dts/mt7621_iptime_ax2004m.dts @@ -148,10 +148,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_iptime_t5004.dts b/target/linux/ramips/dts/mt7621_iptime_t5004.dts index f7a5e8ca17bf5f..4a7f9aaaa1b841 100644 --- a/target/linux/ramips/dts/mt7621_iptime_t5004.dts +++ b/target/linux/ramips/dts/mt7621_iptime_t5004.dts @@ -91,10 +91,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts b/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts index 05980caa6f448f..548ab7ba599f37 100644 --- a/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts +++ b/target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts @@ -168,10 +168,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_jcg_q20.dts b/target/linux/ramips/dts/mt7621_jcg_q20.dts index 49f51ded7fb28a..a8892ac8b1a4b2 100644 --- a/target/linux/ramips/dts/mt7621_jcg_q20.dts +++ b/target/linux/ramips/dts/mt7621_jcg_q20.dts @@ -180,10 +180,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_jcg_y2.dts b/target/linux/ramips/dts/mt7621_jcg_y2.dts index 54141cc2a29256..5012bc3d62f561 100644 --- a/target/linux/ramips/dts/mt7621_jcg_y2.dts +++ b/target/linux/ramips/dts/mt7621_jcg_y2.dts @@ -121,10 +121,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts b/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts index 35d09832f2b857..6ee20c29c5fb0a 100644 --- a/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts +++ b/target/linux/ramips/dts/mt7621_keenetic_kn-3010.dts @@ -201,10 +201,8 @@ }; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &gmac0 { diff --git a/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts b/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts index 03237699901b1f..3b6026f3771181 100644 --- a/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts +++ b/target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts @@ -179,10 +179,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_linksys_e5600.dts b/target/linux/ramips/dts/mt7621_linksys_e5600.dts index a059fd0698ac1f..08fcbbc5154811 100644 --- a/target/linux/ramips/dts/mt7621_linksys_e5600.dts +++ b/target/linux/ramips/dts/mt7621_linksys_e5600.dts @@ -175,10 +175,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_linksys_e7350.dts b/target/linux/ramips/dts/mt7621_linksys_e7350.dts index 77c123720fe17f..db7387ddec760f 100644 --- a/target/linux/ramips/dts/mt7621_linksys_e7350.dts +++ b/target/linux/ramips/dts/mt7621_linksys_e7350.dts @@ -156,10 +156,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts b/target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts index 35a90ea07059f6..83c86ee11dbb62 100644 --- a/target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts +++ b/target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts @@ -16,14 +16,12 @@ phy-handle = <ðphy4>; }; -&mdio { - ethernet-phy@0 { - status = "disabled"; - }; +ðphy0 { + interrupts = <0>; +}; - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi b/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi index 5804f215918ac0..70cf425b2c3304 100644 --- a/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi +++ b/target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi @@ -203,10 +203,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_linksys_re6500.dts b/target/linux/ramips/dts/mt7621_linksys_re6500.dts index d269899980976e..3c026a41a5d52f 100644 --- a/target/linux/ramips/dts/mt7621_linksys_re6500.dts +++ b/target/linux/ramips/dts/mt7621_linksys_re6500.dts @@ -148,10 +148,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts b/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts index aaa75b057320da..c6fa3622efa01d 100644 --- a/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts +++ b/target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts @@ -138,10 +138,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts b/target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts index 2da7f983a93088..ecce30330b00da 100644 --- a/target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts +++ b/target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts @@ -45,10 +45,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_meig_slt866.dts b/target/linux/ramips/dts/mt7621_meig_slt866.dts index d364a917942eb5..d4e040649e7547 100644 --- a/target/linux/ramips/dts/mt7621_meig_slt866.dts +++ b/target/linux/ramips/dts/mt7621_meig_slt866.dts @@ -185,11 +185,6 @@ }; }; -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; -}; - &gmac0 { nvmem-cells = <&macaddr_custom_40 0>; nvmem-cell-names = "mac-address"; @@ -204,10 +199,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts b/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts index fb14bd7829fb08..145b0eeb40d353 100644 --- a/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts +++ b/target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts @@ -145,10 +145,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts b/target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts index aad8a6776d29ed..faa4e53f097ca9 100644 --- a/target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts +++ b/target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts @@ -42,10 +42,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts b/target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts index 223d03b9fd12dd..11171d9535b22e 100644 --- a/target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts +++ b/target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts @@ -96,10 +96,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi index 6e225c0825c0b1..f8dc6ebdbffcc7 100644 --- a/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi +++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi @@ -118,10 +118,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi index 61c3ec37613d02..c125bcc4e3415a 100644 --- a/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi +++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi @@ -184,10 +184,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi b/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi index 13ce338588bb92..273bb9469ced7d 100644 --- a/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi +++ b/target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi @@ -115,10 +115,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_netgear_wac104.dts b/target/linux/ramips/dts/mt7621_netgear_wac104.dts index 9c706530d4b4b2..01583e88874548 100644 --- a/target/linux/ramips/dts/mt7621_netgear_wac104.dts +++ b/target/linux/ramips/dts/mt7621_netgear_wac104.dts @@ -170,10 +170,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_netgear_wax202.dts b/target/linux/ramips/dts/mt7621_netgear_wax202.dts index bf580de6b88f9e..226c46154326a7 100644 --- a/target/linux/ramips/dts/mt7621_netgear_wax202.dts +++ b/target/linux/ramips/dts/mt7621_netgear_wax202.dts @@ -244,10 +244,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_netis_wf2881.dts b/target/linux/ramips/dts/mt7621_netis_wf2881.dts index 58d2c70655ca5b..0baf9d648304de 100644 --- a/target/linux/ramips/dts/mt7621_netis_wf2881.dts +++ b/target/linux/ramips/dts/mt7621_netis_wf2881.dts @@ -162,10 +162,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_oraybox_x3a.dts b/target/linux/ramips/dts/mt7621_oraybox_x3a.dts index 7b33efd6e66a66..b9bccf0f2836fe 100644 --- a/target/linux/ramips/dts/mt7621_oraybox_x3a.dts +++ b/target/linux/ramips/dts/mt7621_oraybox_x3a.dts @@ -156,10 +156,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_phicomm_k2p.dts b/target/linux/ramips/dts/mt7621_phicomm_k2p.dts index 6a733698d2a113..92c76d42065b26 100644 --- a/target/linux/ramips/dts/mt7621_phicomm_k2p.dts +++ b/target/linux/ramips/dts/mt7621_phicomm_k2p.dts @@ -146,10 +146,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_planex_vr500.dts b/target/linux/ramips/dts/mt7621_planex_vr500.dts index 4d281670ef9e84..df12331e247c94 100644 --- a/target/linux/ramips/dts/mt7621_planex_vr500.dts +++ b/target/linux/ramips/dts/mt7621_planex_vr500.dts @@ -104,10 +104,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts b/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts index 98a2ffad5f7f17..f4d893a3668acd 100644 --- a/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts +++ b/target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts @@ -163,10 +163,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts b/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts index b3aaffeafed1c6..b567b14f8e9403 100644 --- a/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts +++ b/target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts @@ -140,10 +140,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_rostelecom_rt-fe-1a.dts b/target/linux/ramips/dts/mt7621_rostelecom_rt-fe-1a.dts index 8afe5f54859605..1c2cb42fa0d6d7 100644 --- a/target/linux/ramips/dts/mt7621_rostelecom_rt-fe-1a.dts +++ b/target/linux/ramips/dts/mt7621_rostelecom_rt-fe-1a.dts @@ -228,10 +228,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts b/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts index 5afed4c695608b..b5818a7e6049a6 100644 --- a/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts +++ b/target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts @@ -146,10 +146,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi b/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi index fd952cbc931fd6..b13b621d2f21a8 100644 --- a/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi +++ b/target/linux/ramips/dts/mt7621_sercomm_dxx_nand_256m.dtsi @@ -208,10 +208,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts index 6ea2c199e310a9..b287056bf114b3 100644 --- a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts +++ b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me1.dts @@ -90,10 +90,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &pcie { diff --git a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts index 3b474819e1630a..cd0e7465ff2ab4 100644 --- a/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts +++ b/target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-lite.dts @@ -112,10 +112,8 @@ status = "okay"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &gmac0 { diff --git a/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts b/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts index 3448db5f03d5a4..4497531aee07ab 100644 --- a/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts +++ b/target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts @@ -154,10 +154,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts b/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts index d1310ad95499d8..42e39c3152245a 100644 --- a/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts +++ b/target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts @@ -125,10 +125,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_totolink_a7000r.dts b/target/linux/ramips/dts/mt7621_totolink_a7000r.dts index 8c0062973d4703..e4937c55c5e22e 100644 --- a/target/linux/ramips/dts/mt7621_totolink_a7000r.dts +++ b/target/linux/ramips/dts/mt7621_totolink_a7000r.dts @@ -135,10 +135,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_totolink_x5000r.dts b/target/linux/ramips/dts/mt7621_totolink_x5000r.dts index 24606904e14d26..e2d706c5db12da 100644 --- a/target/linux/ramips/dts/mt7621_totolink_x5000r.dts +++ b/target/linux/ramips/dts/mt7621_totolink_x5000r.dts @@ -130,10 +130,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts b/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts index 71ef4bc6b6155e..ac03545eca8093 100644 --- a/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts +++ b/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts @@ -181,10 +181,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts b/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts index e9879128a30bae..b1a3e3e1bced0f 100644 --- a/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts +++ b/target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts @@ -206,10 +206,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts b/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts index d814cba261e167..bc56b82cd11cad 100644 --- a/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts +++ b/target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts @@ -189,10 +189,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts b/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts index 2aea6bbbc00760..2694b3890fe1bf 100644 --- a/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts +++ b/target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts @@ -182,10 +182,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts b/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts index 6203308515f3b7..02560669d5eb11 100644 --- a/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts +++ b/target/linux/ramips/dts/mt7621_tplink_ec330-g5u-v1.dts @@ -283,10 +283,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts b/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts index 33070ef6cafcb3..b71b7ad914b9fc 100644 --- a/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts +++ b/target/linux/ramips/dts/mt7621_tplink_er605-v2.dts @@ -155,11 +155,8 @@ }; }; - -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &state_default { diff --git a/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts b/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts index c501727ca837d4..d6f9a368e4fb62 100644 --- a/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts +++ b/target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts @@ -219,10 +219,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts b/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts index db460b43b2a1b2..234202ba87a821 100644 --- a/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts +++ b/target/linux/ramips/dts/mt7621_tplink_mr600-v2-eu.dts @@ -198,13 +198,10 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; - &switch0 { ports { port@1 { diff --git a/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts b/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts index 4665f04f023764..80467c88e98343 100644 --- a/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts +++ b/target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts @@ -14,10 +14,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts b/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts index 0d6d50022292f1..f2fb48cac2b2cb 100644 --- a/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts +++ b/target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts @@ -73,10 +73,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi b/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi index b193aed1034dac..77c06545e860e1 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi @@ -64,10 +64,8 @@ phy-handle = <ðphy0>; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi b/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi index 42f6cea2d3c0e2..79deb7559da8ab 100644 --- a/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi +++ b/target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi @@ -81,10 +81,8 @@ phy-handle = <ðphy4>; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts b/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts index 05d8e4a5aebdd7..7080dad145f0b6 100644 --- a/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts +++ b/target/linux/ramips/dts/mt7621_wavlink_wl-wn573hx1.dts @@ -47,12 +47,6 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; -}; - &pcie { status = "okay"; }; @@ -119,17 +113,6 @@ }; }; -&gmac0 { - nvmem-cells = <&macaddr_factory_3fff4>; - nvmem-cell-names = "mac-address"; -}; - -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; -}; - &switch0 { ports { port@3 { diff --git a/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts b/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts index f9e37bee6e0f65..78bc0ba4b0f2d3 100644 --- a/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts +++ b/target/linux/ramips/dts/mt7621_wavlink_ws-wn572hp3-4g.dts @@ -166,10 +166,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts index f0c7646b26030b..96054135ae0a8e 100644 --- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts +++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts @@ -224,10 +224,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts index 1dfded14b1dd5c..3b377fca7c4b39 100644 --- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts +++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts @@ -85,10 +85,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi index 61359e8b21b120..2d2bf3d6992f8e 100644 --- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi +++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi @@ -47,10 +47,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi index ef637278afb5fd..598fafe871b782 100644 --- a/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi +++ b/target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi @@ -173,10 +173,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi b/target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi index 468f9456bfff5c..e0950e7c6488a0 100644 --- a/target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi +++ b/target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi @@ -45,10 +45,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts b/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts index f1227552e881a4..e04afc81bab6b9 100644 --- a/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts +++ b/target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts @@ -111,10 +111,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts b/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts index c47e34a5d69c84..6475c142e7c5ff 100644 --- a/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts +++ b/target/linux/ramips/dts/mt7621_youhua_wr1200js.dts @@ -165,10 +165,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_youku_yk-l2.dts b/target/linux/ramips/dts/mt7621_youku_yk-l2.dts index 9f4e8cf1ce4f1b..9d2491f6348743 100644 --- a/target/linux/ramips/dts/mt7621_youku_yk-l2.dts +++ b/target/linux/ramips/dts/mt7621_youku_yk-l2.dts @@ -175,10 +175,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_yuncore_ax820.dts b/target/linux/ramips/dts/mt7621_yuncore_ax820.dts index 0cdad1bfe5f32a..316c1800983ab3 100644 --- a/target/linux/ramips/dts/mt7621_yuncore_ax820.dts +++ b/target/linux/ramips/dts/mt7621_yuncore_ax820.dts @@ -174,10 +174,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_yuncore_fap640.dts b/target/linux/ramips/dts/mt7621_yuncore_fap640.dts index 2cc3435a894e30..536b45e03f359b 100644 --- a/target/linux/ramips/dts/mt7621_yuncore_fap640.dts +++ b/target/linux/ramips/dts/mt7621_yuncore_fap640.dts @@ -189,13 +189,10 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; - &switch0 { gpio-controller; #gpio-cells = <2>; diff --git a/target/linux/ramips/dts/mt7621_yuncore_g720.dts b/target/linux/ramips/dts/mt7621_yuncore_g720.dts index 4b88064b4950ac..2170bc83ec17e3 100644 --- a/target/linux/ramips/dts/mt7621_yuncore_g720.dts +++ b/target/linux/ramips/dts/mt7621_yuncore_g720.dts @@ -137,10 +137,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_z-router_zr-2660.dts b/target/linux/ramips/dts/mt7621_z-router_zr-2660.dts index 34b151be75de25..3acc1529e5dbb0 100644 --- a/target/linux/ramips/dts/mt7621_z-router_zr-2660.dts +++ b/target/linux/ramips/dts/mt7621_z-router_zr-2660.dts @@ -93,10 +93,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &nand { diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts index e15c676c8aefd3..7dfe9a769918da 100644 --- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts +++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts @@ -109,10 +109,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts index dfa49a2bc5f6bf..31a4e4482abb47 100644 --- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts +++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts @@ -133,10 +133,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi index bbf121036c2147..c3712fea7b910f 100644 --- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi +++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-v04.dtsi @@ -187,10 +187,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi index b0182ee8961a41..dcad7b26d23b38 100644 --- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi +++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi @@ -186,10 +186,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi index 321274bb15ccfe..fc8a91e39862a6 100644 --- a/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi +++ b/target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi @@ -156,10 +156,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy4: ethernet-phy@4 { - reg = <4>; - }; +ðphy4 { + /delete-property/ interrupts; }; &switch0 { diff --git a/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts b/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts index b82a8669b3f39c..6bf65a02184800 100644 --- a/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts +++ b/target/linux/ramips/dts/mt7621_zyxel_wsm20.dts @@ -193,10 +193,8 @@ nvmem-cell-names = "mac-address"; }; -&mdio { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; +ðphy0 { + /delete-property/ interrupts; }; &pcie { diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c index ca3b6fb302e687..5d4cebb089684e 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c @@ -199,20 +199,12 @@ static void fe_get_ethtool_stats(struct net_device *dev, do { data_src = &hwstats->tx_bytes; data_dst = data; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0) start = u64_stats_fetch_begin(&hwstats->syncp); -#else - start = u64_stats_fetch_begin_irq(&hwstats->syncp); -#endif for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++) *data_dst++ = *data_src++; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0) } while (u64_stats_fetch_retry(&hwstats->syncp, start)); -#else - } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); -#endif } static struct ethtool_ops fe_ethtool_ops = { diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c index 4365e398d3fce9..c8afa4e3bb8f9f 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c @@ -487,11 +487,7 @@ static void fe_get_stats64(struct net_device *dev, } do { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0) start = u64_stats_fetch_begin(&hwstats->syncp); -#else - start = u64_stats_fetch_begin_irq(&hwstats->syncp); -#endif storage->rx_packets = hwstats->rx_packets; storage->tx_packets = hwstats->tx_packets; storage->rx_bytes = hwstats->rx_bytes; @@ -503,11 +499,7 @@ static void fe_get_stats64(struct net_device *dev, storage->rx_crc_errors = hwstats->rx_fcs_errors; storage->rx_errors = hwstats->rx_checksum_errors; storage->tx_aborted_errors = hwstats->tx_skip; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0) } while (u64_stats_fetch_retry(&hwstats->syncp, start)); -#else - } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); -#endif storage->tx_errors = priv->netdev->stats.tx_errors; storage->rx_dropped = priv->netdev->stats.rx_dropped; diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h index 364dd54a58f121..151caae1dcc3ae 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h @@ -21,7 +21,6 @@ #include #include #include -#include enum fe_reg { FE_REG_PDMA_GLO_CFG = 0, diff --git a/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c b/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c index a429bb82a3a081..8b642e28b19abe 100644 --- a/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c +++ b/target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -810,11 +809,7 @@ static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins) gpiochip->set_multiple = aw9523_gpio_set_multiple; gpiochip->set_config = gpiochip_generic_config; gpiochip->parent = dev; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0) gpiochip->fwnode = dev->fwnode; -#else - gpiochip->of_node = dev->of_node; -#endif gpiochip->owner = THIS_MODULE; gpiochip->can_sleep = true; @@ -988,12 +983,7 @@ static int aw9523_hw_init(struct aw9523 *awi) return regmap_reinit_cache(awi->regmap, &aw9523_regmap); } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0) static int aw9523_probe(struct i2c_client *client) -#else -static int aw9523_probe(struct i2c_client *client, - const struct i2c_device_id *id) -#endif { struct device *dev = &client->dev; struct pinctrl_desc *pdesc; diff --git a/target/linux/ramips/mt7620/config-6.1 b/target/linux/ramips/mt7620/config-6.1 deleted file mode 100644 index 111a59ab00f76a..00000000000000 --- a/target/linux/ramips/mt7620/config-6.1 +++ /dev/null @@ -1,215 +0,0 @@ -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_MTMIPS=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_MT7620A_EVAL is not set -# CONFIG_DTB_OMEGA2P is not set -CONFIG_DTB_RT_NONE=y -# CONFIG_DTB_VOCORE2 is not set -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_CDEV=y -# CONFIG_GPIO_MT7621 is not set -CONFIG_GPIO_RALINK=y -CONFIG_GPIO_WATCHDOG=y -# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_ICPLUS_PHY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MT7621_WDT is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_JIMAGE_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_GSW_MT7620=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_MT7620=y -CONFIG_NET_RALINK_MT7620=y -# CONFIG_NET_RALINK_RT3050 is not set -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_SELFTESTS=y -# CONFIG_NET_VENDOR_MEDIATEK is not set -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -# CONFIG_PHY_MT7621_PCI is not set -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_MT7620=y -CONFIG_PINCTRL_RALINK=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZBOOT_LOAD_ADDRESS=0x0 diff --git a/target/linux/ramips/mt7621/config-6.1 b/target/linux/ramips/mt7621/config-6.1 deleted file mode 100644 index 8f2355c56494b7..00000000000000 --- a/target/linux/ramips/mt7621/config-6.1 +++ /dev/null @@ -1,312 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOARD_SCACHE=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CEVT_R4K=y -CONFIG_CLKSRC_MIPS_GIC=y -CONFIG_CLK_MT7621=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DIMLIB=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MT7621=y -# CONFIG_GPIO_RALINK is not set -CONFIG_GPIO_WATCHDOG=y -# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set -CONFIG_GRO_CELLS=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_MT7621=y -CONFIG_ICPLUS_PHY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LED_TRIGGER_PHY=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIKROTIK=y -CONFIG_MIKROTIK_RB_SYSFS=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -CONFIG_MIPS_CM=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_CPC=y -CONFIG_MIPS_CPS=y -# CONFIG_MIPS_CPS_NS16550_BOOL is not set -CONFIG_MIPS_CPU_SCACHE=y -CONFIG_MIPS_GIC=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_NR_CPU_NR_MAP=4 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MT7621_WDT=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MT7621=y -CONFIG_MTD_NAND_MTK_BMT=y -# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_ROUTERBOOT_PARTS=y -CONFIG_MTD_SERCOMM_PARTS=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_MINOR_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_TRX_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_RALINK is not set -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -CONFIG_PCI=y -CONFIG_PCIE_MT7621=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_DRIVERS_GENERIC=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -CONFIG_PHYLINK=y -CONFIG_PHY_MT7621_PCI=y -# CONFIG_PHY_RALINK_USB is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AW9523=y -CONFIG_PINCTRL_MT7621=y -CONFIG_PINCTRL_RALINK=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_SX150X=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_QCOM_NET_PHYLIB=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RALINK=y -# CONFIG_RALINK_WDT is not set -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BQ32K=y -CONFIG_RTC_DRV_PCF8563=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_SCHED_CORE is not set -CONFIG_SCHED_SMT=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -# CONFIG_SOC_MT7620 is not set -CONFIG_SOC_MT7621=y -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT7621=y -# CONFIG_SPI_RT2880 is not set -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYNC_R4K=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MIPS_CPS=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WEAK_ORDERING=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZBOOT_LOAD_ADDRESS=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/ramips/mt76x8/config-6.1 b/target/linux/ramips/mt76x8/config-6.1 deleted file mode 100644 index be779b03d80a69..00000000000000 --- a/target/linux/ramips/mt76x8/config-6.1 +++ /dev/null @@ -1,215 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_MTMIPS=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_MT7620A_EVAL is not set -# CONFIG_DTB_OMEGA2P is not set -CONFIG_DTB_RT_NONE=y -# CONFIG_DTB_VOCORE2 is not set -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MT7621=y -# CONFIG_GPIO_RALINK is not set -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_ICPLUS_PHY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MT7621_WDT=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_ESW_RT3050=y -# CONFIG_NET_RALINK_MT7620 is not set -CONFIG_NET_RALINK_RT3050=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_SELFTESTS=y -# CONFIG_NET_VENDOR_MEDIATEK is not set -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -# CONFIG_PHY_MT7621_PCI is not set -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_MT7620=y -CONFIG_PINCTRL_RALINK=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_RALINK=y -# CONFIG_RALINK_WDT is not set -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT7621=y -# CONFIG_SPI_RT2880 is not set -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZBOOT_LOAD_ADDRESS=0x0 diff --git a/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch b/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch deleted file mode 100644 index 4574f7977fa49b..00000000000000 --- a/target/linux/ramips/patches-6.1/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 35dcae535afc153fa83f2fe51c0812536c192c58 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 6 Feb 2023 09:33:05 +0100 -Subject: [PATCH] clk: ralink: fix 'mt7621_gate_is_enabled()' function - -Compiling clock driver with CONFIG_UBSAN enabled shows the following trace: - -UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15 -shift exponent 131072 is too large for 32-bit type 'long unsigned int' -CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0 -Stack : ... - -Call Trace: -[<80009a58>] show_stack+0x38/0x118 -[<8045ce04>] dump_stack_lvl+0x60/0x80 -[<80458868>] ubsan_epilogue+0x10/0x54 -[<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190 -[<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0 -[<804bb774>] clk_core_is_enabled+0x34/0x90 -[<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4 -[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4 -[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4 -[<80aad900>] clk_disable_unused+0x78/0x120 -[<80002030>] do_one_initcall+0x54/0x1f0 -[<80a922a4>] kernel_init_freeable+0x280/0x31c -[<808047c4>] kernel_init+0x20/0x118 -[<80003e58>] ret_from_kernel_thread+0x14/0x1c - -Shifting a value (131032) larger than the type (32 bit unsigned integer) -is undefined behaviour in C. - -The problem is in 'mt7621_gate_is_enabled()' function which is using the -'BIT()' kernel macro with the bit index for the clock gate to check if the -bit is set. When the clock gates structure is created driver is already -setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra -'BIT()' mask here. Removing it solve the problem and makes this function -correct. However when clock gating is correctly working, the kernel starts -disabling those clocks that are not requested. Some drivers for this SoC -are older than this clock driver itself. So to avoid the kernel to disable -clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL' -flag on gates initialization code. - -Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC") -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/ralink/clk-mt7621.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - ---- a/drivers/clk/ralink/clk-mt7621.c -+++ b/drivers/clk/ralink/clk-mt7621.c -@@ -121,7 +121,7 @@ static int mt7621_gate_is_enabled(struct - if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val)) - return 0; - -- return val & BIT(clk_gate->bit_idx); -+ return val & clk_gate->bit_idx; - } - - static const struct clk_ops mt7621_gate_ops = { -@@ -133,8 +133,14 @@ static const struct clk_ops mt7621_gate_ - static int mt7621_gate_ops_init(struct device *dev, - struct mt7621_gate *sclk) - { -+ /* -+ * There are drivers for this SoC that are older -+ * than clock driver and are not prepared for the clock. -+ * We don't want the kernel to disable anything so we -+ * add CLK_IS_CRITICAL flag here. -+ */ - struct clk_init_data init = { -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, - .num_parents = 1, - .parent_names = &sclk->parent_name, - .ops = &mt7621_gate_ops, diff --git a/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch b/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch deleted file mode 100644 index 94784f7885d82f..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-01-dt-bindings-clock-add-mtmips-SoCs-system-controller.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 612616e6381929e7f9e303f8b8ad3655cc101516 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:33 +0200 -Subject: [PATCH 1/9] dt-bindings: clock: add mtmips SoCs system controller - -Adds device tree binding documentation for system controller node present -in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider -for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350, -RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs. - -Reviewed-by: Rob Herring -Acked-by: Stephen Boyd -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - .../bindings/clock/mediatek,mtmips-sysc.yaml | 64 ++++++++++++++++++++++ - 1 file changed, 64 insertions(+) - create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml -@@ -0,0 +1,64 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MTMIPS SoCs System Controller -+ -+maintainers: -+ - Sergio Paracuellos -+ -+description: | -+ MediaTek MIPS and Ralink SoCs provides a system controller to allow -+ to access to system control registers. These registers include clock -+ and reset related ones so this node is both clock and reset provider -+ for the rest of the world. -+ -+ These SoCs have an XTAL from where the cpu clock is -+ provided as well as derived clocks for the bus and the peripherals. -+ -+properties: -+ compatible: -+ items: -+ - enum: -+ - ralink,mt7620-sysc -+ - ralink,mt7628-sysc -+ - ralink,mt7688-sysc -+ - ralink,rt2880-sysc -+ - ralink,rt3050-sysc -+ - ralink,rt3052-sysc -+ - ralink,rt3352-sysc -+ - ralink,rt3883-sysc -+ - ralink,rt5350-sysc -+ - const: syscon -+ -+ reg: -+ maxItems: 1 -+ -+ '#clock-cells': -+ description: -+ The first cell indicates the clock number. -+ const: 1 -+ -+ '#reset-cells': -+ description: -+ The first cell indicates the reset bit within the register. -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - '#clock-cells' -+ - '#reset-cells' -+ -+additionalProperties: false -+ -+examples: -+ - | -+ syscon@0 { -+ compatible = "ralink,rt5350-sysc", "syscon"; -+ reg = <0x0 0x100>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; diff --git a/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch b/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch deleted file mode 100644 index cef39978e0380f..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch +++ /dev/null @@ -1,1221 +0,0 @@ -From 6f3b15586eef736831abe6a14f2a6906bc0dc074 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:34 +0200 -Subject: [PATCH 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs - -Until now, clock related code for old ralink SoCs was based in fixed clocks -using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code -and not using device tree at all for their definition. Including this driver -is an effort to be able to define proper clocks using device tree and also -cleaning all the clock and reset related code from 'arch/mips/ralink' dir. -This clock and reset driver covers all the ralink SoCs but MT7621 which is -the newest and provides gating and some differences that make it different -from its predecesors. It has its own driver since some time ago. The ralink -SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883, -RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has -been extracted from 'arch/mips/ralink' and cleanly put using kernel clock -driver APIs. The clock plans for this SoCs only talks about relation between -CPU frequency and BUS frequency. This relation is different depending on the -particular SoC. CPU clock is derived from XTAL frequencies. - -Depending on the SoC we have the following frequencies: -* RT2880 SoC: - - XTAL: 40 MHz. - - CPU: 250, 266, 280 or 300 MHz. - - BUS: CPU / 2 MHz. -* RT3050, RT3052, RT3350: - - XTAL: 40 MHz. - - CPU: 320 or 384 MHz. - - BUS: CPU / 3 MHz. -* RT3352: - - XTAL: 40 MHz. - - CPU: 384 or 400 MHz. - - BUS: CPU / 3 MHz. - - PERIPH: 40 MHz. -* RT3383: - - XTAL: 40 MHz. - - CPU: 250, 384, 480 or 500 MHz. - - BUS: Depends on RAM Type and CPU: - + RAM DDR2: 125. ELSE 83 MHz. - + RAM DDR2: 128. ELSE 96 MHz. - + RAM DDR2: 160. ELSE 120 MHz. - + RAM DDR2: 166. ELSE 125 MHz. -* RT5350: - - XTAL: 40 MHz. - - CPU: 300, 320 or 360 MHz. - - BUS: CPU / 3, CPU / 4, CPU / 3 MHz. - - PERIPH: 40 MHz. -* MT7628 and MT7688: - - XTAL: 20 MHz or 40 MHz. - - CPU: 575 or 580 MHz. - - BUS: CPU / 3. - - PCMI2S: 480 MHz. - - PERIPH: 40 MHz. -* MT7620: - - XTAL: 20 MHz or 40 MHz. - - PLL: XTAL, 480, 600 MHz. - - CPU: depends on PLL and some mult and dividers. - - BUS: depends on PLL and some mult and dividers. - - PERIPH: 40 or XTAL MHz. - -MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of -register reads and predividers. To derive CPU and BUS frequencies in the -MT7620 SoC 'mt7620_calc_rate()' helper is used. - -In the case XTAL can have different frequencies and we need a different -clock frequency for peripherals 'periph' clock in introduced. - -The rest of the peripherals present in the SoC just follow their parent -frequencies. - -With this information the clk driver will provide all the clock and reset -functionality from a set of hardcoded clocks allowing to define a nice -device tree without fixed clocks. - -Acked-by: Stephen Boyd -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - drivers/clk/ralink/Kconfig | 7 + - drivers/clk/ralink/Makefile | 1 + - drivers/clk/ralink/clk-mtmips.c | 1115 +++++++++++++++++++++++++++++++++++++++ - 3 files changed, 1123 insertions(+) - create mode 100644 drivers/clk/ralink/clk-mtmips.c - ---- a/drivers/clk/ralink/Kconfig -+++ b/drivers/clk/ralink/Kconfig -@@ -9,3 +9,10 @@ config CLK_MT7621 - select MFD_SYSCON - help - This driver supports MediaTek MT7621 basic clocks. -+ -+config CLK_MTMIPS -+ bool "Clock driver for MTMIPS SoCs" -+ depends on SOC_RT305X || SOC_RT288X || SOC_RT3883 || SOC_MT7620 || COMPILE_TEST -+ select MFD_SYSCON -+ help -+ This driver supports MTMIPS basic clocks. ---- a/drivers/clk/ralink/Makefile -+++ b/drivers/clk/ralink/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o -+obj-$(CONFIG_CLK_MTMIPS) += clk-mtmips.o ---- /dev/null -+++ b/drivers/clk/ralink/clk-mtmips.c -@@ -0,0 +1,1115 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * MTMIPS SoCs Clock Driver -+ * Author: Sergio Paracuellos -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Configuration registers */ -+#define SYSC_REG_SYSTEM_CONFIG 0x10 -+#define SYSC_REG_CLKCFG0 0x2c -+#define SYSC_REG_RESET_CTRL 0x34 -+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c -+#define SYSC_REG_CPLL_CONFIG0 0x54 -+#define SYSC_REG_CPLL_CONFIG1 0x58 -+ -+/* RT2880 SoC */ -+#define RT2880_CONFIG_CPUCLK_SHIFT 20 -+#define RT2880_CONFIG_CPUCLK_MASK 0x3 -+#define RT2880_CONFIG_CPUCLK_250 0x0 -+#define RT2880_CONFIG_CPUCLK_266 0x1 -+#define RT2880_CONFIG_CPUCLK_280 0x2 -+#define RT2880_CONFIG_CPUCLK_300 0x3 -+ -+/* RT305X SoC */ -+#define RT305X_SYSCFG_CPUCLK_SHIFT 18 -+#define RT305X_SYSCFG_CPUCLK_MASK 0x1 -+#define RT305X_SYSCFG_CPUCLK_LOW 0x0 -+#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 -+ -+/* RT3352 SoC */ -+#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 -+#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 -+#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 -+#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 -+ -+/* RT3383 SoC */ -+#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) -+#define RT3883_SYSCFG0_CPUCLK_SHIFT 8 -+#define RT3883_SYSCFG0_CPUCLK_MASK 0x3 -+#define RT3883_SYSCFG0_CPUCLK_250 0x0 -+#define RT3883_SYSCFG0_CPUCLK_384 0x1 -+#define RT3883_SYSCFG0_CPUCLK_480 0x2 -+#define RT3883_SYSCFG0_CPUCLK_500 0x3 -+ -+/* RT5350 SoC */ -+#define RT5350_CLKCFG0_XTAL_SEL BIT(20) -+#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 -+#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 -+#define RT5350_SYSCFG0_CPUCLK_360 0x0 -+#define RT5350_SYSCFG0_CPUCLK_320 0x2 -+#define RT5350_SYSCFG0_CPUCLK_300 0x3 -+ -+/* MT7620 and MT76x8 SoCs */ -+#define MT7620_XTAL_FREQ_SEL BIT(6) -+#define CPLL_CFG0_SW_CFG BIT(31) -+#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 -+#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 -+#define CPLL_CFG0_LC_CURFCK BIT(15) -+#define CPLL_CFG0_BYPASS_REF_CLK BIT(14) -+#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 -+#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 -+#define CPLL_CFG1_CPU_AUX1 BIT(25) -+#define CPLL_CFG1_CPU_AUX0 BIT(24) -+#define CLKCFG0_PERI_CLK_SEL BIT(4) -+#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 -+#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf -+#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ -+#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ -+#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ -+#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ -+#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ -+#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ -+#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ -+#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ -+#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ -+#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 -+#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f -+#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 -+#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f -+ -+/* clock scaling */ -+#define CLKCFG_FDIV_MASK 0x1f00 -+#define CLKCFG_FDIV_USB_VAL 0x0300 -+#define CLKCFG_FFRAC_MASK 0x001f -+#define CLKCFG_FFRAC_USB_VAL 0x0003 -+ -+struct mtmips_clk; -+struct mtmips_clk_fixed; -+struct mtmips_clk_factor; -+ -+struct mtmips_clk_data { -+ struct mtmips_clk *clk_base; -+ size_t num_clk_base; -+ struct mtmips_clk_fixed *clk_fixed; -+ size_t num_clk_fixed; -+ struct mtmips_clk_factor *clk_factor; -+ size_t num_clk_factor; -+ struct mtmips_clk *clk_periph; -+ size_t num_clk_periph; -+}; -+ -+struct mtmips_clk_priv { -+ struct regmap *sysc; -+ const struct mtmips_clk_data *data; -+}; -+ -+struct mtmips_clk { -+ struct clk_hw hw; -+ struct mtmips_clk_priv *priv; -+}; -+ -+struct mtmips_clk_fixed { -+ const char *name; -+ const char *parent; -+ unsigned long rate; -+ struct clk_hw *hw; -+}; -+ -+struct mtmips_clk_factor { -+ const char *name; -+ const char *parent; -+ int mult; -+ int div; -+ unsigned long flags; -+ struct clk_hw *hw; -+}; -+ -+static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ return parent_rate; -+} -+ -+static const struct clk_ops mtmips_periph_clk_ops = { -+ .recalc_rate = mtmips_pherip_clk_rate, -+}; -+ -+#define CLK_PERIPH(_name, _parent) { \ -+ .init = &(const struct clk_init_data) { \ -+ .name = _name, \ -+ .ops = &mtmips_periph_clk_ops, \ -+ .parent_data = &(const struct clk_parent_data) {\ -+ .name = _parent, \ -+ .fw_name = _parent \ -+ }, \ -+ .num_parents = 1, \ -+ /* \ -+ * There are drivers for these SoCs that are \ -+ * older than clock driver and are not prepared \ -+ * for the clock. We don't want the kernel to \ -+ * disable anything so we add CLK_IS_CRITICAL \ -+ * flag here. \ -+ */ \ -+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \ -+ }, \ -+} -+ -+static struct mtmips_clk rt2880_pherip_clks[] = { -+ { CLK_PERIPH("300100.timer", "bus") }, -+ { CLK_PERIPH("300120.watchdog", "bus") }, -+ { CLK_PERIPH("300500.uart", "bus") }, -+ { CLK_PERIPH("300900.i2c", "bus") }, -+ { CLK_PERIPH("300c00.uartlite", "bus") }, -+ { CLK_PERIPH("400000.ethernet", "bus") }, -+ { CLK_PERIPH("480000.wmac", "xtal") } -+}; -+ -+static struct mtmips_clk rt305x_pherip_clks[] = { -+ { CLK_PERIPH("10000100.timer", "bus") }, -+ { CLK_PERIPH("10000120.watchdog", "bus") }, -+ { CLK_PERIPH("10000500.uart", "bus") }, -+ { CLK_PERIPH("10000900.i2c", "bus") }, -+ { CLK_PERIPH("10000a00.i2s", "bus") }, -+ { CLK_PERIPH("10000b00.spi", "bus") }, -+ { CLK_PERIPH("10000b40.spi", "bus") }, -+ { CLK_PERIPH("10000c00.uartlite", "bus") }, -+ { CLK_PERIPH("10100000.ethernet", "bus") }, -+ { CLK_PERIPH("10180000.wmac", "xtal") } -+}; -+ -+static struct mtmips_clk rt5350_pherip_clks[] = { -+ { CLK_PERIPH("10000100.timer", "bus") }, -+ { CLK_PERIPH("10000120.watchdog", "bus") }, -+ { CLK_PERIPH("10000500.uart", "periph") }, -+ { CLK_PERIPH("10000900.i2c", "periph") }, -+ { CLK_PERIPH("10000a00.i2s", "periph") }, -+ { CLK_PERIPH("10000b00.spi", "bus") }, -+ { CLK_PERIPH("10000b40.spi", "bus") }, -+ { CLK_PERIPH("10000c00.uartlite", "periph") }, -+ { CLK_PERIPH("10100000.ethernet", "bus") }, -+ { CLK_PERIPH("10180000.wmac", "xtal") } -+}; -+ -+static struct mtmips_clk mt7620_pherip_clks[] = { -+ { CLK_PERIPH("10000100.timer", "periph") }, -+ { CLK_PERIPH("10000120.watchdog", "periph") }, -+ { CLK_PERIPH("10000500.uart", "periph") }, -+ { CLK_PERIPH("10000900.i2c", "periph") }, -+ { CLK_PERIPH("10000a00.i2s", "periph") }, -+ { CLK_PERIPH("10000b00.spi", "bus") }, -+ { CLK_PERIPH("10000b40.spi", "bus") }, -+ { CLK_PERIPH("10000c00.uartlite", "periph") }, -+ { CLK_PERIPH("10180000.wmac", "xtal") } -+}; -+ -+static struct mtmips_clk mt76x8_pherip_clks[] = { -+ { CLK_PERIPH("10000100.timer", "periph") }, -+ { CLK_PERIPH("10000120.watchdog", "periph") }, -+ { CLK_PERIPH("10000900.i2c", "periph") }, -+ { CLK_PERIPH("10000a00.i2s", "pcmi2s") }, -+ { CLK_PERIPH("10000b00.spi", "bus") }, -+ { CLK_PERIPH("10000b40.spi", "bus") }, -+ { CLK_PERIPH("10000c00.uart0", "periph") }, -+ { CLK_PERIPH("10000d00.uart1", "periph") }, -+ { CLK_PERIPH("10000e00.uart2", "periph") }, -+ { CLK_PERIPH("10300000.wmac", "xtal") } -+}; -+ -+static int mtmips_register_pherip_clocks(struct device_node *np, -+ struct clk_hw_onecell_data *clk_data, -+ struct mtmips_clk_priv *priv) -+{ -+ struct clk_hw **hws = clk_data->hws; -+ struct mtmips_clk *sclk; -+ size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed + -+ priv->data->num_clk_factor; -+ int ret, i; -+ -+ for (i = 0; i < priv->data->num_clk_periph; i++) { -+ int idx = idx_start + i; -+ -+ sclk = &priv->data->clk_periph[i]; -+ ret = of_clk_hw_register(np, &sclk->hw); -+ if (ret) { -+ pr_err("Couldn't register peripheral clock %d\n", idx); -+ goto err_clk_unreg; -+ } -+ -+ hws[idx] = &sclk->hw; -+ } -+ -+ return 0; -+ -+err_clk_unreg: -+ while (--i >= 0) { -+ sclk = &priv->data->clk_periph[i]; -+ clk_hw_unregister(&sclk->hw); -+ } -+ return ret; -+} -+ -+#define CLK_FIXED(_name, _parent, _rate) \ -+ { \ -+ .name = _name, \ -+ .parent = _parent, \ -+ .rate = _rate \ -+ } -+ -+static struct mtmips_clk_fixed rt305x_fixed_clocks[] = { -+ CLK_FIXED("xtal", NULL, 40000000) -+}; -+ -+static struct mtmips_clk_fixed rt3352_fixed_clocks[] = { -+ CLK_FIXED("periph", "xtal", 40000000) -+}; -+ -+static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = { -+ CLK_FIXED("pcmi2s", "xtal", 480000000), -+ CLK_FIXED("periph", "xtal", 40000000) -+}; -+ -+static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data, -+ struct mtmips_clk_priv *priv) -+{ -+ struct clk_hw **hws = clk_data->hws; -+ struct mtmips_clk_fixed *sclk; -+ size_t idx_start = priv->data->num_clk_base; -+ int ret, i; -+ -+ for (i = 0; i < priv->data->num_clk_fixed; i++) { -+ int idx = idx_start + i; -+ -+ sclk = &priv->data->clk_fixed[i]; -+ sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name, -+ sclk->parent, 0, -+ sclk->rate); -+ if (IS_ERR(sclk->hw)) { -+ pr_err("Couldn't register fixed clock %d\n", idx); -+ goto err_clk_unreg; -+ } -+ -+ hws[idx] = sclk->hw; -+ } -+ -+ return 0; -+ -+err_clk_unreg: -+ while (--i >= 0) { -+ sclk = &priv->data->clk_fixed[i]; -+ clk_hw_unregister_fixed_rate(sclk->hw); -+ } -+ return ret; -+} -+ -+#define CLK_FACTOR(_name, _parent, _mult, _div) \ -+ { \ -+ .name = _name, \ -+ .parent = _parent, \ -+ .mult = _mult, \ -+ .div = _div, \ -+ .flags = CLK_SET_RATE_PARENT \ -+ } -+ -+static struct mtmips_clk_factor rt2880_factor_clocks[] = { -+ CLK_FACTOR("bus", "cpu", 1, 2) -+}; -+ -+static struct mtmips_clk_factor rt305x_factor_clocks[] = { -+ CLK_FACTOR("bus", "cpu", 1, 3) -+}; -+ -+static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data, -+ struct mtmips_clk_priv *priv) -+{ -+ struct clk_hw **hws = clk_data->hws; -+ struct mtmips_clk_factor *sclk; -+ size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed; -+ int ret, i; -+ -+ for (i = 0; i < priv->data->num_clk_factor; i++) { -+ int idx = idx_start + i; -+ -+ sclk = &priv->data->clk_factor[i]; -+ sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name, -+ sclk->parent, sclk->flags, -+ sclk->mult, sclk->div); -+ if (IS_ERR(sclk->hw)) { -+ pr_err("Couldn't register factor clock %d\n", idx); -+ goto err_clk_unreg; -+ } -+ -+ hws[idx] = sclk->hw; -+ } -+ -+ return 0; -+ -+err_clk_unreg: -+ while (--i >= 0) { -+ sclk = &priv->data->clk_factor[i]; -+ clk_hw_unregister_fixed_factor(sclk->hw); -+ } -+ return ret; -+} -+ -+static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw) -+{ -+ return container_of(hw, struct mtmips_clk, hw); -+} -+ -+static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 val; -+ -+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val); -+ if (!(val & RT5350_CLKCFG0_XTAL_SEL)) -+ return 20000000; -+ -+ return 40000000; -+} -+ -+static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw, -+ unsigned long xtal_clk) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ -+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); -+ t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK; -+ -+ switch (t) { -+ case RT5350_SYSCFG0_CPUCLK_360: -+ return 360000000; -+ case RT5350_SYSCFG0_CPUCLK_320: -+ return 320000000; -+ case RT5350_SYSCFG0_CPUCLK_300: -+ return 300000000; -+ default: -+ BUG(); -+ } -+} -+ -+static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ if (parent_rate == 320000000) -+ return parent_rate / 4; -+ -+ return parent_rate / 3; -+} -+ -+static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw, -+ unsigned long xtal_clk) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ -+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); -+ t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK; -+ -+ switch (t) { -+ case RT3352_SYSCFG0_CPUCLK_LOW: -+ return 384000000; -+ case RT3352_SYSCFG0_CPUCLK_HIGH: -+ return 400000000; -+ default: -+ BUG(); -+ } -+} -+ -+static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw, -+ unsigned long xtal_clk) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ -+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); -+ t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK; -+ -+ switch (t) { -+ case RT305X_SYSCFG_CPUCLK_LOW: -+ return 320000000; -+ case RT305X_SYSCFG_CPUCLK_HIGH: -+ return 384000000; -+ default: -+ BUG(); -+ } -+} -+ -+static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw, -+ unsigned long xtal_clk) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ -+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); -+ t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK; -+ -+ switch (t) { -+ case RT3883_SYSCFG0_CPUCLK_250: -+ return 250000000; -+ case RT3883_SYSCFG0_CPUCLK_384: -+ return 384000000; -+ case RT3883_SYSCFG0_CPUCLK_480: -+ return 480000000; -+ case RT3883_SYSCFG0_CPUCLK_500: -+ return 500000000; -+ default: -+ BUG(); -+ } -+} -+ -+static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 ddr2; -+ u32 t; -+ -+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); -+ ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2; -+ -+ switch (parent_rate) { -+ case 250000000: -+ return (ddr2) ? 125000000 : 83000000; -+ case 384000000: -+ return (ddr2) ? 128000000 : 96000000; -+ case 480000000: -+ return (ddr2) ? 160000000 : 120000000; -+ case 500000000: -+ return (ddr2) ? 166000000 : 125000000; -+ default: -+ WARN_ON_ONCE(parent_rate == 0); -+ return parent_rate / 4; -+ } -+} -+ -+static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw, -+ unsigned long xtal_clk) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ -+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); -+ t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK; -+ -+ switch (t) { -+ case RT2880_CONFIG_CPUCLK_250: -+ return 250000000; -+ case RT2880_CONFIG_CPUCLK_266: -+ return 266000000; -+ case RT2880_CONFIG_CPUCLK_280: -+ return 280000000; -+ case RT2880_CONFIG_CPUCLK_300: -+ return 300000000; -+ default: -+ BUG(); -+ } -+} -+ -+static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) -+{ -+ u64 t; -+ -+ t = ref_rate; -+ t *= mul; -+ t = div_u64(t, div); -+ -+ return t; -+} -+ -+static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ static const u32 clk_divider[] = { 2, 3, 4, 8 }; -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ unsigned long cpu_pll; -+ u32 t; -+ u32 mul; -+ u32 div; -+ -+ regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t); -+ if (t & CPLL_CFG0_BYPASS_REF_CLK) { -+ cpu_pll = parent_rate; -+ } else if ((t & CPLL_CFG0_SW_CFG) == 0) { -+ cpu_pll = 600000000; -+ } else { -+ mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & -+ CPLL_CFG0_PLL_MULT_RATIO_MASK; -+ mul += 24; -+ if (t & CPLL_CFG0_LC_CURFCK) -+ mul *= 2; -+ -+ div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & -+ CPLL_CFG0_PLL_DIV_RATIO_MASK; -+ -+ WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider)); -+ -+ cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]); -+ } -+ -+ regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t); -+ if (t & CPLL_CFG1_CPU_AUX1) -+ return parent_rate; -+ -+ if (t & CPLL_CFG1_CPU_AUX0) -+ return 480000000; -+ -+ return cpu_pll; -+} -+ -+static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ u32 mul; -+ u32 div; -+ -+ regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); -+ mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; -+ div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & -+ CPU_SYS_CLKCFG_CPU_FDIV_MASK; -+ -+ return mt7620_calc_rate(parent_rate, mul, div); -+} -+ -+static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ static const u32 ocp_dividers[16] = { -+ [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, -+ [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, -+ [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, -+ [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, -+ [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, -+ }; -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ u32 ocp_ratio; -+ u32 div; -+ -+ regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); -+ ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & -+ CPU_SYS_CLKCFG_OCP_RATIO_MASK; -+ -+ if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers))) -+ return parent_rate; -+ -+ div = ocp_dividers[ocp_ratio]; -+ -+ if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) -+ return parent_rate; -+ -+ return parent_rate / div; -+} -+ -+static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ -+ regmap_read(sysc, SYSC_REG_CLKCFG0, &t); -+ if (t & CLKCFG0_PERI_CLK_SEL) -+ return parent_rate; -+ -+ return 40000000; -+} -+ -+static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct mtmips_clk *clk = to_mtmips_clk(hw); -+ struct regmap *sysc = clk->priv->sysc; -+ u32 t; -+ -+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t); -+ if (t & MT7620_XTAL_FREQ_SEL) -+ return 40000000; -+ -+ return 20000000; -+} -+ -+static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw, -+ unsigned long xtal_clk) -+{ -+ if (xtal_clk == 40000000) -+ return 580000000; -+ -+ return 575000000; -+} -+ -+#define CLK_BASE(_name, _parent, _recalc) { \ -+ .init = &(const struct clk_init_data) { \ -+ .name = _name, \ -+ .ops = &(const struct clk_ops) { \ -+ .recalc_rate = _recalc, \ -+ }, \ -+ .parent_data = &(const struct clk_parent_data) { \ -+ .name = _parent, \ -+ .fw_name = _parent \ -+ }, \ -+ .num_parents = _parent ? 1 : 0 \ -+ }, \ -+} -+ -+static struct mtmips_clk rt2880_clks_base[] = { -+ { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) } -+}; -+ -+static struct mtmips_clk rt305x_clks_base[] = { -+ { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) } -+}; -+ -+static struct mtmips_clk rt3352_clks_base[] = { -+ { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, -+ { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) } -+}; -+ -+static struct mtmips_clk rt3883_clks_base[] = { -+ { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) }, -+ { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) } -+}; -+ -+static struct mtmips_clk rt5350_clks_base[] = { -+ { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) }, -+ { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) }, -+ { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) } -+}; -+ -+static struct mtmips_clk mt7620_clks_base[] = { -+ { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, -+ { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) }, -+ { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) }, -+ { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) }, -+ { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) } -+}; -+ -+static struct mtmips_clk mt76x8_clks_base[] = { -+ { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) }, -+ { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) } -+}; -+ -+static int mtmips_register_clocks(struct device_node *np, -+ struct clk_hw_onecell_data *clk_data, -+ struct mtmips_clk_priv *priv) -+{ -+ struct clk_hw **hws = clk_data->hws; -+ struct mtmips_clk *sclk; -+ int ret, i; -+ -+ for (i = 0; i < priv->data->num_clk_base; i++) { -+ sclk = &priv->data->clk_base[i]; -+ sclk->priv = priv; -+ ret = of_clk_hw_register(np, &sclk->hw); -+ if (ret) { -+ pr_err("Couldn't register top clock %i\n", i); -+ goto err_clk_unreg; -+ } -+ -+ hws[i] = &sclk->hw; -+ } -+ -+ return 0; -+ -+err_clk_unreg: -+ while (--i >= 0) { -+ sclk = &priv->data->clk_base[i]; -+ clk_hw_unregister(&sclk->hw); -+ } -+ return ret; -+} -+ -+static const struct mtmips_clk_data rt2880_clk_data = { -+ .clk_base = rt2880_clks_base, -+ .num_clk_base = ARRAY_SIZE(rt2880_clks_base), -+ .clk_fixed = rt305x_fixed_clocks, -+ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), -+ .clk_factor = rt2880_factor_clocks, -+ .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks), -+ .clk_periph = rt2880_pherip_clks, -+ .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks), -+}; -+ -+static const struct mtmips_clk_data rt305x_clk_data = { -+ .clk_base = rt305x_clks_base, -+ .num_clk_base = ARRAY_SIZE(rt305x_clks_base), -+ .clk_fixed = rt305x_fixed_clocks, -+ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), -+ .clk_factor = rt305x_factor_clocks, -+ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), -+ .clk_periph = rt305x_pherip_clks, -+ .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks), -+}; -+ -+static const struct mtmips_clk_data rt3352_clk_data = { -+ .clk_base = rt3352_clks_base, -+ .num_clk_base = ARRAY_SIZE(rt3352_clks_base), -+ .clk_fixed = rt3352_fixed_clocks, -+ .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), -+ .clk_factor = rt305x_factor_clocks, -+ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), -+ .clk_periph = rt5350_pherip_clks, -+ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), -+}; -+ -+static const struct mtmips_clk_data rt3883_clk_data = { -+ .clk_base = rt3883_clks_base, -+ .num_clk_base = ARRAY_SIZE(rt3883_clks_base), -+ .clk_fixed = rt305x_fixed_clocks, -+ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks), -+ .clk_factor = NULL, -+ .num_clk_factor = 0, -+ .clk_periph = rt5350_pherip_clks, -+ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), -+}; -+ -+static const struct mtmips_clk_data rt5350_clk_data = { -+ .clk_base = rt5350_clks_base, -+ .num_clk_base = ARRAY_SIZE(rt5350_clks_base), -+ .clk_fixed = rt3352_fixed_clocks, -+ .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks), -+ .clk_factor = NULL, -+ .num_clk_factor = 0, -+ .clk_periph = rt5350_pherip_clks, -+ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks), -+}; -+ -+static const struct mtmips_clk_data mt7620_clk_data = { -+ .clk_base = mt7620_clks_base, -+ .num_clk_base = ARRAY_SIZE(mt7620_clks_base), -+ .clk_fixed = NULL, -+ .num_clk_fixed = 0, -+ .clk_factor = NULL, -+ .num_clk_factor = 0, -+ .clk_periph = mt7620_pherip_clks, -+ .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks), -+}; -+ -+static const struct mtmips_clk_data mt76x8_clk_data = { -+ .clk_base = mt76x8_clks_base, -+ .num_clk_base = ARRAY_SIZE(mt76x8_clks_base), -+ .clk_fixed = mt76x8_fixed_clocks, -+ .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks), -+ .clk_factor = rt305x_factor_clocks, -+ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks), -+ .clk_periph = mt76x8_pherip_clks, -+ .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks), -+}; -+ -+static const struct of_device_id mtmips_of_match[] = { -+ { -+ .compatible = "ralink,rt2880-sysc", -+ .data = &rt2880_clk_data, -+ }, -+ { -+ .compatible = "ralink,rt3050-sysc", -+ .data = &rt305x_clk_data, -+ }, -+ { -+ .compatible = "ralink,rt3052-sysc", -+ .data = &rt305x_clk_data, -+ }, -+ { -+ .compatible = "ralink,rt3352-sysc", -+ .data = &rt3352_clk_data, -+ }, -+ { -+ .compatible = "ralink,rt3883-sysc", -+ .data = &rt3883_clk_data, -+ }, -+ { -+ .compatible = "ralink,rt5350-sysc", -+ .data = &rt5350_clk_data, -+ }, -+ { -+ .compatible = "ralink,mt7620-sysc", -+ .data = &mt7620_clk_data, -+ }, -+ { -+ .compatible = "ralink,mt7628-sysc", -+ .data = &mt76x8_clk_data, -+ }, -+ { -+ .compatible = "ralink,mt7688-sysc", -+ .data = &mt76x8_clk_data, -+ }, -+ {} -+}; -+ -+static void __init mtmips_clk_regs_init(struct device_node *node, -+ struct mtmips_clk_priv *priv) -+{ -+ u32 t; -+ -+ if (!of_device_is_compatible(node, "ralink,mt7620-sysc")) -+ return; -+ -+ /* -+ * When the CPU goes into sleep mode, the BUS -+ * clock will be too low for USB to function properly. -+ * Adjust the busses fractional divider to fix this -+ */ -+ regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t); -+ t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); -+ t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; -+ regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t); -+} -+ -+static void __init mtmips_clk_init(struct device_node *node) -+{ -+ const struct of_device_id *match; -+ const struct mtmips_clk_data *data; -+ struct mtmips_clk_priv *priv; -+ struct clk_hw_onecell_data *clk_data; -+ int ret, i, count; -+ -+ priv = kzalloc(sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return; -+ -+ priv->sysc = syscon_node_to_regmap(node); -+ if (IS_ERR(priv->sysc)) { -+ pr_err("Could not get sysc syscon regmap\n"); -+ goto free_clk_priv; -+ } -+ -+ mtmips_clk_regs_init(node, priv); -+ -+ match = of_match_node(mtmips_of_match, node); -+ if (WARN_ON(!match)) -+ return; -+ -+ data = match->data; -+ priv->data = data; -+ count = priv->data->num_clk_base + priv->data->num_clk_fixed + -+ priv->data->num_clk_factor + priv->data->num_clk_periph; -+ clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL); -+ if (!clk_data) -+ goto free_clk_priv; -+ -+ ret = mtmips_register_clocks(node, clk_data, priv); -+ if (ret) { -+ pr_err("Couldn't register top clocks\n"); -+ goto free_clk_data; -+ } -+ -+ ret = mtmips_register_fixed_clocks(clk_data, priv); -+ if (ret) { -+ pr_err("Couldn't register fixed clocks\n"); -+ goto unreg_clk_top; -+ } -+ -+ ret = mtmips_register_factor_clocks(clk_data, priv); -+ if (ret) { -+ pr_err("Couldn't register factor clocks\n"); -+ goto unreg_clk_fixed; -+ } -+ -+ ret = mtmips_register_pherip_clocks(node, clk_data, priv); -+ if (ret) { -+ pr_err("Couldn't register peripheral clocks\n"); -+ goto unreg_clk_factor; -+ } -+ -+ clk_data->num = count; -+ -+ ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ if (ret) { -+ pr_err("Couldn't add clk hw provider\n"); -+ goto unreg_clk_periph; -+ } -+ -+ return; -+ -+unreg_clk_periph: -+ for (i = 0; i < priv->data->num_clk_periph; i++) { -+ struct mtmips_clk *sclk = &priv->data->clk_periph[i]; -+ -+ clk_hw_unregister(&sclk->hw); -+ } -+ -+unreg_clk_factor: -+ for (i = 0; i < priv->data->num_clk_factor; i++) { -+ struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i]; -+ -+ clk_hw_unregister_fixed_factor(sclk->hw); -+ } -+ -+unreg_clk_fixed: -+ for (i = 0; i < priv->data->num_clk_fixed; i++) { -+ struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i]; -+ -+ clk_hw_unregister_fixed_rate(sclk->hw); -+ } -+ -+unreg_clk_top: -+ for (i = 0; i < priv->data->num_clk_base; i++) { -+ struct mtmips_clk *sclk = &priv->data->clk_base[i]; -+ -+ clk_hw_unregister(&sclk->hw); -+ } -+ -+free_clk_data: -+ kfree(clk_data); -+ -+free_clk_priv: -+ kfree(priv); -+} -+CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init); -+CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init); -+CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init); -+CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init); -+CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init); -+CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init); -+CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init); -+CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init); -+CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init); -+ -+struct mtmips_rst { -+ struct reset_controller_dev rcdev; -+ struct regmap *sysc; -+}; -+ -+static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev) -+{ -+ return container_of(dev, struct mtmips_rst, rcdev); -+} -+ -+static int mtmips_assert_device(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ struct mtmips_rst *data = to_mtmips_rst(rcdev); -+ struct regmap *sysc = data->sysc; -+ -+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id)); -+} -+ -+static int mtmips_deassert_device(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ struct mtmips_rst *data = to_mtmips_rst(rcdev); -+ struct regmap *sysc = data->sysc; -+ -+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0); -+} -+ -+static int mtmips_reset_device(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ int ret; -+ -+ ret = mtmips_assert_device(rcdev, id); -+ if (ret < 0) -+ return ret; -+ -+ return mtmips_deassert_device(rcdev, id); -+} -+ -+static int mtmips_rst_xlate(struct reset_controller_dev *rcdev, -+ const struct of_phandle_args *reset_spec) -+{ -+ unsigned long id = reset_spec->args[0]; -+ -+ if (id == 0 || id >= rcdev->nr_resets) -+ return -EINVAL; -+ -+ return id; -+} -+ -+static const struct reset_control_ops reset_ops = { -+ .reset = mtmips_reset_device, -+ .assert = mtmips_assert_device, -+ .deassert = mtmips_deassert_device -+}; -+ -+static int mtmips_reset_init(struct device *dev, struct regmap *sysc) -+{ -+ struct mtmips_rst *rst_data; -+ -+ rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); -+ if (!rst_data) -+ return -ENOMEM; -+ -+ rst_data->sysc = sysc; -+ rst_data->rcdev.ops = &reset_ops; -+ rst_data->rcdev.owner = THIS_MODULE; -+ rst_data->rcdev.nr_resets = 32; -+ rst_data->rcdev.of_reset_n_cells = 1; -+ rst_data->rcdev.of_xlate = mtmips_rst_xlate; -+ rst_data->rcdev.of_node = dev_of_node(dev); -+ -+ return devm_reset_controller_register(dev, &rst_data->rcdev); -+} -+ -+static int mtmips_clk_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct device *dev = &pdev->dev; -+ struct mtmips_clk_priv *priv; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->sysc = syscon_node_to_regmap(np); -+ if (IS_ERR(priv->sysc)) -+ return dev_err_probe(dev, PTR_ERR(priv->sysc), -+ "Could not get sysc syscon regmap\n"); -+ -+ ret = mtmips_reset_init(dev, priv->sysc); -+ if (ret) -+ return dev_err_probe(dev, ret, "Could not init reset controller\n"); -+ -+ return 0; -+} -+ -+static const struct of_device_id mtmips_clk_of_match[] = { -+ { .compatible = "ralink,rt2880-reset" }, -+ { .compatible = "ralink,rt2880-sysc" }, -+ { .compatible = "ralink,rt3050-sysc" }, -+ { .compatible = "ralink,rt3052-sysc" }, -+ { .compatible = "ralink,rt3352-sysc" }, -+ { .compatible = "ralink,rt3883-sysc" }, -+ { .compatible = "ralink,rt5350-sysc" }, -+ { .compatible = "ralink,mt7620-sysc" }, -+ { .compatible = "ralink,mt7628-sysc" }, -+ { .compatible = "ralink,mt7688-sysc" }, -+ {} -+}; -+ -+static struct platform_driver mtmips_clk_driver = { -+ .probe = mtmips_clk_probe, -+ .driver = { -+ .name = "mtmips-clk", -+ .of_match_table = mtmips_clk_of_match, -+ }, -+}; -+ -+static int __init mtmips_clk_reset_init(void) -+{ -+ return platform_driver_register(&mtmips_clk_driver); -+} -+arch_initcall(mtmips_clk_reset_init); diff --git a/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch deleted file mode 100644 index df4208b23da137..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch +++ /dev/null @@ -1,81 +0,0 @@ -From ffcdf47379eae86dc8f8f02c62994dacf2c9038e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:35 +0200 -Subject: [PATCH 3/9] mips: ralink: rt288x: remove clock related code - -A properly clock driver for ralink SoCs has been added. Hence there is no -need to have clock related code in 'arch/mips/ralink' folder anymore. - -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/include/asm/mach-ralink/rt288x.h | 10 ---------- - arch/mips/ralink/rt288x.c | 31 ------------------------------ - 2 files changed, 41 deletions(-) - ---- a/arch/mips/include/asm/mach-ralink/rt288x.h -+++ b/arch/mips/include/asm/mach-ralink/rt288x.h -@@ -17,7 +17,6 @@ - #define SYSC_REG_CHIP_NAME1 0x04 - #define SYSC_REG_CHIP_ID 0x0c - #define SYSC_REG_SYSTEM_CONFIG 0x10 --#define SYSC_REG_CLKCFG 0x30 - - #define RT2880_CHIP_NAME0 0x38325452 - #define RT2880_CHIP_NAME1 0x20203038 -@@ -26,15 +25,6 @@ - #define CHIP_ID_ID_SHIFT 8 - #define CHIP_ID_REV_MASK 0xff - --#define SYSTEM_CONFIG_CPUCLK_SHIFT 20 --#define SYSTEM_CONFIG_CPUCLK_MASK 0x3 --#define SYSTEM_CONFIG_CPUCLK_250 0x0 --#define SYSTEM_CONFIG_CPUCLK_266 0x1 --#define SYSTEM_CONFIG_CPUCLK_280 0x2 --#define SYSTEM_CONFIG_CPUCLK_300 0x3 -- --#define CLKCFG_SRAM_CS_N_WDT BIT(9) -- - #define RT2880_SDRAM_BASE 0x08000000 - #define RT2880_MEM_SIZE_MIN 2 - #define RT2880_MEM_SIZE_MAX 128 ---- a/arch/mips/ralink/rt288x.c -+++ b/arch/mips/ralink/rt288x.c -@@ -17,37 +17,6 @@ - - #include "common.h" - --void __init ralink_clk_init(void) --{ -- unsigned long cpu_rate, wmac_rate = 40000000; -- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); -- t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); -- -- switch (t) { -- case SYSTEM_CONFIG_CPUCLK_250: -- cpu_rate = 250000000; -- break; -- case SYSTEM_CONFIG_CPUCLK_266: -- cpu_rate = 266666667; -- break; -- case SYSTEM_CONFIG_CPUCLK_280: -- cpu_rate = 280000000; -- break; -- case SYSTEM_CONFIG_CPUCLK_300: -- cpu_rate = 300000000; -- break; -- } -- -- ralink_clk_add("cpu", cpu_rate); -- ralink_clk_add("300100.timer", cpu_rate / 2); -- ralink_clk_add("300120.watchdog", cpu_rate / 2); -- ralink_clk_add("300500.uart", cpu_rate / 2); -- ralink_clk_add("300900.i2c", cpu_rate / 2); -- ralink_clk_add("300c00.uartlite", cpu_rate / 2); -- ralink_clk_add("400000.ethernet", cpu_rate / 2); -- ralink_clk_add("480000.wmac", wmac_rate); --} -- - void __init ralink_of_remap(void) - { - rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc"); diff --git a/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch deleted file mode 100644 index 12b4623b73ef45..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch +++ /dev/null @@ -1,145 +0,0 @@ -From daf73c70f69386fb15960526772ef584a4efcaf2 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:36 +0200 -Subject: [PATCH 4/9] mips: ralink: rt305x: remove clock related code - -A properly clock driver for ralink SoCs has been added. Hence there is no -need to have clock related code in 'arch/mips/ralink' folder anymore. - -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/include/asm/mach-ralink/rt305x.h | 21 -------- - arch/mips/ralink/rt305x.c | 78 ------------------------------ - 2 files changed, 99 deletions(-) - ---- a/arch/mips/include/asm/mach-ralink/rt305x.h -+++ b/arch/mips/include/asm/mach-ralink/rt305x.h -@@ -66,26 +66,9 @@ static inline int soc_is_rt5350(void) - #define CHIP_ID_ID_SHIFT 8 - #define CHIP_ID_REV_MASK 0xff - --#define RT305X_SYSCFG_CPUCLK_SHIFT 18 --#define RT305X_SYSCFG_CPUCLK_MASK 0x1 --#define RT305X_SYSCFG_CPUCLK_LOW 0x0 --#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 -- - #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 --#define RT305X_SYSCFG_CPUCLK_MASK 0x1 - #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1 - --#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 --#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 --#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 --#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 -- --#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 --#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 --#define RT5350_SYSCFG0_CPUCLK_360 0x0 --#define RT5350_SYSCFG0_CPUCLK_320 0x2 --#define RT5350_SYSCFG0_CPUCLK_300 0x3 -- - #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 - #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 - #define RT5350_SYSCFG0_DRAM_SIZE_2M 0 -@@ -116,13 +99,9 @@ static inline int soc_is_rt5350(void) - - #define RT3352_SYSC_REG_SYSCFG0 0x010 - #define RT3352_SYSC_REG_SYSCFG1 0x014 --#define RT3352_SYSC_REG_CLKCFG1 0x030 - #define RT3352_SYSC_REG_RSTCTRL 0x034 - #define RT3352_SYSC_REG_USB_PS 0x05c - --#define RT3352_CLKCFG0_XTAL_SEL BIT(20) --#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) --#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) - #define RT3352_RSTCTRL_UHST BIT(22) - #define RT3352_RSTCTRL_UDEV BIT(25) - #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) ---- a/arch/mips/ralink/rt305x.c -+++ b/arch/mips/ralink/rt305x.c -@@ -53,84 +53,6 @@ static unsigned long rt5350_get_mem_size - return ret; - } - --void __init ralink_clk_init(void) --{ -- unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; -- unsigned long wmac_rate = 40000000; -- -- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); -- -- if (soc_is_rt305x() || soc_is_rt3350()) { -- t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & -- RT305X_SYSCFG_CPUCLK_MASK; -- switch (t) { -- case RT305X_SYSCFG_CPUCLK_LOW: -- cpu_rate = 320000000; -- break; -- case RT305X_SYSCFG_CPUCLK_HIGH: -- cpu_rate = 384000000; -- break; -- } -- sys_rate = uart_rate = wdt_rate = cpu_rate / 3; -- } else if (soc_is_rt3352()) { -- t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & -- RT3352_SYSCFG0_CPUCLK_MASK; -- switch (t) { -- case RT3352_SYSCFG0_CPUCLK_LOW: -- cpu_rate = 384000000; -- break; -- case RT3352_SYSCFG0_CPUCLK_HIGH: -- cpu_rate = 400000000; -- break; -- } -- sys_rate = wdt_rate = cpu_rate / 3; -- uart_rate = 40000000; -- } else if (soc_is_rt5350()) { -- t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & -- RT5350_SYSCFG0_CPUCLK_MASK; -- switch (t) { -- case RT5350_SYSCFG0_CPUCLK_360: -- cpu_rate = 360000000; -- sys_rate = cpu_rate / 3; -- break; -- case RT5350_SYSCFG0_CPUCLK_320: -- cpu_rate = 320000000; -- sys_rate = cpu_rate / 4; -- break; -- case RT5350_SYSCFG0_CPUCLK_300: -- cpu_rate = 300000000; -- sys_rate = cpu_rate / 3; -- break; -- default: -- BUG(); -- } -- uart_rate = 40000000; -- wdt_rate = sys_rate; -- } else { -- BUG(); -- } -- -- if (soc_is_rt3352() || soc_is_rt5350()) { -- u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0); -- -- if (!(val & RT3352_CLKCFG0_XTAL_SEL)) -- wmac_rate = 20000000; -- } -- -- ralink_clk_add("cpu", cpu_rate); -- ralink_clk_add("sys", sys_rate); -- ralink_clk_add("10000900.i2c", uart_rate); -- ralink_clk_add("10000a00.i2s", uart_rate); -- ralink_clk_add("10000b00.spi", sys_rate); -- ralink_clk_add("10000b40.spi", sys_rate); -- ralink_clk_add("10000100.timer", wdt_rate); -- ralink_clk_add("10000120.watchdog", wdt_rate); -- ralink_clk_add("10000500.uart", uart_rate); -- ralink_clk_add("10000c00.uartlite", uart_rate); -- ralink_clk_add("10100000.ethernet", sys_rate); -- ralink_clk_add("10180000.wmac", wmac_rate); --} -- - void __init ralink_of_remap(void) - { - rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); diff --git a/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch deleted file mode 100644 index c13c4215f3a51f..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-05-mips-ralink-rt3883-remove-clock-related-code.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 7cd1bb48885449a9323c7ff0f10012925e93b4e1 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:37 +0200 -Subject: [PATCH 5/9] mips: ralink: rt3883: remove clock related code - -A properly clock driver for ralink SoCs has been added. Hence there is no -need to have clock related code in 'arch/mips/ralink' folder anymore. - -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/include/asm/mach-ralink/rt3883.h | 8 ------ - arch/mips/ralink/rt3883.c | 44 ------------------------------ - 2 files changed, 52 deletions(-) - ---- a/arch/mips/include/asm/mach-ralink/rt3883.h -+++ b/arch/mips/include/asm/mach-ralink/rt3883.h -@@ -90,14 +90,6 @@ - #define RT3883_REVID_VER_ID_SHIFT 8 - #define RT3883_REVID_ECO_ID_MASK 0x0f - --#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17) --#define RT3883_SYSCFG0_CPUCLK_SHIFT 8 --#define RT3883_SYSCFG0_CPUCLK_MASK 0x3 --#define RT3883_SYSCFG0_CPUCLK_250 0x0 --#define RT3883_SYSCFG0_CPUCLK_384 0x1 --#define RT3883_SYSCFG0_CPUCLK_480 0x2 --#define RT3883_SYSCFG0_CPUCLK_500 0x3 -- - #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10) - #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8) - #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7) ---- a/arch/mips/ralink/rt3883.c -+++ b/arch/mips/ralink/rt3883.c -@@ -17,50 +17,6 @@ - - #include "common.h" - --void __init ralink_clk_init(void) --{ -- unsigned long cpu_rate, sys_rate; -- u32 syscfg0; -- u32 clksel; -- u32 ddr2; -- -- syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); -- clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & -- RT3883_SYSCFG0_CPUCLK_MASK); -- ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; -- -- switch (clksel) { -- case RT3883_SYSCFG0_CPUCLK_250: -- cpu_rate = 250000000; -- sys_rate = (ddr2) ? 125000000 : 83000000; -- break; -- case RT3883_SYSCFG0_CPUCLK_384: -- cpu_rate = 384000000; -- sys_rate = (ddr2) ? 128000000 : 96000000; -- break; -- case RT3883_SYSCFG0_CPUCLK_480: -- cpu_rate = 480000000; -- sys_rate = (ddr2) ? 160000000 : 120000000; -- break; -- case RT3883_SYSCFG0_CPUCLK_500: -- cpu_rate = 500000000; -- sys_rate = (ddr2) ? 166000000 : 125000000; -- break; -- } -- -- ralink_clk_add("cpu", cpu_rate); -- ralink_clk_add("10000100.timer", sys_rate); -- ralink_clk_add("10000120.watchdog", sys_rate); -- ralink_clk_add("10000500.uart", 40000000); -- ralink_clk_add("10000900.i2c", 40000000); -- ralink_clk_add("10000a00.i2s", 40000000); -- ralink_clk_add("10000b00.spi", sys_rate); -- ralink_clk_add("10000b40.spi", sys_rate); -- ralink_clk_add("10000c00.uartlite", 40000000); -- ralink_clk_add("10100000.ethernet", sys_rate); -- ralink_clk_add("10180000.wmac", 40000000); --} -- - void __init ralink_of_remap(void) - { - rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc"); diff --git a/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch deleted file mode 100644 index 7b83cf54b49e15..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch +++ /dev/null @@ -1,327 +0,0 @@ -From 04b153abdfcbaba70ceef5a846067d4447fd0078 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:38 +0200 -Subject: [PATCH 6/9] mips: ralink: mt7620: remove clock related code - -A proper clock driver for ralink SoCs has been added. Hence there is no -need to have clock related code in 'arch/mips/ralink' folder anymore. -Since this is the last clock related code removal, remove also remaining -prototypes in 'common.h' header file. - -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/include/asm/mach-ralink/mt7620.h | 35 ----- - arch/mips/ralink/common.h | 3 - - arch/mips/ralink/mt7620.c | 226 ----------------------------- - 3 files changed, 264 deletions(-) - ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -19,52 +19,17 @@ - #define SYSC_REG_CHIP_REV 0x0c - #define SYSC_REG_SYSTEM_CONFIG0 0x10 - #define SYSC_REG_SYSTEM_CONFIG1 0x14 --#define SYSC_REG_CLKCFG0 0x2c --#define SYSC_REG_CPU_SYS_CLKCFG 0x3c --#define SYSC_REG_CPLL_CONFIG0 0x54 --#define SYSC_REG_CPLL_CONFIG1 0x58 - - #define MT7620_CHIP_NAME0 0x3637544d - #define MT7620_CHIP_NAME1 0x20203032 - #define MT7628_CHIP_NAME1 0x20203832 - --#define SYSCFG0_XTAL_FREQ_SEL BIT(6) -- - #define CHIP_REV_PKG_MASK 0x1 - #define CHIP_REV_PKG_SHIFT 16 - #define CHIP_REV_VER_MASK 0xf - #define CHIP_REV_VER_SHIFT 8 - #define CHIP_REV_ECO_MASK 0xf - --#define CLKCFG0_PERI_CLK_SEL BIT(4) -- --#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 --#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf --#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ --#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ --#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ --#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ --#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ --#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ --#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ --#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ --#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ --#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 --#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f --#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 --#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f -- --#define CPLL_CFG0_SW_CFG BIT(31) --#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 --#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 --#define CPLL_CFG0_LC_CURFCK BIT(15) --#define CPLL_CFG0_BYPASS_REF_CLK BIT(14) --#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 --#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 -- --#define CPLL_CFG1_CPU_AUX1 BIT(25) --#define CPLL_CFG1_CPU_AUX0 BIT(24) -- - #define SYSCFG0_DRAM_TYPE_MASK 0x3 - #define SYSCFG0_DRAM_TYPE_SHIFT 4 - #define SYSCFG0_DRAM_TYPE_SDRAM 0 ---- a/arch/mips/ralink/common.h -+++ b/arch/mips/ralink/common.h -@@ -23,9 +23,6 @@ extern struct ralink_soc_info soc_info; - - extern void ralink_of_remap(void); - --extern void ralink_clk_init(void); --extern void ralink_clk_add(const char *dev, unsigned long rate); -- - extern void ralink_rst_init(void); - - extern void __init prom_soc_init(struct ralink_soc_info *soc_info); ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -34,12 +34,6 @@ - #define PMU1_CFG 0x8C - #define DIG_SW_SEL BIT(25) - --/* clock scaling */ --#define CLKCFG_FDIV_MASK 0x1f00 --#define CLKCFG_FDIV_USB_VAL 0x0300 --#define CLKCFG_FFRAC_MASK 0x001f --#define CLKCFG_FFRAC_USB_VAL 0x0003 -- - /* EFUSE bits */ - #define EFUSE_MT7688 0x100000 - -@@ -49,226 +43,6 @@ - /* does the board have sdram or ddram */ - static int dram_type; - --static __init u32 --mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) --{ -- u64 t; -- -- t = ref_rate; -- t *= mul; -- do_div(t, div); -- -- return t; --} -- --#define MHZ(x) ((x) * 1000 * 1000) -- --static __init unsigned long --mt7620_get_xtal_rate(void) --{ -- u32 reg; -- -- reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); -- if (reg & SYSCFG0_XTAL_FREQ_SEL) -- return MHZ(40); -- -- return MHZ(20); --} -- --static __init unsigned long --mt7620_get_periph_rate(unsigned long xtal_rate) --{ -- u32 reg; -- -- reg = rt_sysc_r32(SYSC_REG_CLKCFG0); -- if (reg & CLKCFG0_PERI_CLK_SEL) -- return xtal_rate; -- -- return MHZ(40); --} -- --static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 }; -- --static __init unsigned long --mt7620_get_cpu_pll_rate(unsigned long xtal_rate) --{ -- u32 reg; -- u32 mul; -- u32 div; -- -- reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); -- if (reg & CPLL_CFG0_BYPASS_REF_CLK) -- return xtal_rate; -- -- if ((reg & CPLL_CFG0_SW_CFG) == 0) -- return MHZ(600); -- -- mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & -- CPLL_CFG0_PLL_MULT_RATIO_MASK; -- mul += 24; -- if (reg & CPLL_CFG0_LC_CURFCK) -- mul *= 2; -- -- div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & -- CPLL_CFG0_PLL_DIV_RATIO_MASK; -- -- WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider)); -- -- return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]); --} -- --static __init unsigned long --mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate) --{ -- u32 reg; -- -- reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); -- if (reg & CPLL_CFG1_CPU_AUX1) -- return xtal_rate; -- -- if (reg & CPLL_CFG1_CPU_AUX0) -- return MHZ(480); -- -- return cpu_pll_rate; --} -- --static __init unsigned long --mt7620_get_cpu_rate(unsigned long pll_rate) --{ -- u32 reg; -- u32 mul; -- u32 div; -- -- reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); -- -- mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; -- div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & -- CPU_SYS_CLKCFG_CPU_FDIV_MASK; -- -- return mt7620_calc_rate(pll_rate, mul, div); --} -- --static const u32 mt7620_ocp_dividers[16] __initconst = { -- [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2, -- [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3, -- [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4, -- [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5, -- [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10, --}; -- --static __init unsigned long --mt7620_get_dram_rate(unsigned long pll_rate) --{ -- if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM) -- return pll_rate / 4; -- -- return pll_rate / 3; --} -- --static __init unsigned long --mt7620_get_sys_rate(unsigned long cpu_rate) --{ -- u32 reg; -- u32 ocp_ratio; -- u32 div; -- -- reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); -- -- ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & -- CPU_SYS_CLKCFG_OCP_RATIO_MASK; -- -- if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers))) -- return cpu_rate; -- -- div = mt7620_ocp_dividers[ocp_ratio]; -- if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio)) -- return cpu_rate; -- -- return cpu_rate / div; --} -- --void __init ralink_clk_init(void) --{ -- unsigned long xtal_rate; -- unsigned long cpu_pll_rate; -- unsigned long pll_rate; -- unsigned long cpu_rate; -- unsigned long sys_rate; -- unsigned long dram_rate; -- unsigned long periph_rate; -- unsigned long pcmi2s_rate; -- -- xtal_rate = mt7620_get_xtal_rate(); -- --#define RFMT(label) label ":%lu.%03luMHz " --#define RINT(x) ((x) / 1000000) --#define RFRAC(x) (((x) / 1000) % 1000) -- -- if (is_mt76x8()) { -- if (xtal_rate == MHZ(40)) -- cpu_rate = MHZ(580); -- else -- cpu_rate = MHZ(575); -- dram_rate = sys_rate = cpu_rate / 3; -- periph_rate = MHZ(40); -- pcmi2s_rate = MHZ(480); -- -- ralink_clk_add("10000d00.uartlite", periph_rate); -- ralink_clk_add("10000e00.uartlite", periph_rate); -- } else { -- cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); -- pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); -- -- cpu_rate = mt7620_get_cpu_rate(pll_rate); -- dram_rate = mt7620_get_dram_rate(pll_rate); -- sys_rate = mt7620_get_sys_rate(cpu_rate); -- periph_rate = mt7620_get_periph_rate(xtal_rate); -- pcmi2s_rate = periph_rate; -- -- pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"), -- RINT(xtal_rate), RFRAC(xtal_rate), -- RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), -- RINT(pll_rate), RFRAC(pll_rate)); -- -- ralink_clk_add("10000500.uart", periph_rate); -- } -- -- pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), -- RINT(cpu_rate), RFRAC(cpu_rate), -- RINT(dram_rate), RFRAC(dram_rate), -- RINT(sys_rate), RFRAC(sys_rate), -- RINT(periph_rate), RFRAC(periph_rate)); --#undef RFRAC --#undef RINT --#undef RFMT -- -- ralink_clk_add("cpu", cpu_rate); -- ralink_clk_add("10000100.timer", periph_rate); -- ralink_clk_add("10000120.watchdog", periph_rate); -- ralink_clk_add("10000900.i2c", periph_rate); -- ralink_clk_add("10000a00.i2s", pcmi2s_rate); -- ralink_clk_add("10000b00.spi", sys_rate); -- ralink_clk_add("10000b40.spi", sys_rate); -- ralink_clk_add("10000c00.uartlite", periph_rate); -- ralink_clk_add("10000d00.uart1", periph_rate); -- ralink_clk_add("10000e00.uart2", periph_rate); -- ralink_clk_add("10180000.wmac", xtal_rate); -- -- if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { -- /* -- * When the CPU goes into sleep mode, the BUS clock will be -- * too low for USB to function properly. Adjust the busses -- * fractional divider to fix this -- */ -- u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); -- -- val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); -- val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; -- -- rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); -- } --} -- - void __init ralink_of_remap(void) - { - rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); diff --git a/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch deleted file mode 100644 index e96a9084a63d9e..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-07-mips-ralink-remove-reset-related-code.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 201ddc05777cd8e084b508bcdda22214bfe2895e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:39 +0200 -Subject: [PATCH 7/9] mips: ralink: remove reset related code - -A proper clock driver for ralink SoCs has been added. This driver is also -a reset provider for the SoC. Hence there is no need to have reset related -code in 'arch/mips/ralink' folder anymore. The only code that remains is -the one related with mips_reboot_setup where a PCI reset is performed. -We maintain this because I cannot test old ralink board with PCI to be -sure all works if we remove also this code. - -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/ralink/common.h | 2 -- - arch/mips/ralink/of.c | 4 ---- - arch/mips/ralink/reset.c | 61 ----------------------------------------------- - 3 files changed, 67 deletions(-) - ---- a/arch/mips/ralink/common.h -+++ b/arch/mips/ralink/common.h -@@ -23,8 +23,6 @@ extern struct ralink_soc_info soc_info; - - extern void ralink_of_remap(void); - --extern void ralink_rst_init(void); -- - extern void __init prom_soc_init(struct ralink_soc_info *soc_info); - - __iomem void *plat_of_remap_node(const char *node); ---- a/arch/mips/ralink/of.c -+++ b/arch/mips/ralink/of.c -@@ -81,10 +81,6 @@ static int __init plat_of_setup(void) - { - __dt_register_buses(soc_info.compatible, "palmbus"); - -- /* make sure that the reset controller is setup early */ -- if (ralink_soc != MT762X_SOC_MT7621AT) -- ralink_rst_init(); -- - return 0; - } - ---- a/arch/mips/ralink/reset.c -+++ b/arch/mips/ralink/reset.c -@@ -10,7 +10,6 @@ - #include - #include - #include --#include - - #include - -@@ -22,66 +21,6 @@ - #define RSTCTL_RESET_PCI BIT(26) - #define RSTCTL_RESET_SYSTEM BIT(0) - --static int ralink_assert_device(struct reset_controller_dev *rcdev, -- unsigned long id) --{ -- u32 val; -- -- if (id == 0) -- return -1; -- -- val = rt_sysc_r32(SYSC_REG_RESET_CTRL); -- val |= BIT(id); -- rt_sysc_w32(val, SYSC_REG_RESET_CTRL); -- -- return 0; --} -- --static int ralink_deassert_device(struct reset_controller_dev *rcdev, -- unsigned long id) --{ -- u32 val; -- -- if (id == 0) -- return -1; -- -- val = rt_sysc_r32(SYSC_REG_RESET_CTRL); -- val &= ~BIT(id); -- rt_sysc_w32(val, SYSC_REG_RESET_CTRL); -- -- return 0; --} -- --static int ralink_reset_device(struct reset_controller_dev *rcdev, -- unsigned long id) --{ -- ralink_assert_device(rcdev, id); -- return ralink_deassert_device(rcdev, id); --} -- --static const struct reset_control_ops reset_ops = { -- .reset = ralink_reset_device, -- .assert = ralink_assert_device, -- .deassert = ralink_deassert_device, --}; -- --static struct reset_controller_dev reset_dev = { -- .ops = &reset_ops, -- .owner = THIS_MODULE, -- .nr_resets = 32, -- .of_reset_n_cells = 1, --}; -- --void ralink_rst_init(void) --{ -- reset_dev.of_node = of_find_compatible_node(NULL, NULL, -- "ralink,rt2880-reset"); -- if (!reset_dev.of_node) -- pr_err("Failed to find reset controller node"); -- else -- reset_controller_register(&reset_dev); --} -- - static void ralink_restart(char *command) - { - if (IS_ENABLED(CONFIG_PCI)) { diff --git a/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch b/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch deleted file mode 100644 index 2430c1f3753ce7..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-08-mips-ralink-get-cpu-rate-from-new-driver-code.patch +++ /dev/null @@ -1,102 +0,0 @@ -From ad38c17b0c26ae2108b50ac1eb0281a2e1ce08e9 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:40 +0200 -Subject: [PATCH 8/9] mips: ralink: get cpu rate from new driver code - -At very early stage on boot, there is a need to set 'mips_hpt_frequency'. -This timer frequency is a half of the CPU frequency. To get clocks properly -set we need to call to 'of_clk_init()' and properly get cpu clock frequency -afterwards. Depending on the SoC, CPU clock index and compatible differs, so -use them to get the proper clock frm the clock provider. Hence, adapt code -to be aligned with new clock driver. - -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/ralink/clk.c | 61 ++++++++++++++++++++++++++++++++++++++++++-------- - 1 file changed, 52 insertions(+), 9 deletions(-) - ---- a/arch/mips/ralink/clk.c -+++ b/arch/mips/ralink/clk.c -@@ -11,29 +11,72 @@ - #include - #include - #include -+#include - - #include - - #include "common.h" - --void ralink_clk_add(const char *dev, unsigned long rate) -+static const char *clk_cpu(int *idx) - { -- struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate); -- -- if (!clk) -- panic("failed to add clock"); -- -- clkdev_create(clk, NULL, "%s", dev); -+ switch (ralink_soc) { -+ case RT2880_SOC: -+ *idx = 0; -+ return "ralink,rt2880-sysc"; -+ case RT3883_SOC: -+ *idx = 0; -+ return "ralink,rt3883-sysc"; -+ case RT305X_SOC_RT3050: -+ *idx = 0; -+ return "ralink,rt3050-sysc"; -+ case RT305X_SOC_RT3052: -+ *idx = 0; -+ return "ralink,rt3052-sysc"; -+ case RT305X_SOC_RT3350: -+ *idx = 1; -+ return "ralink,rt3350-sysc"; -+ case RT305X_SOC_RT3352: -+ *idx = 1; -+ return "ralink,rt3352-sysc"; -+ case RT305X_SOC_RT5350: -+ *idx = 1; -+ return "ralink,rt5350-sysc"; -+ case MT762X_SOC_MT7620A: -+ *idx = 2; -+ return "ralink,mt7620-sysc"; -+ case MT762X_SOC_MT7620N: -+ *idx = 2; -+ return "ralink,mt7620-sysc"; -+ case MT762X_SOC_MT7628AN: -+ *idx = 1; -+ return "ralink,mt7628-sysc"; -+ case MT762X_SOC_MT7688: -+ *idx = 1; -+ return "ralink,mt7688-sysc"; -+ default: -+ *idx = -1; -+ return "invalid"; -+ } - } - - void __init plat_time_init(void) - { -+ struct of_phandle_args clkspec; -+ const char *compatible; - struct clk *clk; -+ int cpu_clk_idx; - - ralink_of_remap(); - -- ralink_clk_init(); -- clk = clk_get_sys("cpu", NULL); -+ compatible = clk_cpu(&cpu_clk_idx); -+ if (cpu_clk_idx == -1) -+ panic("unable to get CPU clock index"); -+ -+ of_clk_init(NULL); -+ clkspec.np = of_find_compatible_node(NULL, NULL, compatible); -+ clkspec.args_count = 1; -+ clkspec.args[0] = cpu_clk_idx; -+ clk = of_clk_get_from_provider(&clkspec); - if (IS_ERR(clk)) - panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); - pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); diff --git a/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch b/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch deleted file mode 100644 index f7ab99bc761022..00000000000000 --- a/target/linux/ramips/patches-6.1/005-v6.5-09-MAINTAINERS-add-Mediatek-MTMIPS-Clock-maintainer.patch +++ /dev/null @@ -1,28 +0,0 @@ -From fc15a7193a4d37d79e873fa06cc423180ddd2ddf Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Mon, 19 Jun 2023 06:09:41 +0200 -Subject: [PATCH 9/9] MAINTAINERS: add Mediatek MTMIPS Clock maintainer - -Adding myself as maintainer for Mediatek MTMIPS clock driver. - -Signed-off-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - MAINTAINERS | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -13021,6 +13021,12 @@ S: Maintained - F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml - F: drivers/clk/ralink/clk-mt7621.c - -+MEDIATEK MTMIPS CLOCK DRIVER -+M: Sergio Paracuellos -+S: Maintained -+F: Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml -+F: drivers/clk/ralink/clk-mtmips.c -+ - MEDIATEK MT7621/28/88 I2C DRIVER - M: Stefan Roese - L: linux-i2c@vger.kernel.org diff --git a/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch b/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch deleted file mode 100644 index f5c148101f0051..00000000000000 --- a/target/linux/ramips/patches-6.1/006-v6.5-mips-ralink-introduce-commonly-used-remap-node-funct.patch +++ /dev/null @@ -1,191 +0,0 @@ -From fd99ac5055d4705e91c73d1adba18bc71c8511a8 Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Tue, 20 Jun 2023 19:44:32 +0800 -Subject: [PATCH] mips: ralink: introduce commonly used remap node function - -The ralink_of_remap() function is repeated several times on SoC specific -source files. They have the same structure, but just differ in compatible -strings. In order to make commonly use of these codes, this patch -introduces a newly designed mtmips_of_remap_node() function to match and -remap all supported system controller and memory controller nodes. - -Build and run tested on MT7620 and MT7628. - -Signed-off-by: Shiji Yang -Reviewed-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/ralink/common.h | 2 -- - arch/mips/ralink/mt7620.c | 9 --------- - arch/mips/ralink/mt7621.c | 9 --------- - arch/mips/ralink/of.c | 42 +++++++++++++++++++++++++++++++++++------- - arch/mips/ralink/rt288x.c | 9 --------- - arch/mips/ralink/rt305x.c | 9 --------- - arch/mips/ralink/rt3883.c | 9 --------- - 7 files changed, 35 insertions(+), 54 deletions(-) - ---- a/arch/mips/ralink/common.h -+++ b/arch/mips/ralink/common.h -@@ -25,6 +25,4 @@ extern void ralink_of_remap(void); - - extern void __init prom_soc_init(struct ralink_soc_info *soc_info); - --__iomem void *plat_of_remap_node(const char *node); -- - #endif /* _RALINK_COMMON_H__ */ ---- a/arch/mips/ralink/mt7620.c -+++ b/arch/mips/ralink/mt7620.c -@@ -43,15 +43,6 @@ - /* does the board have sdram or ddram */ - static int dram_type; - --void __init ralink_of_remap(void) --{ -- rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); -- rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc"); -- -- if (!rt_sysc_membase || !rt_memc_membase) -- panic("Failed to remap core resources"); --} -- - static __init void - mt7620_dram_init(struct ralink_soc_info *soc_info) - { ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -89,15 +89,6 @@ static void __init mt7621_memory_detect( - memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE); - } - --void __init ralink_of_remap(void) --{ -- rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc"); -- rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc"); -- -- if (!rt_sysc_membase || !rt_memc_membase) -- panic("Failed to remap core resources"); --} -- - static unsigned int __init mt7621_get_soc_name0(void) - { - return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0); ---- a/arch/mips/ralink/of.c -+++ b/arch/mips/ralink/of.c -@@ -29,28 +29,56 @@ __iomem void *rt_sysc_membase; - __iomem void *rt_memc_membase; - EXPORT_SYMBOL_GPL(rt_sysc_membase); - --__iomem void *plat_of_remap_node(const char *node) -+static const struct of_device_id mtmips_memc_match[] = { -+ { .compatible = "mediatek,mt7621-memc" }, -+ { .compatible = "ralink,mt7620a-memc" }, -+ { .compatible = "ralink,rt2880-memc" }, -+ { .compatible = "ralink,rt3050-memc" }, -+ { .compatible = "ralink,rt3883-memc" }, -+ {} -+}; -+ -+static const struct of_device_id mtmips_sysc_match[] = { -+ { .compatible = "mediatek,mt7621-sysc" }, -+ { .compatible = "ralink,mt7620a-sysc" }, -+ { .compatible = "ralink,rt2880-sysc" }, -+ { .compatible = "ralink,rt3050-sysc" }, -+ { .compatible = "ralink,rt3883-sysc" }, -+ {} -+}; -+ -+static __iomem void * -+mtmips_of_remap_node(const struct of_device_id *match, const char *type) - { - struct resource res; - struct device_node *np; - -- np = of_find_compatible_node(NULL, NULL, node); -+ np = of_find_matching_node(NULL, match); - if (!np) -- panic("Failed to find %s node", node); -+ panic("Failed to find %s controller node", type); - - if (of_address_to_resource(np, 0, &res)) -- panic("Failed to get resource for %s", node); -- -- of_node_put(np); -+ panic("Failed to get resource for %s node", np->name); - - if (!request_mem_region(res.start, - resource_size(&res), - res.name)) -- panic("Failed to request resources for %s", node); -+ panic("Failed to request resources for %s node", np->name); -+ -+ of_node_put(np); - - return ioremap(res.start, resource_size(&res)); - } - -+void __init ralink_of_remap(void) -+{ -+ rt_sysc_membase = mtmips_of_remap_node(mtmips_sysc_match, "system"); -+ rt_memc_membase = mtmips_of_remap_node(mtmips_memc_match, "memory"); -+ -+ if (!rt_sysc_membase || !rt_memc_membase) -+ panic("Failed to remap core resources"); -+} -+ - void __init plat_mem_setup(void) - { - void *dtb; ---- a/arch/mips/ralink/rt288x.c -+++ b/arch/mips/ralink/rt288x.c -@@ -17,15 +17,6 @@ - - #include "common.h" - --void __init ralink_of_remap(void) --{ -- rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc"); -- rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc"); -- -- if (!rt_sysc_membase || !rt_memc_membase) -- panic("Failed to remap core resources"); --} -- - void __init prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE); ---- a/arch/mips/ralink/rt305x.c -+++ b/arch/mips/ralink/rt305x.c -@@ -53,15 +53,6 @@ static unsigned long rt5350_get_mem_size - return ret; - } - --void __init ralink_of_remap(void) --{ -- rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); -- rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); -- -- if (!rt_sysc_membase || !rt_memc_membase) -- panic("Failed to remap core resources"); --} -- - void __init prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); ---- a/arch/mips/ralink/rt3883.c -+++ b/arch/mips/ralink/rt3883.c -@@ -17,15 +17,6 @@ - - #include "common.h" - --void __init ralink_of_remap(void) --{ -- rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc"); -- rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc"); -- -- if (!rt_sysc_membase || !rt_memc_membase) -- panic("Failed to remap core resources"); --} -- - void __init prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE); diff --git a/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch b/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch deleted file mode 100644 index c0c2a6e204fcd5..00000000000000 --- a/target/linux/ramips/patches-6.1/007-v6.5-clk-ralink-mtmips-Fix-uninitialized-use-of-ret-in-mt.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 6e68dae946e3a0333fbde5487ce163142ca10ae0 Mon Sep 17 00:00:00 2001 -From: Nathan Chancellor -Date: Thu, 22 Jun 2023 15:56:19 +0000 -Subject: clk: ralink: mtmips: Fix uninitialized use of ret in - mtmips_register_{fixed,factor}_clocks() - -Clang warns: - - drivers/clk/ralink/clk-mtmips.c:309:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] - 309 | return ret; - | ^~~ - drivers/clk/ralink/clk-mtmips.c:285:9: note: initialize the variable 'ret' to silence this warning - 285 | int ret, i; - | ^ - | = 0 - drivers/clk/ralink/clk-mtmips.c:359:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized] - 359 | return ret; - | ^~~ - drivers/clk/ralink/clk-mtmips.c:335:9: note: initialize the variable 'ret' to silence this warning - 335 | int ret, i; - | ^ - | = 0 - 2 errors generated. - -Set ret to the return value of clk_hw_register_fixed_rate() using the -PTR_ERR() macro, which ensures ret is not used uninitialized, clearing -up the warning. - -Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs") -Closes: https://github.com/ClangBuiltLinux/linux/issues/1879 -Signed-off-by: Nathan Chancellor -Reviewed-by: Nick Desaulniers -Acked-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - drivers/clk/ralink/clk-mtmips.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/clk/ralink/clk-mtmips.c -+++ b/drivers/clk/ralink/clk-mtmips.c -@@ -292,6 +292,7 @@ static int mtmips_register_fixed_clocks( - sclk->parent, 0, - sclk->rate); - if (IS_ERR(sclk->hw)) { -+ ret = PTR_ERR(sclk->hw); - pr_err("Couldn't register fixed clock %d\n", idx); - goto err_clk_unreg; - } -@@ -342,6 +343,7 @@ static int mtmips_register_factor_clocks - sclk->parent, sclk->flags, - sclk->mult, sclk->div); - if (IS_ERR(sclk->hw)) { -+ ret = PTR_ERR(sclk->hw); - pr_err("Couldn't register factor clock %d\n", idx); - goto err_clk_unreg; - } diff --git a/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch b/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch deleted file mode 100644 index 6940a2b4b98c02..00000000000000 --- a/target/linux/ramips/patches-6.1/008-v6.5-mips-ralink-match-all-supported-system-controller-co.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 670f77f76f650b1b341d31d009cc2fb03a4d1fcf Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Fri, 23 Jun 2023 08:17:48 +0800 -Subject: mips: ralink: match all supported system controller compatible - strings - -Recently, A new clock and reset controller driver has been introduced to -the ralink mips target[1]. It provides proper system control and adds more -SoC specific compatible strings. In order to better initialize CPUs, this -patch removes the outdated "ralink,mt7620a-sysc" and add all dt-binding -documented compatible strings to the system controller match table. - -[1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com/ - -Signed-off-by: Shiji Yang -Reviewed-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/ralink/of.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/arch/mips/ralink/of.c -+++ b/arch/mips/ralink/of.c -@@ -40,10 +40,15 @@ static const struct of_device_id mtmips_ - - static const struct of_device_id mtmips_sysc_match[] = { - { .compatible = "mediatek,mt7621-sysc" }, -- { .compatible = "ralink,mt7620a-sysc" }, -+ { .compatible = "ralink,mt7620-sysc" }, -+ { .compatible = "ralink,mt7628-sysc" }, -+ { .compatible = "ralink,mt7688-sysc" }, - { .compatible = "ralink,rt2880-sysc" }, - { .compatible = "ralink,rt3050-sysc" }, -+ { .compatible = "ralink,rt3052-sysc" }, -+ { .compatible = "ralink,rt3352-sysc" }, - { .compatible = "ralink,rt3883-sysc" }, -+ { .compatible = "ralink,rt5350-sysc" }, - {} - }; - diff --git a/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch b/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch deleted file mode 100644 index e06d5621e10fd7..00000000000000 --- a/target/linux/ramips/patches-6.1/009-v6.3-01-watchdog-mt7621-wdt-avoid-static-global-declarations.patch +++ /dev/null @@ -1,213 +0,0 @@ -From 783c7cb4659b53b5e1b809dac5e8cdf250145919 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Tue, 14 Feb 2023 11:39:35 +0100 -Subject: [PATCH 1/2] watchdog: mt7621-wdt: avoid static global declarations - -Instead of using static global definitions in driver code, refactor code -introducing a new watchdog driver data structure and use it along the -code. - -Reviewed-by: Guenter Roeck -Signed-off-by: Sergio Paracuellos -Link: https://lore.kernel.org/r/20230214103936.1061078-5-sergio.paracuellos@gmail.com -[groeck: unsigned -> unsigned int] -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/mt7621_wdt.c | 102 +++++++++++++++++++++++++++--------------- - 1 file changed, 65 insertions(+), 37 deletions(-) - ---- a/drivers/watchdog/mt7621_wdt.c -+++ b/drivers/watchdog/mt7621_wdt.c -@@ -31,8 +31,11 @@ - #define TMR1CTL_RESTART BIT(9) - #define TMR1CTL_PRESCALE_SHIFT 16 - --static void __iomem *mt7621_wdt_base; --static struct reset_control *mt7621_wdt_reset; -+struct mt7621_wdt_data { -+ void __iomem *base; -+ struct reset_control *rst; -+ struct watchdog_device wdt; -+}; - - static bool nowayout = WATCHDOG_NOWAYOUT; - module_param(nowayout, bool, 0); -@@ -40,27 +43,31 @@ MODULE_PARM_DESC(nowayout, - "Watchdog cannot be stopped once started (default=" - __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); - --static inline void rt_wdt_w32(unsigned reg, u32 val) -+static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val) - { -- iowrite32(val, mt7621_wdt_base + reg); -+ iowrite32(val, base + reg); - } - --static inline u32 rt_wdt_r32(unsigned reg) -+static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg) - { -- return ioread32(mt7621_wdt_base + reg); -+ return ioread32(base + reg); - } - - static int mt7621_wdt_ping(struct watchdog_device *w) - { -- rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART); -+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); -+ -+ rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); - - return 0; - } - - static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t) - { -+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); -+ - w->timeout = t; -- rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000); -+ rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000); - mt7621_wdt_ping(w); - - return 0; -@@ -68,29 +75,31 @@ static int mt7621_wdt_set_timeout(struct - - static int mt7621_wdt_start(struct watchdog_device *w) - { -+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); - u32 t; - - /* set the prescaler to 1ms == 1000us */ -- rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); -+ rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); - - mt7621_wdt_set_timeout(w, w->timeout); - -- t = rt_wdt_r32(TIMER_REG_TMR1CTL); -+ t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL); - t |= TMR1CTL_ENABLE; -- rt_wdt_w32(TIMER_REG_TMR1CTL, t); -+ rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t); - - return 0; - } - - static int mt7621_wdt_stop(struct watchdog_device *w) - { -+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); - u32 t; - - mt7621_wdt_ping(w); - -- t = rt_wdt_r32(TIMER_REG_TMR1CTL); -+ t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL); - t &= ~TMR1CTL_ENABLE; -- rt_wdt_w32(TIMER_REG_TMR1CTL, t); -+ rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t); - - return 0; - } -@@ -105,7 +114,9 @@ static int mt7621_wdt_bootcause(void) - - static int mt7621_wdt_is_running(struct watchdog_device *w) - { -- return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE); -+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w); -+ -+ return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE); - } - - static const struct watchdog_info mt7621_wdt_info = { -@@ -121,30 +132,39 @@ static const struct watchdog_ops mt7621_ - .set_timeout = mt7621_wdt_set_timeout, - }; - --static struct watchdog_device mt7621_wdt_dev = { -- .info = &mt7621_wdt_info, -- .ops = &mt7621_wdt_ops, -- .min_timeout = 1, -- .max_timeout = 0xfffful / 1000, --}; -- - static int mt7621_wdt_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -- mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0); -- if (IS_ERR(mt7621_wdt_base)) -- return PTR_ERR(mt7621_wdt_base); -- -- mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL); -- if (!IS_ERR(mt7621_wdt_reset)) -- reset_control_deassert(mt7621_wdt_reset); -- -- mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause(); -- -- watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout, -- dev); -- watchdog_set_nowayout(&mt7621_wdt_dev, nowayout); -- if (mt7621_wdt_is_running(&mt7621_wdt_dev)) { -+ struct watchdog_device *mt7621_wdt; -+ struct mt7621_wdt_data *drvdata; -+ int err; -+ -+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); -+ if (!drvdata) -+ return -ENOMEM; -+ -+ drvdata->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(drvdata->base)) -+ return PTR_ERR(drvdata->base); -+ -+ drvdata->rst = devm_reset_control_get_exclusive(dev, NULL); -+ if (!IS_ERR(drvdata->rst)) -+ reset_control_deassert(drvdata->rst); -+ -+ mt7621_wdt = &drvdata->wdt; -+ mt7621_wdt->info = &mt7621_wdt_info; -+ mt7621_wdt->ops = &mt7621_wdt_ops; -+ mt7621_wdt->min_timeout = 1; -+ mt7621_wdt->max_timeout = 0xfffful / 1000; -+ mt7621_wdt->parent = dev; -+ -+ mt7621_wdt->bootstatus = mt7621_wdt_bootcause(); -+ -+ watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev); -+ watchdog_set_nowayout(mt7621_wdt, nowayout); -+ watchdog_set_drvdata(mt7621_wdt, drvdata); -+ -+ if (mt7621_wdt_is_running(mt7621_wdt)) { - /* - * Make sure to apply timeout from watchdog core, taking - * the prescaler of this driver here into account (the -@@ -154,17 +174,25 @@ static int mt7621_wdt_probe(struct platf - * we first disable the watchdog, set the new prescaler - * and timeout, and then re-enable the watchdog. - */ -- mt7621_wdt_stop(&mt7621_wdt_dev); -- mt7621_wdt_start(&mt7621_wdt_dev); -- set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status); -+ mt7621_wdt_stop(mt7621_wdt); -+ mt7621_wdt_start(mt7621_wdt); -+ set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status); - } - -- return devm_watchdog_register_device(dev, &mt7621_wdt_dev); -+ err = devm_watchdog_register_device(dev, &drvdata->wdt); -+ if (err) -+ return err; -+ -+ platform_set_drvdata(pdev, drvdata); -+ -+ return 0; - } - - static void mt7621_wdt_shutdown(struct platform_device *pdev) - { -- mt7621_wdt_stop(&mt7621_wdt_dev); -+ struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev); -+ -+ mt7621_wdt_stop(&drvdata->wdt); - } - - static const struct of_device_id mt7621_wdt_match[] = { diff --git a/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch b/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch deleted file mode 100644 index 7e4e45df13fe82..00000000000000 --- a/target/linux/ramips/patches-6.1/009-v6.3-02-watchdog-mt7621-wdt-avoid-ralink-architecture-depend.patch +++ /dev/null @@ -1,104 +0,0 @@ -From ff8ec4ac39ad413b580d611dbf68e1d8a82eba56 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Tue, 14 Feb 2023 11:39:36 +0100 -Subject: [PATCH 2/2] watchdog: mt7621-wdt: avoid ralink architecture dependent code - -MT7621 SoC has a system controller node. Watchdog need to access to reset -status register. Ralink architecture and related driver are old and from -the beggining they are using some architecture dependent operations for -accessing this shared registers through 'asm/mach-ralink/ralink_regs.h' -header file. However this is not ideal from a driver perspective which can -just access to the system controller registers in an arch independent way -using regmap syscon APIs. Update Kconfig accordingly to select new added -dependencies and allow driver to be compile tested. - -Signed-off-by: Sergio Paracuellos -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20230214103936.1061078-6-sergio.paracuellos@gmail.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/Kconfig | 4 +++- - drivers/watchdog/mt7621_wdt.c | 22 +++++++++++++++++----- - 2 files changed, 20 insertions(+), 6 deletions(-) - ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -1865,7 +1865,9 @@ config GXP_WATCHDOG - config MT7621_WDT - tristate "Mediatek SoC watchdog" - select WATCHDOG_CORE -- depends on SOC_MT7620 || SOC_MT7621 -+ select REGMAP_MMIO -+ select MFD_SYSCON -+ depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST - help - Hardware driver for the Mediatek/Ralink MT7621/8 SoC Watchdog Timer. - ---- a/drivers/watchdog/mt7621_wdt.c -+++ b/drivers/watchdog/mt7621_wdt.c -@@ -15,8 +15,8 @@ - #include - #include - #include -- --#include -+#include -+#include - - #define SYSC_RSTSTAT 0x38 - #define WDT_RST_CAUSE BIT(1) -@@ -34,6 +34,7 @@ - struct mt7621_wdt_data { - void __iomem *base; - struct reset_control *rst; -+ struct regmap *sysc; - struct watchdog_device wdt; - }; - -@@ -104,9 +105,12 @@ static int mt7621_wdt_stop(struct watchd - return 0; - } - --static int mt7621_wdt_bootcause(void) -+static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d) - { -- if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) -+ u32 val; -+ -+ regmap_read(d->sysc, SYSC_RSTSTAT, &val); -+ if (val & WDT_RST_CAUSE) - return WDIOF_CARDRESET; - - return 0; -@@ -134,6 +138,7 @@ static const struct watchdog_ops mt7621_ - - static int mt7621_wdt_probe(struct platform_device *pdev) - { -+ struct device_node *np = pdev->dev.of_node; - struct device *dev = &pdev->dev; - struct watchdog_device *mt7621_wdt; - struct mt7621_wdt_data *drvdata; -@@ -143,6 +148,13 @@ static int mt7621_wdt_probe(struct platf - if (!drvdata) - return -ENOMEM; - -+ drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "mediatek,sysctl"); -+ if (IS_ERR(drvdata->sysc)) { -+ drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc"); -+ if (IS_ERR(drvdata->sysc)) -+ return PTR_ERR(drvdata->sysc); -+ } -+ - drvdata->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(drvdata->base)) - return PTR_ERR(drvdata->base); -@@ -158,7 +170,7 @@ static int mt7621_wdt_probe(struct platf - mt7621_wdt->max_timeout = 0xfffful / 1000; - mt7621_wdt->parent = dev; - -- mt7621_wdt->bootstatus = mt7621_wdt_bootcause(); -+ mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata); - - watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev); - watchdog_set_nowayout(mt7621_wdt, nowayout); diff --git a/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch b/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch deleted file mode 100644 index 704e861b8211dc..00000000000000 --- a/target/linux/ramips/patches-6.1/010-v6.5-01-mips-pci-mt7620-do-not-print-NFTS-register-value-as-.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 9f9a035e6156a57d9da062b26d2a48d031744a1e Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Tue, 20 Jun 2023 18:43:22 +0800 -Subject: [PATCH 1/2] mips: pci-mt7620: do not print NFTS register value as - error log - -These codes are used to read NFTS_TIMEOUT_DELAY register value and -write it into kernel log after writing the register. they are only -used for debugging during driver development, so there is no need -to keep them now. - -Tested on MT7628AN router Motorola MWR03. - -Signed-off-by: Shiji Yang -Reviewed-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/pci/pci-mt7620.c | 3 --- - 1 file changed, 3 deletions(-) - ---- a/arch/mips/pci/pci-mt7620.c -+++ b/arch/mips/pci/pci-mt7620.c -@@ -274,9 +274,6 @@ static int mt7628_pci_hw_init(struct pla - val |= 0x50 << 8; - pci_config_write(NULL, 0, 0x70c, 4, val); - -- pci_config_read(NULL, 0, 0x70c, 4, &val); -- dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val); -- - return 0; - } - diff --git a/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch b/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch deleted file mode 100644 index 5898a110ea972c..00000000000000 --- a/target/linux/ramips/patches-6.1/010-v6.5-02-mips-pci-mt7620-use-dev_info-to-log-PCIe-device-dete.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 89ec9bbe60b61cc6ae3eddd6d4f43e128f8a88de Mon Sep 17 00:00:00 2001 -From: Shiji Yang -Date: Tue, 20 Jun 2023 18:43:23 +0800 -Subject: [PATCH 2/2] mips: pci-mt7620: use dev_info() to log PCIe device - detection result - -Usually, We only need to print the error log when there is a PCIe card but -initialization fails. Whether the driver finds the PCIe card or not is the -expected behavior. So it's better to log these information with dev_info(). - -Tested on MT7628AN router Motorola MWR03. - -Signed-off-by: Shiji Yang -Reviewed-by: Sergio Paracuellos -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/pci/pci-mt7620.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/pci/pci-mt7620.c -+++ b/arch/mips/pci/pci-mt7620.c -@@ -331,7 +331,7 @@ static int mt7620_pci_probe(struct platf - rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); - if (ralink_soc == MT762X_SOC_MT7620A) - rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV); -- dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n"); -+ dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n"); - return -1; - } - -@@ -374,7 +374,7 @@ int pcibios_map_irq(const struct pci_dev - dev->bus->number, slot); - return 0; - } -- dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", -+ dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", - dev->bus->number, slot, irq); - - /* configure the cache line size to 0x14 */ diff --git a/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch b/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch deleted file mode 100644 index ad2191e6555744..00000000000000 --- a/target/linux/ramips/patches-6.1/110-v6.4-PCI-mt7621-Use-dev_info-to-log-PCIe-card-detection.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 50233e105a0332ec0f3bc83180c416e6b200471e Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Fri, 24 Mar 2023 08:37:33 +0100 -Subject: PCI: mt7621: Use dev_info() to log PCIe card detection - -When there is no card plugged on a PCIe port a log reporting that -the port will be disabled is flagged as an error (dev_err()). - -Since this is not an error at all, change the log level by using -dev_info() instead. - -Link: https://lore.kernel.org/r/20230324073733.1596231-1-sergio.paracuellos@gmail.com -Signed-off-by: Sergio Paracuellos -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pcie-mt7621.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/pci/controller/pcie-mt7621.c -+++ b/drivers/pci/controller/pcie-mt7621.c -@@ -378,8 +378,8 @@ static int mt7621_pcie_init_ports(struct - u32 slot = port->slot; - - if (!mt7621_pcie_port_is_linkup(port)) { -- dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", -- slot); -+ dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n", -+ slot); - mt7621_control_assert(port); - port->enabled = false; - num_disabled++; diff --git a/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch b/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch deleted file mode 100644 index c52c12526b4ce1..00000000000000 --- a/target/linux/ramips/patches-6.1/200-add-ralink-eth.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -166,6 +166,7 @@ source "drivers/net/ethernet/pensando/Kc - source "drivers/net/ethernet/qlogic/Kconfig" - source "drivers/net/ethernet/brocade/Kconfig" - source "drivers/net/ethernet/qualcomm/Kconfig" -+source "drivers/net/ethernet/ralink/Kconfig" - source "drivers/net/ethernet/rdc/Kconfig" - source "drivers/net/ethernet/realtek/Kconfig" - source "drivers/net/ethernet/renesas/Kconfig" ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -77,6 +77,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES) - obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/ - obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/ - obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/ -+obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/ - obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/ - obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/ - obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ diff --git a/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch b/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch deleted file mode 100644 index 4f4fe9018a1cec..00000000000000 --- a/target/linux/ramips/patches-6.1/300-mt7620-export-chip-version-and-pkg.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -61,4 +61,16 @@ static inline int mt7620_get_eco(void) - return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; - } - -+static inline int mt7620_get_chipver(void) -+{ -+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) & -+ CHIP_REV_VER_MASK; -+} -+ -+static inline int mt7620_get_pkg(void) -+{ -+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) & -+ CHIP_REV_PKG_MASK; -+} -+ - #endif diff --git a/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch deleted file mode 100644 index 172cf98ad153dc..00000000000000 --- a/target/linux/ramips/patches-6.1/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch +++ /dev/null @@ -1,100 +0,0 @@ -From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 14 Jul 2013 23:08:11 +0200 -Subject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k - irq - -Signed-off-by: John Crispin ---- - arch/mips/ralink/Kconfig | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -1,12 +1,17 @@ - # SPDX-License-Identifier: GPL-2.0 - if RALINK - -+config CEVT_SYSTICK_QUIRK -+ bool -+ default n -+ - config CLKEVT_RT3352 - bool - depends on SOC_RT305X || SOC_MT7620 - default y - select TIMER_OF - select CLKSRC_MMIO -+ select CEVT_SYSTICK_QUIRK - - config RALINK_ILL_ACC - bool ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -16,6 +16,31 @@ - #include - #include - -+#ifdef CONFIG_CEVT_SYSTICK_QUIRK -+static int mips_state_oneshot(struct clock_event_device *evt) -+{ -+ unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; -+ if (!cp0_timer_irq_installed) { -+ cp0_timer_irq_installed = 1; -+ if (request_irq(evt->irq, c0_compare_interrupt, flags, "timer", -+ c0_compare_interrupt)) -+ pr_err("Failed to request irq %d (timer)\n", evt->irq); -+ } -+ -+ return 0; -+} -+ -+static int mips_state_shutdown(struct clock_event_device *evt) -+{ -+ if (cp0_timer_irq_installed) { -+ cp0_timer_irq_installed = 0; -+ free_irq(evt->irq, NULL); -+ } -+ -+ return 0; -+} -+#endif -+ - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -292,7 +317,9 @@ core_initcall(r4k_register_cpufreq_notif - - int r4k_clockevent_init(void) - { -+#ifndef CONFIG_CEVT_SYSTICK_QUIRK - unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; -+#endif - unsigned int cpu = smp_processor_id(); - struct clock_event_device *cd; - unsigned int irq, min_delta; -@@ -322,11 +349,16 @@ int r4k_clockevent_init(void) - cd->rating = 300; - cd->irq = irq; - cd->cpumask = cpumask_of(cpu); -+#ifdef CONFIG_CEVT_SYSTICK_QUIRK -+ cd->set_state_shutdown = mips_state_shutdown; -+ cd->set_state_oneshot = mips_state_oneshot; -+#endif - cd->set_next_event = mips_next_event; - cd->event_handler = mips_event_handler; - - clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff); - -+#ifndef CONFIG_CEVT_SYSTICK_QUIRK - if (cp0_timer_irq_installed) - return 0; - -@@ -335,6 +367,7 @@ int r4k_clockevent_init(void) - if (request_irq(irq, c0_compare_interrupt, flags, "timer", - c0_compare_interrupt)) - pr_err("Failed to request irq %d (timer)\n", irq); -+#endif - - return 0; - } diff --git a/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch b/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch deleted file mode 100644 index 0d70770941ecf8..00000000000000 --- a/target/linux/ramips/patches-6.1/312-MIPS-ralink-add-cpu-frequency-scaling.patch +++ /dev/null @@ -1,195 +0,0 @@ -From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 28 Jul 2013 16:26:41 +0200 -Subject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling - -This feature will break udelay() and cause the delay loop to have longer delays -when the frequency is scaled causing a performance hit. - -Signed-off-by: John Crispin ---- - arch/mips/ralink/cevt-rt3352.c | 38 ++++++++++++++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/arch/mips/ralink/cevt-rt3352.c -+++ b/arch/mips/ralink/cevt-rt3352.c -@@ -29,6 +29,10 @@ - /* enable the counter */ - #define CFG_CNT_EN 0x1 - -+/* mt7620 frequency scaling defines */ -+#define CLK_LUT_CFG 0x40 -+#define SLEEP_EN BIT(31) -+ - struct systick_device { - void __iomem *membase; - struct clock_event_device dev; -@@ -36,21 +40,53 @@ struct systick_device { - int freq_scale; - }; - -+static void (*systick_freq_scaling)(struct systick_device *sdev, int status); -+ - static int systick_set_oneshot(struct clock_event_device *evt); - static int systick_shutdown(struct clock_event_device *evt); - -+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) -+{ -+ if (sdev->freq_scale == status) -+ return; -+ -+ sdev->freq_scale = status; -+ -+ pr_info("%s: %s autosleep mode\n", sdev->dev.name, -+ (status) ? ("enable") : ("disable")); -+ if (status) -+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG); -+ else -+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG); -+} -+ -+static inline unsigned int read_count(struct systick_device *sdev) -+{ -+ return ioread32(sdev->membase + SYSTICK_COUNT); -+} -+ -+static inline unsigned int read_compare(struct systick_device *sdev) -+{ -+ return ioread32(sdev->membase + SYSTICK_COMPARE); -+} -+ -+static inline void write_compare(struct systick_device *sdev, unsigned int val) -+{ -+ iowrite32(val, sdev->membase + SYSTICK_COMPARE); -+} -+ - static int systick_next_event(unsigned long delta, - struct clock_event_device *evt) - { - struct systick_device *sdev; -- u32 count; -+ int res; - - sdev = container_of(evt, struct systick_device, dev); -- count = ioread32(sdev->membase + SYSTICK_COUNT); -- count = (count + delta) % SYSTICK_FREQ; -- iowrite32(count, sdev->membase + SYSTICK_COMPARE); -+ delta += read_count(sdev); -+ write_compare(sdev, delta); -+ res = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0; - -- return 0; -+ return res; - } - - static void systick_event_handler(struct clock_event_device *dev) -@@ -60,20 +96,25 @@ static void systick_event_handler(struct - - static irqreturn_t systick_interrupt(int irq, void *dev_id) - { -- struct clock_event_device *dev = (struct clock_event_device *) dev_id; -+ int ret = 0; -+ struct clock_event_device *cdev; -+ struct systick_device *sdev; - -- dev->event_handler(dev); -+ if (read_c0_cause() & STATUSF_IP7) { -+ cdev = (struct clock_event_device *) dev_id; -+ sdev = container_of(cdev, struct systick_device, dev); -+ -+ /* Clear Count/Compare Interrupt */ -+ write_compare(sdev, read_compare(sdev)); -+ cdev->event_handler(cdev); -+ ret = 1; -+ } - -- return IRQ_HANDLED; -+ return IRQ_RETVAL(ret); - } - - static struct systick_device systick = { - .dev = { -- /* -- * cevt-r4k uses 300, make sure systick -- * gets used if available -- */ -- .rating = 310, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = systick_next_event, - .set_state_shutdown = systick_shutdown, -@@ -91,7 +132,13 @@ static int systick_shutdown(struct clock - if (sdev->irq_requested) - free_irq(systick.dev.irq, &systick.dev); - sdev->irq_requested = 0; -- iowrite32(0, systick.membase + SYSTICK_CONFIG); -+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); -+ -+ if (systick_freq_scaling) -+ systick_freq_scaling(sdev, 0); -+ -+ if (systick_freq_scaling) -+ systick_freq_scaling(sdev, 1); - - return 0; - } -@@ -116,33 +163,46 @@ static int systick_set_oneshot(struct cl - return 0; - } - -+static const struct of_device_id systick_match[] = { -+ { .compatible = "ralink,mt7620a-systick", .data = mt7620_freq_scaling}, -+ {}, -+}; -+ - static int __init ralink_systick_init(struct device_node *np) - { -- int ret; -+ const struct of_device_id *match; -+ int rating = 200; - - systick.membase = of_iomap(np, 0); - if (!systick.membase) - return -ENXIO; - -- systick.dev.name = np->name; -- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60); -- systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev); -- systick.dev.max_delta_ticks = 0x7fff; -- systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev); -- systick.dev.min_delta_ticks = 0x3; -+ match = of_match_node(systick_match, np); -+ if (match) { -+ systick_freq_scaling = match->data; -+ /* -+ * cevt-r4k uses 300, make sure systick -+ * gets used if available -+ */ -+ rating = 310; -+ } -+ -+ /* enable counter than register clock source */ -+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); -+ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, -+ SYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up); -+ -+ /* register clock event */ - systick.dev.irq = irq_of_parse_and_map(np, 0); - if (!systick.dev.irq) { - pr_err("%pOFn: request_irq failed", np); - return -EINVAL; - } - -- ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, -- SYSTICK_FREQ, 301, 16, -- clocksource_mmio_readl_up); -- if (ret) -- return ret; -- -- clockevents_register_device(&systick.dev); -+ systick.dev.name = np->name; -+ systick.dev.rating = rating; -+ systick.dev.cpumask = cpumask_of(0); -+ clockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff); - - pr_info("%pOFn: running - mult: %d, shift: %d\n", - np, systick.dev.mult, systick.dev.shift); diff --git a/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch b/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch deleted file mode 100644 index 26a28167c637a1..00000000000000 --- a/target/linux/ramips/patches-6.1/314-MIPS-add-bootargs-override-property.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Thu, 31 Dec 2020 18:49:12 +0100 -Subject: [PATCH] MIPS: add bootargs-override property - -Add support for the bootargs-override property to the chosen node -similar to the one used on ipq806x or mpc85xx. - -This is necessary, as the U-Boot used on some boards, notably the -Ubiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen -node leading to a kernel panic when loading OpenWrt. - -Signed-off-by: David Bauer ---- - arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -557,8 +557,28 @@ static int __init bootcmdline_scan_chose - - #endif /* CONFIG_OF_EARLY_FLATTREE */ - -+static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname, -+ int depth, void *data) -+{ -+ bool *dt_bootargs = data; -+ const char *p; -+ int l; -+ -+ if (depth != 1 || !data || strcmp(uname, "chosen") != 0) -+ return 0; -+ -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) { -+ strlcpy(boot_command_line, p, COMMAND_LINE_SIZE); -+ *dt_bootargs = true; -+ } -+ -+ return 1; -+} -+ - static void __init bootcmdline_init(void) - { -+ bool dt_bootargs_override = false; - bool dt_bootargs = false; - - /* -@@ -572,6 +592,14 @@ static void __init bootcmdline_init(void - } - - /* -+ * If bootargs-override in the chosen node is set, use this as the -+ * command line -+ */ -+ of_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override); -+ if (dt_bootargs_override) -+ return; -+ -+ /* - * If the user specified a built-in command line & - * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is - * prepended to arguments from the bootloader or DT so we'll copy them diff --git a/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch deleted file mode 100644 index c31e6d7cde28f9..00000000000000 --- a/target/linux/ramips/patches-6.1/315-owrt-hack-fix-mt7688-cache-issue.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:15:32 +0100 -Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue - -Signed-off-by: John Crispin ---- - arch/mips/kernel/setup.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -699,7 +699,6 @@ static void __init arch_mem_init(char ** - mips_reserve_vmcore(); - - mips_parse_crashkernel(); -- device_tree_init(); - - /* - * In order to reduce the possibility of kernel panic when failed to -@@ -834,6 +833,7 @@ void __init setup_arch(char **cmdline_p) - - cpu_cache_init(); - paging_init(); -+ device_tree_init(); - - memblock_dump_all(); - diff --git a/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch b/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch deleted file mode 100644 index 1dc54ccf232627..00000000000000 --- a/target/linux/ramips/patches-6.1/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:18:05 +0100 -Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by - default - -Signed-off-by: John Crispin ---- - arch/mips/ralink/Kconfig | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -14,9 +14,9 @@ config CLKEVT_RT3352 - select CEVT_SYSTICK_QUIRK - - config RALINK_ILL_ACC -- bool -+ bool "illegal access irq" - depends on SOC_RT305X -- default y -+ default n - - config IRQ_INTC - bool diff --git a/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch b/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch deleted file mode 100644 index ef54835f89c2a3..00000000000000 --- a/target/linux/ramips/patches-6.1/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Wed, 7 Apr 2021 13:07:38 -0700 -Subject: [PATCH] MIPS: add support for buggy MT7621S core detection - -Most MT7621 SoCs have 2 cores, which is detected and supported properly -by CPS. - -Unfortunately, MT7621 SoC has a less common S variant with only one core. -On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when -starting SMP. CPULAUNCH registers can be used in that case to detect the -absence of the second core and override the GCR_CONFIG PCORES field. - -Rework a long-standing OpenWrt patch to override the value of -mips_cps_numcores on single-core MT7621 systems. - -Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core -MT7621 device (Netgear R6220). - -Original 4.14 OpenWrt patch: -Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7 -Current 5.10 OpenWrt patch: -Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904 - -Suggested-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mips-cps.h -+++ b/arch/mips/include/asm/mips-cps.h -@@ -11,6 +11,8 @@ - #include - #include - -+#include -+ - extern unsigned long __cps_access_bad_size(void) - __compiletime_error("Bad size for CPS accessor"); - -@@ -162,12 +164,31 @@ static inline uint64_t mips_cps_cluster_ - */ - static inline unsigned int mips_cps_numcores(unsigned int cluster) - { -+ unsigned int ncores; -+ - if (!mips_cm_present()) - return 0; - - /* Add one before masking to handle 0xff indicating no cores */ -- return FIELD_GET(CM_GCR_CONFIG_PCORES, -+ ncores = FIELD_GET(CM_GCR_CONFIG_PCORES, - mips_cps_cluster_config(cluster) + 1); -+ -+ if (IS_ENABLED(CONFIG_SOC_MT7621)) { -+ struct cpulaunch *launch; -+ -+ /* -+ * Ralink MT7621S SoC is single core, but the GCR_CONFIG method -+ * always reports 2 cores. Check the second core's LAUNCH_FREADY -+ * flag to detect if the second core is missing. This method -+ * only works before the core has been started. -+ */ -+ launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); -+ launch += 2; /* MT7621 has 2 VPEs per core */ -+ if (!(launch->flags & LAUNCH_FREADY)) -+ ncores = 1; -+ } -+ -+ return ncores; - } - - /** diff --git a/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch b/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch deleted file mode 100644 index dfeac7eb993dcd..00000000000000 --- a/target/linux/ramips/patches-6.1/324-mt7621-perfctr-fix.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/arch/mips/ralink/irq-gic.c -+++ b/arch/mips/ralink/irq-gic.c -@@ -13,6 +13,12 @@ - - int get_c0_perfcount_int(void) - { -+ /* -+ * Performance counter events are routed through GIC. -+ * Prevent them from firing on CPU IRQ7 as well -+ */ -+ clear_c0_status(IE_SW0 << 7); -+ - return gic_get_c0_perfcount_int(); - } - EXPORT_SYMBOL_GPL(get_c0_perfcount_int); diff --git a/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch b/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch deleted file mode 100644 index 7011bbe50b2d4a..00000000000000 --- a/target/linux/ramips/patches-6.1/400-mtd-cfi-cmdset-0002-force-word-write.patch +++ /dev/null @@ -1,20 +0,0 @@ -From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 15 Jul 2013 00:39:21 +0200 -Subject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write - ---- - drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -40,7 +40,7 @@ - #include - - #define AMD_BOOTLOC_BUG --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MAX_RETRIES 3 - diff --git a/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch b/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch deleted file mode 100644 index 3b88f786028842..00000000000000 --- a/target/linux/ramips/patches-6.1/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Thu, 6 May 2021 17:49:55 +0200 -Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as - -Add MTD support for the BoHong bh25q128as SPI NOR chip. -The chip has 16MB of total capacity, divided into a total of 256 -sectors, each 64KB sized. The chip also supports 4KB sectors. -Additionally, it supports dual and quad read modes. - -Functionality was verified on an Tenbay WR1800K / MTK MT7621 board. - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/Makefile | 1 + - drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++ - drivers/mtd/spi-nor/core.c | 1 + - drivers/mtd/spi-nor/core.h | 1 + - 4 files changed, 24 insertions(+) - create mode 100644 drivers/mtd/spi-nor/bohong.c - ---- a/drivers/mtd/spi-nor/Makefile -+++ b/drivers/mtd/spi-nor/Makefile -@@ -2,6 +2,7 @@ - - spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o - spi-nor-objs += atmel.o -+spi-nor-objs += bohong.o - spi-nor-objs += catalyst.o - spi-nor-objs += eon.o - spi-nor-objs += esmt.o ---- /dev/null -+++ b/drivers/mtd/spi-nor/bohong.c -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2005, Intec Automation Inc. -+ * Copyright (C) 2014, Freescale Semiconductor, Inc. -+ */ -+ -+#include -+ -+#include "core.h" -+ -+static const struct flash_info bohong_parts[] = { -+ /* BoHong Microelectronics */ -+ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256) -+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+}; -+ -+const struct spi_nor_manufacturer spi_nor_bohong = { -+ .name = "bohong", -+ .parts = bohong_parts, -+ .nparts = ARRAY_SIZE(bohong_parts), -+}; ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -1620,6 +1620,7 @@ int spi_nor_sr2_bit7_quad_enable(struct - - static const struct spi_nor_manufacturer *manufacturers[] = { - &spi_nor_atmel, -+ &spi_nor_bohong, - &spi_nor_catalyst, - &spi_nor_eon, - &spi_nor_esmt, ---- a/drivers/mtd/spi-nor/core.h -+++ b/drivers/mtd/spi-nor/core.h -@@ -617,6 +617,7 @@ struct sfdp { - - /* Manufacturer drivers. */ - extern const struct spi_nor_manufacturer spi_nor_atmel; -+extern const struct spi_nor_manufacturer spi_nor_bohong; - extern const struct spi_nor_manufacturer spi_nor_catalyst; - extern const struct spi_nor_manufacturer spi_nor_eon; - extern const struct spi_nor_manufacturer spi_nor_esmt; diff --git a/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch b/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch deleted file mode 100644 index 438cc1ea8fe830..00000000000000 --- a/target/linux/ramips/patches-6.1/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch +++ /dev/null @@ -1,47 +0,0 @@ -From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 1 Apr 2020 02:07:58 +0800 -Subject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand - flash controller - -This patch adds NAND flash controller driver for MediaTek MT7621 SoC. - -The NAND flash controller is similar with controllers described in -mtk_nand.c, except that the controller from MT7621 doesn't support DMA -transmission, and some registers' offset and fields are different. - -Signed-off-by: Weijie Gao ---- - drivers/mtd/nand/raw/Kconfig | 8 + - drivers/mtd/nand/raw/Makefile | 1 + - drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 1357 insertions(+) - create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c - ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -352,6 +352,14 @@ config MTD_NAND_QCOM - Enables support for NAND flash chips on SoCs containing the EBI2 NAND - controller. This controller is found on IPQ806x SoC. - -+config MTD_NAND_MT7621 -+ tristate "MT7621 NAND controller" -+ depends on SOC_MT7621 || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ Enables support for NAND controller on MT7621 SoC. -+ This driver uses PIO mode for data transmission instead of DMA mode. -+ - config MTD_NAND_MTK - tristate "MTK NAND controller" - depends on MTD_NAND_ECC_MEDIATEK ---- a/drivers/mtd/nand/raw/Makefile -+++ b/drivers/mtd/nand/raw/Makefile -@@ -48,6 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n - obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ - obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o -+obj-$(CONFIG_MTD_NAND_MT7621) += mt7621_nand.o - obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o - obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o - obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o diff --git a/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch b/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch deleted file mode 100644 index 3d122c10c04314..00000000000000 --- a/target/linux/ramips/patches-6.1/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 1 Apr 2020 02:07:59 +0800 -Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver - -This patch adds documentation for MediaTek MT7621 NAND flash controller -driver. - -Signed-off-by: Weijie Gao ---- - .../bindings/mtd/mediatek,mt7621-nfc.yaml | 68 ++++++++++++++++++++++ - 1 file changed, 68 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml -@@ -0,0 +1,68 @@ -+# SPDX-License-Identifier: GPL-2.0 -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding -+ -+maintainers: -+ - Weijie Gao -+ -+description: | -+ This driver uses a single node to describe both NAND Flash controller -+ interface (NFI) and ECC engine for MT7621 SoC. -+ MT7621 supports only one chip select. -+ -+properties: -+ "#address-cells": false -+ "#size-cells": false -+ -+ compatible: -+ enum: -+ - mediatek,mt7621-nfc -+ -+ reg: -+ items: -+ - description: Register base of NFI core -+ - description: Register base of ECC engine -+ -+ reg-names: -+ items: -+ - const: nfi -+ - const: ecc -+ -+ clocks: -+ items: -+ - description: Source clock for NFI core, fixed 125MHz -+ -+ clock-names: -+ items: -+ - const: nfi_clk -+ -+required: -+ - compatible -+ - reg -+ - reg-names -+ - clocks -+ - clock-names -+ -+examples: -+ - | -+ nficlock: nficlock { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ -+ clock-frequency = <125000000>; -+ }; -+ -+ nand@1e003000 { -+ compatible = "mediatek,mt7621-nfc"; -+ -+ reg = <0x1e003000 0x800 -+ 0x1e003800 0x800>; -+ reg-names = "nfi", "ecc"; -+ -+ clocks = <&nficlock>; -+ clock-names = "nfi_clk"; -+ }; diff --git a/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch deleted file mode 100644 index a6e2aa04ca3053..00000000000000 --- a/target/linux/ramips/patches-6.1/700-net-ethernet-mediatek-support-net-labels.patch +++ /dev/null @@ -1,34 +0,0 @@ -From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= -Date: Fri, 21 Jun 2019 10:04:05 +0200 -Subject: [PATCH] net: ethernet: mediatek: support net-labels - -With this patch, device name can be set within dts file in the same way as dsa -port can. -Add: label = "wan"; to GMAC node. - -Signed-off-by: René van Dorst ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4643,6 +4643,7 @@ static const struct net_device_ops mtk_n - - static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) - { -+ const char *name = of_get_property(np, "label", NULL); - const __be32 *_id = of_get_property(np, "reg", NULL); - struct device_node *pcs_np; - phy_interface_t phy_mode; -@@ -4840,6 +4841,9 @@ static int mtk_add_mac(struct mtk_eth *e - register_netdevice_notifier(&mac->device_notifier); - } - -+ if (name) -+ strlcpy(eth->netdev[id]->name, name, IFNAMSIZ); -+ - return 0; - - free_netdev: diff --git a/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch deleted file mode 100644 index 91159f2c6347de..00000000000000 --- a/target/linux/ramips/patches-6.1/720-Revert-net-phy-simplify-phy_link_change-arguments.patch +++ /dev/null @@ -1,118 +0,0 @@ -From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Sat, 27 Feb 2021 20:20:07 -0800 -Subject: [PATCH] Revert "net: phy: simplify phy_link_change arguments" - -This reverts commit a307593a644443db12888f45eed0dafb5869e2cc. - -This brings back the do_carrier flags used by the (hacky) next patch, -still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c ---- - drivers/net/phy/phy.c | 12 ++++++------ - drivers/net/phy/phy_device.c | 12 +++++++----- - drivers/net/phy/phylink.c | 3 ++- - include/linux/phy.h | 2 +- - 4 files changed, 16 insertions(+), 13 deletions(-) - ---- a/drivers/net/phy/phy.c -+++ b/drivers/net/phy/phy.c -@@ -71,13 +71,13 @@ static void phy_process_state_change(str - - static void phy_link_up(struct phy_device *phydev) - { -- phydev->phy_link_change(phydev, true); -+ phydev->phy_link_change(phydev, true, true); - phy_led_trigger_change_speed(phydev); - } - --static void phy_link_down(struct phy_device *phydev) -+static void phy_link_down(struct phy_device *phydev, bool do_carrier) - { -- phydev->phy_link_change(phydev, false); -+ phydev->phy_link_change(phydev, false, do_carrier); - phy_led_trigger_change_speed(phydev); - } - -@@ -595,7 +595,7 @@ int phy_start_cable_test(struct phy_devi - goto out; - - /* Mark the carrier down until the test is complete */ -- phy_link_down(phydev); -+ phy_link_down(phydev, true); - - netif_testing_on(dev); - err = phydev->drv->cable_test_start(phydev); -@@ -666,7 +666,7 @@ int phy_start_cable_test_tdr(struct phy_ - goto out; - - /* Mark the carrier down until the test is complete */ -- phy_link_down(phydev); -+ phy_link_down(phydev, true); - - netif_testing_on(dev); - err = phydev->drv->cable_test_tdr_start(phydev, config); -@@ -738,7 +738,7 @@ static int phy_check_link_status(struct - phy_link_up(phydev); - } else if (!phydev->link && phydev->state != PHY_NOLINK) { - phydev->state = PHY_NOLINK; -- phy_link_down(phydev); -+ phy_link_down(phydev, true); - } - - return 0; -@@ -1224,7 +1224,7 @@ void phy_state_machine(struct work_struc - case PHY_HALTED: - if (phydev->link) { - phydev->link = 0; -- phy_link_down(phydev); -+ phy_link_down(phydev, true); - } - do_suspend = true; - break; ---- a/drivers/net/phy/phy_device.c -+++ b/drivers/net/phy/phy_device.c -@@ -1037,14 +1037,16 @@ struct phy_device *phy_find_first(struct - } - EXPORT_SYMBOL(phy_find_first); - --static void phy_link_change(struct phy_device *phydev, bool up) -+static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier) - { - struct net_device *netdev = phydev->attached_dev; - -- if (up) -- netif_carrier_on(netdev); -- else -- netif_carrier_off(netdev); -+ if (do_carrier) { -+ if (up) -+ netif_carrier_on(netdev); -+ else -+ netif_carrier_off(netdev); -+ } - phydev->adjust_link(netdev); - if (phydev->mii_ts && phydev->mii_ts->link_state) - phydev->mii_ts->link_state(phydev->mii_ts, phydev); ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -1687,7 +1687,8 @@ bool phylink_expects_phy(struct phylink - } - EXPORT_SYMBOL_GPL(phylink_expects_phy); - --static void phylink_phy_change(struct phy_device *phydev, bool up) -+static void phylink_phy_change(struct phy_device *phydev, bool up, -+ bool do_carrier) - { - struct phylink *pl = phydev->phylink; - bool tx_pause, rx_pause; ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -739,7 +739,7 @@ struct phy_device { - - int pma_extable; - -- void (*phy_link_change)(struct phy_device *phydev, bool up); -+ void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier); - void (*adjust_link)(struct net_device *dev); - - #if IS_ENABLED(CONFIG_MACSEC) diff --git a/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch b/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch deleted file mode 100644 index 2594c66048fe2e..00000000000000 --- a/target/linux/ramips/patches-6.1/721-NET-no-auto-carrier-off-support.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:38:50 +0100 -Subject: [PATCH 34/53] NET: multi phy support - -Signed-off-by: John Crispin ---- - drivers/net/phy/phy.c | 9 ++++++--- - include/linux/phy.h | 1 + - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/phy.c -+++ b/drivers/net/phy/phy.c -@@ -738,7 +738,10 @@ static int phy_check_link_status(struct - phy_link_up(phydev); - } else if (!phydev->link && phydev->state != PHY_NOLINK) { - phydev->state = PHY_NOLINK; -- phy_link_down(phydev, true); -+ if (!phydev->no_auto_carrier_off) -+ phy_link_down(phydev, true); -+ else -+ phy_link_down(phydev, false); - } - - return 0; -@@ -1224,7 +1227,10 @@ void phy_state_machine(struct work_struc - case PHY_HALTED: - if (phydev->link) { - phydev->link = 0; -- phy_link_down(phydev, true); -+ if (!phydev->no_auto_carrier_off) -+ phy_link_down(phydev, true); -+ else -+ phy_link_down(phydev, false); - } - do_suspend = true; - break; ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -647,6 +647,7 @@ struct phy_device { - unsigned downshifted_rate:1; - unsigned is_on_sfp_module:1; - unsigned mac_managed_pm:1; -+ unsigned no_auto_carrier_off:1; - - unsigned autoneg:1; - /* The most recently read link state */ diff --git a/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch b/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch deleted file mode 100644 index a793011223b8c7..00000000000000 --- a/target/linux/ramips/patches-6.1/800-dmaengine-mediatek-add-HSDMA-support-for-mt7621.patch +++ /dev/null @@ -1,37 +0,0 @@ -From d94fc5ce1dc395747c3934ecffcdec0396583755 Mon Sep 17 00:00:00 2001 -From: Nick Hainke -Date: Fri, 26 May 2023 19:46:33 +0200 -Subject: [PATCH] dmaengine: mediatek: add HSDMA support for mt7621 - -Commit 87dd67f496f7 ("staging: mt7621-dma: remove driver from tree") -removed the mt7621-dma driver. Move the driver from staging to the -folder "drivers/dma/mediatek" containing already other mediatek dma -driver implementations and maintain it downstream in OpenWrt. - -This patch will not be sent to upstream linux. It is just a workaround. - -Signed-off-by: Nick Hainke ---- - drivers/dma/mediatek/Kconfig | 6 ++++++ - drivers/dma/mediatek/Makefile | 1 + - 2 files changed, 7 insertions(+) - ---- a/drivers/dma/mediatek/Kconfig -+++ b/drivers/dma/mediatek/Kconfig -@@ -36,3 +36,9 @@ config MTK_UART_APDMA - When SERIAL_8250_MT6577 is enabled, and if you want to use DMA, - you can enable the config. The DMA engine can only be used - with MediaTek SoCs. -+ -+config MTK_HSDMA -+ tristate "MTK HSDMA support" -+ depends on RALINK && SOC_MT7621 -+ select DMA_ENGINE -+ select DMA_VIRTUAL_CHANNELS ---- a/drivers/dma/mediatek/Makefile -+++ b/drivers/dma/mediatek/Makefile -@@ -2,3 +2,4 @@ - obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o - obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o - obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o -+obj-$(CONFIG_MTK_HSDMA) += hsdma-mt7621.o diff --git a/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch b/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch deleted file mode 100644 index 93dabf877626d0..00000000000000 --- a/target/linux/ramips/patches-6.1/801-DT-Add-documentation-for-gpio-ralink.patch +++ /dev/null @@ -1,59 +0,0 @@ -From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 28 Jul 2013 19:45:30 +0200 -Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink - -Describe gpio-ralink binding. - -Signed-off-by: John Crispin -Cc: linux-mips@linux-mips.org -Cc: devicetree@vger.kernel.org -Cc: linux-gpio@vger.kernel.org ---- - .../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++ - 1 file changed, 40 insertions(+) - create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -@@ -0,0 +1,40 @@ -+Ralink SoC GPIO controller bindings -+ -+Required properties: -+- compatible: -+ - "ralink,rt2880-gpio" for Ralink controllers -+- #gpio-cells : Should be two. -+ - first cell is the pin number -+ - second cell is used to specify optional parameters (unused) -+- gpio-controller : Marks the device node as a GPIO controller -+- reg : Physical base address and length of the controller's registers -+- interrupt-parent: phandle to the INTC device node -+- interrupts : Specify the INTC interrupt number -+- ngpios : Specify the number of GPIOs -+- ralink,register-map : The register layout depends on the GPIO bank and actual -+ SoC type. Register offsets need to be in this order. -+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ] -+ -+Optional properties: -+- ralink,gpio-base : Specify the GPIO chips base number -+ -+Example: -+ -+ gpio0: gpio@600 { -+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio"; -+ -+ #gpio-cells = <2>; -+ gpio-controller; -+ -+ reg = <0x600 0x34>; -+ -+ interrupt-parent = <&intc>; -+ interrupts = <6>; -+ -+ ngpios = <24>; -+ ralink,gpio-base = <0>; -+ ralink,register-map = [ 00 04 08 0c -+ 20 24 28 2c -+ 30 34 ]; -+ -+ }; diff --git a/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch b/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch deleted file mode 100644 index ff60b33cd42d80..00000000000000 --- a/target/linux/ramips/patches-6.1/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch +++ /dev/null @@ -1,416 +0,0 @@ -From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 4 Aug 2014 20:36:29 +0200 -Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC - -Add gpio driver for Ralink SoC. This driver makes the gpio core on -RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work. - -Signed-off-by: John Crispin -Cc: linux-mips@linux-mips.org -Cc: linux-gpio@vger.kernel.org ---- - arch/mips/include/asm/mach-ralink/gpio.h | 24 ++ - drivers/gpio/Kconfig | 6 + - drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++ - 4 files changed, 386 insertions(+) - create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h - create mode 100644 drivers/gpio/gpio-ralink.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-ralink/gpio.h -@@ -0,0 +1,24 @@ -+/* -+ * Ralink SoC GPIO API support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MACH_RALINK_GPIO_H -+#define __ASM_MACH_RALINK_GPIO_H -+ -+#define ARCH_NR_GPIOS 128 -+#include -+ -+#define gpio_get_value __gpio_get_value -+#define gpio_set_value __gpio_set_value -+#define gpio_cansleep __gpio_cansleep -+#define gpio_to_irq __gpio_to_irq -+ -+#endif /* __ASM_MACH_RALINK_GPIO_H */ ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -585,6 +585,12 @@ config GPIO_SNPS_CREG - where only several fields in register belong to GPIO lines and - each GPIO line owns a field with different length and on/off value. - -+config GPIO_RALINK -+ bool "Ralink GPIO Support" -+ depends on RALINK -+ help -+ Say yes here to support the Ralink SoC GPIO device -+ - config GPIO_SPEAR_SPICS - bool "ST SPEAr13xx SPI Chip Select as GPIO support" - depends on PLAT_SPEAR ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -122,6 +122,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos - obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o - obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o - obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o -+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o - obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o - obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o - obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o ---- /dev/null -+++ b/drivers/gpio/gpio-ralink.c -@@ -0,0 +1,341 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2009-2011 Gabor Juhos -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+enum ralink_gpio_reg { -+ GPIO_REG_INT = 0, -+ GPIO_REG_EDGE, -+ GPIO_REG_RENA, -+ GPIO_REG_FENA, -+ GPIO_REG_DATA, -+ GPIO_REG_DIR, -+ GPIO_REG_POL, -+ GPIO_REG_SET, -+ GPIO_REG_RESET, -+ GPIO_REG_TOGGLE, -+ GPIO_REG_MAX -+}; -+ -+struct ralink_gpio_chip { -+ struct gpio_chip chip; -+ u8 regs[GPIO_REG_MAX]; -+ -+ spinlock_t lock; -+ void __iomem *membase; -+ struct irq_domain *domain; -+ int irq; -+ -+ u32 rising; -+ u32 falling; -+}; -+ -+#define MAP_MAX 4 -+static struct irq_domain *irq_map[MAP_MAX]; -+static int irq_map_count; -+static atomic_t irq_refcount = ATOMIC_INIT(0); -+ -+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip) -+{ -+ struct ralink_gpio_chip *rg; -+ -+ rg = container_of(chip, struct ralink_gpio_chip, chip); -+ -+ return rg; -+} -+ -+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val) -+{ -+ iowrite32(val, rg->membase + rg->regs[reg]); -+} -+ -+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg) -+{ -+ return ioread32(rg->membase + rg->regs[reg]); -+} -+ -+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset)); -+} -+ -+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset)); -+} -+ -+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ t = rt_gpio_r32(rg, GPIO_REG_DIR); -+ t &= ~BIT(offset); -+ rt_gpio_w32(rg, GPIO_REG_DIR, t); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ return 0; -+} -+ -+static int ralink_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ ralink_gpio_set(chip, offset, value); -+ t = rt_gpio_r32(rg, GPIO_REG_DIR); -+ t |= BIT(offset); -+ rt_gpio_w32(rg, GPIO_REG_DIR, t); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ return 0; -+} -+ -+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ if (rg->irq < 1) -+ return -1; -+ -+ return irq_create_mapping(rg->domain, pin); -+} -+ -+static void ralink_gpio_irq_handler(struct irq_desc *desc) -+{ -+ int i; -+ -+ for (i = 0; i < irq_map_count; i++) { -+ struct irq_domain *domain = irq_map[i]; -+ struct ralink_gpio_chip *rg; -+ unsigned long pending; -+ int bit; -+ -+ rg = (struct ralink_gpio_chip *) domain->host_data; -+ pending = rt_gpio_r32(rg, GPIO_REG_INT); -+ -+ for_each_set_bit(bit, &pending, rg->chip.ngpio) { -+ u32 map = irq_find_mapping(domain, bit); -+ generic_handle_irq(map); -+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit)); -+ } -+ } -+} -+ -+static void ralink_gpio_irq_unmask(struct irq_data *d) -+{ -+ struct ralink_gpio_chip *rg; -+ unsigned long flags; -+ u32 rise, fall; -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ rise = rt_gpio_r32(rg, GPIO_REG_RENA); -+ fall = rt_gpio_r32(rg, GPIO_REG_FENA); -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising)); -+ rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling)); -+ spin_unlock_irqrestore(&rg->lock, flags); -+} -+ -+static void ralink_gpio_irq_mask(struct irq_data *d) -+{ -+ struct ralink_gpio_chip *rg; -+ unsigned long flags; -+ u32 rise, fall; -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ rise = rt_gpio_r32(rg, GPIO_REG_RENA); -+ fall = rt_gpio_r32(rg, GPIO_REG_FENA); -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq)); -+ rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq)); -+ spin_unlock_irqrestore(&rg->lock, flags); -+} -+ -+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type) -+{ -+ struct ralink_gpio_chip *rg; -+ u32 mask = BIT(d->hwirq); -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ -+ if (type == IRQ_TYPE_PROBE) { -+ if ((rg->rising | rg->falling) & mask) -+ return 0; -+ -+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; -+ } -+ -+ if (type & IRQ_TYPE_EDGE_RISING) -+ rg->rising |= mask; -+ else -+ rg->rising &= ~mask; -+ -+ if (type & IRQ_TYPE_EDGE_FALLING) -+ rg->falling |= mask; -+ else -+ rg->falling &= ~mask; -+ -+ return 0; -+} -+ -+static struct irq_chip ralink_gpio_irq_chip = { -+ .name = "GPIO", -+ .irq_unmask = ralink_gpio_irq_unmask, -+ .irq_mask = ralink_gpio_irq_mask, -+ .irq_mask_ack = ralink_gpio_irq_mask, -+ .irq_set_type = ralink_gpio_irq_type, -+}; -+ -+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -+{ -+ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq); -+ irq_set_handler_data(irq, d); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops irq_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = gpio_map, -+}; -+ -+static void ralink_gpio_irq_init(struct device_node *np, -+ struct ralink_gpio_chip *rg) -+{ -+ if (irq_map_count >= MAP_MAX) -+ return; -+ -+ rg->irq = irq_of_parse_and_map(np, 0); -+ if (!rg->irq) -+ return; -+ -+ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, -+ &irq_domain_ops, rg); -+ if (!rg->domain) { -+ dev_err(rg->chip.parent, "irq_domain_add_linear failed\n"); -+ return; -+ } -+ -+ irq_map[irq_map_count++] = rg->domain; -+ -+ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0); -+ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0); -+ -+ if (!atomic_read(&irq_refcount)) -+ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler); -+ atomic_inc(&irq_refcount); -+ -+ dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio); -+} -+ -+static int ralink_gpio_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ struct ralink_gpio_chip *rg; -+ const __be32 *ngpio, *gpiobase; -+ -+ if (!res) { -+ dev_err(&pdev->dev, "failed to find resource\n"); -+ return -ENOMEM; -+ } -+ -+ rg = devm_kzalloc(&pdev->dev, -+ sizeof(struct ralink_gpio_chip), GFP_KERNEL); -+ if (!rg) -+ return -ENOMEM; -+ -+ rg->membase = devm_ioremap_resource(&pdev->dev, res); -+ if (!rg->membase) { -+ dev_err(&pdev->dev, "cannot remap I/O memory region\n"); -+ return -ENOMEM; -+ } -+ -+ if (of_property_read_u8_array(np, "ralink,register-map", -+ rg->regs, GPIO_REG_MAX)) { -+ dev_err(&pdev->dev, "failed to read register definition\n"); -+ return -EINVAL; -+ } -+ -+ ngpio = of_get_property(np, "ngpios", NULL); -+ if (!ngpio) { -+ dev_err(&pdev->dev, "failed to read number of pins\n"); -+ return -EINVAL; -+ } -+ -+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL); -+ if (gpiobase) -+ rg->chip.base = be32_to_cpu(*gpiobase); -+ else -+ rg->chip.base = -1; -+ -+ spin_lock_init(&rg->lock); -+ -+ rg->chip.parent = &pdev->dev; -+ rg->chip.label = dev_name(&pdev->dev); -+ rg->chip.of_node = np; -+ rg->chip.ngpio = be32_to_cpu(*ngpio); -+ rg->chip.direction_input = ralink_gpio_direction_input; -+ rg->chip.direction_output = ralink_gpio_direction_output; -+ rg->chip.get = ralink_gpio_get; -+ rg->chip.set = ralink_gpio_set; -+ rg->chip.request = gpiochip_generic_request; -+ rg->chip.to_irq = ralink_gpio_to_irq; -+ rg->chip.free = gpiochip_generic_free; -+ -+ /* set polarity to low for all lines */ -+ rt_gpio_w32(rg, GPIO_REG_POL, 0); -+ -+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio); -+ -+ ralink_gpio_irq_init(np, rg); -+ -+ return gpiochip_add(&rg->chip); -+} -+ -+static const struct of_device_id ralink_gpio_match[] = { -+ { .compatible = "ralink,rt2880-gpio" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ralink_gpio_match); -+ -+static struct platform_driver ralink_gpio_driver = { -+ .probe = ralink_gpio_probe, -+ .driver = { -+ .name = "rt2880_gpio", -+ .owner = THIS_MODULE, -+ .of_match_table = ralink_gpio_match, -+ }, -+}; -+ -+static int __init ralink_gpio_init(void) -+{ -+ return platform_driver_register(&ralink_gpio_driver); -+} -+ -+subsys_initcall(ralink_gpio_init); diff --git a/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch b/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch deleted file mode 100644 index 8520ce32ff7b2f..00000000000000 --- a/target/linux/ramips/patches-6.1/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001 -From: Daniel Santos -Date: Sun, 4 Nov 2018 20:24:32 -0600 -Subject: gpio-ralink: Add support for GPIO as interrupt-controller - -Signed-off-by: Daniel Santos ---- - Documentation/devicetree/bindings/gpio/gpio-ralink.txt | 6 ++++++ - drivers/gpio/gpio-ralink.c | 2 +- - 2 files changed, 7 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -@@ -17,6 +17,9 @@ Required properties: - - Optional properties: - - ralink,gpio-base : Specify the GPIO chips base number -+- interrupt-controller : marks this as an interrupt controller -+- #interrupt-cells : a standard two-cell interrupt flag, see -+ interrupt-controller/interrupts.txt - - Example: - -@@ -28,6 +31,9 @@ Example: - - reg = <0x600 0x34>; - -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ - interrupt-parent = <&intc>; - interrupts = <6>; - ---- a/drivers/gpio/gpio-ralink.c -+++ b/drivers/gpio/gpio-ralink.c -@@ -220,7 +220,7 @@ static int gpio_map(struct irq_domain *d - } - - static const struct irq_domain_ops irq_domain_ops = { -- .xlate = irq_domain_xlate_onecell, -+ .xlate = irq_domain_xlate_twocell, - .map = gpio_map, - }; - diff --git a/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch b/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch deleted file mode 100644 index f9fa791fe1d05d..00000000000000 --- a/target/linux/ramips/patches-6.1/805-pinctrl-AW9523.patch +++ /dev/null @@ -1,72 +0,0 @@ -From: AngeloGioacchino Del Regno - -To: linus.walleij@linaro.org -Cc: linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, - marijn.suijten@somainline.org, martin.botka@somainline.org, - phone-devel@vger.kernel.org, linux-gpio@vger.kernel.org, - devicetree@vger.kernel.org, robh+dt@kernel.org, - AngeloGioacchino Del Regno - -Subject: [PATCH v5 1/2] pinctrl: Add driver for Awinic AW9523/B I2C GPIO - Expander -Date: Mon, 25 Jan 2021 19:22:18 +0100 - -The Awinic AW9523(B) is a multi-function I2C gpio expander in a -TQFN-24L package, featuring PWM (max 37mA per pin, or total max -power 3.2Watts) for LED driving capability. - -It has two ports with 8 pins per port (for a total of 16 pins), -configurable as either PWM with 1/256 stepping or GPIO input/output, -1.8V logic input; each GPIO can be configured as input or output -independently from each other. - -This IC also has an internal interrupt controller, which is capable -of generating an interrupt for each GPIO, depending on the -configuration, and will raise an interrupt on the INTN pin to -advertise this to an external interrupt controller. - -Signed-off-by: AngeloGioacchino Del Regno ---- - drivers/pinctrl/Kconfig | 17 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++ - 3 files changed, 1140 insertions(+) - create mode 100644 drivers/pinctrl/pinctrl-aw9523.c - ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -113,6 +113,24 @@ config PINCTRL_AT91PIO4 - Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4 - controller available on sama5d2 SoC. - -+config PINCTRL_AW9523 -+ bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver" -+ depends on OF && I2C -+ select PINMUX -+ select PINCONF -+ select GENERIC_PINCONF -+ select GPIOLIB -+ select GPIOLIB_IRQCHIP -+ select REGMAP -+ select REGMAP_I2C -+ help -+ The Awinic AW9523/AW9523B is a multi-function I2C GPIO -+ expander with PWM functionality. This driver bundles a -+ pinctrl driver to select the function muxing and a GPIO -+ driver to handle GPIO, when the GPIO function is selected. -+ -+ Say yes to enable pinctrl and GPIO support for the AW9523(B). -+ - config PINCTRL_AXP209 - tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support" - depends on MFD_AXP20X ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl - obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o - obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o - obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o -+obj-$(CONFIG_PINCTRL_AW9523) += pinctrl-aw9523.o - obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o - obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o - obj-$(CONFIG_PINCTRL_CY8C95X0) += pinctrl-cy8c95x0.o diff --git a/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch b/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch deleted file mode 100644 index 047808f1e6904d..00000000000000 --- a/target/linux/ramips/patches-6.1/808-pinctrl-mtmips-support-requesting-different-function.patch +++ /dev/null @@ -1,45 +0,0 @@ -From: Shiji Yang -Date: Wed, 26 Jul 2023 01:32:55 +0800 -Subject: [PATCH] pinctrl: mtmips: support requesting different functions for - same group - -Sometimes pinctrl consumers may request different functions for the -same pin group in different situations. This patch can help to reset -the group function flag when requesting a different function. - -Signed-off-by: Shiji Yang ---- - drivers/pinctrl/ralink/pinctrl-ralink.c | 21 +++++++++++++++++---- - 1 file changed, 17 insertions(+), 4 deletions(-) - ---- a/drivers/pinctrl/ralink/pinctrl-ralink.c -+++ b/drivers/pinctrl/ralink/pinctrl-ralink.c -@@ -123,11 +123,24 @@ static int ralink_pmx_group_enable(struc - int i; - int shift; - -- /* dont allow double use */ -+ /* -+ * for the same pin group, if request a different function, -+ * then clear the group function flag and continue, else exit. -+ */ - if (p->groups[group].enabled) { -- dev_err(p->dev, "%s is already enabled\n", -- p->groups[group].name); -- return 0; -+ for (i = 0; i < p->groups[group].func_count; i++) { -+ if (p->groups[group].func[i].enabled == 1) { -+ if (!strcmp(p->func[func]->name, -+ p->groups[group].func[i].name)) -+ return 0; -+ p->groups[group].func[i].enabled = 0; -+ break; -+ } -+ } -+ -+ /* exit if request the "gpio" function again */ -+ if (i == p->groups[group].func_count && func == 0) -+ return 0; - } - - p->groups[group].enabled = 1; diff --git a/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch b/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch deleted file mode 100644 index d48b668484fb3a..00000000000000 --- a/target/linux/ramips/patches-6.1/810-uvc-add-iPassion-iP2970-support.patch +++ /dev/null @@ -1,244 +0,0 @@ -From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 19 Sep 2013 01:50:59 +0200 -Subject: [PATCH 31/53] uvc: add iPassion iP2970 support - -Signed-off-by: John Crispin ---- - drivers/media/usb/uvc/uvc_driver.c | 12 +++ - drivers/media/usb/uvc/uvc_status.c | 2 + - drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++ - drivers/media/usb/uvc/uvcvideo.h | 5 +- - 4 files changed, 165 insertions(+), 1 deletion(-) - ---- a/drivers/media/usb/uvc/uvc_driver.c -+++ b/drivers/media/usb/uvc/uvc_driver.c -@@ -2981,6 +2981,18 @@ static const struct usb_device_id uvc_id - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 0, - .driver_info = UVC_INFO_META(V4L2_META_FMT_D4XX) }, -+ /* iPassion iP2970 */ -+ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE -+ | USB_DEVICE_ID_MATCH_INT_INFO, -+ .idVendor = 0x1B3B, -+ .idProduct = 0x2970, -+ .bInterfaceClass = USB_CLASS_VIDEO, -+ .bInterfaceSubClass = 1, -+ .bInterfaceProtocol = 0, -+ .driver_info = UVC_QUIRK_PROBE_MINMAX -+ | UVC_QUIRK_STREAM_NO_FID -+ | UVC_QUIRK_MOTION -+ | UVC_QUIRK_SINGLE_ISO }, - /* Generic USB Video Class */ - { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) }, - { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) }, ---- a/drivers/media/usb/uvc/uvc_status.c -+++ b/drivers/media/usb/uvc/uvc_status.c -@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u - if (uvc_event_control(urb, status, len)) - /* The URB will be resubmitted in work context. */ - return; -+ dev->motion = 1; - break; - } - -@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d - } - - pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress); -+ dev->motion = 0; - - /* - * For high-speed interrupt endpoints, the bInterval value is used as ---- a/drivers/media/usb/uvc/uvc_video.c -+++ b/drivers/media/usb/uvc/uvc_video.c -@@ -19,6 +19,11 @@ - #include - #include - #include -+#include -+#include -+#include -+#include -+#include - - #include - -@@ -1231,9 +1236,149 @@ static void uvc_video_decode_data(struct - uvc_urb->async_operations++; - } - -+struct bh_priv { -+ unsigned long seen; -+}; -+ -+struct bh_event { -+ const char *name; -+ struct sk_buff *skb; -+ struct work_struct work; -+}; -+ -+#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args ) -+#define BH_DBG(fmt, args...) do {} while (0) -+#define BH_SKB_SIZE 2048 -+ -+extern u64 uevent_next_seqnum(void); -+static int seen = 0; -+ -+static int bh_event_add_var(struct bh_event *event, int argv, -+ const char *format, ...) -+{ -+ static char buf[128]; -+ char *s; -+ va_list args; -+ int len; -+ -+ if (argv) -+ return 0; -+ -+ va_start(args, format); -+ len = vsnprintf(buf, sizeof(buf), format, args); -+ va_end(args); -+ -+ if (len >= sizeof(buf)) { -+ BH_ERR("buffer size too small\n"); -+ WARN_ON(1); -+ return -ENOMEM; -+ } -+ -+ s = skb_put(event->skb, len + 1); -+ strcpy(s, buf); -+ -+ BH_DBG("added variable '%s'\n", s); -+ -+ return 0; -+} -+ -+static int motion_hotplug_fill_event(struct bh_event *event) -+{ -+ int s = jiffies; -+ int ret; -+ -+ if (!seen) -+ seen = jiffies; -+ -+ ret = bh_event_add_var(event, 0, "HOME=%s", "/"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "PATH=%s", -+ "/sbin:/bin:/usr/sbin:/usr/bin"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "ACTION=motion"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen); -+ if (ret) -+ return ret; -+ seen = s; -+ -+ ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum()); -+ -+ return ret; -+} -+ -+static void motion_hotplug_work(struct work_struct *work) -+{ -+ struct bh_event *event = container_of(work, struct bh_event, work); -+ int ret = 0; -+ -+ event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL); -+ if (!event->skb) -+ goto out_free_event; -+ -+ ret = bh_event_add_var(event, 0, "%s@", "add"); -+ if (ret) -+ goto out_free_skb; -+ -+ ret = motion_hotplug_fill_event(event); -+ if (ret) -+ goto out_free_skb; -+ -+ NETLINK_CB(event->skb).dst_group = 1; -+ broadcast_uevent(event->skb, 0, 1, GFP_KERNEL); -+ -+out_free_skb: -+ if (ret) { -+ BH_ERR("work error %d\n", ret); -+ kfree_skb(event->skb); -+ } -+out_free_event: -+ kfree(event); -+} -+ -+static int motion_hotplug_create_event(void) -+{ -+ struct bh_event *event; -+ -+ event = kzalloc(sizeof(*event), GFP_KERNEL); -+ if (!event) -+ return -ENOMEM; -+ -+ event->name = "motion"; -+ -+ INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work); -+ schedule_work(&event->work); -+ -+ return 0; -+} -+ -+#define MOTION_FLAG_OFFSET 4 - static void uvc_video_decode_end(struct uvc_streaming *stream, - struct uvc_buffer *buf, const u8 *data, int len) - { -+ if ((stream->dev->quirks & UVC_QUIRK_MOTION) && -+ (data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) { -+ u8 *mem; -+ buf->state = UVC_BUF_STATE_READY; -+ mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET); -+ if ( stream->dev->motion ) { -+ stream->dev->motion = 0; -+ motion_hotplug_create_event(); -+ } else { -+ *mem &= 0x7f; -+ } -+ } -+ - /* Mark the buffer as done if the EOF marker is set. */ - if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) { - uvc_dbg(stream->dev, FRAME, "Frame complete (EOF found)\n"); -@@ -1815,6 +1960,8 @@ static int uvc_init_video_isoc(struct uv - if (npackets == 0) - return -ENOMEM; - -+ if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO) -+ npackets = 1; - size = npackets * psize; - - for_each_uvc_urb(uvc_urb, stream) { ---- a/drivers/media/usb/uvc/uvcvideo.h -+++ b/drivers/media/usb/uvc/uvcvideo.h -@@ -75,6 +75,8 @@ - #define UVC_QUIRK_FORCE_Y8 0x00000800 - #define UVC_QUIRK_FORCE_BPP 0x00001000 - #define UVC_QUIRK_WAKE_AUTOSUSPEND 0x00002000 -+#define UVC_QUIRK_MOTION 0x00004000 -+#define UVC_QUIRK_SINGLE_ISO 0x00008000 - - /* Format flags */ - #define UVC_FMT_FLAG_COMPRESSED 0x00000001 -@@ -562,6 +564,7 @@ struct uvc_device { - u8 *status; - struct input_dev *input; - char input_phys[64]; -+ int motion; - - struct uvc_ctrl_work { - struct work_struct work; diff --git a/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch b/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch deleted file mode 100644 index e2643e3f2544e0..00000000000000 --- a/target/linux/ramips/patches-6.1/820-DT-Add-documentation-for-spi-rt2880.patch +++ /dev/null @@ -1,44 +0,0 @@ -From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 9 Aug 2013 20:12:59 +0200 -Subject: [PATCH 41/53] DT: Add documentation for spi-rt2880 - -Describe the SPI master found on the MIPS based Ralink RT2880 SoC. - -Signed-off-by: John Crispin ---- - .../devicetree/bindings/spi/spi-rt2880.txt | 28 ++++++++++++++++++++ - 1 file changed, 28 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt -@@ -0,0 +1,28 @@ -+Ralink SoC RT2880 SPI master controller. -+ -+This SPI controller is found on most wireless SoCs made by ralink. -+ -+Required properties: -+- compatible : "ralink,rt2880-spi" -+- reg : The register base for the controller. -+- #address-cells : <1>, as required by generic SPI binding. -+- #size-cells : <0>, also as required by generic SPI binding. -+ -+Child nodes as per the generic SPI binding. -+ -+Example: -+ -+ spi@b00 { -+ compatible = "ralink,rt2880-spi"; -+ reg = <0xb00 0x100>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ m25p80@0 { -+ compatible = "m25p80"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+ }; -+ diff --git a/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch deleted file mode 100644 index 9aaf86ffc71545..00000000000000 --- a/target/linux/ramips/patches-6.1/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch +++ /dev/null @@ -1,579 +0,0 @@ -From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 11:15:12 +0100 -Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver - -Add the driver needed to make SPI work on Ralink SoC. - -Signed-off-by: Gabor Juhos -Acked-by: John Crispin ---- - drivers/spi/Kconfig | 6 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-rt2880.c | 530 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 537 insertions(+) - create mode 100644 drivers/spi/spi-rt2880.c - ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -823,6 +823,12 @@ config SPI_QCOM_GENI - This driver can also be built as a module. If so, the module - will be called spi-geni-qcom. - -+config SPI_RT2880 -+ tristate "Ralink RT288x SPI Controller" -+ depends on RALINK -+ help -+ This selects a driver for the Ralink RT288x/RT305x SPI Controller. -+ - config SPI_S3C24XX - tristate "Samsung S3C24XX series SPI" - depends on ARCH_S3C24XX ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o - obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o - obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o - obj-$(CONFIG_SPI_RSPI) += spi-rspi.o -+obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o - obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o - spi-s3c24xx-hw-y := spi-s3c24xx.o - obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o ---- /dev/null -+++ b/drivers/spi/spi-rt2880.c -@@ -0,0 +1,535 @@ -+/* -+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver -+ * -+ * Copyright (C) 2011 Sergiy -+ * Copyright (C) 2011-2013 Gabor Juhos -+ * -+ * Some parts are based on spi-orion.c: -+ * Author: Shadi Ammouri -+ * Copyright (C) 2007-2008 Marvell Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "spi-rt2880" -+ -+#define RAMIPS_SPI_STAT 0x00 -+#define RAMIPS_SPI_CFG 0x10 -+#define RAMIPS_SPI_CTL 0x14 -+#define RAMIPS_SPI_DATA 0x20 -+#define RAMIPS_SPI_ADDR 0x24 -+#define RAMIPS_SPI_BS 0x28 -+#define RAMIPS_SPI_USER 0x2C -+#define RAMIPS_SPI_TXFIFO 0x30 -+#define RAMIPS_SPI_RXFIFO 0x34 -+#define RAMIPS_SPI_FIFO_STAT 0x38 -+#define RAMIPS_SPI_MODE 0x3C -+#define RAMIPS_SPI_DEV_OFFSET 0x40 -+#define RAMIPS_SPI_DMA 0x80 -+#define RAMIPS_SPI_DMASTAT 0x84 -+#define RAMIPS_SPI_ARBITER 0xF0 -+ -+/* SPISTAT register bit field */ -+#define SPISTAT_BUSY BIT(0) -+ -+/* SPICFG register bit field */ -+#define SPICFG_ADDRMODE BIT(12) -+#define SPICFG_RXENVDIS BIT(11) -+#define SPICFG_RXCAP BIT(10) -+#define SPICFG_SPIENMODE BIT(9) -+#define SPICFG_MSBFIRST BIT(8) -+#define SPICFG_SPICLKPOL BIT(6) -+#define SPICFG_RXCLKEDGE_FALLING BIT(5) -+#define SPICFG_TXCLKEDGE_FALLING BIT(4) -+#define SPICFG_HIZSPI BIT(3) -+#define SPICFG_SPICLK_PRESCALE_MASK 0x7 -+#define SPICFG_SPICLK_DIV2 0 -+#define SPICFG_SPICLK_DIV4 1 -+#define SPICFG_SPICLK_DIV8 2 -+#define SPICFG_SPICLK_DIV16 3 -+#define SPICFG_SPICLK_DIV32 4 -+#define SPICFG_SPICLK_DIV64 5 -+#define SPICFG_SPICLK_DIV128 6 -+#define SPICFG_SPICLK_DISABLE 7 -+ -+/* SPICTL register bit field */ -+#define SPICTL_START BIT(4) -+#define SPICTL_HIZSDO BIT(3) -+#define SPICTL_STARTWR BIT(2) -+#define SPICTL_STARTRD BIT(1) -+#define SPICTL_SPIENA BIT(0) -+ -+/* SPIUSER register bit field */ -+#define SPIUSER_USERMODE BIT(21) -+#define SPIUSER_INSTR_PHASE BIT(20) -+#define SPIUSER_ADDR_PHASE_MASK 0x7 -+#define SPIUSER_ADDR_PHASE_OFFSET 17 -+#define SPIUSER_MODE_PHASE BIT(16) -+#define SPIUSER_DUMMY_PHASE_MASK 0x3 -+#define SPIUSER_DUMMY_PHASE_OFFSET 14 -+#define SPIUSER_DATA_PHASE_MASK 0x3 -+#define SPIUSER_DATA_PHASE_OFFSET 12 -+#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET) -+#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET) -+#define SPIUSER_ADDR_TYPE_OFFSET 9 -+#define SPIUSER_MODE_TYPE_OFFSET 6 -+#define SPIUSER_DUMMY_TYPE_OFFSET 3 -+#define SPIUSER_DATA_TYPE_OFFSET 0 -+#define SPIUSER_TRANSFER_MASK 0x7 -+#define SPIUSER_TRANSFER_SINGLE BIT(0) -+#define SPIUSER_TRANSFER_DUAL BIT(1) -+#define SPIUSER_TRANSFER_QUAD BIT(2) -+ -+#define SPIUSER_TRANSFER_TYPE(type) ( \ -+ (type << SPIUSER_ADDR_TYPE_OFFSET) | \ -+ (type << SPIUSER_MODE_TYPE_OFFSET) | \ -+ (type << SPIUSER_DUMMY_TYPE_OFFSET) | \ -+ (type << SPIUSER_DATA_TYPE_OFFSET) \ -+) -+ -+/* SPIFIFOSTAT register bit field */ -+#define SPIFIFOSTAT_TXEMPTY BIT(19) -+#define SPIFIFOSTAT_RXEMPTY BIT(18) -+#define SPIFIFOSTAT_TXFULL BIT(17) -+#define SPIFIFOSTAT_RXFULL BIT(16) -+#define SPIFIFOSTAT_FIFO_MASK 0xff -+#define SPIFIFOSTAT_TX_OFFSET 8 -+#define SPIFIFOSTAT_RX_OFFSET 0 -+ -+#define SPI_FIFO_DEPTH 16 -+ -+/* SPIMODE register bit field */ -+#define SPIMODE_MODE_OFFSET 24 -+#define SPIMODE_DUMMY_OFFSET 0 -+ -+/* SPIARB register bit field */ -+#define SPICTL_ARB_EN BIT(31) -+#define SPICTL_CSCTL1 BIT(16) -+#define SPI1_POR BIT(1) -+#define SPI0_POR BIT(0) -+ -+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \ -+ SPI_CS_HIGH) -+ -+static atomic_t hw_reset_count = ATOMIC_INIT(0); -+ -+struct rt2880_spi { -+ struct spi_master *master; -+ void __iomem *base; -+ u32 speed; -+ u16 wait_loops; -+ u16 mode; -+ struct clk *clk; -+}; -+ -+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg) -+{ -+ return ioread32(rs->base + reg); -+} -+ -+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, -+ const u32 val) -+{ -+ iowrite32(val, rs->base + reg); -+} -+ -+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask) -+{ -+ void __iomem *addr = rs->base + reg; -+ -+ iowrite32((ioread32(addr) | mask), addr); -+} -+ -+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask) -+{ -+ void __iomem *addr = rs->base + reg; -+ -+ iowrite32((ioread32(addr) & ~mask), addr); -+} -+ -+static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed) -+{ -+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi); -+ u32 rate; -+ u32 prescale; -+ -+ /* -+ * the supported rates are: 2, 4, 8, ... 128 -+ * round up as we look for equal or less speed -+ */ -+ rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed); -+ rate = roundup_pow_of_two(rate); -+ -+ /* Convert the rate to SPI clock divisor value. */ -+ prescale = ilog2(rate / 2); -+ -+ /* some tolerance. double and add 100 */ -+ rs->wait_loops = (8 * HZ * loops_per_jiffy) / -+ (clk_get_rate(rs->clk) / rate); -+ rs->wait_loops = (rs->wait_loops << 1) + 100; -+ rs->speed = speed; -+ -+ dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n", -+ clk_get_rate(rs->clk) / rate, speed, rate, prescale, -+ rs->wait_loops); -+ -+ return prescale; -+} -+ -+static u32 get_arbiter_offset(struct spi_master *master) -+{ -+ u32 offset; -+ -+ offset = RAMIPS_SPI_ARBITER; -+ if (master->bus_num == 1) -+ offset -= RAMIPS_SPI_DEV_OFFSET; -+ -+ return offset; -+} -+ -+static void rt2880_spi_set_cs(struct spi_device *spi, bool enable) -+{ -+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi); -+ -+ if (enable) -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); -+ else -+ rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); -+} -+ -+static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len) -+{ -+ int loop = rs->wait_loops * len; -+ -+ while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop) -+ cpu_relax(); -+ -+ if (loop) -+ return 0; -+ -+ return -ETIMEDOUT; -+} -+ -+static void rt2880_dump_reg(struct spi_master *master) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ -+ dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \ -+ "data: %08x, arb: %08x\n", -+ rt2880_spi_read(rs, RAMIPS_SPI_STAT), -+ rt2880_spi_read(rs, RAMIPS_SPI_CFG), -+ rt2880_spi_read(rs, RAMIPS_SPI_CTL), -+ rt2880_spi_read(rs, RAMIPS_SPI_DATA), -+ rt2880_spi_read(rs, get_arbiter_offset(master))); -+} -+ -+static int rt2880_spi_transfer_one(struct spi_master *master, -+ struct spi_device *spi, struct spi_transfer *xfer) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ unsigned len; -+ const u8 *tx = xfer->tx_buf; -+ u8 *rx = xfer->rx_buf; -+ int err = 0; -+ -+ /* change clock speed */ -+ if (unlikely(rs->speed != xfer->speed_hz)) { -+ u32 reg; -+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG); -+ reg &= ~SPICFG_SPICLK_PRESCALE_MASK; -+ reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz); -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg); -+ } -+ -+ if (tx) { -+ len = xfer->len; -+ while (len-- > 0) { -+ rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++); -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR); -+ err = rt2880_spi_wait_ready(rs, 1); -+ if (err) { -+ dev_err(&spi->dev, "TX failed, err=%d\n", err); -+ goto out; -+ } -+ } -+ } -+ -+ if (rx) { -+ len = xfer->len; -+ while (len-- > 0) { -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD); -+ err = rt2880_spi_wait_ready(rs, 1); -+ if (err) { -+ dev_err(&spi->dev, "RX failed, err=%d\n", err); -+ goto out; -+ } -+ *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA); -+ } -+ } -+ -+out: -+ return err; -+} -+ -+/* copy from spi.c */ -+static void spi_set_cs(struct spi_device *spi, bool enable) -+{ -+ if (spi->mode & SPI_CS_HIGH) -+ enable = !enable; -+ -+ if (spi->cs_gpiod) -+ gpiod_set_value(spi->cs_gpiod, !enable); -+ else if (spi->master->set_cs) -+ spi->master->set_cs(spi, !enable); -+} -+ -+static int rt2880_spi_setup(struct spi_device *spi) -+{ -+ struct spi_master *master = spi->master; -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ u32 reg, old_reg, arbit_off; -+ -+ if ((spi->max_speed_hz > master->max_speed_hz) || -+ (spi->max_speed_hz < master->min_speed_hz)) { -+ dev_err(&spi->dev, "invalide requested speed %d Hz\n", -+ spi->max_speed_hz); -+ return -EINVAL; -+ } -+ -+ if (!(master->bits_per_word_mask & -+ BIT(spi->bits_per_word - 1))) { -+ dev_err(&spi->dev, "invalide bits_per_word %d\n", -+ spi->bits_per_word); -+ return -EINVAL; -+ } -+ -+ /* the hardware seems can't work on mode0 force it to mode3 */ -+ if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) { -+ dev_warn(&spi->dev, "force spi mode3\n"); -+ spi->mode |= SPI_MODE_3; -+ } -+ -+ /* chip polarity */ -+ arbit_off = get_arbiter_offset(master); -+ reg = old_reg = rt2880_spi_read(rs, arbit_off); -+ if (spi->mode & SPI_CS_HIGH) { -+ switch (master->bus_num) { -+ case 1: -+ reg |= SPI1_POR; -+ break; -+ default: -+ reg |= SPI0_POR; -+ break; -+ } -+ } else { -+ switch (master->bus_num) { -+ case 1: -+ reg &= ~SPI1_POR; -+ break; -+ default: -+ reg &= ~SPI0_POR; -+ break; -+ } -+ } -+ -+ /* enable spi1 */ -+ if (master->bus_num == 1) -+ reg |= SPICTL_ARB_EN; -+ -+ if (reg != old_reg) -+ rt2880_spi_write(rs, arbit_off, reg); -+ -+ /* deselected the spi device */ -+ spi_set_cs(spi, false); -+ -+ rt2880_dump_reg(master); -+ -+ return 0; -+} -+ -+static int rt2880_spi_prepare_message(struct spi_master *master, -+ struct spi_message *msg) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ struct spi_device *spi = msg->spi; -+ u32 reg; -+ -+ if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz)) -+ return 0; -+ -+#if 0 -+ /* set spido to tri-state */ -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO); -+#endif -+ -+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG); -+ -+ reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL | -+ SPICFG_RXCLKEDGE_FALLING | -+ SPICFG_TXCLKEDGE_FALLING | -+ SPICFG_SPICLK_PRESCALE_MASK); -+ -+ /* MSB */ -+ if (!(spi->mode & SPI_LSB_FIRST)) -+ reg |= SPICFG_MSBFIRST; -+ -+ /* spi mode */ -+ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { -+ case SPI_MODE_0: -+ reg |= SPICFG_TXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_1: -+ reg |= SPICFG_RXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_2: -+ reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_3: -+ reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING; -+ break; -+ } -+ rs->mode = spi->mode; -+ -+#if 0 -+ /* set spiclk and spiena to tri-state */ -+ reg |= SPICFG_HIZSPI; -+#endif -+ -+ /* clock divide */ -+ reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz); -+ -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg); -+ -+ return 0; -+} -+ -+static int rt2880_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct rt2880_spi *rs; -+ void __iomem *base; -+ struct resource *r; -+ struct clk *clk; -+ int ret; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, r); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "unable to get SYS clock\n"); -+ return PTR_ERR(clk); -+ } -+ -+ ret = clk_prepare_enable(clk); -+ if (ret) -+ goto err_clk; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*rs)); -+ if (master == NULL) { -+ dev_dbg(&pdev->dev, "master allocation failed\n"); -+ ret = -ENOMEM; -+ goto err_clk; -+ } -+ -+ master->dev.of_node = pdev->dev.of_node; -+ master->mode_bits = RT2880_SPI_MODE_BITS; -+ master->bits_per_word_mask = SPI_BPW_MASK(8); -+ master->min_speed_hz = clk_get_rate(clk) / 128; -+ master->max_speed_hz = clk_get_rate(clk) / 2; -+ master->flags = SPI_MASTER_HALF_DUPLEX; -+ master->setup = rt2880_spi_setup; -+ master->prepare_message = rt2880_spi_prepare_message; -+ master->set_cs = rt2880_spi_set_cs; -+ master->transfer_one = rt2880_spi_transfer_one, -+ -+ dev_set_drvdata(&pdev->dev, master); -+ -+ rs = spi_master_get_devdata(master); -+ rs->master = master; -+ rs->base = base; -+ rs->clk = clk; -+ -+ if (atomic_inc_return(&hw_reset_count) == 1) { -+ ret = device_reset(&pdev->dev); -+ if (ret) { -+ dev_err(&pdev->dev, "device_reset error.\n"); -+ goto err_master; -+ } -+ } -+ -+ ret = devm_spi_register_master(&pdev->dev, master); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "devm_spi_register_master error.\n"); -+ goto err_master; -+ } -+ -+ return ret; -+ -+err_master: -+ spi_master_put(master); -+ kfree(master); -+err_clk: -+ clk_disable_unprepare(clk); -+ -+ return ret; -+} -+ -+static int rt2880_spi_remove(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct rt2880_spi *rs; -+ -+ master = dev_get_drvdata(&pdev->dev); -+ rs = spi_master_get_devdata(master); -+ -+ clk_disable_unprepare(rs->clk); -+ atomic_dec(&hw_reset_count); -+ -+ return 0; -+} -+ -+MODULE_ALIAS("platform:" DRIVER_NAME); -+ -+static const struct of_device_id rt2880_spi_match[] = { -+ { .compatible = "ralink,rt2880-spi" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, rt2880_spi_match); -+ -+static struct platform_driver rt2880_spi_driver = { -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = rt2880_spi_match, -+ }, -+ .probe = rt2880_spi_probe, -+ .remove = rt2880_spi_remove, -+}; -+ -+module_platform_driver(rt2880_spi_driver); -+ -+MODULE_DESCRIPTION("Ralink SPI driver"); -+MODULE_AUTHOR("Sergiy "); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch b/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch deleted file mode 100644 index 461cf6e222423c..00000000000000 --- a/target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch +++ /dev/null @@ -1,512 +0,0 @@ -From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:52:56 +0100 -Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver - -Signed-off-by: John Crispin ---- - .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++ - drivers/i2c/busses/Kconfig | 4 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++ - 4 files changed, 359 insertions(+) - create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt - create mode 100644 drivers/i2c/busses/i2c-ralink.c - ---- /dev/null -+++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt -@@ -0,0 +1,27 @@ -+I2C for Ralink platforms -+ -+Required properties : -+- compatible : Must be "link,rt3052-i2c" -+- reg: physical base address of the controller and length of memory mapped -+ region. -+- #address-cells = <1>; -+- #size-cells = <0>; -+ -+Optional properties: -+- Child nodes conforming to i2c bus binding -+ -+Example : -+ -+palmbus@10000000 { -+ i2c@900 { -+ compatible = "link,rt3052-i2c"; -+ reg = <0x900 0x100>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hwmon@4b { -+ compatible = "national,lm92"; -+ reg = <0x4b>; -+ }; -+ }; -+}; ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -998,6 +998,11 @@ config I2C_RK3X - This driver can also be built as a module. If so, the module will - be called i2c-rk3x. - -+config I2C_RALINK -+ tristate "Ralink I2C Controller" -+ depends on RALINK && !SOC_MT7621 -+ select OF_I2C -+ - config I2C_RZV2M - tristate "Renesas RZ/V2M adapter" - depends on ARCH_RENESAS || COMPILE_TEST ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pc - obj-$(CONFIG_I2C_PNX) += i2c-pnx.o - obj-$(CONFIG_I2C_PXA) += i2c-pxa.o - obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o -+obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o - obj-$(CONFIG_I2C_QCOM_CCI) += i2c-qcom-cci.o - obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o - obj-$(CONFIG_I2C_QUP) += i2c-qup.o ---- /dev/null -+++ b/drivers/i2c/busses/i2c-ralink.c -@@ -0,0 +1,440 @@ -+/* -+ * drivers/i2c/busses/i2c-ralink.c -+ * -+ * Copyright (C) 2013 Steven Liu -+ * Copyright (C) 2016 Michael Lee -+ * -+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus. -+ * (C) 2014 Sittisak -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define REG_CONFIG_REG 0x00 -+#define REG_CLKDIV_REG 0x04 -+#define REG_DEVADDR_REG 0x08 -+#define REG_ADDR_REG 0x0C -+#define REG_DATAOUT_REG 0x10 -+#define REG_DATAIN_REG 0x14 -+#define REG_STATUS_REG 0x18 -+#define REG_STARTXFR_REG 0x1C -+#define REG_BYTECNT_REG 0x20 -+ -+/* REG_CONFIG_REG */ -+#define I2C_ADDRLEN_OFFSET 5 -+#define I2C_DEVADLEN_OFFSET 2 -+#define I2C_ADDRLEN_MASK 0x3 -+#define I2C_ADDR_DIS BIT(1) -+#define I2C_DEVADDR_DIS BIT(0) -+#define I2C_ADDRLEN_8 (7 << I2C_ADDRLEN_OFFSET) -+#define I2C_DEVADLEN_7 (6 << I2C_DEVADLEN_OFFSET) -+#define I2C_CONF_DEFAULT (I2C_ADDRLEN_8 | I2C_DEVADLEN_7) -+ -+/* REG_CLKDIV_REG */ -+#define I2C_CLKDIV_MASK 0xffff -+ -+/* REG_DEVADDR_REG */ -+#define I2C_DEVADDR_MASK 0x7f -+ -+/* REG_ADDR_REG */ -+#define I2C_ADDR_MASK 0xff -+ -+/* REG_STATUS_REG */ -+#define I2C_STARTERR BIT(4) -+#define I2C_ACKERR BIT(3) -+#define I2C_DATARDY BIT(2) -+#define I2C_SDOEMPTY BIT(1) -+#define I2C_BUSY BIT(0) -+ -+/* REG_STARTXFR_REG */ -+#define NOSTOP_CMD BIT(2) -+#define NODATA_CMD BIT(1) -+#define READ_CMD BIT(0) -+ -+/* REG_BYTECNT_REG */ -+#define BYTECNT_MAX 64 -+#define SET_BYTECNT(x) (x - 1) -+ -+/* timeout waiting for I2C devices to respond (clock streching) */ -+#define TIMEOUT_MS 1000 -+#define DELAY_INTERVAL_US 100 -+ -+struct rt_i2c { -+ void __iomem *base; -+ struct clk *clk; -+ struct device *dev; -+ struct i2c_adapter adap; -+ u32 cur_clk; -+ u32 clk_div; -+ u32 flags; -+}; -+ -+static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg) -+{ -+ iowrite32(val, i2c->base + reg); -+} -+ -+static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg) -+{ -+ return ioread32(i2c->base + reg); -+} -+ -+static int poll_down_timeout(void __iomem *addr, u32 mask) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); -+ -+ do { -+ if (!(readl_relaxed(addr) & mask)) -+ return 0; -+ -+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); -+ } while (time_before(jiffies, timeout)); -+ -+ return (readl_relaxed(addr) & mask) ? -EAGAIN : 0; -+} -+ -+static int rt_i2c_wait_idle(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "idle err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static int poll_up_timeout(void __iomem *addr, u32 mask) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); -+ u32 status; -+ -+ do { -+ status = readl_relaxed(addr); -+ -+ /* check error status */ -+ if (status & I2C_STARTERR) -+ return -EAGAIN; -+ else if (status & I2C_ACKERR) -+ return -ENXIO; -+ else if (status & mask) -+ return 0; -+ -+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); -+ } while (time_before(jiffies, timeout)); -+ -+ return -ETIMEDOUT; -+} -+ -+static int rt_i2c_wait_rx_done(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "rx err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static int rt_i2c_wait_tx_done(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "tx err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static void rt_i2c_reset(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = device_reset(i2c->adap.dev.parent); -+ if (ret) -+ dev_err(i2c->dev, "Failed to reset device"); -+ -+ barrier(); -+ rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG); -+} -+ -+static void rt_i2c_dump_reg(struct rt_i2c *i2c) -+{ -+ dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \ -+ "addr %08x, dataout %08x, datain %08x, " \ -+ "status %08x, startxfr %08x, bytecnt %08x\n", -+ rt_i2c_r32(i2c, REG_CONFIG_REG), -+ rt_i2c_r32(i2c, REG_CLKDIV_REG), -+ rt_i2c_r32(i2c, REG_DEVADDR_REG), -+ rt_i2c_r32(i2c, REG_ADDR_REG), -+ rt_i2c_r32(i2c, REG_DATAOUT_REG), -+ rt_i2c_r32(i2c, REG_DATAIN_REG), -+ rt_i2c_r32(i2c, REG_STATUS_REG), -+ rt_i2c_r32(i2c, REG_STARTXFR_REG), -+ rt_i2c_r32(i2c, REG_BYTECNT_REG)); -+} -+ -+static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, -+ int num) -+{ -+ struct rt_i2c *i2c; -+ struct i2c_msg *pmsg; -+ unsigned char addr; -+ int i, j, ret; -+ u32 cmd; -+ -+ i2c = i2c_get_adapdata(adap); -+ -+ for (i = 0; i < num; i++) { -+ pmsg = &msgs[i]; -+ if (i == (num - 1)) -+ cmd = 0; -+ else -+ cmd = NOSTOP_CMD; -+ -+ dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n", -+ pmsg->addr, pmsg->len, pmsg->flags, -+ (cmd == 0)? 1 : 0); -+ -+ /* wait hardware idle */ -+ if ((ret = rt_i2c_wait_idle(i2c))) -+ goto err_timeout; -+ -+ if (pmsg->flags & I2C_M_TEN) { -+ rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG); -+ /* 10 bits address */ -+ addr = 0x78 | ((pmsg->addr >> 8) & 0x03); -+ rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK, -+ REG_DEVADDR_REG); -+ rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK, -+ REG_ADDR_REG); -+ } else { -+ rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS, -+ REG_CONFIG_REG); -+ /* 7 bits address */ -+ rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK, -+ REG_DEVADDR_REG); -+ } -+ -+ /* buffer length */ -+ if (pmsg->len == 0) -+ cmd |= NODATA_CMD; -+ else -+ rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len), -+ REG_BYTECNT_REG); -+ -+ j = 0; -+ if (pmsg->flags & I2C_M_RD) { -+ cmd |= READ_CMD; -+ /* start transfer */ -+ barrier(); -+ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG); -+ do { -+ /* wait */ -+ if ((ret = rt_i2c_wait_rx_done(i2c))) -+ goto err_timeout; -+ /* read data */ -+ if (pmsg->len) -+ pmsg->buf[j] = rt_i2c_r32(i2c, -+ REG_DATAIN_REG); -+ j++; -+ } while (j < pmsg->len); -+ } else { -+ do { -+ /* write data */ -+ if (pmsg->len) -+ rt_i2c_w32(i2c, pmsg->buf[j], -+ REG_DATAOUT_REG); -+ /* start transfer */ -+ if (j == 0) { -+ barrier(); -+ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG); -+ } -+ /* wait */ -+ if ((ret = rt_i2c_wait_tx_done(i2c))) -+ goto err_timeout; -+ j++; -+ } while (j < pmsg->len); -+ } -+ } -+ /* the return value is number of executed messages */ -+ ret = i; -+ -+ return ret; -+ -+err_timeout: -+ rt_i2c_dump_reg(i2c); -+ rt_i2c_reset(i2c); -+ return ret; -+} -+ -+static u32 rt_i2c_func(struct i2c_adapter *a) -+{ -+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -+} -+ -+static const struct i2c_algorithm rt_i2c_algo = { -+ .master_xfer = rt_i2c_master_xfer, -+ .functionality = rt_i2c_func, -+}; -+ -+static const struct of_device_id i2c_rt_dt_ids[] = { -+ { .compatible = "ralink,rt2880-i2c" }, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids); -+ -+static struct i2c_adapter_quirks rt_i2c_quirks = { -+ .max_write_len = BYTECNT_MAX, -+ .max_read_len = BYTECNT_MAX, -+}; -+ -+static int rt_i2c_init(struct rt_i2c *i2c) -+{ -+ u32 reg; -+ -+ /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */ -+ i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) / -+ (2 * i2c->cur_clk); -+ if (i2c->clk_div < 8) -+ i2c->clk_div = 8; -+ if (i2c->clk_div > I2C_CLKDIV_MASK) -+ i2c->clk_div = I2C_CLKDIV_MASK; -+ -+ /* check support combinde/repeated start message */ -+ rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG); -+ reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD; -+ -+ rt_i2c_reset(i2c); -+ -+ return reg; -+} -+ -+static int rt_i2c_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ struct rt_i2c *i2c; -+ struct i2c_adapter *adap; -+ const struct of_device_id *match; -+ int ret, restart; -+ -+ match = of_match_device(i2c_rt_dt_ids, &pdev->dev); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "no memory resource found\n"); -+ return -ENODEV; -+ } -+ -+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL); -+ if (!i2c) { -+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n"); -+ return -ENOMEM; -+ } -+ -+ i2c->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(i2c->base)) -+ return PTR_ERR(i2c->base); -+ -+ i2c->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(i2c->clk)) { -+ dev_err(&pdev->dev, "no clock defined\n"); -+ return -ENODEV; -+ } -+ clk_prepare_enable(i2c->clk); -+ i2c->dev = &pdev->dev; -+ -+ if (of_property_read_u32(pdev->dev.of_node, -+ "clock-frequency", &i2c->cur_clk)) -+ i2c->cur_clk = 100000; -+ -+ adap = &i2c->adap; -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; -+ adap->algo = &rt_i2c_algo; -+ adap->retries = 3; -+ adap->dev.parent = &pdev->dev; -+ i2c_set_adapdata(adap, i2c); -+ adap->dev.of_node = pdev->dev.of_node; -+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); -+ adap->quirks = &rt_i2c_quirks; -+ -+ platform_set_drvdata(pdev, i2c); -+ -+ restart = rt_i2c_init(i2c); -+ -+ ret = i2c_add_adapter(adap); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to add adapter\n"); -+ clk_disable_unprepare(i2c->clk); -+ return ret; -+ } -+ -+ dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n", -+ i2c->cur_clk/1000, restart ? "" : "not "); -+ -+ return ret; -+} -+ -+static int rt_i2c_remove(struct platform_device *pdev) -+{ -+ struct rt_i2c *i2c = platform_get_drvdata(pdev); -+ -+ i2c_del_adapter(&i2c->adap); -+ clk_disable_unprepare(i2c->clk); -+ -+ return 0; -+} -+ -+static struct platform_driver rt_i2c_driver = { -+ .probe = rt_i2c_probe, -+ .remove = rt_i2c_remove, -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "i2c-ralink", -+ .of_match_table = i2c_rt_dt_ids, -+ }, -+}; -+ -+static int __init i2c_rt_init (void) -+{ -+ return platform_driver_register(&rt_i2c_driver); -+} -+subsys_initcall(i2c_rt_init); -+ -+static void __exit i2c_rt_exit (void) -+{ -+ platform_driver_unregister(&rt_i2c_driver); -+} -+module_exit(i2c_rt_exit); -+ -+MODULE_AUTHOR("Steven Liu "); -+MODULE_DESCRIPTION("Ralink I2c host driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:Ralink-I2C"); diff --git a/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch deleted file mode 100644 index 37a10589a379a1..00000000000000 --- a/target/linux/ramips/patches-6.1/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 13 Nov 2014 19:08:40 +0100 -Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC - -Signed-off-by: John Crispin ---- - drivers/mmc/host/Kconfig | 2 + - drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/mtk-mmc/Kconfig | 16 + - drivers/mmc/host/mtk-mmc/Makefile | 42 + - drivers/mmc/host/mtk-mmc/board.h | 137 ++ - drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++ - drivers/mmc/host/mtk-mmc/dbg.h | 156 ++ - drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++ - drivers/mmc/host/mtk-mmc/sd.c | 3060 ++++++++++++++++++++++++++++++++++ - 9 files changed, 4762 insertions(+) - create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig - create mode 100644 drivers/mmc/host/mtk-mmc/Makefile - create mode 100644 drivers/mmc/host/mtk-mmc/board.h - create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c - create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h - create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h - create mode 100644 drivers/mmc/host/mtk-mmc/sd.c - ---- a/drivers/mmc/host/Kconfig -+++ b/drivers/mmc/host/Kconfig -@@ -1102,6 +1102,8 @@ config MMC_OWL - config MMC_SDHCI_EXTERNAL_DMA - bool - -+source "drivers/mmc/host/mtk-mmc/Kconfig" -+ - config MMC_LITEX - tristate "LiteX MMC Host Controller support" - depends on ((PPC_MICROWATT || LITEX) && OF && HAVE_CLK) || COMPILE_TEST ---- a/drivers/mmc/host/Makefile -+++ b/drivers/mmc/host/Makefile -@@ -3,6 +3,7 @@ - # Makefile for MMC/SD host controller drivers - # - -+obj-$(CONFIG_MTK_MMC) += mtk-mmc/ - obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o - armmmci-y := mmci.o - armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o diff --git a/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch b/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch deleted file mode 100644 index 57f0ec2c506c29..00000000000000 --- a/target/linux/ramips/patches-6.1/835-asoc-add-mt7620-support.patch +++ /dev/null @@ -1,1031 +0,0 @@ -From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:31:47 +0100 -Subject: [PATCH 48/53] asoc: add mt7620 support - -Signed-off-by: John Crispin ---- - arch/mips/ralink/of.c | 2 + - sound/soc/Kconfig | 1 + - sound/soc/Makefile | 1 + - sound/soc/ralink/Kconfig | 15 ++ - sound/soc/ralink/Makefile | 11 + - sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++ - sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++ - 7 files changed, 699 insertions(+) - create mode 100644 sound/soc/ralink/Kconfig - create mode 100644 sound/soc/ralink/Makefile - create mode 100644 sound/soc/ralink/mt7620-i2s.c - create mode 100644 sound/soc/ralink/mt7620-wm8960.c - ---- a/sound/soc/Kconfig -+++ b/sound/soc/Kconfig -@@ -86,6 +86,7 @@ source "sound/soc/mxs/Kconfig" - source "sound/soc/pxa/Kconfig" - source "sound/soc/qcom/Kconfig" - source "sound/soc/rockchip/Kconfig" -+source "sound/soc/ralink/Kconfig" - source "sound/soc/samsung/Kconfig" - source "sound/soc/sh/Kconfig" - source "sound/soc/sof/Kconfig" ---- a/sound/soc/Makefile -+++ b/sound/soc/Makefile -@@ -54,6 +54,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/ - obj-$(CONFIG_SND_SOC) += pxa/ - obj-$(CONFIG_SND_SOC) += qcom/ - obj-$(CONFIG_SND_SOC) += rockchip/ -+obj-$(CONFIG_SND_SOC) += ralink/ - obj-$(CONFIG_SND_SOC) += samsung/ - obj-$(CONFIG_SND_SOC) += sh/ - obj-$(CONFIG_SND_SOC) += sof/ ---- /dev/null -+++ b/sound/soc/ralink/Kconfig -@@ -0,0 +1,8 @@ -+config SND_RALINK_SOC_I2S -+ depends on RALINK && SND_SOC && !SOC_RT288X -+ select SND_SOC_GENERIC_DMAENGINE_PCM -+ select REGMAP_MMIO -+ tristate "SoC Audio (I2S protocol) for Ralink SoC" -+ help -+ Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek -+ based boards. ---- /dev/null -+++ b/sound/soc/ralink/Makefile -@@ -0,0 +1,6 @@ -+# -+# Ralink/MediaTek Platform Support -+# -+snd-soc-ralink-i2s-objs := ralink-i2s.o -+ -+obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o ---- /dev/null -+++ b/sound/soc/ralink/ralink-i2s.c -@@ -0,0 +1,968 @@ -+/* -+ * Copyright (C) 2010, Lars-Peter Clausen -+ * Copyright (C) 2016 Michael Lee -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "ralink-i2s" -+ -+#define I2S_REG_CFG0 0x00 -+#define I2S_REG_INT_STATUS 0x04 -+#define I2S_REG_INT_EN 0x08 -+#define I2S_REG_FF_STATUS 0x0c -+#define I2S_REG_WREG 0x10 -+#define I2S_REG_RREG 0x14 -+#define I2S_REG_CFG1 0x18 -+#define I2S_REG_DIVCMP 0x20 -+#define I2S_REG_DIVINT 0x24 -+ -+/* I2S_REG_CFG0 */ -+#define I2S_REG_CFG0_EN BIT(31) -+#define I2S_REG_CFG0_DMA_EN BIT(30) -+#define I2S_REG_CFG0_BYTE_SWAP BIT(28) -+#define I2S_REG_CFG0_TX_EN BIT(24) -+#define I2S_REG_CFG0_RX_EN BIT(20) -+#define I2S_REG_CFG0_SLAVE BIT(16) -+#define I2S_REG_CFG0_RX_THRES 12 -+#define I2S_REG_CFG0_TX_THRES 4 -+#define I2S_REG_CFG0_THRES_MASK (0xf << I2S_REG_CFG0_RX_THRES) | \ -+ (4 << I2S_REG_CFG0_TX_THRES) -+#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \ -+ (4 << I2S_REG_CFG0_TX_THRES) -+/* RT305x */ -+#define I2S_REG_CFG0_CLK_DIS BIT(8) -+#define I2S_REG_CFG0_TXCH_SWAP BIT(3) -+#define I2S_REG_CFG0_TXCH1_OFF BIT(2) -+#define I2S_REG_CFG0_TXCH0_OFF BIT(1) -+#define I2S_REG_CFG0_SLAVE_EN BIT(0) -+/* RT3883 */ -+#define I2S_REG_CFG0_RXCH_SWAP BIT(11) -+#define I2S_REG_CFG0_RXCH1_OFF BIT(10) -+#define I2S_REG_CFG0_RXCH0_OFF BIT(9) -+#define I2S_REG_CFG0_WS_INV BIT(0) -+/* MT7628 */ -+#define I2S_REG_CFG0_FMT_LE BIT(29) -+#define I2S_REG_CFG0_SYS_BE BIT(28) -+#define I2S_REG_CFG0_NORM_24 BIT(18) -+#define I2S_REG_CFG0_DATA_24 BIT(17) -+ -+/* I2S_REG_INT_STATUS */ -+#define I2S_REG_INT_RX_FAULT BIT(7) -+#define I2S_REG_INT_RX_OVRUN BIT(6) -+#define I2S_REG_INT_RX_UNRUN BIT(5) -+#define I2S_REG_INT_RX_THRES BIT(4) -+#define I2S_REG_INT_TX_FAULT BIT(3) -+#define I2S_REG_INT_TX_OVRUN BIT(2) -+#define I2S_REG_INT_TX_UNRUN BIT(1) -+#define I2S_REG_INT_TX_THRES BIT(0) -+#define I2S_REG_INT_TX_MASK 0xf -+#define I2S_REG_INT_RX_MASK 0xf0 -+ -+/* I2S_REG_INT_STATUS */ -+#define I2S_RX_AVCNT(x) ((x >> 4) & 0xf) -+#define I2S_TX_AVCNT(x) (x & 0xf) -+/* MT7628 */ -+#define MT7628_I2S_RX_AVCNT(x) ((x >> 8) & 0x1f) -+#define MT7628_I2S_TX_AVCNT(x) (x & 0x1f) -+ -+/* I2S_REG_CFG1 */ -+#define I2S_REG_CFG1_LBK BIT(31) -+#define I2S_REG_CFG1_EXTLBK BIT(30) -+/* RT3883 */ -+#define I2S_REG_CFG1_LEFT_J BIT(0) -+#define I2S_REG_CFG1_RIGHT_J BIT(1) -+#define I2S_REG_CFG1_FMT_MASK 0x3 -+ -+/* I2S_REG_DIVCMP */ -+#define I2S_REG_DIVCMP_CLKEN BIT(31) -+#define I2S_REG_DIVCMP_DIVCOMP_MASK 0x1ff -+ -+/* I2S_REG_DIVINT */ -+#define I2S_REG_DIVINT_MASK 0x3ff -+ -+/* BCLK dividers */ -+#define RALINK_I2S_DIVCMP 0 -+#define RALINK_I2S_DIVINT 1 -+ -+/* FIFO */ -+#define RALINK_I2S_FIFO_SIZE 32 -+ -+/* feature flags */ -+#define RALINK_FLAGS_TXONLY BIT(0) -+#define RALINK_FLAGS_LEFT_J BIT(1) -+#define RALINK_FLAGS_RIGHT_J BIT(2) -+#define RALINK_FLAGS_ENDIAN BIT(3) -+#define RALINK_FLAGS_24BIT BIT(4) -+ -+#define RALINK_I2S_INT_EN 0 -+ -+struct ralink_i2s_stats { -+ u32 dmafault; -+ u32 overrun; -+ u32 underrun; -+ u32 belowthres; -+}; -+ -+struct ralink_i2s { -+ struct device *dev; -+ void __iomem *regs; -+ struct clk *clk; -+ struct regmap *regmap; -+ u32 flags; -+ unsigned int fmt; -+ u16 txdma_req; -+ u16 rxdma_req; -+ -+ struct snd_dmaengine_dai_dma_data playback_dma_data; -+ struct snd_dmaengine_dai_dma_data capture_dma_data; -+ -+ struct dentry *dbg_dir; -+ struct dentry *dbg_stats; -+ struct ralink_i2s_stats txstats; -+ struct ralink_i2s_stats rxstats; -+}; -+ -+static void ralink_i2s_dump_regs(struct ralink_i2s *i2s) -+{ -+ u32 buf[10]; -+ int ret; -+ -+ ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0, -+ buf, ARRAY_SIZE(buf)); -+ -+ dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \ -+ "FFSTAT: %08x, WREG: %08x, RREG: %08x, " \ -+ "CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n", -+ buf[0], buf[1], buf[2], buf[3], buf[4], -+ buf[5], buf[6], buf[8], buf[9]); -+} -+ -+static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai, -+ int clk_id, unsigned int freq, int dir) -+{ -+ return 0; -+} -+ -+static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned long clk = clk_get_rate(i2s->clk); -+ int div; -+ uint32_t data; -+ -+ /* disable clock at slave mode */ -+ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) == -+ SND_SOC_DAIFMT_CBM_CFM) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_CLK_DIS, -+ I2S_REG_CFG0_CLK_DIS); -+ return 0; -+ } -+ -+ /* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */ -+ div = (clk / rate ) - 1; -+ -+ data = rt_sysc_r32(0x30); -+ data &= (0xff << 8); -+ data |= (0x1 << 15) | (div << 8); -+ rt_sysc_w32(data, 0x30); -+ -+ /* enable clock */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0); -+ -+ dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n", -+ clk, rate, div); -+ -+ return 0; -+} -+ -+static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned long clk = clk_get_rate(i2s->clk); -+ int divint, divcomp; -+ -+ /* disable clock at slave mode */ -+ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) == -+ SND_SOC_DAIFMT_CBM_CFM) { -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, -+ I2S_REG_DIVCMP_CLKEN, 0); -+ return 0; -+ } -+ -+ /* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */ -+ clk = clk / (2 * 2 * width); -+ divint = clk / rate; -+ divcomp = ((clk % rate) * 512) / rate; -+ -+ if ((divint > I2S_REG_DIVINT_MASK) || -+ (divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK)) -+ return -EINVAL; -+ -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVINT, -+ I2S_REG_DIVINT_MASK, divint); -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, -+ I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp); -+ -+ /* enable clock */ -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN, -+ I2S_REG_DIVCMP_CLKEN); -+ -+ dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n", -+ clk_get_rate(i2s->clk), rate, divint, divcomp); -+ -+ return 0; -+} -+ -+static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned int cfg0 = 0, cfg1 = 0; -+ -+ /* set master/slave audio interface */ -+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBM_CFM: -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ cfg0 |= I2S_REG_CFG0_SLAVE_EN; -+ else -+ cfg0 |= I2S_REG_CFG0_SLAVE; -+ break; -+ case SND_SOC_DAIFMT_CBS_CFS: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* interface format */ -+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_I2S: -+ break; -+ case SND_SOC_DAIFMT_RIGHT_J: -+ if (i2s->flags & RALINK_FLAGS_RIGHT_J) { -+ cfg1 |= I2S_REG_CFG1_RIGHT_J; -+ break; -+ } -+ return -EINVAL; -+ case SND_SOC_DAIFMT_LEFT_J: -+ if (i2s->flags & RALINK_FLAGS_LEFT_J) { -+ cfg1 |= I2S_REG_CFG1_LEFT_J; -+ break; -+ } -+ return -EINVAL; -+ default: -+ return -EINVAL; -+ } -+ -+ /* clock inversion */ -+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_NB_NF: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SLAVE_EN, cfg0); -+ } else { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SLAVE, cfg0); -+ } -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG1, -+ I2S_REG_CFG1_FMT_MASK, cfg1); -+ i2s->fmt = fmt; -+ -+ return 0; -+} -+ -+static int ralink_i2s_startup(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ if (snd_soc_dai_active(dai)) -+ return 0; -+ -+ /* setup status interrupt */ -+#if (RALINK_I2S_INT_EN) -+ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff); -+#else -+ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0); -+#endif -+ -+ /* enable */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN | -+ I2S_REG_CFG0_THRES_MASK, -+ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN | -+ I2S_REG_CFG0_DFT_THRES); -+ -+ return 0; -+} -+ -+static void ralink_i2s_shutdown(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ /* If both streams are stopped, disable module and clock */ -+ if (snd_soc_dai_active(dai)) -+ return; -+ -+ /* -+ * datasheet mention when disable all control regs are cleared -+ * to initial values. need reinit at startup. -+ */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0); -+} -+ -+static int ralink_i2s_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ int width; -+ int ret; -+ -+ width = params_width(params); -+ switch (width) { -+ case 16: -+ if (i2s->flags & RALINK_FLAGS_24BIT) -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_DATA_24, 0); -+ break; -+ case 24: -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_DATA_24, -+ I2S_REG_CFG0_DATA_24); -+ break; -+ } -+ return -EINVAL; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (params_channels(params)) { -+ case 2: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (i2s->flags & RALINK_FLAGS_ENDIAN) { -+ /* system endian */ -+#ifdef SNDRV_LITTLE_ENDIAN -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SYS_BE, 0); -+#else -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SYS_BE, -+ I2S_REG_CFG0_SYS_BE); -+#endif -+ -+ /* data endian */ -+ switch (params_format(params)) { -+ case SNDRV_PCM_FORMAT_S16_LE: -+ case SNDRV_PCM_FORMAT_S24_LE: -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_FMT_LE, -+ I2S_REG_CFG0_FMT_LE); -+ break; -+ case SNDRV_PCM_FORMAT_S16_BE: -+ case SNDRV_PCM_FORMAT_S24_BE: -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_FMT_LE, 0); -+ break; -+ default: -+ return -EINVAL; -+ } -+ } -+ -+ /* setup bclk rate */ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params)); -+ else -+ ret = ralink_i2s_set_bclk(dai, width, params_rate(params)); -+ -+ return ret; -+} -+ -+static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned int mask, val; -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ mask = I2S_REG_CFG0_TX_EN; -+ else -+ mask = I2S_REG_CFG0_RX_EN; -+ -+ switch (cmd) { -+ case SNDRV_PCM_TRIGGER_START: -+ case SNDRV_PCM_TRIGGER_RESUME: -+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: -+ val = mask; -+ break; -+ case SNDRV_PCM_TRIGGER_STOP: -+ case SNDRV_PCM_TRIGGER_SUSPEND: -+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: -+ val = 0; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val); -+ -+ return 0; -+} -+ -+static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s, -+ struct resource *res) -+{ -+ struct snd_dmaengine_dai_dma_data *dma_data; -+ -+ /* Playback */ -+ dma_data = &i2s->playback_dma_data; -+ dma_data->addr = res->start + I2S_REG_WREG; -+ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ dma_data->maxburst = 1; -+ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ return; -+ -+ /* Capture */ -+ dma_data = &i2s->capture_dma_data; -+ dma_data->addr = res->start + I2S_REG_RREG; -+ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ dma_data->maxburst = 1; -+} -+ -+static int ralink_i2s_dai_probe(struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, -+ &i2s->capture_dma_data); -+ -+ return 0; -+} -+ -+static int ralink_i2s_dai_remove(struct snd_soc_dai *dai) -+{ -+ return 0; -+} -+ -+static const struct snd_soc_dai_ops ralink_i2s_dai_ops = { -+ .set_sysclk = ralink_i2s_set_sysclk, -+ .set_fmt = ralink_i2s_set_fmt, -+ .startup = ralink_i2s_startup, -+ .shutdown = ralink_i2s_shutdown, -+ .hw_params = ralink_i2s_hw_params, -+ .trigger = ralink_i2s_trigger, -+}; -+ -+static struct snd_soc_dai_driver ralink_i2s_dai = { -+ .name = DRV_NAME, -+ .probe = ralink_i2s_dai_probe, -+ .remove = ralink_i2s_dai_remove, -+ .ops = &ralink_i2s_dai_ops, -+ .capture = { -+ .stream_name = "I2S Capture", -+ .channels_min = 2, -+ .channels_max = 2, -+ .rate_min = 5512, -+ .rate_max = 192000, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ }, -+ .playback = { -+ .stream_name = "I2S Playback", -+ .channels_min = 2, -+ .channels_max = 2, -+ .rate_min = 5512, -+ .rate_max = 192000, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ }, -+ .symmetric_rate = 1, -+}; -+ -+static struct snd_pcm_hardware ralink_pcm_hardware = { -+ .info = SNDRV_PCM_INFO_MMAP | -+ SNDRV_PCM_INFO_MMAP_VALID | -+ SNDRV_PCM_INFO_INTERLEAVED | -+ SNDRV_PCM_INFO_BLOCK_TRANSFER, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ .channels_min = 2, -+ .channels_max = 2, -+ .period_bytes_min = PAGE_SIZE, -+ .period_bytes_max = PAGE_SIZE * 2, -+ .periods_min = 2, -+ .periods_max = 128, -+ .buffer_bytes_max = 128 * 1024, -+ .fifo_size = RALINK_I2S_FIFO_SIZE, -+}; -+ -+static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = { -+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, -+ .pcm_hardware = &ralink_pcm_hardware, -+ .prealloc_buffer_size = 256 * PAGE_SIZE, -+}; -+ -+static const struct snd_soc_component_driver ralink_i2s_component = { -+ .name = DRV_NAME, -+}; -+ -+static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg) -+{ -+ return true; -+} -+ -+static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case I2S_REG_INT_STATUS: -+ case I2S_REG_FF_STATUS: -+ return true; -+ } -+ return false; -+} -+ -+static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case I2S_REG_FF_STATUS: -+ case I2S_REG_RREG: -+ return false; -+ } -+ return true; -+} -+ -+static const struct regmap_config ralink_i2s_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .writeable_reg = ralink_i2s_writeable_reg, -+ .readable_reg = ralink_i2s_readable_reg, -+ .volatile_reg = ralink_i2s_volatile_reg, -+ .max_register = I2S_REG_DIVINT, -+}; -+ -+#if (RALINK_I2S_INT_EN) -+static irqreturn_t ralink_i2s_irq(int irq, void *devid) -+{ -+ struct ralink_i2s *i2s = devid; -+ u32 status; -+ -+ regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status); -+ if (unlikely(!status)) -+ return IRQ_NONE; -+ -+ /* tx stats */ -+ if (status & I2S_REG_INT_TX_MASK) { -+ if (status & I2S_REG_INT_TX_THRES) -+ i2s->txstats.belowthres++; -+ if (status & I2S_REG_INT_TX_UNRUN) -+ i2s->txstats.underrun++; -+ if (status & I2S_REG_INT_TX_OVRUN) -+ i2s->txstats.overrun++; -+ if (status & I2S_REG_INT_TX_FAULT) -+ i2s->txstats.dmafault++; -+ } -+ -+ /* rx stats */ -+ if (status & I2S_REG_INT_RX_MASK) { -+ if (status & I2S_REG_INT_RX_THRES) -+ i2s->rxstats.belowthres++; -+ if (status & I2S_REG_INT_RX_UNRUN) -+ i2s->rxstats.underrun++; -+ if (status & I2S_REG_INT_RX_OVRUN) -+ i2s->rxstats.overrun++; -+ if (status & I2S_REG_INT_RX_FAULT) -+ i2s->rxstats.dmafault++; -+ } -+ -+ /* clean status bits */ -+ regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status); -+ -+ return IRQ_HANDLED; -+} -+#endif -+ -+#if IS_ENABLED(CONFIG_DEBUG_FS) -+static int ralink_i2s_stats_show(struct seq_file *s, void *unused) -+{ -+ struct ralink_i2s *i2s = s->private; -+ -+ seq_printf(s, "tx stats\n"); -+ seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres); -+ seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun); -+ seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun); -+ seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault); -+ -+ seq_printf(s, "rx stats\n"); -+ seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres); -+ seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun); -+ seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun); -+ seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault); -+ -+ ralink_i2s_dump_regs(i2s); -+ -+ return 0; -+} -+ -+static int ralink_i2s_stats_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, ralink_i2s_stats_show, inode->i_private); -+} -+ -+static const struct file_operations ralink_i2s_stats_ops = { -+ .open = ralink_i2s_stats_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s) -+{ -+ i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL); -+ if (!i2s->dbg_dir) -+ return -ENOMEM; -+ -+ i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO, -+ i2s->dbg_dir, i2s, &ralink_i2s_stats_ops); -+ if (!i2s->dbg_stats) { -+ debugfs_remove(i2s->dbg_dir); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s) -+{ -+ debugfs_remove(i2s->dbg_stats); -+ debugfs_remove(i2s->dbg_dir); -+} -+#else -+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s) -+{ -+ return 0; -+} -+ -+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s) -+{ -+} -+#endif -+ -+/* -+ * TODO: these refclk setup functions should use -+ * clock framework instead. hardcode it now. -+ */ -+static void rt3350_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data |= (0x1 << 8); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void rt3883_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x3 << 13); -+ data |= (0x1 << 13); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void rt3552_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0xf << 8); -+ data |= (0x3 << 8); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7620_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x7 << 9); -+ data |= 0x1 << 9; -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7621_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x1f << 18); -+ data |= (0x19 << 18); -+ data &= ~(0x1f << 12); -+ data |= (0x1 << 12); -+ data &= ~(0x7 << 9); -+ data |= (0x5 << 9); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7628_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set i2s and refclk digital pad */ -+ data = rt_sysc_r32(0x3c); -+ data |= 0x1f; -+ rt_sysc_w32(data, 0x3c); -+ -+ /* Adjust REFCLK0's driving strength */ -+ data = rt_sysc_r32(0x1354); -+ data &= ~(0x1 << 5); -+ rt_sysc_w32(data, 0x1354); -+ data = rt_sysc_r32(0x1364); -+ data |= ~(0x1 << 5); -+ rt_sysc_w32(data, 0x1364); -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x7 << 9); -+ data |= 0x1 << 9; -+ rt_sysc_w32(data, 0x2c); -+} -+ -+struct rt_i2s_data { -+ u32 flags; -+ void (*refclk_setup)(void); -+}; -+ -+struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY }; -+struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY, -+ .refclk_setup = rt3350_refclk_setup }; -+struct rt_i2s_data rt3883_i2s_data = { -+ .flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J), -+ .refclk_setup = rt3883_refclk_setup }; -+struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup}; -+struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup}; -+struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup}; -+struct rt_i2s_data mt7628_i2s_data = { -+ .flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT | -+ RALINK_FLAGS_LEFT_J), -+ .refclk_setup = mt7628_refclk_setup}; -+ -+static const struct of_device_id ralink_i2s_match_table[] = { -+ { .compatible = "ralink,rt3050-i2s", -+ .data = (void *)&rt3050_i2s_data }, -+ { .compatible = "ralink,rt3350-i2s", -+ .data = (void *)&rt3350_i2s_data }, -+ { .compatible = "ralink,rt3883-i2s", -+ .data = (void *)&rt3883_i2s_data }, -+ { .compatible = "ralink,rt3352-i2s", -+ .data = (void *)&rt3352_i2s_data }, -+ { .compatible = "mediatek,mt7620-i2s", -+ .data = (void *)&mt7620_i2s_data }, -+ { .compatible = "mediatek,mt7621-i2s", -+ .data = (void *)&mt7621_i2s_data }, -+ { .compatible = "mediatek,mt7628-i2s", -+ .data = (void *)&mt7628_i2s_data }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ralink_i2s_match_table); -+ -+static int ralink_i2s_probe(struct platform_device *pdev) -+{ -+ const struct of_device_id *match; -+ struct device_node *np = pdev->dev.of_node; -+ struct ralink_i2s *i2s; -+ struct resource *res; -+ int irq, ret; -+ u32 dma_req; -+ struct rt_i2s_data *data; -+ -+ i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); -+ if (!i2s) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, i2s); -+ i2s->dev = &pdev->dev; -+ -+ match = of_match_device(ralink_i2s_match_table, &pdev->dev); -+ if (!match) -+ return -EINVAL; -+ data = (struct rt_i2s_data *)match->data; -+ i2s->flags = data->flags; -+ /* setup out 12Mhz refclk to codec as mclk */ -+ if (data->refclk_setup) -+ data->refclk_setup(); -+ -+ if (of_property_read_u32(np, "txdma-req", &dma_req)) { -+ dev_err(&pdev->dev, "no txdma-req define\n"); -+ return -EINVAL; -+ } -+ i2s->txdma_req = (u16)dma_req; -+ if (!(i2s->flags & RALINK_FLAGS_TXONLY)) { -+ if (of_property_read_u32(np, "rxdma-req", &dma_req)) { -+ dev_err(&pdev->dev, "no rxdma-req define\n"); -+ return -EINVAL; -+ } -+ i2s->rxdma_req = (u16)dma_req; -+ } -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ i2s->regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(i2s->regs)) -+ return PTR_ERR(i2s->regs); -+ -+ i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs, -+ &ralink_i2s_regmap_config); -+ if (IS_ERR(i2s->regmap)) { -+ dev_err(&pdev->dev, "regmap init failed\n"); -+ return PTR_ERR(i2s->regmap); -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(&pdev->dev, "failed to get irq\n"); -+ return -EINVAL; -+ } -+ -+#if (RALINK_I2S_INT_EN) -+ ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq, -+ 0, dev_name(&pdev->dev), i2s); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request irq\n"); -+ return ret; -+ } -+#endif -+ -+ i2s->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(i2s->clk)) { -+ dev_err(&pdev->dev, "no clock defined\n"); -+ return PTR_ERR(i2s->clk); -+ } -+ -+ ret = clk_prepare_enable(i2s->clk); -+ if (ret) -+ return ret; -+ -+ ralink_i2s_init_dma_data(i2s, res); -+ -+ ret = device_reset(&pdev->dev); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to reset device\n"); -+ goto err_clk_disable; -+ } -+ -+ ret = ralink_i2s_debugfs_create(i2s); -+ if (ret) { -+ dev_err(&pdev->dev, "create debugfs failed\n"); -+ goto err_clk_disable; -+ } -+ -+ /* enable 24bits support */ -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE; -+ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE; -+ } -+ -+ /* enable big endian support */ -+ if (i2s->flags & RALINK_FLAGS_ENDIAN) { -+ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ ralink_i2s_dai.capture.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ ralink_i2s_dai.playback.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ ralink_pcm_hardware.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ } -+ } -+ -+ /* disable capture support */ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture), -+ 0); -+ -+ ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component, -+ &ralink_i2s_dai, 1); -+ if (ret) -+ goto err_debugfs; -+ -+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, -+ &ralink_dmaengine_pcm_config, -+ SND_DMAENGINE_PCM_FLAG_COMPAT); -+ if (ret) -+ goto err_debugfs; -+ -+ dev_info(i2s->dev, "mclk %luMHz\n", clk_get_rate(i2s->clk) / 1000000); -+ -+ return 0; -+ -+err_debugfs: -+ ralink_i2s_debugfs_remove(i2s); -+ -+err_clk_disable: -+ clk_disable_unprepare(i2s->clk); -+ -+ return ret; -+} -+ -+static int ralink_i2s_remove(struct platform_device *pdev) -+{ -+ struct ralink_i2s *i2s = platform_get_drvdata(pdev); -+ -+ ralink_i2s_debugfs_remove(i2s); -+ clk_disable_unprepare(i2s->clk); -+ -+ return 0; -+} -+ -+static struct platform_driver ralink_i2s_driver = { -+ .probe = ralink_i2s_probe, -+ .remove = ralink_i2s_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .of_match_table = ralink_i2s_match_table, -+ }, -+}; -+module_platform_driver(ralink_i2s_driver); -+ -+MODULE_AUTHOR("Lars-Peter Clausen, "); -+MODULE_DESCRIPTION("Ralink/MediaTek I2S driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:" DRV_NAME); diff --git a/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch b/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch deleted file mode 100644 index 42a15a935c9567..00000000000000 --- a/target/linux/ramips/patches-6.1/840-serial-add-ugly-custom-baud-rate-hack.patch +++ /dev/null @@ -1,22 +0,0 @@ -From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:31:08 +0100 -Subject: [PATCH 51/53] serial: add ugly custom baud rate hack - -Signed-off-by: John Crispin ---- - drivers/tty/serial/serial_core.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/tty/serial/serial_core.c -+++ b/drivers/tty/serial/serial_core.c -@@ -445,6 +445,9 @@ uart_get_baud_rate(struct uart_port *por - break; - } - -+ if (tty_termios_baud_rate(termios) == 2500000) -+ return 250000; -+ - for (try = 0; try < 2; try++) { - baud = tty_termios_baud_rate(termios); - diff --git a/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch b/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch deleted file mode 100644 index ab164f5ab83f4a..00000000000000 --- a/target/linux/ramips/patches-6.1/845-pwm-add-mediatek-support.patch +++ /dev/null @@ -1,241 +0,0 @@ -From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:16:50 +0100 -Subject: [PATCH 52/53] pwm: add mediatek support - -Signed-off-by: John Crispin ---- - drivers/pwm/Kconfig | 9 +++ - drivers/pwm/Makefile | 1 + - drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 183 insertions(+) - create mode 100644 drivers/pwm/pwm-mediatek.c - ---- a/drivers/pwm/Kconfig -+++ b/drivers/pwm/Kconfig -@@ -393,6 +393,15 @@ config PWM_MEDIATEK - To compile this driver as a module, choose M here: the module - will be called pwm-mediatek. - -+config PWM_MEDIATEK_RAMIPS -+ tristate "Mediatek PWM support" -+ depends on RALINK && OF -+ help -+ Generic PWM framework driver for Mediatek ARM SoC. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called pwm-mxs. -+ - config PWM_MXS - tristate "Freescale MXS PWM support" - depends on ARCH_MXS || COMPILE_TEST ---- a/drivers/pwm/Makefile -+++ b/drivers/pwm/Makefile -@@ -34,6 +34,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p - obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o - obj-$(CONFIG_PWM_MESON) += pwm-meson.o - obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o -+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS) += pwm-mediatek-ramips.o - obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o - obj-$(CONFIG_PWM_MXS) += pwm-mxs.o - obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o ---- /dev/null -+++ b/drivers/pwm/pwm-mediatek-ramips.c -@@ -0,0 +1,197 @@ -+/* -+ * Mediatek Pulse Width Modulator driver -+ * -+ * Copyright (C) 2015 John Crispin -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define NUM_PWM 4 -+ -+/* PWM registers and bits definitions */ -+#define PWMCON 0x00 -+#define PWMHDUR 0x04 -+#define PWMLDUR 0x08 -+#define PWMGDUR 0x0c -+#define PWMWAVENUM 0x28 -+#define PWMDWIDTH 0x2c -+#define PWMTHRES 0x30 -+ -+/** -+ * struct mtk_pwm_chip - struct representing pwm chip -+ * -+ * @mmio_base: base address of pwm chip -+ * @chip: linux pwm chip representation -+ */ -+struct mtk_pwm_chip { -+ void __iomem *mmio_base; -+ struct pwm_chip chip; -+}; -+ -+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) -+{ -+ return container_of(chip, struct mtk_pwm_chip, chip); -+} -+ -+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, -+ unsigned long offset) -+{ -+ return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset); -+} -+ -+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, -+ unsigned int num, unsigned long offset, -+ unsigned long val) -+{ -+ iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset); -+} -+ -+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, -+ int duty_ns, int period_ns) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 resolution = 100 / 4; -+ u32 clkdiv = 0; -+ -+ while (period_ns / resolution > 8191) { -+ clkdiv++; -+ resolution *= 2; -+ } -+ -+ if (clkdiv > 7) -+ return -1; -+ -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution); -+ return 0; -+} -+ -+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 val; -+ -+ val = ioread32(pc->mmio_base); -+ val |= BIT(pwm->hwpwm); -+ iowrite32(val, pc->mmio_base); -+ -+ return 0; -+} -+ -+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 val; -+ -+ val = ioread32(pc->mmio_base); -+ val &= ~BIT(pwm->hwpwm); -+ iowrite32(val, pc->mmio_base); -+} -+ -+static int mtk_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, -+ const struct pwm_state *state) -+{ -+ int err; -+ bool enabled = pwm->state.enabled; -+ -+ if (!state->enabled) { -+ if (enabled) -+ mtk_pwm_disable(chip, pwm); -+ -+ return 0; -+ } -+ -+ err = mtk_pwm_config(pwm->chip, pwm, -+ state->duty_cycle, state->period); -+ if (err) -+ return err; -+ -+ if (!enabled) -+ err = mtk_pwm_enable(chip, pwm); -+ -+ return err; -+} -+ -+static const struct pwm_ops mtk_pwm_ops = { -+ .apply = mtk_pwm_apply, -+ .owner = THIS_MODULE, -+}; -+ -+static int mtk_pwm_probe(struct platform_device *pdev) -+{ -+ struct mtk_pwm_chip *pc; -+ struct resource *r; -+ int ret; -+ -+ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); -+ if (!pc) -+ return -ENOMEM; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); -+ if (IS_ERR(pc->mmio_base)) -+ return PTR_ERR(pc->mmio_base); -+ -+ platform_set_drvdata(pdev, pc); -+ -+ pc->chip.dev = &pdev->dev; -+ pc->chip.ops = &mtk_pwm_ops; -+ pc->chip.base = -1; -+ pc->chip.npwm = NUM_PWM; -+ -+ ret = pwmchip_add(&pc->chip); -+ if (ret < 0) -+ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+static int mtk_pwm_remove(struct platform_device *pdev) -+{ -+ struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); -+ int i; -+ -+ for (i = 0; i < NUM_PWM; i++) -+ pwm_disable(&pc->chip.pwms[i]); -+ -+ pwmchip_remove(&pc->chip); -+ -+ return 0; -+} -+ -+static const struct of_device_id mtk_pwm_of_match[] = { -+ { .compatible = "mediatek,mt7628-pwm" }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); -+ -+static struct platform_driver mtk_pwm_driver = { -+ .driver = { -+ .name = "mtk-pwm", -+ .owner = THIS_MODULE, -+ .of_match_table = mtk_pwm_of_match, -+ }, -+ .probe = mtk_pwm_probe, -+ .remove = mtk_pwm_remove, -+}; -+ -+module_platform_driver(mtk_pwm_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("John Crispin "); -+MODULE_ALIAS("platform:mtk-pwm"); diff --git a/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch b/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch deleted file mode 100644 index 01ce44d70007aa..00000000000000 --- a/target/linux/ramips/patches-6.1/850-awake-rt305x-dwc2-controller.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/drivers/usb/dwc2/platform.c -+++ b/drivers/usb/dwc2/platform.c -@@ -462,6 +462,12 @@ static int dwc2_driver_probe(struct plat - if (retval) - return retval; - -+ /* Enable USB port before any regs access */ -+ if (readl(hsotg->regs + PCGCTL) & 0x0f) { -+ writel(0x00, hsotg->regs + PCGCTL); -+ /* TODO: mdelay(25) here? vendor driver don't use it */ -+ } -+ - hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); - - retval = dwc2_get_dr_mode(hsotg); diff --git a/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch b/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch deleted file mode 100644 index cd81601a72901d..00000000000000 --- a/target/linux/ramips/patches-6.1/855-linkit_bootstrap.patch +++ /dev/null @@ -1,97 +0,0 @@ ---- a/drivers/misc/Makefile -+++ b/drivers/misc/Makefile -@@ -50,6 +50,7 @@ obj-$(CONFIG_ECHO) += echo/ - obj-$(CONFIG_CXL_BASE) += cxl/ - obj-$(CONFIG_DW_XDATA_PCIE) += dw-xdata-pcie.o - obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o -+obj-$(CONFIG_SOC_MT7620) += linkit.o - obj-$(CONFIG_OCXL) += ocxl/ - obj-$(CONFIG_BCM_VK) += bcm-vk/ - obj-y += cardreader/ ---- /dev/null -+++ b/drivers/misc/linkit.c -@@ -0,0 +1,84 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * publishhed by the Free Software Foundation. -+ * -+ * Copyright (C) 2015 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define LINKIT_LATCH_GPIO 11 -+ -+struct linkit_hw_data { -+ char board[16]; -+ char rev[16]; -+}; -+ -+static void sanify_string(char *s) -+{ -+ int i; -+ -+ for (i = 0; i < 15; i++) -+ if (s[i] <= 0x20) -+ s[i] = '\0'; -+ s[15] = '\0'; -+} -+ -+static int linkit_probe(struct platform_device *pdev) -+{ -+ struct linkit_hw_data hw; -+ struct mtd_info *mtd; -+ size_t retlen; -+ int ret; -+ -+ mtd = get_mtd_device_nm("factory"); -+ if (IS_ERR(mtd)) -+ return PTR_ERR(mtd); -+ -+ ret = mtd_read(mtd, 0x400, sizeof(hw), &retlen, (u_char *) &hw); -+ put_mtd_device(mtd); -+ -+ sanify_string(hw.board); -+ sanify_string(hw.rev); -+ -+ dev_info(&pdev->dev, "Version : %s\n", hw.board); -+ dev_info(&pdev->dev, "Revision : %s\n", hw.rev); -+ -+ if (!strcmp(hw.board, "LINKITS7688")) { -+ dev_info(&pdev->dev, "setting up bootstrap latch\n"); -+ -+ if (devm_gpio_request(&pdev->dev, LINKIT_LATCH_GPIO, "bootstrap")) { -+ dev_err(&pdev->dev, "failed to setup bootstrap gpio\n"); -+ return -1; -+ } -+ gpio_direction_output(LINKIT_LATCH_GPIO, 0); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id linkit_match[] = { -+ { .compatible = "mediatek,linkit" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, linkit_match); -+ -+static struct platform_driver linkit_driver = { -+ .probe = linkit_probe, -+ .driver = { -+ .name = "mtk-linkit", -+ .owner = THIS_MODULE, -+ .of_match_table = linkit_match, -+ }, -+}; -+ -+int __init linkit_init(void) -+{ -+ return platform_driver_register(&linkit_driver); -+} -+late_initcall_sync(linkit_init); diff --git a/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch b/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch deleted file mode 100644 index 275b81e715967d..00000000000000 --- a/target/linux/ramips/patches-6.1/860-ramips-add-eip93-driver.patch +++ /dev/null @@ -1,3276 +0,0 @@ ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/Kconfig -@@ -0,0 +1,64 @@ -+# SPDX-License-Identifier: GPL-2.0 -+config CRYPTO_DEV_EIP93_SKCIPHER -+ tristate -+ -+config CRYPTO_DEV_EIP93_HMAC -+ tristate -+ -+config CRYPTO_DEV_EIP93 -+ tristate "Support for EIP93 crypto HW accelerators" -+ depends on SOC_MT7621 || COMPILE_TEST -+ help -+ EIP93 have various crypto HW accelerators. Select this if -+ you want to use the EIP93 modules for any of the crypto algorithms. -+ -+if CRYPTO_DEV_EIP93 -+ -+config CRYPTO_DEV_EIP93_AES -+ bool "Register AES algorithm implementations with the Crypto API" -+ default y -+ select CRYPTO_DEV_EIP93_SKCIPHER -+ select CRYPTO_LIB_AES -+ select CRYPTO_SKCIPHER -+ help -+ Selecting this will offload AES - ECB, CBC and CTR crypto -+ to the EIP-93 crypto engine. -+ -+config CRYPTO_DEV_EIP93_DES -+ bool "Register legacy DES / 3DES algorithm with the Crypto API" -+ default y -+ select CRYPTO_DEV_EIP93_SKCIPHER -+ select CRYPTO_LIB_DES -+ select CRYPTO_SKCIPHER -+ help -+ Selecting this will offload DES and 3DES ECB and CBC -+ crypto to the EIP-93 crypto engine. -+ -+config CRYPTO_DEV_EIP93_AEAD -+ bool "Register AEAD algorithm with the Crypto API" -+ default y -+ select CRYPTO_DEV_EIP93_HMAC -+ select CRYPTO_AEAD -+ select CRYPTO_AUTHENC -+ select CRYPTO_MD5 -+ select CRYPTO_SHA1 -+ select CRYPTO_SHA256 -+ help -+ Selecting this will offload AEAD authenc(hmac(x), cipher(y)) -+ crypto to the EIP-93 crypto engine. -+ -+config CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN -+ int "Max skcipher software fallback length" -+ default 256 -+ help -+ Max length of crypt request which -+ will fallback to software crypt of skcipher *except* AES-128. -+ -+config CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN -+ int "Max AES-128 skcipher software fallback length" -+ default 512 -+ help -+ Max length of crypt request which -+ will fallback to software crypt of AES-128 skcipher. -+ -+endif ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/Makefile -@@ -0,0 +1,7 @@ -+obj-$(CONFIG_CRYPTO_DEV_EIP93) += crypto-hw-eip93.o -+ -+crypto-hw-eip93-y += eip93-main.o eip93-common.o -+ -+crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER) += eip93-cipher.o -+crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_AEAD) += eip93-aead.o -+ ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-aead.c -@@ -0,0 +1,768 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+#include -+#endif -+ -+#include -+#include -+ -+#include "eip93-aead.h" -+#include "eip93-cipher.h" -+#include "eip93-common.h" -+#include "eip93-regs.h" -+ -+void mtk_aead_handle_result(struct crypto_async_request *async, int err) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm); -+ struct mtk_device *mtk = ctx->mtk; -+ struct aead_request *req = aead_request_cast(async); -+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req); -+ -+ mtk_unmap_dma(mtk, rctx, req->src, req->dst); -+ mtk_handle_result(mtk, rctx, req->iv); -+ -+ if (err == 1) -+ err = -EBADMSG; -+ /* let software handle anti-replay errors */ -+ if (err == 4) -+ err = 0; -+ -+ aead_request_complete(req, err); -+} -+ -+static int mtk_aead_send_req(struct crypto_async_request *async) -+{ -+ struct aead_request *req = aead_request_cast(async); -+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req); -+ int err; -+ -+ err = check_valid_request(rctx); -+ if (err) { -+ aead_request_complete(req, err); -+ return err; -+ } -+ -+ return mtk_send_req(async, req->iv, rctx); -+} -+ -+/* Crypto aead API functions */ -+static int mtk_aead_cra_init(struct crypto_tfm *tfm) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg, -+ struct mtk_alg_template, alg.aead.base); -+ u32 flags = tmpl->flags; -+ char *alg_base; -+ -+ crypto_aead_set_reqsize(__crypto_aead_cast(tfm), -+ sizeof(struct mtk_cipher_reqctx)); -+ -+ ctx->mtk = tmpl->mtk; -+ ctx->in_first = true; -+ ctx->out_first = true; -+ -+ ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL); -+ if (!ctx->sa_in) -+ return -ENOMEM; -+ -+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ -+ ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL); -+ if (!ctx->sa_out) -+ return -ENOMEM; -+ -+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ -+ /* software workaround for now */ -+ if (IS_HASH_MD5(flags)) -+ alg_base = "md5"; -+ if (IS_HASH_SHA1(flags)) -+ alg_base = "sha1"; -+ if (IS_HASH_SHA224(flags)) -+ alg_base = "sha224"; -+ if (IS_HASH_SHA256(flags)) -+ alg_base = "sha256"; -+ -+ ctx->shash = crypto_alloc_shash(alg_base, 0, CRYPTO_ALG_NEED_FALLBACK); -+ -+ if (IS_ERR(ctx->shash)) { -+ dev_err(ctx->mtk->dev, "base driver %s could not be loaded.\n", -+ alg_base); -+ return PTR_ERR(ctx->shash); -+ } -+ -+ return 0; -+} -+ -+static void mtk_aead_cra_exit(struct crypto_tfm *tfm) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm); -+ -+ if (ctx->shash) -+ crypto_free_shash(ctx->shash); -+ -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ kfree(ctx->sa_in); -+ kfree(ctx->sa_out); -+} -+ -+static int mtk_aead_setkey(struct crypto_aead *ctfm, const u8 *key, -+ unsigned int len) -+{ -+ struct crypto_tfm *tfm = crypto_aead_tfm(ctfm); -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg, -+ struct mtk_alg_template, alg.skcipher.base); -+ u32 flags = tmpl->flags; -+ u32 nonce = 0; -+ struct crypto_authenc_keys keys; -+ struct crypto_aes_ctx aes; -+ struct saRecord_s *saRecord = ctx->sa_out; -+ int sa_size = sizeof(struct saRecord_s); -+ int err = -EINVAL; -+ -+ -+ if (crypto_authenc_extractkeys(&keys, key, len)) -+ return err; -+ -+ if (IS_RFC3686(flags)) { -+ if (keys.enckeylen < CTR_RFC3686_NONCE_SIZE) -+ return err; -+ -+ keys.enckeylen -= CTR_RFC3686_NONCE_SIZE; -+ memcpy(&nonce, keys.enckey + keys.enckeylen, -+ CTR_RFC3686_NONCE_SIZE); -+ } -+ -+ switch ((flags & MTK_ALG_MASK)) { -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+ case MTK_ALG_DES: -+ err = verify_aead_des_key(ctfm, keys.enckey, keys.enckeylen); -+ break; -+ case MTK_ALG_3DES: -+ if (keys.enckeylen != DES3_EDE_KEY_SIZE) -+ return -EINVAL; -+ -+ err = verify_aead_des3_key(ctfm, keys.enckey, keys.enckeylen); -+ break; -+#endif -+ case MTK_ALG_AES: -+ err = aes_expandkey(&aes, keys.enckey, keys.enckeylen); -+ } -+ if (err) -+ return err; -+ -+ ctx->blksize = crypto_aead_blocksize(ctfm); -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size, -+ DMA_TO_DEVICE); -+ -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size, -+ DMA_TO_DEVICE); -+ /* Encryption key */ -+ mtk_set_saRecord(saRecord, keys.enckeylen, flags); -+ saRecord->saCmd0.bits.opCode = 1; -+ saRecord->saCmd0.bits.digestLength = ctx->authsize >> 2; -+ -+ memcpy(saRecord->saKey, keys.enckey, keys.enckeylen); -+ ctx->saNonce = nonce; -+ saRecord->saNonce = nonce; -+ -+ /* authentication key */ -+ err = mtk_authenc_setkey(ctx->shash, saRecord, keys.authkey, -+ keys.authkeylen); -+ -+ saRecord->saCmd0.bits.direction = 0; -+ memcpy(ctx->sa_in, saRecord, sa_size); -+ ctx->sa_in->saCmd0.bits.direction = 1; -+ ctx->sa_in->saCmd1.bits.copyDigest = 0; -+ -+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size, -+ DMA_TO_DEVICE); -+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size, -+ DMA_TO_DEVICE); -+ ctx->in_first = true; -+ ctx->out_first = true; -+ -+ return err; -+} -+ -+static int mtk_aead_setauthsize(struct crypto_aead *ctfm, -+ unsigned int authsize) -+{ -+ struct crypto_tfm *tfm = crypto_aead_tfm(ctfm); -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm); -+ -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ -+ ctx->authsize = authsize; -+ ctx->sa_in->saCmd0.bits.digestLength = ctx->authsize >> 2; -+ ctx->sa_out->saCmd0.bits.digestLength = ctx->authsize >> 2; -+ -+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ return 0; -+} -+ -+static void mtk_aead_setassoc(struct mtk_crypto_ctx *ctx, -+ struct aead_request *req, bool in) -+{ -+ struct saRecord_s *saRecord; -+ -+ if (in) { -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ saRecord = ctx->sa_in; -+ saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2; -+ -+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ ctx->assoclen_in = req->assoclen; -+ } else { -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ saRecord = ctx->sa_out; -+ saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2; -+ -+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ ctx->assoclen_out = req->assoclen; -+ } -+} -+ -+static int mtk_aead_crypt(struct aead_request *req) -+{ -+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req); -+ struct crypto_async_request *async = &req->base; -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm); -+ struct crypto_aead *aead = crypto_aead_reqtfm(req); -+ -+ rctx->textsize = req->cryptlen; -+ rctx->blksize = ctx->blksize; -+ rctx->assoclen = req->assoclen; -+ rctx->authsize = ctx->authsize; -+ rctx->sg_src = req->src; -+ rctx->sg_dst = req->dst; -+ rctx->ivsize = crypto_aead_ivsize(aead); -+ rctx->flags |= MTK_DESC_AEAD; -+ -+ if IS_DECRYPT(rctx->flags) -+ rctx->textsize -= rctx->authsize; -+ -+ return mtk_aead_send_req(async); -+} -+ -+static int mtk_aead_encrypt(struct aead_request *req) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm); -+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req); -+ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg, -+ struct mtk_alg_template, alg.aead.base); -+ -+ rctx->flags = tmpl->flags; -+ rctx->flags |= MTK_ENCRYPT; -+ if (ctx->out_first) { -+ mtk_aead_setassoc(ctx, req, false); -+ ctx->out_first = false; -+ } -+ -+ if (req->assoclen != ctx->assoclen_out) { -+ dev_err(ctx->mtk->dev, "Request AAD length error\n"); -+ return -EINVAL; -+ } -+ -+ rctx->saRecord_base = ctx->sa_base_out; -+ -+ return mtk_aead_crypt(req); -+} -+ -+static int mtk_aead_decrypt(struct aead_request *req) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm); -+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req); -+ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg, -+ struct mtk_alg_template, alg.aead.base); -+ -+ rctx->flags = tmpl->flags; -+ rctx->flags |= MTK_DECRYPT; -+ if (ctx->in_first) { -+ mtk_aead_setassoc(ctx, req, true); -+ ctx->in_first = false; -+ } -+ -+ if (req->assoclen != ctx->assoclen_in) { -+ dev_err(ctx->mtk->dev, "Request AAD length error\n"); -+ return -EINVAL; -+ } -+ -+ rctx->saRecord_base = ctx->sa_base_in; -+ -+ return mtk_aead_crypt(req); -+} -+ -+/* Available authenc algorithms in this module */ -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES) -+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_AES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = AES_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = MD5_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(md5),cbc(aes))", -+ .cra_driver_name = -+ "authenc(hmac(md5-eip93), cbc(aes-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_AES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = AES_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA1_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha1),cbc(aes))", -+ .cra_driver_name = -+ "authenc(hmac(sha1-eip93),cbc(aes-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_AES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = AES_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA224_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha224),cbc(aes))", -+ .cra_driver_name = -+ "authenc(hmac(sha224-eip93),cbc(aes-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_AES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = AES_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA256_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha256),cbc(aes))", -+ .cra_driver_name = -+ "authenc(hmac(sha256-eip93),cbc(aes-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | -+ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = CTR_RFC3686_IV_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = MD5_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(md5),rfc3686(ctr(aes)))", -+ .cra_driver_name = -+ "authenc(hmac(md5-eip93),rfc3686(ctr(aes-eip93)))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = 1, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | -+ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = CTR_RFC3686_IV_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA1_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha1),rfc3686(ctr(aes)))", -+ .cra_driver_name = -+ "authenc(hmac(sha1-eip93),rfc3686(ctr(aes-eip93)))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = 1, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | -+ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = CTR_RFC3686_IV_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA224_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha224),rfc3686(ctr(aes)))", -+ .cra_driver_name = -+ "authenc(hmac(sha224-eip93),rfc3686(ctr(aes-eip93)))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = 1, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | -+ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = CTR_RFC3686_IV_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA256_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha256),rfc3686(ctr(aes)))", -+ .cra_driver_name = -+ "authenc(hmac(sha256-eip93),rfc3686(ctr(aes-eip93)))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = 1, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_DES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = DES_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = MD5_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(md5),cbc(des))", -+ .cra_driver_name = -+ "authenc(hmac(md5-eip93),cbc(des-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_DES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = DES_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA1_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha1),cbc(des))", -+ .cra_driver_name = -+ "authenc(hmac(sha1-eip93),cbc(des-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_DES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = DES_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA224_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha224),cbc(des))", -+ .cra_driver_name = -+ "authenc(hmac(sha224-eip93),cbc(des-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_DES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = DES_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA256_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha256),cbc(des))", -+ .cra_driver_name = -+ "authenc(hmac(sha256-eip93),cbc(des-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_3DES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = MD5_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(md5),cbc(des3_ede))", -+ .cra_driver_name = -+ "authenc(hmac(md5-eip93),cbc(des3_ede-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES3_EDE_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0x0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_3DES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA1_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha1),cbc(des3_ede))", -+ .cra_driver_name = -+ "authenc(hmac(sha1-eip93),cbc(des3_ede-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES3_EDE_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0x0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_3DES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA224_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha224),cbc(des3_ede))", -+ .cra_driver_name = -+ "authenc(hmac(sha224-eip93),cbc(des3_ede-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES3_EDE_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0x0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede = { -+ .type = MTK_ALG_TYPE_AEAD, -+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_3DES, -+ .alg.aead = { -+ .setkey = mtk_aead_setkey, -+ .encrypt = mtk_aead_encrypt, -+ .decrypt = mtk_aead_decrypt, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ .setauthsize = mtk_aead_setauthsize, -+ .maxauthsize = SHA256_DIGEST_SIZE, -+ .base = { -+ .cra_name = "authenc(hmac(sha256),cbc(des3_ede))", -+ .cra_driver_name = -+ "authenc(hmac(sha256-eip93),cbc(des3_ede-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES3_EDE_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0x0, -+ .cra_init = mtk_aead_cra_init, -+ .cra_exit = mtk_aead_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+#endif ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-aead.h -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+#ifndef _EIP93_AEAD_H_ -+#define _EIP93_AEAD_H_ -+ -+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes; -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede; -+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede; -+#endif -+ -+void mtk_aead_handle_result(struct crypto_async_request *async, int err); -+ -+#endif /* _EIP93_AEAD_H_ */ ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-aes.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+#ifndef _EIP93_AES_H_ -+#define _EIP93_AES_H_ -+ -+extern struct mtk_alg_template mtk_alg_ecb_aes; -+extern struct mtk_alg_template mtk_alg_cbc_aes; -+extern struct mtk_alg_template mtk_alg_ctr_aes; -+extern struct mtk_alg_template mtk_alg_rfc3686_aes; -+ -+#endif /* _EIP93_AES_H_ */ ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-cipher.c -@@ -0,0 +1,483 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+ -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES) -+#include -+#include -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+#include -+#endif -+#include -+ -+#include "eip93-cipher.h" -+#include "eip93-common.h" -+#include "eip93-regs.h" -+ -+void mtk_skcipher_handle_result(struct crypto_async_request *async, int err) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm); -+ struct mtk_device *mtk = ctx->mtk; -+ struct skcipher_request *req = skcipher_request_cast(async); -+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req); -+ -+ mtk_unmap_dma(mtk, rctx, req->src, req->dst); -+ mtk_handle_result(mtk, rctx, req->iv); -+ -+ skcipher_request_complete(req, err); -+} -+ -+static inline bool mtk_skcipher_is_fallback(const struct crypto_tfm *tfm, -+ u32 flags) -+{ -+ return (tfm->__crt_alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) && -+ !IS_RFC3686(flags); -+} -+ -+static int mtk_skcipher_send_req(struct crypto_async_request *async) -+{ -+ struct skcipher_request *req = skcipher_request_cast(async); -+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req); -+ int err; -+ -+ err = check_valid_request(rctx); -+ -+ if (err) { -+ skcipher_request_complete(req, err); -+ return err; -+ } -+ -+ return mtk_send_req(async, req->iv, rctx); -+} -+ -+/* Crypto skcipher API functions */ -+static int mtk_skcipher_cra_init(struct crypto_tfm *tfm) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg, -+ struct mtk_alg_template, alg.skcipher.base); -+ bool fallback = mtk_skcipher_is_fallback(tfm, tmpl->flags); -+ -+ if (fallback) { -+ ctx->fallback = crypto_alloc_skcipher( -+ crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_NEED_FALLBACK); -+ if (IS_ERR(ctx->fallback)) -+ return PTR_ERR(ctx->fallback); -+ } -+ -+ crypto_skcipher_set_reqsize( -+ __crypto_skcipher_cast(tfm), -+ sizeof(struct mtk_cipher_reqctx) + -+ (fallback ? crypto_skcipher_reqsize(ctx->fallback) : -+ 0)); -+ -+ ctx->mtk = tmpl->mtk; -+ -+ ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL); -+ if (!ctx->sa_in) -+ return -ENOMEM; -+ -+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ -+ ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL); -+ if (!ctx->sa_out) -+ return -ENOMEM; -+ -+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ return 0; -+} -+ -+static void mtk_skcipher_cra_exit(struct crypto_tfm *tfm) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm); -+ -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, -+ sizeof(struct saRecord_s), DMA_TO_DEVICE); -+ kfree(ctx->sa_in); -+ kfree(ctx->sa_out); -+ -+ crypto_free_skcipher(ctx->fallback); -+} -+ -+static int mtk_skcipher_setkey(struct crypto_skcipher *ctfm, const u8 *key, -+ unsigned int len) -+{ -+ struct crypto_tfm *tfm = crypto_skcipher_tfm(ctfm); -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg, -+ struct mtk_alg_template, alg.skcipher.base); -+ struct saRecord_s *saRecord = ctx->sa_out; -+ u32 flags = tmpl->flags; -+ u32 nonce = 0; -+ unsigned int keylen = len; -+ int sa_size = sizeof(struct saRecord_s); -+ int err = -EINVAL; -+ -+ if (!key || !keylen) -+ return err; -+ -+ ctx->keylen = keylen; -+ -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES) -+ if (IS_RFC3686(flags)) { -+ if (len < CTR_RFC3686_NONCE_SIZE) -+ return err; -+ -+ keylen = len - CTR_RFC3686_NONCE_SIZE; -+ memcpy(&nonce, key + keylen, CTR_RFC3686_NONCE_SIZE); -+ } -+#endif -+ -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+ if (flags & MTK_ALG_DES) { -+ ctx->blksize = DES_BLOCK_SIZE; -+ err = verify_skcipher_des_key(ctfm, key); -+ } -+ if (flags & MTK_ALG_3DES) { -+ ctx->blksize = DES3_EDE_BLOCK_SIZE; -+ err = verify_skcipher_des3_key(ctfm, key); -+ } -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES) -+ if (flags & MTK_ALG_AES) { -+ struct crypto_aes_ctx aes; -+ bool fallback = mtk_skcipher_is_fallback(tfm, flags); -+ -+ if (fallback && !IS_RFC3686(flags)) { -+ err = crypto_skcipher_setkey(ctx->fallback, key, -+ keylen); -+ if (err) -+ return err; -+ } -+ -+ ctx->blksize = AES_BLOCK_SIZE; -+ err = aes_expandkey(&aes, key, keylen); -+ } -+#endif -+ if (err) -+ return err; -+ -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size, -+ DMA_TO_DEVICE); -+ -+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size, -+ DMA_TO_DEVICE); -+ -+ mtk_set_saRecord(saRecord, keylen, flags); -+ -+ memcpy(saRecord->saKey, key, keylen); -+ ctx->saNonce = nonce; -+ saRecord->saNonce = nonce; -+ saRecord->saCmd0.bits.direction = 0; -+ -+ memcpy(ctx->sa_in, saRecord, sa_size); -+ ctx->sa_in->saCmd0.bits.direction = 1; -+ -+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size, -+ DMA_TO_DEVICE); -+ -+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size, -+ DMA_TO_DEVICE); -+ return err; -+} -+ -+static int mtk_skcipher_crypt(struct skcipher_request *req, bool encrypt) -+{ -+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req); -+ struct crypto_async_request *async = &req->base; -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm); -+ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); -+ bool fallback = mtk_skcipher_is_fallback(req->base.tfm, rctx->flags); -+ -+ if (!req->cryptlen) -+ return 0; -+ -+ /* -+ * ECB and CBC algorithms require message lengths to be -+ * multiples of block size. -+ */ -+ if (IS_ECB(rctx->flags) || IS_CBC(rctx->flags)) -+ if (!IS_ALIGNED(req->cryptlen, -+ crypto_skcipher_blocksize(skcipher))) -+ return -EINVAL; -+ -+ if (fallback && -+ req->cryptlen <= (AES_KEYSIZE_128 ? -+ CONFIG_CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN : -+ CONFIG_CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN)) { -+ skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); -+ skcipher_request_set_callback(&rctx->fallback_req, -+ req->base.flags, -+ req->base.complete, -+ req->base.data); -+ skcipher_request_set_crypt(&rctx->fallback_req, req->src, -+ req->dst, req->cryptlen, req->iv); -+ return encrypt ? crypto_skcipher_encrypt(&rctx->fallback_req) : -+ crypto_skcipher_decrypt(&rctx->fallback_req); -+ } -+ -+ rctx->assoclen = 0; -+ rctx->textsize = req->cryptlen; -+ rctx->authsize = 0; -+ rctx->sg_src = req->src; -+ rctx->sg_dst = req->dst; -+ rctx->ivsize = crypto_skcipher_ivsize(skcipher); -+ rctx->blksize = ctx->blksize; -+ rctx->flags |= MTK_DESC_SKCIPHER; -+ if (!IS_ECB(rctx->flags)) -+ rctx->flags |= MTK_DESC_DMA_IV; -+ -+ return mtk_skcipher_send_req(async); -+} -+ -+static int mtk_skcipher_encrypt(struct skcipher_request *req) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm); -+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req); -+ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg, -+ struct mtk_alg_template, alg.skcipher.base); -+ -+ rctx->flags = tmpl->flags; -+ rctx->flags |= MTK_ENCRYPT; -+ rctx->saRecord_base = ctx->sa_base_out; -+ -+ return mtk_skcipher_crypt(req, true); -+} -+ -+static int mtk_skcipher_decrypt(struct skcipher_request *req) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm); -+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req); -+ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg, -+ struct mtk_alg_template, alg.skcipher.base); -+ -+ rctx->flags = tmpl->flags; -+ rctx->flags |= MTK_DECRYPT; -+ rctx->saRecord_base = ctx->sa_base_in; -+ -+ return mtk_skcipher_crypt(req, false); -+} -+ -+/* Available algorithms in this module */ -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES) -+struct mtk_alg_template mtk_alg_ecb_aes = { -+ .type = MTK_ALG_TYPE_SKCIPHER, -+ .flags = MTK_MODE_ECB | MTK_ALG_AES, -+ .alg.skcipher = { -+ .setkey = mtk_skcipher_setkey, -+ .encrypt = mtk_skcipher_encrypt, -+ .decrypt = mtk_skcipher_decrypt, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .ivsize = 0, -+ .base = { -+ .cra_name = "ecb(aes)", -+ .cra_driver_name = "ecb(aes-eip93)", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0xf, -+ .cra_init = mtk_skcipher_cra_init, -+ .cra_exit = mtk_skcipher_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_cbc_aes = { -+ .type = MTK_ALG_TYPE_SKCIPHER, -+ .flags = MTK_MODE_CBC | MTK_ALG_AES, -+ .alg.skcipher = { -+ .setkey = mtk_skcipher_setkey, -+ .encrypt = mtk_skcipher_encrypt, -+ .decrypt = mtk_skcipher_decrypt, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ .base = { -+ .cra_name = "cbc(aes)", -+ .cra_driver_name = "cbc(aes-eip93)", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = AES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0xf, -+ .cra_init = mtk_skcipher_cra_init, -+ .cra_exit = mtk_skcipher_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_ctr_aes = { -+ .type = MTK_ALG_TYPE_SKCIPHER, -+ .flags = MTK_MODE_CTR | MTK_ALG_AES, -+ .alg.skcipher = { -+ .setkey = mtk_skcipher_setkey, -+ .encrypt = mtk_skcipher_encrypt, -+ .decrypt = mtk_skcipher_decrypt, -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .ivsize = AES_BLOCK_SIZE, -+ .base = { -+ .cra_name = "ctr(aes)", -+ .cra_driver_name = "ctr(aes-eip93)", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = 1, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0xf, -+ .cra_init = mtk_skcipher_cra_init, -+ .cra_exit = mtk_skcipher_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_rfc3686_aes = { -+ .type = MTK_ALG_TYPE_SKCIPHER, -+ .flags = MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES, -+ .alg.skcipher = { -+ .setkey = mtk_skcipher_setkey, -+ .encrypt = mtk_skcipher_encrypt, -+ .decrypt = mtk_skcipher_decrypt, -+ .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE, -+ .ivsize = CTR_RFC3686_IV_SIZE, -+ .base = { -+ .cra_name = "rfc3686(ctr(aes))", -+ .cra_driver_name = "rfc3686(ctr(aes-eip93))", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_NEED_FALLBACK | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = 1, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0xf, -+ .cra_init = mtk_skcipher_cra_init, -+ .cra_exit = mtk_skcipher_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+struct mtk_alg_template mtk_alg_ecb_des = { -+ .type = MTK_ALG_TYPE_SKCIPHER, -+ .flags = MTK_MODE_ECB | MTK_ALG_DES, -+ .alg.skcipher = { -+ .setkey = mtk_skcipher_setkey, -+ .encrypt = mtk_skcipher_encrypt, -+ .decrypt = mtk_skcipher_decrypt, -+ .min_keysize = DES_KEY_SIZE, -+ .max_keysize = DES_KEY_SIZE, -+ .ivsize = 0, -+ .base = { -+ .cra_name = "ecb(des)", -+ .cra_driver_name = "ebc(des-eip93)", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_skcipher_cra_init, -+ .cra_exit = mtk_skcipher_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_cbc_des = { -+ .type = MTK_ALG_TYPE_SKCIPHER, -+ .flags = MTK_MODE_CBC | MTK_ALG_DES, -+ .alg.skcipher = { -+ .setkey = mtk_skcipher_setkey, -+ .encrypt = mtk_skcipher_encrypt, -+ .decrypt = mtk_skcipher_decrypt, -+ .min_keysize = DES_KEY_SIZE, -+ .max_keysize = DES_KEY_SIZE, -+ .ivsize = DES_BLOCK_SIZE, -+ .base = { -+ .cra_name = "cbc(des)", -+ .cra_driver_name = "cbc(des-eip93)", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_skcipher_cra_init, -+ .cra_exit = mtk_skcipher_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_ecb_des3_ede = { -+ .type = MTK_ALG_TYPE_SKCIPHER, -+ .flags = MTK_MODE_ECB | MTK_ALG_3DES, -+ .alg.skcipher = { -+ .setkey = mtk_skcipher_setkey, -+ .encrypt = mtk_skcipher_encrypt, -+ .decrypt = mtk_skcipher_decrypt, -+ .min_keysize = DES3_EDE_KEY_SIZE, -+ .max_keysize = DES3_EDE_KEY_SIZE, -+ .ivsize = 0, -+ .base = { -+ .cra_name = "ecb(des3_ede)", -+ .cra_driver_name = "ecb(des3_ede-eip93)", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES3_EDE_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_skcipher_cra_init, -+ .cra_exit = mtk_skcipher_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+ -+struct mtk_alg_template mtk_alg_cbc_des3_ede = { -+ .type = MTK_ALG_TYPE_SKCIPHER, -+ .flags = MTK_MODE_CBC | MTK_ALG_3DES, -+ .alg.skcipher = { -+ .setkey = mtk_skcipher_setkey, -+ .encrypt = mtk_skcipher_encrypt, -+ .decrypt = mtk_skcipher_decrypt, -+ .min_keysize = DES3_EDE_KEY_SIZE, -+ .max_keysize = DES3_EDE_KEY_SIZE, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ .base = { -+ .cra_name = "cbc(des3_ede)", -+ .cra_driver_name = "cbc(des3_ede-eip93)", -+ .cra_priority = MTK_CRA_PRIORITY, -+ .cra_flags = CRYPTO_ALG_ASYNC | -+ CRYPTO_ALG_KERN_DRIVER_ONLY, -+ .cra_blocksize = DES3_EDE_BLOCK_SIZE, -+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx), -+ .cra_alignmask = 0, -+ .cra_init = mtk_skcipher_cra_init, -+ .cra_exit = mtk_skcipher_cra_exit, -+ .cra_module = THIS_MODULE, -+ }, -+ }, -+}; -+#endif ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-cipher.h -@@ -0,0 +1,66 @@ -+/* SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+#ifndef _EIP93_CIPHER_H_ -+#define _EIP93_CIPHER_H_ -+ -+#include "eip93-main.h" -+ -+struct mtk_crypto_ctx { -+ struct mtk_device *mtk; -+ struct saRecord_s *sa_in; -+ dma_addr_t sa_base_in; -+ struct saRecord_s *sa_out; -+ dma_addr_t sa_base_out; -+ uint32_t saNonce; -+ int blksize; -+ /* AEAD specific */ -+ unsigned int authsize; -+ unsigned int assoclen_in; -+ unsigned int assoclen_out; -+ bool in_first; -+ bool out_first; -+ struct crypto_shash *shash; -+ unsigned int keylen; -+ struct crypto_skcipher *fallback; -+}; -+ -+struct mtk_cipher_reqctx { -+ unsigned long flags; -+ unsigned int blksize; -+ unsigned int ivsize; -+ unsigned int textsize; -+ unsigned int assoclen; -+ unsigned int authsize; -+ dma_addr_t saRecord_base; -+ struct saState_s *saState; -+ dma_addr_t saState_base; -+ uint32_t saState_idx; -+ struct eip93_descriptor_s *cdesc; -+ struct scatterlist *sg_src; -+ struct scatterlist *sg_dst; -+ int src_nents; -+ int dst_nents; -+ struct saState_s *saState_ctr; -+ dma_addr_t saState_base_ctr; -+ uint32_t saState_ctr_idx; -+ struct skcipher_request fallback_req; // keep at the end -+}; -+ -+int check_valid_request(struct mtk_cipher_reqctx *rctx); -+ -+void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx, -+ struct scatterlist *reqsrc, struct scatterlist *reqdst); -+ -+void mtk_skcipher_handle_result(struct crypto_async_request *async, int err); -+ -+int mtk_send_req(struct crypto_async_request *async, -+ const u8 *reqiv, struct mtk_cipher_reqctx *rctx); -+ -+void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx, -+ u8 *reqiv); -+ -+#endif /* _EIP93_CIPHER_H_ */ ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-common.c -@@ -0,0 +1,749 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "eip93-cipher.h" -+#include "eip93-common.h" -+#include "eip93-main.h" -+#include "eip93-regs.h" -+ -+inline void *mtk_ring_next_wptr(struct mtk_device *mtk, -+ struct mtk_desc_ring *ring) -+{ -+ void *ptr = ring->write; -+ -+ if ((ring->write == ring->read - ring->offset) || -+ (ring->read == ring->base && ring->write == ring->base_end)) -+ return ERR_PTR(-ENOMEM); -+ -+ if (ring->write == ring->base_end) -+ ring->write = ring->base; -+ else -+ ring->write += ring->offset; -+ -+ return ptr; -+} -+ -+inline void *mtk_ring_next_rptr(struct mtk_device *mtk, -+ struct mtk_desc_ring *ring) -+{ -+ void *ptr = ring->read; -+ -+ if (ring->write == ring->read) -+ return ERR_PTR(-ENOENT); -+ -+ if (ring->read == ring->base_end) -+ ring->read = ring->base; -+ else -+ ring->read += ring->offset; -+ -+ return ptr; -+} -+ -+inline int mtk_put_descriptor(struct mtk_device *mtk, -+ struct eip93_descriptor_s *desc) -+{ -+ struct eip93_descriptor_s *cdesc; -+ struct eip93_descriptor_s *rdesc; -+ unsigned long irqflags; -+ -+ spin_lock_irqsave(&mtk->ring->write_lock, irqflags); -+ -+ rdesc = mtk_ring_next_wptr(mtk, &mtk->ring->rdr); -+ -+ if (IS_ERR(rdesc)) { -+ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags); -+ return -ENOENT; -+ } -+ -+ cdesc = mtk_ring_next_wptr(mtk, &mtk->ring->cdr); -+ -+ if (IS_ERR(cdesc)) { -+ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags); -+ return -ENOENT; -+ } -+ -+ memset(rdesc, 0, sizeof(struct eip93_descriptor_s)); -+ memcpy(cdesc, desc, sizeof(struct eip93_descriptor_s)); -+ -+ atomic_dec(&mtk->ring->free); -+ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags); -+ -+ return 0; -+} -+ -+inline void *mtk_get_descriptor(struct mtk_device *mtk) -+{ -+ struct eip93_descriptor_s *cdesc; -+ void *ptr; -+ unsigned long irqflags; -+ -+ spin_lock_irqsave(&mtk->ring->read_lock, irqflags); -+ -+ cdesc = mtk_ring_next_rptr(mtk, &mtk->ring->cdr); -+ -+ if (IS_ERR(cdesc)) { -+ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags); -+ return ERR_PTR(-ENOENT); -+ } -+ -+ memset(cdesc, 0, sizeof(struct eip93_descriptor_s)); -+ -+ ptr = mtk_ring_next_rptr(mtk, &mtk->ring->rdr); -+ if (IS_ERR(ptr)) { -+ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags); -+ return ERR_PTR(-ENOENT); -+ } -+ -+ atomic_inc(&mtk->ring->free); -+ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags); -+ -+ return ptr; -+} -+ -+inline int mtk_get_free_saState(struct mtk_device *mtk) -+{ -+ struct mtk_state_pool *saState_pool; -+ int i; -+ -+ for (i = 0; i < MTK_RING_SIZE; i++) { -+ saState_pool = &mtk->ring->saState_pool[i]; -+ if (saState_pool->in_use == false) { -+ saState_pool->in_use = true; -+ return i; -+ } -+ -+ } -+ -+ return -ENOENT; -+} -+ -+static inline void mtk_free_sg_copy(const int len, struct scatterlist **sg) -+{ -+ if (!*sg || !len) -+ return; -+ -+ free_pages((unsigned long)sg_virt(*sg), get_order(len)); -+ kfree(*sg); -+ *sg = NULL; -+} -+ -+static inline int mtk_make_sg_copy(struct scatterlist *src, -+ struct scatterlist **dst, -+ const uint32_t len, const bool copy) -+{ -+ void *pages; -+ -+ *dst = kmalloc(sizeof(**dst), GFP_KERNEL); -+ if (!*dst) -+ return -ENOMEM; -+ -+ -+ pages = (void *)__get_free_pages(GFP_KERNEL | GFP_DMA, -+ get_order(len)); -+ -+ if (!pages) { -+ kfree(*dst); -+ *dst = NULL; -+ return -ENOMEM; -+ } -+ -+ sg_init_table(*dst, 1); -+ sg_set_buf(*dst, pages, len); -+ -+ /* copy only as requested */ -+ if (copy) -+ sg_copy_to_buffer(src, sg_nents(src), pages, len); -+ -+ return 0; -+} -+ -+static inline bool mtk_is_sg_aligned(struct scatterlist *sg, u32 len, -+ const int blksize) -+{ -+ int nents; -+ -+ for (nents = 0; sg; sg = sg_next(sg), ++nents) { -+ if (!IS_ALIGNED(sg->offset, 4)) -+ return false; -+ -+ if (len <= sg->length) { -+ if (!IS_ALIGNED(len, blksize)) -+ return false; -+ -+ return true; -+ } -+ -+ if (!IS_ALIGNED(sg->length, blksize)) -+ return false; -+ -+ len -= sg->length; -+ } -+ return false; -+} -+ -+int check_valid_request(struct mtk_cipher_reqctx *rctx) -+{ -+ struct scatterlist *src = rctx->sg_src; -+ struct scatterlist *dst = rctx->sg_dst; -+ uint32_t src_nents, dst_nents; -+ u32 textsize = rctx->textsize; -+ u32 authsize = rctx->authsize; -+ u32 blksize = rctx->blksize; -+ u32 totlen_src = rctx->assoclen + rctx->textsize; -+ u32 totlen_dst = rctx->assoclen + rctx->textsize; -+ u32 copy_len; -+ bool src_align, dst_align; -+ int err = -EINVAL; -+ -+ if (!IS_CTR(rctx->flags)) { -+ if (!IS_ALIGNED(textsize, blksize)) -+ return err; -+ } -+ -+ if (authsize) { -+ if (IS_ENCRYPT(rctx->flags)) -+ totlen_dst += authsize; -+ else -+ totlen_src += authsize; -+ } -+ -+ src_nents = sg_nents_for_len(src, totlen_src); -+ dst_nents = sg_nents_for_len(dst, totlen_dst); -+ -+ if (src == dst) { -+ src_nents = max(src_nents, dst_nents); -+ dst_nents = src_nents; -+ if (unlikely((totlen_src || totlen_dst) && (src_nents <= 0))) -+ return err; -+ -+ } else { -+ if (unlikely(totlen_src && (src_nents <= 0))) -+ return err; -+ -+ if (unlikely(totlen_dst && (dst_nents <= 0))) -+ return err; -+ } -+ -+ if (authsize) { -+ if (dst_nents == 1 && src_nents == 1) { -+ src_align = mtk_is_sg_aligned(src, totlen_src, blksize); -+ if (src == dst) -+ dst_align = src_align; -+ else -+ dst_align = mtk_is_sg_aligned(dst, -+ totlen_dst, blksize); -+ } else { -+ src_align = false; -+ dst_align = false; -+ } -+ } else { -+ src_align = mtk_is_sg_aligned(src, totlen_src, blksize); -+ if (src == dst) -+ dst_align = src_align; -+ else -+ dst_align = mtk_is_sg_aligned(dst, totlen_dst, blksize); -+ } -+ -+ copy_len = max(totlen_src, totlen_dst); -+ if (!src_align) { -+ err = mtk_make_sg_copy(src, &rctx->sg_src, copy_len, true); -+ if (err) -+ return err; -+ } -+ -+ if (!dst_align) { -+ err = mtk_make_sg_copy(dst, &rctx->sg_dst, copy_len, false); -+ if (err) -+ return err; -+ } -+ -+ rctx->src_nents = sg_nents_for_len(rctx->sg_src, totlen_src); -+ rctx->dst_nents = sg_nents_for_len(rctx->sg_dst, totlen_dst); -+ -+ return 0; -+} -+/* -+ * Set saRecord function: -+ * Even saRecord is set to "0", keep " = 0" for readability. -+ */ -+void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen, -+ const u32 flags) -+{ -+ saRecord->saCmd0.bits.ivSource = 2; -+ if (IS_ECB(flags)) -+ saRecord->saCmd0.bits.saveIv = 0; -+ else -+ saRecord->saCmd0.bits.saveIv = 1; -+ -+ saRecord->saCmd0.bits.opGroup = 0; -+ saRecord->saCmd0.bits.opCode = 0; -+ -+ switch ((flags & MTK_ALG_MASK)) { -+ case MTK_ALG_AES: -+ saRecord->saCmd0.bits.cipher = 3; -+ saRecord->saCmd1.bits.aesKeyLen = keylen >> 3; -+ break; -+ case MTK_ALG_3DES: -+ saRecord->saCmd0.bits.cipher = 1; -+ break; -+ case MTK_ALG_DES: -+ saRecord->saCmd0.bits.cipher = 0; -+ break; -+ default: -+ saRecord->saCmd0.bits.cipher = 15; -+ } -+ -+ switch ((flags & MTK_HASH_MASK)) { -+ case MTK_HASH_SHA256: -+ saRecord->saCmd0.bits.hash = 3; -+ break; -+ case MTK_HASH_SHA224: -+ saRecord->saCmd0.bits.hash = 2; -+ break; -+ case MTK_HASH_SHA1: -+ saRecord->saCmd0.bits.hash = 1; -+ break; -+ case MTK_HASH_MD5: -+ saRecord->saCmd0.bits.hash = 0; -+ break; -+ default: -+ saRecord->saCmd0.bits.hash = 15; -+ } -+ -+ saRecord->saCmd0.bits.hdrProc = 0; -+ saRecord->saCmd0.bits.padType = 3; -+ saRecord->saCmd0.bits.extPad = 0; -+ saRecord->saCmd0.bits.scPad = 0; -+ -+ switch ((flags & MTK_MODE_MASK)) { -+ case MTK_MODE_CBC: -+ saRecord->saCmd1.bits.cipherMode = 1; -+ break; -+ case MTK_MODE_CTR: -+ saRecord->saCmd1.bits.cipherMode = 2; -+ break; -+ case MTK_MODE_ECB: -+ saRecord->saCmd1.bits.cipherMode = 0; -+ break; -+ } -+ -+ saRecord->saCmd1.bits.byteOffset = 0; -+ saRecord->saCmd1.bits.hashCryptOffset = 0; -+ saRecord->saCmd0.bits.digestLength = 0; -+ saRecord->saCmd1.bits.copyPayload = 0; -+ -+ if (IS_HMAC(flags)) { -+ saRecord->saCmd1.bits.hmac = 1; -+ saRecord->saCmd1.bits.copyDigest = 1; -+ saRecord->saCmd1.bits.copyHeader = 1; -+ } else { -+ saRecord->saCmd1.bits.hmac = 0; -+ saRecord->saCmd1.bits.copyDigest = 0; -+ saRecord->saCmd1.bits.copyHeader = 0; -+ } -+ -+ saRecord->saCmd1.bits.seqNumCheck = 0; -+ saRecord->saSpi = 0x0; -+ saRecord->saSeqNumMask[0] = 0xFFFFFFFF; -+ saRecord->saSeqNumMask[1] = 0x0; -+} -+ -+/* -+ * Poor mans Scatter/gather function: -+ * Create a Descriptor for every segment to avoid copying buffers. -+ * For performance better to wait for hardware to perform multiple DMA -+ * -+ */ -+static inline int mtk_scatter_combine(struct mtk_device *mtk, -+ struct mtk_cipher_reqctx *rctx, -+ u32 datalen, u32 split, int offsetin) -+{ -+ struct eip93_descriptor_s *cdesc = rctx->cdesc; -+ struct scatterlist *sgsrc = rctx->sg_src; -+ struct scatterlist *sgdst = rctx->sg_dst; -+ unsigned int remainin = sg_dma_len(sgsrc); -+ unsigned int remainout = sg_dma_len(sgdst); -+ dma_addr_t saddr = sg_dma_address(sgsrc); -+ dma_addr_t daddr = sg_dma_address(sgdst); -+ dma_addr_t stateAddr; -+ u32 srcAddr, dstAddr, len, n; -+ bool nextin = false; -+ bool nextout = false; -+ int offsetout = 0; -+ int ndesc_cdr = 0, err; -+ -+ if (IS_ECB(rctx->flags)) -+ rctx->saState_base = 0; -+ -+ if (split < datalen) { -+ stateAddr = rctx->saState_base_ctr; -+ n = split; -+ } else { -+ stateAddr = rctx->saState_base; -+ n = datalen; -+ } -+ -+ do { -+ if (nextin) { -+ sgsrc = sg_next(sgsrc); -+ remainin = sg_dma_len(sgsrc); -+ if (remainin == 0) -+ continue; -+ -+ saddr = sg_dma_address(sgsrc); -+ offsetin = 0; -+ nextin = false; -+ } -+ -+ if (nextout) { -+ sgdst = sg_next(sgdst); -+ remainout = sg_dma_len(sgdst); -+ if (remainout == 0) -+ continue; -+ -+ daddr = sg_dma_address(sgdst); -+ offsetout = 0; -+ nextout = false; -+ } -+ srcAddr = saddr + offsetin; -+ dstAddr = daddr + offsetout; -+ -+ if (remainin == remainout) { -+ len = remainin; -+ if (len > n) { -+ len = n; -+ remainin -= n; -+ remainout -= n; -+ offsetin += n; -+ offsetout += n; -+ } else { -+ nextin = true; -+ nextout = true; -+ } -+ } else if (remainin < remainout) { -+ len = remainin; -+ if (len > n) { -+ len = n; -+ remainin -= n; -+ remainout -= n; -+ offsetin += n; -+ offsetout += n; -+ } else { -+ offsetout += len; -+ remainout -= len; -+ nextin = true; -+ } -+ } else { -+ len = remainout; -+ if (len > n) { -+ len = n; -+ remainin -= n; -+ remainout -= n; -+ offsetin += n; -+ offsetout += n; -+ } else { -+ offsetin += len; -+ remainin -= len; -+ nextout = true; -+ } -+ } -+ n -= len; -+ -+ cdesc->srcAddr = srcAddr; -+ cdesc->dstAddr = dstAddr; -+ cdesc->stateAddr = stateAddr; -+ cdesc->peLength.bits.peReady = 0; -+ cdesc->peLength.bits.byPass = 0; -+ cdesc->peLength.bits.length = len; -+ cdesc->peLength.bits.hostReady = 1; -+ -+ if (n == 0) { -+ n = datalen - split; -+ split = datalen; -+ stateAddr = rctx->saState_base; -+ } -+ -+ if (n == 0) -+ cdesc->userId |= MTK_DESC_LAST; -+ -+ /* Loop - Delay - No need to rollback -+ * Maybe refine by slowing down at MTK_RING_BUSY -+ */ -+again: -+ err = mtk_put_descriptor(mtk, cdesc); -+ if (err) { -+ udelay(500); -+ goto again; -+ } -+ /* Writing new descriptor count starts DMA action */ -+ writel(1, mtk->base + EIP93_REG_PE_CD_COUNT); -+ -+ ndesc_cdr++; -+ } while (n); -+ -+ return -EINPROGRESS; -+} -+ -+int mtk_send_req(struct crypto_async_request *async, -+ const u8 *reqiv, struct mtk_cipher_reqctx *rctx) -+{ -+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm); -+ struct mtk_device *mtk = ctx->mtk; -+ struct scatterlist *src = rctx->sg_src; -+ struct scatterlist *dst = rctx->sg_dst; -+ struct saState_s *saState; -+ struct mtk_state_pool *saState_pool; -+ struct eip93_descriptor_s cdesc; -+ u32 flags = rctx->flags; -+ int idx; -+ int offsetin = 0, err = -ENOMEM; -+ u32 datalen = rctx->assoclen + rctx->textsize; -+ u32 split = datalen; -+ u32 start, end, ctr, blocks; -+ u32 iv[AES_BLOCK_SIZE / sizeof(u32)]; -+ -+ rctx->saState_ctr = NULL; -+ rctx->saState = NULL; -+ -+ if (IS_ECB(flags)) -+ goto skip_iv; -+ -+ memcpy(iv, reqiv, rctx->ivsize); -+ -+ if (!IS_ALIGNED((u32)reqiv, rctx->ivsize) || IS_RFC3686(flags)) { -+ rctx->flags &= ~MTK_DESC_DMA_IV; -+ flags = rctx->flags; -+ } -+ -+ if (IS_DMA_IV(flags)) { -+ rctx->saState = (void *)reqiv; -+ } else { -+ idx = mtk_get_free_saState(mtk); -+ if (idx < 0) -+ goto send_err; -+ saState_pool = &mtk->ring->saState_pool[idx]; -+ rctx->saState_idx = idx; -+ rctx->saState = saState_pool->base; -+ rctx->saState_base = saState_pool->base_dma; -+ memcpy(rctx->saState->stateIv, iv, rctx->ivsize); -+ } -+ -+ saState = rctx->saState; -+ -+ if (IS_RFC3686(flags)) { -+ saState->stateIv[0] = ctx->saNonce; -+ saState->stateIv[1] = iv[0]; -+ saState->stateIv[2] = iv[1]; -+ saState->stateIv[3] = cpu_to_be32(1); -+ } else if (!IS_HMAC(flags) && IS_CTR(flags)) { -+ /* Compute data length. */ -+ blocks = DIV_ROUND_UP(rctx->textsize, AES_BLOCK_SIZE); -+ ctr = be32_to_cpu(iv[3]); -+ /* Check 32bit counter overflow. */ -+ start = ctr; -+ end = start + blocks - 1; -+ if (end < start) { -+ split = AES_BLOCK_SIZE * -start; -+ /* -+ * Increment the counter manually to cope with -+ * the hardware counter overflow. -+ */ -+ iv[3] = 0xffffffff; -+ crypto_inc((u8 *)iv, AES_BLOCK_SIZE); -+ idx = mtk_get_free_saState(mtk); -+ if (idx < 0) -+ goto free_state; -+ saState_pool = &mtk->ring->saState_pool[idx]; -+ rctx->saState_ctr_idx = idx; -+ rctx->saState_ctr = saState_pool->base; -+ rctx->saState_base_ctr = saState_pool->base_dma; -+ -+ memcpy(rctx->saState_ctr->stateIv, reqiv, rctx->ivsize); -+ memcpy(saState->stateIv, iv, rctx->ivsize); -+ } -+ } -+ -+ if (IS_DMA_IV(flags)) { -+ rctx->saState_base = dma_map_single(mtk->dev, (void *)reqiv, -+ rctx->ivsize, DMA_TO_DEVICE); -+ if (dma_mapping_error(mtk->dev, rctx->saState_base)) -+ goto free_state; -+ } -+skip_iv: -+ cdesc.peCrtlStat.bits.hostReady = 1; -+ cdesc.peCrtlStat.bits.prngMode = 0; -+ cdesc.peCrtlStat.bits.hashFinal = 0; -+ cdesc.peCrtlStat.bits.padCrtlStat = 0; -+ cdesc.peCrtlStat.bits.peReady = 0; -+ cdesc.saAddr = rctx->saRecord_base; -+ cdesc.arc4Addr = (uint32_t)async; -+ cdesc.userId = flags; -+ rctx->cdesc = &cdesc; -+ -+ /* map DMA_BIDIRECTIONAL to invalidate cache on destination -+ * implies __dma_cache_wback_inv -+ */ -+ dma_map_sg(mtk->dev, dst, rctx->dst_nents, DMA_BIDIRECTIONAL); -+ if (src != dst) -+ dma_map_sg(mtk->dev, src, rctx->src_nents, DMA_TO_DEVICE); -+ -+ err = mtk_scatter_combine(mtk, rctx, datalen, split, offsetin); -+ -+ return err; -+ -+free_state: -+ if (rctx->saState) { -+ saState_pool = &mtk->ring->saState_pool[rctx->saState_idx]; -+ saState_pool->in_use = false; -+ } -+ -+ if (rctx->saState_ctr) { -+ saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx]; -+ saState_pool->in_use = false; -+ } -+send_err: -+ return err; -+} -+ -+void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx, -+ struct scatterlist *reqsrc, struct scatterlist *reqdst) -+{ -+ u32 len = rctx->assoclen + rctx->textsize; -+ u32 authsize = rctx->authsize; -+ u32 flags = rctx->flags; -+ u32 *otag; -+ int i; -+ -+ if (rctx->sg_src == rctx->sg_dst) { -+ dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents, -+ DMA_BIDIRECTIONAL); -+ goto process_tag; -+ } -+ -+ dma_unmap_sg(mtk->dev, rctx->sg_src, rctx->src_nents, -+ DMA_TO_DEVICE); -+ -+ if (rctx->sg_src != reqsrc) -+ mtk_free_sg_copy(len + rctx->authsize, &rctx->sg_src); -+ -+ dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents, -+ DMA_BIDIRECTIONAL); -+ -+ /* SHA tags need conversion from net-to-host */ -+process_tag: -+ if (IS_DECRYPT(flags)) -+ authsize = 0; -+ -+ if (authsize) { -+ if (!IS_HASH_MD5(flags)) { -+ otag = sg_virt(rctx->sg_dst) + len; -+ for (i = 0; i < (authsize / 4); i++) -+ otag[i] = ntohl(otag[i]); -+ } -+ } -+ -+ if (rctx->sg_dst != reqdst) { -+ sg_copy_from_buffer(reqdst, sg_nents(reqdst), -+ sg_virt(rctx->sg_dst), len + authsize); -+ mtk_free_sg_copy(len + rctx->authsize, &rctx->sg_dst); -+ } -+} -+ -+void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx, -+ u8 *reqiv) -+{ -+ struct mtk_state_pool *saState_pool; -+ -+ if (IS_DMA_IV(rctx->flags)) -+ dma_unmap_single(mtk->dev, rctx->saState_base, rctx->ivsize, -+ DMA_TO_DEVICE); -+ -+ if (!IS_ECB(rctx->flags)) -+ memcpy(reqiv, rctx->saState->stateIv, rctx->ivsize); -+ -+ if ((rctx->saState) && !(IS_DMA_IV(rctx->flags))) { -+ saState_pool = &mtk->ring->saState_pool[rctx->saState_idx]; -+ saState_pool->in_use = false; -+ } -+ -+ if (rctx->saState_ctr) { -+ saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx]; -+ saState_pool->in_use = false; -+ } -+} -+ -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC) -+/* basically this is set hmac - key */ -+int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa, -+ const u8 *authkey, unsigned int authkeylen) -+{ -+ int bs = crypto_shash_blocksize(cshash); -+ int ds = crypto_shash_digestsize(cshash); -+ int ss = crypto_shash_statesize(cshash); -+ u8 *ipad, *opad; -+ unsigned int i, err; -+ -+ SHASH_DESC_ON_STACK(shash, cshash); -+ -+ shash->tfm = cshash; -+ -+ /* auth key -+ * -+ * EIP93 can only authenticate with hash of the key -+ * do software shash until EIP93 hash function complete. -+ */ -+ ipad = kcalloc(2, SHA256_BLOCK_SIZE + ss, GFP_KERNEL); -+ if (!ipad) -+ return -ENOMEM; -+ -+ opad = ipad + SHA256_BLOCK_SIZE + ss; -+ -+ if (authkeylen > bs) { -+ err = crypto_shash_digest(shash, authkey, -+ authkeylen, ipad); -+ if (err) -+ return err; -+ -+ authkeylen = ds; -+ } else -+ memcpy(ipad, authkey, authkeylen); -+ -+ memset(ipad + authkeylen, 0, bs - authkeylen); -+ memcpy(opad, ipad, bs); -+ -+ for (i = 0; i < bs; i++) { -+ ipad[i] ^= HMAC_IPAD_VALUE; -+ opad[i] ^= HMAC_OPAD_VALUE; -+ } -+ -+ err = crypto_shash_init(shash) ?: -+ crypto_shash_update(shash, ipad, bs) ?: -+ crypto_shash_export(shash, ipad) ?: -+ crypto_shash_init(shash) ?: -+ crypto_shash_update(shash, opad, bs) ?: -+ crypto_shash_export(shash, opad); -+ -+ if (err) -+ return err; -+ -+ /* add auth key */ -+ memcpy(&sa->saIDigest, ipad, SHA256_DIGEST_SIZE); -+ memcpy(&sa->saODigest, opad, SHA256_DIGEST_SIZE); -+ -+ kfree(ipad); -+ return 0; -+} -+#endif ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-common.h -@@ -0,0 +1,28 @@ -+/* SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+ -+#ifndef _EIP93_COMMON_H_ -+#define _EIP93_COMMON_H_ -+ -+#include "eip93-main.h" -+ -+inline int mtk_put_descriptor(struct mtk_device *mtk, -+ struct eip93_descriptor_s *desc); -+ -+inline void *mtk_get_descriptor(struct mtk_device *mtk); -+ -+inline int mtk_get_free_saState(struct mtk_device *mtk); -+ -+void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen, -+ const u32 flags); -+ -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC) -+int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa, -+ const u8 *authkey, unsigned int authkeylen); -+#endif -+ -+#endif /* _EIP93_COMMON_H_ */ ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-des.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+#ifndef _EIP93_DES_H_ -+#define _EIP93_DES_H_ -+ -+extern struct mtk_alg_template mtk_alg_ecb_des; -+extern struct mtk_alg_template mtk_alg_cbc_des; -+extern struct mtk_alg_template mtk_alg_ecb_des3_ede; -+extern struct mtk_alg_template mtk_alg_cbc_des3_ede; -+ -+#endif /* _EIP93_DES_H_ */ ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-main.c -@@ -0,0 +1,467 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "eip93-main.h" -+#include "eip93-regs.h" -+#include "eip93-common.h" -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER) -+#include "eip93-cipher.h" -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES) -+#include "eip93-aes.h" -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+#include "eip93-des.h" -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD) -+#include "eip93-aead.h" -+#endif -+ -+static struct mtk_alg_template *mtk_algs[] = { -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+ &mtk_alg_ecb_des, -+ &mtk_alg_cbc_des, -+ &mtk_alg_ecb_des3_ede, -+ &mtk_alg_cbc_des3_ede, -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES) -+ &mtk_alg_ecb_aes, -+ &mtk_alg_cbc_aes, -+ &mtk_alg_ctr_aes, -+ &mtk_alg_rfc3686_aes, -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD) -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+ &mtk_alg_authenc_hmac_md5_cbc_des, -+ &mtk_alg_authenc_hmac_sha1_cbc_des, -+ &mtk_alg_authenc_hmac_sha224_cbc_des, -+ &mtk_alg_authenc_hmac_sha256_cbc_des, -+ &mtk_alg_authenc_hmac_md5_cbc_des3_ede, -+ &mtk_alg_authenc_hmac_sha1_cbc_des3_ede, -+ &mtk_alg_authenc_hmac_sha224_cbc_des3_ede, -+ &mtk_alg_authenc_hmac_sha256_cbc_des3_ede, -+#endif -+ &mtk_alg_authenc_hmac_md5_cbc_aes, -+ &mtk_alg_authenc_hmac_sha1_cbc_aes, -+ &mtk_alg_authenc_hmac_sha224_cbc_aes, -+ &mtk_alg_authenc_hmac_sha256_cbc_aes, -+ &mtk_alg_authenc_hmac_md5_rfc3686_aes, -+ &mtk_alg_authenc_hmac_sha1_rfc3686_aes, -+ &mtk_alg_authenc_hmac_sha224_rfc3686_aes, -+ &mtk_alg_authenc_hmac_sha256_rfc3686_aes, -+#endif -+}; -+ -+inline void mtk_irq_disable(struct mtk_device *mtk, u32 mask) -+{ -+ __raw_writel(mask, mtk->base + EIP93_REG_MASK_DISABLE); -+} -+ -+inline void mtk_irq_enable(struct mtk_device *mtk, u32 mask) -+{ -+ __raw_writel(mask, mtk->base + EIP93_REG_MASK_ENABLE); -+} -+ -+inline void mtk_irq_clear(struct mtk_device *mtk, u32 mask) -+{ -+ __raw_writel(mask, mtk->base + EIP93_REG_INT_CLR); -+} -+ -+static void mtk_unregister_algs(unsigned int i) -+{ -+ unsigned int j; -+ -+ for (j = 0; j < i; j++) { -+ switch (mtk_algs[j]->type) { -+ case MTK_ALG_TYPE_SKCIPHER: -+ crypto_unregister_skcipher(&mtk_algs[j]->alg.skcipher); -+ break; -+ case MTK_ALG_TYPE_AEAD: -+ crypto_unregister_aead(&mtk_algs[j]->alg.aead); -+ break; -+ } -+ } -+} -+ -+static int mtk_register_algs(struct mtk_device *mtk) -+{ -+ unsigned int i; -+ int err = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(mtk_algs); i++) { -+ mtk_algs[i]->mtk = mtk; -+ -+ switch (mtk_algs[i]->type) { -+ case MTK_ALG_TYPE_SKCIPHER: -+ err = crypto_register_skcipher(&mtk_algs[i]->alg.skcipher); -+ break; -+ case MTK_ALG_TYPE_AEAD: -+ err = crypto_register_aead(&mtk_algs[i]->alg.aead); -+ break; -+ } -+ if (err) -+ goto fail; -+ } -+ -+ return 0; -+ -+fail: -+ mtk_unregister_algs(i); -+ -+ return err; -+} -+ -+static void mtk_handle_result_descriptor(struct mtk_device *mtk) -+{ -+ struct crypto_async_request *async; -+ struct eip93_descriptor_s *rdesc; -+ bool last_entry; -+ u32 flags; -+ int handled, ready, err; -+ union peCrtlStat_w done1; -+ union peLength_w done2; -+ -+get_more: -+ handled = 0; -+ -+ ready = readl(mtk->base + EIP93_REG_PE_RD_COUNT) & GENMASK(10, 0); -+ -+ if (!ready) { -+ mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ); -+ mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ); -+ return; -+ } -+ -+ last_entry = false; -+ -+ while (ready) { -+ rdesc = mtk_get_descriptor(mtk); -+ if (IS_ERR(rdesc)) { -+ dev_err(mtk->dev, "Ndesc: %d nreq: %d\n", -+ handled, ready); -+ err = -EIO; -+ break; -+ } -+ /* make sure DMA is finished writing */ -+ do { -+ done1.word = READ_ONCE(rdesc->peCrtlStat.word); -+ done2.word = READ_ONCE(rdesc->peLength.word); -+ } while ((!done1.bits.peReady) || (!done2.bits.peReady)); -+ -+ err = rdesc->peCrtlStat.bits.errStatus; -+ -+ flags = rdesc->userId; -+ async = (struct crypto_async_request *)rdesc->arc4Addr; -+ -+ writel(1, mtk->base + EIP93_REG_PE_RD_COUNT); -+ mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ); -+ -+ handled++; -+ ready--; -+ -+ if (flags & MTK_DESC_LAST) { -+ last_entry = true; -+ break; -+ } -+ } -+ -+ if (!last_entry) -+ goto get_more; -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER) -+ if (flags & MTK_DESC_SKCIPHER) -+ mtk_skcipher_handle_result(async, err); -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD) -+ if (flags & MTK_DESC_AEAD) -+ mtk_aead_handle_result(async, err); -+#endif -+ goto get_more; -+} -+ -+static void mtk_done_task(unsigned long data) -+{ -+ struct mtk_device *mtk = (struct mtk_device *)data; -+ -+ mtk_handle_result_descriptor(mtk); -+} -+ -+static irqreturn_t mtk_irq_handler(int irq, void *dev_id) -+{ -+ struct mtk_device *mtk = (struct mtk_device *)dev_id; -+ u32 irq_status; -+ -+ irq_status = readl(mtk->base + EIP93_REG_INT_MASK_STAT); -+ -+ if (irq_status & EIP93_INT_PE_RDRTHRESH_REQ) { -+ mtk_irq_disable(mtk, EIP93_INT_PE_RDRTHRESH_REQ); -+ tasklet_schedule(&mtk->ring->done_task); -+ return IRQ_HANDLED; -+ } -+ -+ mtk_irq_clear(mtk, irq_status); -+ if (irq_status) -+ mtk_irq_disable(mtk, irq_status); -+ -+ return IRQ_NONE; -+} -+ -+static void mtk_initialize(struct mtk_device *mtk) -+{ -+ union peConfig_w peConfig; -+ union peEndianCfg_w peEndianCfg; -+ union peIntCfg_w peIntCfg; -+ union peClockCfg_w peClockCfg; -+ union peBufThresh_w peBufThresh; -+ union peRingThresh_w peRingThresh; -+ -+ /* Reset Engine and setup Mode */ -+ peConfig.word = 0; -+ peConfig.bits.resetPE = 1; -+ peConfig.bits.resetRing = 1; -+ peConfig.bits.peMode = 3; -+ peConfig.bits.enCDRupdate = 1; -+ -+ writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG); -+ -+ udelay(10); -+ -+ peConfig.bits.resetPE = 0; -+ peConfig.bits.resetRing = 0; -+ -+ writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG); -+ -+ /* Initialize the BYTE_ORDER_CFG register */ -+ peEndianCfg.word = 0; -+ writel(peEndianCfg.word, mtk->base + EIP93_REG_PE_ENDIAN_CONFIG); -+ -+ /* Initialize the INT_CFG register */ -+ peIntCfg.word = 0; -+ writel(peIntCfg.word, mtk->base + EIP93_REG_INT_CFG); -+ -+ /* Config Clocks */ -+ peClockCfg.word = 0; -+ peClockCfg.bits.enPEclk = 1; -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES) -+ peClockCfg.bits.enDESclk = 1; -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES) -+ peClockCfg.bits.enAESclk = 1; -+#endif -+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC) -+ peClockCfg.bits.enHASHclk = 1; -+#endif -+ writel(peClockCfg.word, mtk->base + EIP93_REG_PE_CLOCK_CTRL); -+ -+ /* Config DMA thresholds */ -+ peBufThresh.word = 0; -+ peBufThresh.bits.inputBuffer = 128; -+ peBufThresh.bits.outputBuffer = 128; -+ -+ writel(peBufThresh.word, mtk->base + EIP93_REG_PE_BUF_THRESH); -+ -+ /* Clear/ack all interrupts before disable all */ -+ mtk_irq_clear(mtk, 0xFFFFFFFF); -+ mtk_irq_disable(mtk, 0xFFFFFFFF); -+ -+ /* Config Ring Threshold */ -+ peRingThresh.word = 0; -+ peRingThresh.bits.CDRThresh = MTK_RING_SIZE - MTK_RING_BUSY; -+ peRingThresh.bits.RDRThresh = 0; -+ peRingThresh.bits.RDTimeout = 5; -+ peRingThresh.bits.enTimeout = 1; -+ -+ writel(peRingThresh.word, mtk->base + EIP93_REG_PE_RING_THRESH); -+} -+ -+static void mtk_desc_free(struct mtk_device *mtk) -+{ -+ writel(0, mtk->base + EIP93_REG_PE_RING_CONFIG); -+ writel(0, mtk->base + EIP93_REG_PE_CDR_BASE); -+ writel(0, mtk->base + EIP93_REG_PE_RDR_BASE); -+} -+ -+static int mtk_set_ring(struct mtk_device *mtk, struct mtk_desc_ring *ring, -+ int Offset) -+{ -+ ring->offset = Offset; -+ ring->base = dmam_alloc_coherent(mtk->dev, Offset * MTK_RING_SIZE, -+ &ring->base_dma, GFP_KERNEL); -+ if (!ring->base) -+ return -ENOMEM; -+ -+ ring->write = ring->base; -+ ring->base_end = ring->base + Offset * (MTK_RING_SIZE - 1); -+ ring->read = ring->base; -+ -+ return 0; -+} -+ -+static int mtk_desc_init(struct mtk_device *mtk) -+{ -+ struct mtk_state_pool *saState_pool; -+ struct mtk_desc_ring *cdr = &mtk->ring->cdr; -+ struct mtk_desc_ring *rdr = &mtk->ring->rdr; -+ union peRingCfg_w peRingCfg; -+ int RingOffset, err, i; -+ -+ RingOffset = sizeof(struct eip93_descriptor_s); -+ -+ err = mtk_set_ring(mtk, cdr, RingOffset); -+ if (err) -+ return err; -+ -+ err = mtk_set_ring(mtk, rdr, RingOffset); -+ if (err) -+ return err; -+ -+ writel((u32)cdr->base_dma, mtk->base + EIP93_REG_PE_CDR_BASE); -+ writel((u32)rdr->base_dma, mtk->base + EIP93_REG_PE_RDR_BASE); -+ -+ peRingCfg.word = 0; -+ peRingCfg.bits.ringSize = MTK_RING_SIZE - 1; -+ peRingCfg.bits.ringOffset = RingOffset / 4; -+ -+ writel(peRingCfg.word, mtk->base + EIP93_REG_PE_RING_CONFIG); -+ -+ atomic_set(&mtk->ring->free, MTK_RING_SIZE - 1); -+ /* Create State record DMA pool */ -+ RingOffset = sizeof(struct saState_s); -+ mtk->ring->saState = dmam_alloc_coherent(mtk->dev, -+ RingOffset * MTK_RING_SIZE, -+ &mtk->ring->saState_dma, GFP_KERNEL); -+ if (!mtk->ring->saState) -+ return -ENOMEM; -+ -+ mtk->ring->saState_pool = devm_kcalloc(mtk->dev, 1, -+ sizeof(struct mtk_state_pool) * MTK_RING_SIZE, -+ GFP_KERNEL); -+ -+ for (i = 0; i < MTK_RING_SIZE; i++) { -+ saState_pool = &mtk->ring->saState_pool[i]; -+ saState_pool->base = mtk->ring->saState + (i * RingOffset); -+ saState_pool->base_dma = mtk->ring->saState_dma + (i * RingOffset); -+ saState_pool->in_use = false; -+ } -+ -+ return 0; -+} -+ -+static void mtk_cleanup(struct mtk_device *mtk) -+{ -+ tasklet_kill(&mtk->ring->done_task); -+ -+ /* Clear/ack all interrupts before disable all */ -+ mtk_irq_clear(mtk, 0xFFFFFFFF); -+ mtk_irq_disable(mtk, 0xFFFFFFFF); -+ -+ writel(0, mtk->base + EIP93_REG_PE_CLOCK_CTRL); -+ -+ mtk_desc_free(mtk); -+} -+ -+static int mtk_crypto_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct mtk_device *mtk; -+ struct resource *res; -+ int err; -+ -+ mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); -+ if (!mtk) -+ return -ENOMEM; -+ -+ mtk->dev = dev; -+ platform_set_drvdata(pdev, mtk); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ mtk->base = devm_ioremap_resource(&pdev->dev, res); -+ -+ if (IS_ERR(mtk->base)) -+ return PTR_ERR(mtk->base); -+ -+ mtk->irq = platform_get_irq(pdev, 0); -+ -+ if (mtk->irq < 0) -+ return mtk->irq; -+ -+ err = devm_request_threaded_irq(mtk->dev, mtk->irq, mtk_irq_handler, -+ NULL, IRQF_ONESHOT, -+ dev_name(mtk->dev), mtk); -+ -+ mtk->ring = devm_kcalloc(mtk->dev, 1, sizeof(*mtk->ring), GFP_KERNEL); -+ -+ if (!mtk->ring) -+ return -ENOMEM; -+ -+ err = mtk_desc_init(mtk); -+ if (err) -+ return err; -+ -+ tasklet_init(&mtk->ring->done_task, mtk_done_task, (unsigned long)mtk); -+ -+ spin_lock_init(&mtk->ring->read_lock); -+ spin_lock_init(&mtk->ring->write_lock); -+ -+ mtk_initialize(mtk); -+ -+ /* Init. finished, enable RDR interupt */ -+ mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ); -+ -+ err = mtk_register_algs(mtk); -+ if (err) { -+ mtk_cleanup(mtk); -+ return err; -+ } -+ -+ dev_info(mtk->dev, "EIP93 Crypto Engine Initialized."); -+ -+ return 0; -+} -+ -+static int mtk_crypto_remove(struct platform_device *pdev) -+{ -+ struct mtk_device *mtk = platform_get_drvdata(pdev); -+ -+ mtk_unregister_algs(ARRAY_SIZE(mtk_algs)); -+ mtk_cleanup(mtk); -+ dev_info(mtk->dev, "EIP93 removed.\n"); -+ -+ return 0; -+} -+ -+#if defined(CONFIG_OF) -+static const struct of_device_id mtk_crypto_of_match[] = { -+ { .compatible = "mediatek,mtk-eip93", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, mtk_crypto_of_match); -+#endif -+ -+static struct platform_driver mtk_crypto_driver = { -+ .probe = mtk_crypto_probe, -+ .remove = mtk_crypto_remove, -+ .driver = { -+ .name = "mtk-eip93", -+ .of_match_table = of_match_ptr(mtk_crypto_of_match), -+ }, -+}; -+module_platform_driver(mtk_crypto_driver); -+ -+MODULE_AUTHOR("Richard van Schagen "); -+MODULE_ALIAS("platform:" KBUILD_MODNAME); -+MODULE_DESCRIPTION("Mediatek EIP-93 crypto engine driver"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-main.h -@@ -0,0 +1,146 @@ -+/* SPDX-License-Identifier: GPL-2.0 -+ * -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+#ifndef _EIP93_MAIN_H_ -+#define _EIP93_MAIN_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MTK_RING_SIZE 512 -+#define MTK_RING_BUSY 32 -+#define MTK_CRA_PRIORITY 1500 -+ -+/* cipher algorithms */ -+#define MTK_ALG_DES BIT(0) -+#define MTK_ALG_3DES BIT(1) -+#define MTK_ALG_AES BIT(2) -+#define MTK_ALG_MASK GENMASK(2, 0) -+/* hash and hmac algorithms */ -+#define MTK_HASH_MD5 BIT(3) -+#define MTK_HASH_SHA1 BIT(4) -+#define MTK_HASH_SHA224 BIT(5) -+#define MTK_HASH_SHA256 BIT(6) -+#define MTK_HASH_HMAC BIT(7) -+#define MTK_HASH_MASK GENMASK(6, 3) -+/* cipher modes */ -+#define MTK_MODE_CBC BIT(8) -+#define MTK_MODE_ECB BIT(9) -+#define MTK_MODE_CTR BIT(10) -+#define MTK_MODE_RFC3686 BIT(11) -+#define MTK_MODE_MASK GENMASK(10, 8) -+ -+/* cipher encryption/decryption operations */ -+#define MTK_ENCRYPT BIT(12) -+#define MTK_DECRYPT BIT(13) -+ -+#define MTK_BUSY BIT(14) -+ -+/* descriptor flags */ -+#define MTK_DESC_ASYNC BIT(31) -+#define MTK_DESC_SKCIPHER BIT(30) -+#define MTK_DESC_AEAD BIT(29) -+#define MTK_DESC_AHASH BIT(28) -+#define MTK_DESC_PRNG BIT(27) -+#define MTK_DESC_FAKE_HMAC BIT(26) -+#define MTK_DESC_LAST BIT(25) -+#define MTK_DESC_FINISH BIT(24) -+#define MTK_DESC_IPSEC BIT(23) -+#define MTK_DESC_DMA_IV BIT(22) -+ -+#define IS_DES(flags) (flags & MTK_ALG_DES) -+#define IS_3DES(flags) (flags & MTK_ALG_3DES) -+#define IS_AES(flags) (flags & MTK_ALG_AES) -+ -+#define IS_HASH_MD5(flags) (flags & MTK_HASH_MD5) -+#define IS_HASH_SHA1(flags) (flags & MTK_HASH_SHA1) -+#define IS_HASH_SHA224(flags) (flags & MTK_HASH_SHA224) -+#define IS_HASH_SHA256(flags) (flags & MTK_HASH_SHA256) -+#define IS_HMAC(flags) (flags & MTK_HASH_HMAC) -+ -+#define IS_CBC(mode) (mode & MTK_MODE_CBC) -+#define IS_ECB(mode) (mode & MTK_MODE_ECB) -+#define IS_CTR(mode) (mode & MTK_MODE_CTR) -+#define IS_RFC3686(mode) (mode & MTK_MODE_RFC3686) -+ -+#define IS_BUSY(flags) (flags & MTK_BUSY) -+#define IS_DMA_IV(flags) (flags & MTK_DESC_DMA_IV) -+ -+#define IS_ENCRYPT(dir) (dir & MTK_ENCRYPT) -+#define IS_DECRYPT(dir) (dir & MTK_DECRYPT) -+ -+#define IS_CIPHER(flags) (flags & (MTK_ALG_DES || \ -+ MTK_ALG_3DES || \ -+ MTK_ALG_AES)) -+ -+#define IS_HASH(flags) (flags & (MTK_HASH_MD5 || \ -+ MTK_HASH_SHA1 || \ -+ MTK_HASH_SHA224 || \ -+ MTK_HASH_SHA256)) -+ -+/** -+ * struct mtk_device - crypto engine device structure -+ */ -+struct mtk_device { -+ void __iomem *base; -+ struct device *dev; -+ struct clk *clk; -+ int irq; -+ struct mtk_ring *ring; -+ struct mtk_state_pool *saState_pool; -+}; -+ -+struct mtk_desc_ring { -+ void *base; -+ void *base_end; -+ dma_addr_t base_dma; -+ /* write and read pointers */ -+ void *read; -+ void *write; -+ /* descriptor element offset */ -+ u32 offset; -+}; -+ -+struct mtk_state_pool { -+ void *base; -+ dma_addr_t base_dma; -+ bool in_use; -+}; -+ -+struct mtk_ring { -+ struct tasklet_struct done_task; -+ /* command/result rings */ -+ struct mtk_desc_ring cdr; -+ struct mtk_desc_ring rdr; -+ spinlock_t write_lock; -+ spinlock_t read_lock; -+ atomic_t free; -+ /* saState */ -+ struct mtk_state_pool *saState_pool; -+ void *saState; -+ dma_addr_t saState_dma; -+}; -+ -+enum mtk_alg_type { -+ MTK_ALG_TYPE_AEAD, -+ MTK_ALG_TYPE_SKCIPHER, -+}; -+ -+struct mtk_alg_template { -+ struct mtk_device *mtk; -+ enum mtk_alg_type type; -+ u32 flags; -+ union { -+ struct aead_alg aead; -+ struct skcipher_alg skcipher; -+ } alg; -+}; -+ -+#endif /* _EIP93_MAIN_H_ */ ---- /dev/null -+++ b/drivers/crypto/mtk-eip93/eip93-regs.h -@@ -0,0 +1,382 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2019 - 2021 -+ * -+ * Richard van Schagen -+ */ -+#ifndef REG_EIP93_H -+#define REG_EIP93_H -+ -+#define EIP93_REG_WIDTH 4 -+/*----------------------------------------------------------------------------- -+ * Register Map -+ */ -+#define DESP_BASE 0x0000000 -+#define EIP93_REG_PE_CTRL_STAT ((DESP_BASE)+(0x00 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_SOURCE_ADDR ((DESP_BASE)+(0x01 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_DEST_ADDR ((DESP_BASE)+(0x02 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_SA_ADDR ((DESP_BASE)+(0x03 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_ADDR ((DESP_BASE)+(0x04 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_USER_ID ((DESP_BASE)+(0x06 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_LENGTH ((DESP_BASE)+(0x07 * EIP93_REG_WIDTH)) -+ -+//PACKET ENGINE RING configuration registers -+#define PE_RNG_BASE 0x0000080 -+ -+#define EIP93_REG_PE_CDR_BASE ((PE_RNG_BASE)+(0x00 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_RDR_BASE ((PE_RNG_BASE)+(0x01 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_RING_CONFIG ((PE_RNG_BASE)+(0x02 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_RING_THRESH ((PE_RNG_BASE)+(0x03 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_CD_COUNT ((PE_RNG_BASE)+(0x04 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_RD_COUNT ((PE_RNG_BASE)+(0x05 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_RING_RW_PNTR ((PE_RNG_BASE)+(0x06 * EIP93_REG_WIDTH)) -+ -+//PACKET ENGINE configuration registers -+#define PE_CFG_BASE 0x0000100 -+#define EIP93_REG_PE_CONFIG ((PE_CFG_BASE)+(0x00 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_STATUS ((PE_CFG_BASE)+(0x01 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_BUF_THRESH ((PE_CFG_BASE)+(0x03 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_INBUF_COUNT ((PE_CFG_BASE)+(0x04 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_OUTBUF_COUNT ((PE_CFG_BASE)+(0x05 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_BUF_RW_PNTR ((PE_CFG_BASE)+(0x06 * EIP93_REG_WIDTH)) -+ -+//PACKET ENGINE endian config -+#define EN_CFG_BASE 0x00001CC -+#define EIP93_REG_PE_ENDIAN_CONFIG ((EN_CFG_BASE)+(0x00 * EIP93_REG_WIDTH)) -+ -+//EIP93 CLOCK control registers -+#define CLOCK_BASE 0x01E8 -+#define EIP93_REG_PE_CLOCK_CTRL ((CLOCK_BASE)+(0x00 * EIP93_REG_WIDTH)) -+ -+//EIP93 Device Option and Revision Register -+#define REV_BASE 0x01F4 -+#define EIP93_REG_PE_OPTION_1 ((REV_BASE)+(0x00 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_OPTION_0 ((REV_BASE)+(0x01 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PE_REVISION ((REV_BASE)+(0x02 * EIP93_REG_WIDTH)) -+ -+//EIP93 Interrupt Control Register -+#define INT_BASE 0x0200 -+#define EIP93_REG_INT_UNMASK_STAT ((INT_BASE)+(0x00 * EIP93_REG_WIDTH)) -+#define EIP93_REG_INT_MASK_STAT ((INT_BASE)+(0x01 * EIP93_REG_WIDTH)) -+#define EIP93_REG_INT_CLR ((INT_BASE)+(0x01 * EIP93_REG_WIDTH)) -+#define EIP93_REG_INT_MASK ((INT_BASE)+(0x02 * EIP93_REG_WIDTH)) -+#define EIP93_REG_INT_CFG ((INT_BASE)+(0x03 * EIP93_REG_WIDTH)) -+#define EIP93_REG_MASK_ENABLE ((INT_BASE)+(0X04 * EIP93_REG_WIDTH)) -+#define EIP93_REG_MASK_DISABLE ((INT_BASE)+(0X05 * EIP93_REG_WIDTH)) -+ -+//EIP93 SA Record register -+#define SA_BASE 0x0400 -+#define EIP93_REG_SA_CMD_0 ((SA_BASE)+(0x00 * EIP93_REG_WIDTH)) -+#define EIP93_REG_SA_CMD_1 ((SA_BASE)+(0x01 * EIP93_REG_WIDTH)) -+ -+//#define EIP93_REG_SA_READY ((SA_BASE)+(31 * EIP93_REG_WIDTH)) -+ -+//State save register -+#define STATE_BASE 0x0500 -+#define EIP93_REG_STATE_IV_0 ((STATE_BASE)+(0x00 * EIP93_REG_WIDTH)) -+#define EIP93_REG_STATE_IV_1 ((STATE_BASE)+(0x01 * EIP93_REG_WIDTH)) -+ -+#define EIP93_PE_ARC4STATE_BASEADDR_REG 0x0700 -+ -+//RAM buffer start address -+#define EIP93_INPUT_BUFFER 0x0800 -+#define EIP93_OUTPUT_BUFFER 0x0800 -+ -+//EIP93 PRNG Configuration Register -+#define PRNG_BASE 0x0300 -+#define EIP93_REG_PRNG_STAT ((PRNG_BASE)+(0x00 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_CTRL ((PRNG_BASE)+(0x01 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_SEED_0 ((PRNG_BASE)+(0x02 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_SEED_1 ((PRNG_BASE)+(0x03 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_SEED_2 ((PRNG_BASE)+(0x04 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_SEED_3 ((PRNG_BASE)+(0x05 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_KEY_0 ((PRNG_BASE)+(0x06 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_KEY_1 ((PRNG_BASE)+(0x07 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_KEY_2 ((PRNG_BASE)+(0x08 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_KEY_3 ((PRNG_BASE)+(0x09 * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_RES_0 ((PRNG_BASE)+(0x0A * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_RES_1 ((PRNG_BASE)+(0x0B * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_RES_2 ((PRNG_BASE)+(0x0C * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_RES_3 ((PRNG_BASE)+(0x0D * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_LFSR_0 ((PRNG_BASE)+(0x0E * EIP93_REG_WIDTH)) -+#define EIP93_REG_PRNG_LFSR_1 ((PRNG_BASE)+(0x0F * EIP93_REG_WIDTH)) -+ -+/*----------------------------------------------------------------------------- -+ * Constants & masks -+ */ -+ -+#define EIP93_SUPPORTED_INTERRUPTS_MASK 0xffff7f00 -+#define EIP93_PRNG_DT_TEXT_LOWERHALF 0xDEAD -+#define EIP93_PRNG_DT_TEXT_UPPERHALF 0xC0DE -+#define EIP93_10BITS_MASK 0X3FF -+#define EIP93_12BITS_MASK 0XFFF -+#define EIP93_4BITS_MASK 0X04 -+#define EIP93_20BITS_MASK 0xFFFFF -+ -+#define EIP93_MIN_DESC_DONE_COUNT 0 -+#define EIP93_MAX_DESC_DONE_COUNT 15 -+ -+#define EIP93_MIN_DESC_PENDING_COUNT 0 -+#define EIP93_MAX_DESC_PENDING_COUNT 1023 -+ -+#define EIP93_MIN_TIMEOUT_COUNT 0 -+#define EIP93_MAX_TIMEOUT_COUNT 15 -+ -+#define EIP93_MIN_PE_INPUT_THRESHOLD 1 -+#define EIP93_MAX_PE_INPUT_THRESHOLD 511 -+ -+#define EIP93_MIN_PE_OUTPUT_THRESHOLD 1 -+#define EIP93_MAX_PE_OUTPUT_THRESHOLD 432 -+ -+#define EIP93_MIN_PE_RING_SIZE 1 -+#define EIP93_MAX_PE_RING_SIZE 1023 -+ -+#define EIP93_MIN_PE_DESCRIPTOR_SIZE 7 -+#define EIP93_MAX_PE_DESCRIPTOR_SIZE 15 -+ -+//3DES keys,seed,known data and its result -+#define EIP93_KEY_0 0x133b3454 -+#define EIP93_KEY_1 0x5e5b890b -+#define EIP93_KEY_2 0x5eb30757 -+#define EIP93_KEY_3 0x93ab15f7 -+#define EIP93_SEED_0 0x62c4bf5e -+#define EIP93_SEED_1 0x972667c8 -+#define EIP93_SEED_2 0x6345bf67 -+#define EIP93_SEED_3 0xcb3482bf -+#define EIP93_LFSR_0 0xDEADC0DE -+#define EIP93_LFSR_1 0xBEEFF00D -+ -+/*----------------------------------------------------------------------------- -+ * EIP93 device initialization specifics -+ */ -+ -+/*---------------------------------------------------------------------------- -+ * Byte Order Reversal Mechanisms Supported in EIP93 -+ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word -+ * EIP93_BO_REVERSE_WORD : reverse the byte order within a word -+ * EIP93_BO_REVERSE_DUAL_WORD : reverse the byte order within a dual-word -+ * EIP93_BO_REVERSE_QUAD_WORD : reverse the byte order within a quad-word -+ */ -+enum EIP93_Byte_Order_Value_t { -+ EIP93_BO_REVERSE_HALF_WORD = 1, -+ EIP93_BO_REVERSE_WORD = 2, -+ EIP93_BO_REVERSE_DUAL_WORD = 4, -+ EIP93_BO_REVERSE_QUAD_WORD = 8, -+}; -+ -+/*---------------------------------------------------------------------------- -+ * Byte Order Reversal Mechanisms Supported in EIP93 for Target Data -+ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word -+ * EIP93_BO_REVERSE_WORD : reverse the byte order within a word -+ */ -+enum EIP93_Byte_Order_Value_TD_t { -+ EIP93_BO_REVERSE_HALF_WORD_TD = 1, -+ EIP93_BO_REVERSE_WORD_TD = 2, -+}; -+ -+// BYTE_ORDER_CFG register values -+#define EIP93_BYTE_ORDER_PD EIP93_BO_REVERSE_WORD -+#define EIP93_BYTE_ORDER_SA EIP93_BO_REVERSE_WORD -+#define EIP93_BYTE_ORDER_DATA EIP93_BO_REVERSE_WORD -+#define EIP93_BYTE_ORDER_TD EIP93_BO_REVERSE_WORD_TD -+ -+// INT_CFG register values -+#define EIP93_INT_HOST_OUTPUT_TYPE 0 -+#define EIP93_INT_PULSE_CLEAR 0 -+ -+/* -+ * Interrupts of EIP93 -+ */ -+ -+enum EIP93_InterruptSource_t { -+ EIP93_INT_PE_CDRTHRESH_REQ = BIT(0), -+ EIP93_INT_PE_RDRTHRESH_REQ = BIT(1), -+ EIP93_INT_PE_OPERATION_DONE = BIT(9), -+ EIP93_INT_PE_INBUFTHRESH_REQ = BIT(10), -+ EIP93_INT_PE_OUTBURTHRSH_REQ = BIT(11), -+ EIP93_INT_PE_PRNG_IRQ = BIT(12), -+ EIP93_INT_PE_ERR_REG = BIT(13), -+ EIP93_INT_PE_RD_DONE_IRQ = BIT(16), -+}; -+ -+union peConfig_w { -+ u32 word; -+ struct { -+ u32 resetPE :1; -+ u32 resetRing :1; -+ u32 reserved :6; -+ u32 peMode :2; -+ u32 enCDRupdate :1; -+ u32 reserved2 :5; -+ u32 swapCDRD :1; -+ u32 swapSA :1; -+ u32 swapData :1; -+ u32 reserved3 :13; -+ } bits; -+} __packed; -+ -+union peEndianCfg_w { -+ u32 word; -+ struct { -+ u32 masterByteSwap :8; -+ u32 reserved :8; -+ u32 targetByteSwap :8; -+ u32 reserved2 :8; -+ } bits; -+} __packed; -+ -+union peIntCfg_w { -+ u32 word; -+ struct { -+ u32 PulseClear :1; -+ u32 IntType :1; -+ u32 reserved :30; -+ } bits; -+} __packed; -+ -+union peClockCfg_w { -+ u32 word; -+ struct { -+ u32 enPEclk :1; -+ u32 enDESclk :1; -+ u32 enAESclk :1; -+ u32 reserved :1; -+ u32 enHASHclk :1; -+ u32 reserved2 :27; -+ } bits; -+} __packed; -+ -+union peBufThresh_w { -+ u32 word; -+ struct { -+ u32 inputBuffer :8; -+ u32 reserved :8; -+ u32 outputBuffer :8; -+ u32 reserved2 :8; -+ } bits; -+} __packed; -+ -+union peRingThresh_w { -+ u32 word; -+ struct { -+ u32 CDRThresh :10; -+ u32 reserved :6; -+ u32 RDRThresh :10; -+ u32 RDTimeout :4; -+ u32 reserved2 :1; -+ u32 enTimeout :1; -+ } bits; -+} __packed; -+ -+union peRingCfg_w { -+ u32 word; -+ struct { -+ u32 ringSize :10; -+ u32 reserved :6; -+ u32 ringOffset :8; -+ u32 reserved2 :8; -+ } bits; -+} __packed; -+ -+union saCmd0 { -+ u32 word; -+ struct { -+ u32 opCode :3; -+ u32 direction :1; -+ u32 opGroup :2; -+ u32 padType :2; -+ u32 cipher :4; -+ u32 hash :4; -+ u32 reserved2 :1; -+ u32 scPad :1; -+ u32 extPad :1; -+ u32 hdrProc :1; -+ u32 digestLength :4; -+ u32 ivSource :2; -+ u32 hashSource :2; -+ u32 saveIv :1; -+ u32 saveHash :1; -+ u32 reserved1 :2; -+ } bits; -+} __packed; -+ -+union saCmd1 { -+ u32 word; -+ struct { -+ u32 copyDigest :1; -+ u32 copyHeader :1; -+ u32 copyPayload :1; -+ u32 copyPad :1; -+ u32 reserved4 :4; -+ u32 cipherMode :2; -+ u32 reserved3 :1; -+ u32 sslMac :1; -+ u32 hmac :1; -+ u32 byteOffset :1; -+ u32 reserved2 :2; -+ u32 hashCryptOffset :8; -+ u32 aesKeyLen :3; -+ u32 reserved1 :1; -+ u32 aesDecKey :1; -+ u32 seqNumCheck :1; -+ u32 reserved0 :2; -+ } bits; -+} __packed; -+ -+struct saRecord_s { -+ union saCmd0 saCmd0; -+ union saCmd1 saCmd1; -+ u32 saKey[8]; -+ u32 saIDigest[8]; -+ u32 saODigest[8]; -+ u32 saSpi; -+ u32 saSeqNum[2]; -+ u32 saSeqNumMask[2]; -+ u32 saNonce; -+} __packed; -+ -+struct saState_s { -+ u32 stateIv[4]; -+ u32 stateByteCnt[2]; -+ u32 stateIDigest[8]; -+} __packed; -+ -+union peCrtlStat_w { -+ u32 word; -+ struct { -+ u32 hostReady :1; -+ u32 peReady :1; -+ u32 reserved :1; -+ u32 initArc4 :1; -+ u32 hashFinal :1; -+ u32 haltMode :1; -+ u32 prngMode :2; -+ u32 padValue :8; -+ u32 errStatus :8; -+ u32 padCrtlStat :8; -+ } bits; -+} __packed; -+ -+union peLength_w { -+ u32 word; -+ struct { -+ u32 length :20; -+ u32 reserved :2; -+ u32 hostReady :1; -+ u32 peReady :1; -+ u32 byPass :8; -+ } bits; -+} __packed; -+ -+struct eip93_descriptor_s { -+ union peCrtlStat_w peCrtlStat; -+ u32 srcAddr; -+ u32 dstAddr; -+ u32 saAddr; -+ u32 stateAddr; -+ u32 arc4Addr; -+ u32 userId; -+ union peLength_w peLength; -+} __packed; -+ -+#endif ---- a/drivers/crypto/Kconfig -+++ b/drivers/crypto/Kconfig -@@ -824,4 +824,6 @@ config CRYPTO_DEV_SA2UL - source "drivers/crypto/keembay/Kconfig" - source "drivers/crypto/aspeed/Kconfig" - -+source "drivers/crypto/mtk-eip93/Kconfig" -+ - endif # CRYPTO_HW ---- a/drivers/crypto/Makefile -+++ b/drivers/crypto/Makefile -@@ -53,3 +53,4 @@ obj-y += xilinx/ - obj-y += hisilicon/ - obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/ - obj-y += keembay/ -+obj-$(CONFIG_CRYPTO_DEV_EIP93) += mtk-eip93/ diff --git a/target/linux/ramips/patches-6.6/314-MIPS-add-bootargs-override-property.patch b/target/linux/ramips/patches-6.6/314-MIPS-add-bootargs-override-property.patch index f9975986fe6c8c..ac3f3b7aba6436 100644 --- a/target/linux/ramips/patches-6.6/314-MIPS-add-bootargs-override-property.patch +++ b/target/linux/ramips/patches-6.6/314-MIPS-add-bootargs-override-property.patch @@ -17,7 +17,7 @@ Signed-off-by: David Bauer --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c -@@ -563,8 +563,28 @@ static int __init bootcmdline_scan_chose +@@ -564,8 +564,28 @@ static int __init bootcmdline_scan_chose #endif /* CONFIG_OF_EARLY_FLATTREE */ @@ -46,7 +46,7 @@ Signed-off-by: David Bauer bool dt_bootargs = false; /* -@@ -578,6 +598,14 @@ static void __init bootcmdline_init(void +@@ -579,6 +599,14 @@ static void __init bootcmdline_init(void } /* diff --git a/target/linux/ramips/patches-6.6/315-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-6.6/315-owrt-hack-fix-mt7688-cache-issue.patch index 04f0a67325d35a..2bb3d55d709213 100644 --- a/target/linux/ramips/patches-6.6/315-owrt-hack-fix-mt7688-cache-issue.patch +++ b/target/linux/ramips/patches-6.6/315-owrt-hack-fix-mt7688-cache-issue.patch @@ -10,7 +10,7 @@ Signed-off-by: John Crispin --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c -@@ -705,7 +705,6 @@ static void __init arch_mem_init(char ** +@@ -706,7 +706,6 @@ static void __init arch_mem_init(char ** mips_reserve_vmcore(); mips_parse_crashkernel(); @@ -18,7 +18,7 @@ Signed-off-by: John Crispin /* * In order to reduce the possibility of kernel panic when failed to -@@ -841,6 +840,7 @@ void __init setup_arch(char **cmdline_p) +@@ -842,6 +841,7 @@ void __init setup_arch(char **cmdline_p) cpu_cache_init(); paging_init(); diff --git a/target/linux/ramips/rt288x/config-6.1 b/target/linux/ramips/rt288x/config-6.1 deleted file mode 100644 index d8b89934b99e00..00000000000000 --- a/target/linux/ramips/rt288x/config-6.1 +++ /dev/null @@ -1,201 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CEVT_R4K=y -CONFIG_CLK_MTMIPS=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_INFO=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_RT2880_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_RALINK=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IP17XX_PHY=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_AUTO_PFN_OFFSET=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_L1_CACHE_SHIFT=4 -CONFIG_MIPS_L1_CACHE_SHIFT_4=y -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_LZMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_RT2880=y -CONFIG_NET_RALINK_RT2880=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NLS=m -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -# CONFIG_PHY_MT7621_PCI is not set -# CONFIG_PHY_RALINK_USB is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RALINK=y -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -CONFIG_SOC_RT288X=y -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB=m -CONFIG_USB_COMMON=m -CONFIG_USB_EHCI_HCD=m -CONFIG_USB_EHCI_HCD_PLATFORM=m -CONFIG_USB_OHCI_HCD=m -CONFIG_USB_OHCI_HCD_PLATFORM=m -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZBOOT_LOAD_ADDRESS=0x0 diff --git a/target/linux/ramips/rt305x/config-6.1 b/target/linux/ramips/rt305x/config-6.1 deleted file mode 100644 index 8b1b17033a911c..00000000000000 --- a/target/linux/ramips/rt305x/config-6.1 +++ /dev/null @@ -1,196 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_MTMIPS=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_RT305X_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_RALINK=y -CONFIG_GPIO_WATCHDOG=y -# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_JIMAGE_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_ESW_RT3050=y -CONFIG_NET_RALINK_RT3050=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -# CONFIG_PHY_MT7621_PCI is not set -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RALINK=y -CONFIG_PINCTRL_RT305X=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_RALINK=y -# CONFIG_RALINK_ILL_ACC is not set -CONFIG_RALINK_WDT=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -CONFIG_SOC_RT305X=y -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZBOOT_LOAD_ADDRESS=0x0 diff --git a/target/linux/ramips/rt3883/config-6.1 b/target/linux/ramips/rt3883/config-6.1 deleted file mode 100644 index 2aaebdc702f243..00000000000000 --- a/target/linux/ramips/rt3883/config-6.1 +++ /dev/null @@ -1,196 +0,0 @@ -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CEVT_R4K=y -CONFIG_CLK_MTMIPS=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_RT3883_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_RALINK=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_RT2880=y -CONFIG_NET_RALINK_RT3883=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_NVMEM_LAYOUTS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLIB_LEDS=y -# CONFIG_PHY_MT7621_PCI is not set -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RALINK=y -CONFIG_PINCTRL_RT3883=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTL8366_SMI=y -CONFIG_RTL8367B_PHY=y -CONFIG_RTL8367_PHY=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -CONFIG_SOC_RT3883=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZBOOT_LOAD_ADDRESS=0x0 diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index d6e97b91fac807..8729bd52f22600 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -23,6 +23,9 @@ rockchip_setup_interfaces() friendlyarm,nanopi-r5s) ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' ;; + sinovoip,rk3568-bpi-r2pro) + ucidef_set_interfaces_lan_wan 'lan0 lan1 lan2 lan3' 'eth0' + ;; *) ucidef_set_interface_lan 'eth0' ;; @@ -44,7 +47,8 @@ rockchip_setup_macs() ;; friendlyarm,nanopi-r2c-plus|\ friendlyarm,nanopi-r4s|\ - friendlyarm,nanopi-r5s) + friendlyarm,nanopi-r5s|\ + sinovoip,rk3568-bpi-r2pro) wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1) lan_mac=$(macaddr_add "$wan_mac" 1) ;; diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 5753d1e856023b..8bbce1c32857e4 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -44,7 +44,8 @@ friendlyarm,nanopi-r4s-enterprise) set_interface_core 20 "eth1" ;; friendlyarm,nanopi-r5c|\ -radxa,e25) +radxa,e25|\ +sinovoip,rk3568-bpi-r2pro) set_interface_core 2 "eth0" set_interface_core 4 "eth1" ;; diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1 index 1830a89c93a279..6337245ff8abe4 100644 --- a/target/linux/rockchip/armv8/config-6.1 +++ b/target/linux/rockchip/armv8/config-6.1 @@ -295,6 +295,8 @@ CONFIG_HUGETLB_PAGE=y CONFIG_HWMON=y CONFIG_HWSPINLOCK=y CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ROCKCHIP=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y @@ -363,6 +365,7 @@ CONFIG_MDIO_BUS_MUX_GPIO=y CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y +CONFIG_MEDIATEK_GE_PHY=y CONFIG_MEMFD_CREATE=y CONFIG_MEMORY_ISOLATION=y CONFIG_MFD_CORE=y @@ -399,9 +402,16 @@ CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_MT7530_MDIO=y +CONFIG_NET_DSA_MT7530_MMIO=y +CONFIG_NET_DSA_TAG_MTK=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NET_SELFTESTS=y +CONFIG_NET_SWITCHDEV=y CONFIG_NLS=y CONFIG_NLS_ISO8859_1=y CONFIG_NOP_USB_XCEIV=y @@ -456,6 +466,7 @@ CONFIG_PCI_DOMAINS_GENERIC=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_STUB=y +CONFIG_PCS_MTK_LYNXI=y CONFIG_PCS_XPCS=y CONFIG_PGTABLE_LEVELS=4 CONFIG_PHYLIB=y @@ -548,6 +559,7 @@ CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_HYM8563=y CONFIG_RTC_DRV_RK808=y CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTC_NVMEM=y diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index d457058282f786..df0ca6ffb58e6b 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -130,6 +130,15 @@ define Device/radxa_rock-pi-e endef TARGET_DEVICES += radxa_rock-pi-e +define Device/sinovoip_bpi-r2-pro + DEVICE_VENDOR := Sinovoip + DEVICE_MODEL := Bananapi-R2 Pro + SOC := rk3568 + SUPPORTED_DEVICES := sinovoip,rk3568-bpi-r2pro + DEVICE_PACKAGES := kmod-ata-ahci-dwc +endef +TARGET_DEVICES += sinovoip_bpi-r2-pro + define Device/xunlong_orangepi-r1-plus DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi R1 Plus diff --git a/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch new file mode 100644 index 00000000000000..9be609f6616aa0 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch @@ -0,0 +1,27 @@ +From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Wed, 14 Feb 2024 15:07:30 +1100 +Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board + +Adjust compatible string to match the board vendor of Sinovoip + +Signed-off-by: Tim Lunn +Reviewed-by: Dragan Simic +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -13,7 +13,7 @@ + + / { + model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; +- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; ++ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; diff --git a/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch b/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch new file mode 100644 index 00000000000000..6a5622b813ee57 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/031-v6.10arm64-dts-rockchip-set-PHY-address-of-MT7531-switch-.patch @@ -0,0 +1,40 @@ +From a2ac2a1b02590a22a236c43c455f421cdede45f5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Thu, 14 Mar 2024 15:24:35 +0300 +Subject: [PATCH] arm64: dts: rockchip: set PHY address of MT7531 switch to + 0x1f +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MT7531 switch listens on PHY address 0x1f on an MDIO bus. I've got two +findings that support this. There's no bootstrapping option to change the +PHY address of the switch. The Linux driver hardcodes 0x1f as the PHY +address of the switch. So the reg property on the device tree is currently +ignored by the Linux driver. + +Therefore, describe the correct PHY address on Banana Pi BPI-R2 Pro that +has this switch. + +Signed-off-by: Arınç ÜNAL +Fixes: c1804463e5c6 ("arm64: dts: rockchip: Add mt7531 dsa node to BPI-R2-Pro board") +Link: https://lore.kernel.org/r/20240314-for-rockchip-mt7531-phy-address-v1-1-743b5873358f@arinc9.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -521,9 +521,9 @@ + #address-cells = <1>; + #size-cells = <0>; + +- switch@0 { ++ switch@1f { + compatible = "mediatek,mt7531"; +- reg = <0>; ++ reg = <0x1f>; + + ports { + #address-cells = <1>; diff --git a/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch b/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch new file mode 100644 index 00000000000000..dca18f5c584e38 --- /dev/null +++ b/target/linux/rockchip/patches-6.1/032-v6.10-arm64-dts-rockchip-regulator-for-sd-needs-to-be-alwa.patch @@ -0,0 +1,33 @@ +From 433d54818f64a2fe0562f8c04c7a81f562368515 Mon Sep 17 00:00:00 2001 +From: Jose Ignacio Tornos Martinez +Date: Tue, 5 Mar 2024 15:32:18 +0100 +Subject: [PATCH] arm64: dts: rockchip: regulator for sd needs to be always on + for BPI-R2Pro + +With default dts configuration for BPI-R2Pro, the regulator for sd card is +powered off when reboot is commanded, and the only solution to detect the +sd card again, and therefore, allow rebooting from there, is to do a +hardware reset. + +Configure the regulator for sd to be always on for BPI-R2Pro in order to +avoid this issue. + +Fixes: f901aaadaa2a ("arm64: dts: rockchip: Add Bananapi R2 Pro") +Signed-off-by: Jose Ignacio Tornos Martinez +Link: https://lore.kernel.org/r/20240305143222.189413-1-jtornosm@redhat.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -412,6 +412,8 @@ + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + diff --git a/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch b/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch new file mode 100644 index 00000000000000..6a2d35889bb5bf --- /dev/null +++ b/target/linux/rockchip/patches-6.1/300-hwrng-add-Rockchip-SoC-hwrng-driver.patch @@ -0,0 +1,339 @@ +From patchwork Sat Nov 12 14:10:58 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Aurelien Jarno +X-Patchwork-Id: 13041222 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +From: Aurelien Jarno +To: Olivia Mackall , + Herbert Xu , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Lin Jinhan +Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR + CORE), + devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE + BINDINGS), + linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC + support), + linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), + linux-kernel@vger.kernel.org (open list), + Aurelien Jarno +Subject: [PATCH v1 2/3] hwrng: add Rockchip SoC hwrng driver +Date: Sat, 12 Nov 2022 15:10:58 +0100 +Message-Id: <20221112141059.3802506-3-aurelien@aurel32.net> +In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> +References: <20221112141059.3802506-1-aurelien@aurel32.net> +MIME-Version: 1.0 +List-Id: + +Rockchip SoCs used to have a random number generator as part of their +crypto device, and support for it has to be added to the corresponding +driver. However newer Rockchip SoCs like the RK356x have an independent +True Random Number Generator device. This patch adds a driver for it, +greatly inspired from the downstream driver. + +The TRNG device does not seem to have a signal conditionner and the FIPS +140-2 test returns a lot of failures. They can be reduced by increasing +RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value +has been adjusted to get ~90% of successes and the quality value has +been set accordingly. + +Signed-off-by: Aurelien Jarno +--- + drivers/char/hw_random/Kconfig | 14 ++ + drivers/char/hw_random/Makefile | 1 + + drivers/char/hw_random/rockchip-rng.c | 251 ++++++++++++++++++++++++++ + 3 files changed, 266 insertions(+) + create mode 100644 drivers/char/hw_random/rockchip-rng.c + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -549,6 +549,20 @@ config HW_RANDOM_CN10K + To compile this driver as a module, choose M here. + The module will be called cn10k_rng. If unsure, say Y. + ++config HW_RANDOM_ROCKCHIP ++ tristate "Rockchip True Random Number Generator" ++ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST) ++ depends on HAS_IOMEM ++ default HW_RANDOM ++ help ++ This driver provides kernel-side support for the True Random Number ++ Generator hardware found on some Rockchip SoC like RK3566 or RK3568. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called rockchip-rng. ++ ++ If unsure, say Y. ++ + endif # HW_RANDOM + + config UML_RANDOM +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -47,3 +47,4 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe + obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o + obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o + obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o ++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o +--- /dev/null ++++ b/drivers/char/hw_random/rockchip-rng.c +@@ -0,0 +1,251 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs ++ * ++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2022, Aurelien Jarno ++ * Authors: ++ * Lin Jinhan ++ * Aurelien Jarno ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RK_RNG_AUTOSUSPEND_DELAY 100 ++#define RK_RNG_MAX_BYTE 32 ++#define RK_RNG_POLL_PERIOD_US 100 ++#define RK_RNG_POLL_TIMEOUT_US 10000 ++ ++/* ++ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is ++ * a tradeoff between speed and quality and has been adjusted to get a quality ++ * of ~900 (~90% of FIPS 140-2 successes). ++ */ ++#define RK_RNG_SAMPLE_CNT 1000 ++ ++/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */ ++#define TRNG_RST_CTL 0x0004 ++#define TRNG_RNG_CTL 0x0400 ++#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4) ++#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4) ++#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4) ++#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2) ++#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2) ++#define TRNG_RNG_CTL_ENABLE BIT(1) ++#define TRNG_RNG_CTL_START BIT(0) ++#define TRNG_RNG_SAMPLE_CNT 0x0404 ++#define TRNG_RNG_DOUT_0 0x0410 ++#define TRNG_RNG_DOUT_1 0x0414 ++#define TRNG_RNG_DOUT_2 0x0418 ++#define TRNG_RNG_DOUT_3 0x041c ++#define TRNG_RNG_DOUT_4 0x0420 ++#define TRNG_RNG_DOUT_5 0x0424 ++#define TRNG_RNG_DOUT_6 0x0428 ++#define TRNG_RNG_DOUT_7 0x042c ++ ++struct rk_rng { ++ struct hwrng rng; ++ void __iomem *base; ++ struct reset_control *rst; ++ int clk_num; ++ struct clk_bulk_data *clk_bulks; ++}; ++ ++/* The mask determine the bits that are updated */ ++static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask) ++{ ++ writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL); ++} ++ ++static int rk_rng_init(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ int ret; ++ ++ /* start clocks */ ++ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); ++ if (ret < 0) { ++ dev_err((struct device *) rk_rng->rng.priv, ++ "Failed to enable clks %d\n", ret); ++ return ret; ++ } ++ ++ /* set the sample period */ ++ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); ++ ++ /* set osc ring speed and enable it */ ++ reg = TRNG_RNG_CTL_LEN_256_BIT | ++ TRNG_RNG_CTL_OSC_RING_SPEED_0 | ++ TRNG_RNG_CTL_ENABLE; ++ rk_rng_write_ctl(rk_rng, reg, 0xffff); ++ ++ return 0; ++} ++ ++static void rk_rng_cleanup(struct hwrng *rng) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ ++ /* stop TRNG */ ++ reg = 0; ++ rk_rng_write_ctl(rk_rng, reg, 0xffff); ++ ++ /* stop clocks */ ++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); ++} ++ ++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) ++{ ++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); ++ u32 reg; ++ int ret = 0; ++ int i; ++ ++ pm_runtime_get_sync((struct device *) rk_rng->rng.priv); ++ ++ /* Start collecting random data */ ++ reg = TRNG_RNG_CTL_START; ++ rk_rng_write_ctl(rk_rng, reg, reg); ++ ++ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg, ++ !(reg & TRNG_RNG_CTL_START), ++ RK_RNG_POLL_PERIOD_US, ++ RK_RNG_POLL_TIMEOUT_US); ++ if (ret < 0) ++ goto out; ++ ++ /* Read random data stored in big endian in the registers */ ++ ret = min_t(size_t, max, RK_RNG_MAX_BYTE); ++ for (i = 0; i < ret; i += 4) { ++ reg = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i); ++ *(u32 *)(buf + i) = be32_to_cpu(reg); ++ } ++ ++out: ++ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); ++ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); ++ ++ return ret; ++} ++ ++static int rk_rng_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rk_rng *rk_rng; ++ int ret; ++ ++ rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL); ++ if (!rk_rng) ++ return -ENOMEM; ++ ++ rk_rng->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(rk_rng->base)) ++ return PTR_ERR(rk_rng->base); ++ ++ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks); ++ if (rk_rng->clk_num < 0) ++ return dev_err_probe(dev, rk_rng->clk_num, ++ "Failed to get clks property\n"); ++ ++ rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false); ++ if (IS_ERR(rk_rng->rst)) ++ return dev_err_probe(dev, PTR_ERR(rk_rng->rst), ++ "Failed to get reset property\n"); ++ ++ reset_control_assert(rk_rng->rst); ++ udelay(2); ++ reset_control_deassert(rk_rng->rst); ++ ++ platform_set_drvdata(pdev, rk_rng); ++ ++ rk_rng->rng.name = dev_driver_string(dev); ++#ifndef CONFIG_PM ++ rk_rng->rng.init = rk_rng_init; ++ rk_rng->rng.cleanup = rk_rng_cleanup; ++#endif ++ rk_rng->rng.read = rk_rng_read; ++ rk_rng->rng.priv = (unsigned long) dev; ++ rk_rng->rng.quality = 900; ++ ++ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); ++ pm_runtime_use_autosuspend(dev); ++ pm_runtime_enable(dev); ++ ++ ret = devm_hwrng_register(dev, &rk_rng->rng); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); ++ ++ dev_info(&pdev->dev, "Registered Rockchip hwrng\n"); ++ ++ return 0; ++} ++ ++static int rk_rng_remove(struct platform_device *pdev) ++{ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int rk_rng_runtime_suspend(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ rk_rng_cleanup(&rk_rng->rng); ++ ++ return 0; ++} ++ ++static int rk_rng_runtime_resume(struct device *dev) ++{ ++ struct rk_rng *rk_rng = dev_get_drvdata(dev); ++ ++ return rk_rng_init(&rk_rng->rng); ++} ++#endif ++ ++static const struct dev_pm_ops rk_rng_pm_ops = { ++ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, ++ rk_rng_runtime_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++}; ++ ++static const struct of_device_id rk_rng_dt_match[] = { ++ { ++ .compatible = "rockchip,rk3568-rng", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, rk_rng_dt_match); ++ ++static struct platform_driver rk_rng_driver = { ++ .driver = { ++ .name = "rockchip-rng", ++ .pm = &rk_rng_pm_ops, ++ .of_match_table = rk_rng_dt_match, ++ }, ++ .probe = rk_rng_probe, ++ .remove = rk_rng_remove, ++}; ++ ++module_platform_driver(rk_rng_driver); ++ ++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver"); ++MODULE_AUTHOR("Lin Jinhan , Aurelien Jarno "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch b/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch new file mode 100644 index 00000000000000..bb34ba76e01c9d --- /dev/null +++ b/target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch @@ -0,0 +1,56 @@ +From patchwork Sat Nov 12 14:10:59 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Aurelien Jarno +X-Patchwork-Id: 13041221 +From: Aurelien Jarno +To: Olivia Mackall , + Herbert Xu , + Rob Herring , + Krzysztof Kozlowski , + Heiko Stuebner , + Philipp Zabel , + Lin Jinhan +Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR + CORE), + devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE + BINDINGS), + linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC + support), + linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), + linux-kernel@vger.kernel.org (open list), + Aurelien Jarno +Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x +Date: Sat, 12 Nov 2022 15:10:59 +0100 +Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net> +In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net> +References: <20221112141059.3802506-1-aurelien@aurel32.net> +MIME-Version: 1.0 +List-Id: + +Enable the just added Rockchip RNG driver for RK356x SoCs. + +Signed-off-by: Aurelien Jarno +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1773,6 +1773,15 @@ + }; + }; + ++ rng: rng@fe388000 { ++ compatible = "rockchip,rk3568-rng"; ++ reg = <0x0 0xfe388000 0x0 0x4000>; ++ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; ++ clock-names = "trng_clk", "trng_hclk"; ++ resets = <&cru SRST_TRNG_NS>; ++ reset-names = "reset"; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; diff --git a/target/linux/sifiveu/Makefile b/target/linux/sifiveu/Makefile index 3a003a35fcd555..2e2ea96b4bfaaa 100644 --- a/target/linux/sifiveu/Makefile +++ b/target/linux/sifiveu/Makefile @@ -11,8 +11,7 @@ FEATURES:=ext4 KERNELNAME:=Image dtbs SUBTARGETS:=generic -KERNEL_PATCHVER:=6.1 -KERNEL_TESTING_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.6 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/sifiveu/config-6.1 b/target/linux/sifiveu/config-6.1 deleted file mode 100644 index 98283f4e0d8233..00000000000000 --- a/target/linux/sifiveu/config-6.1 +++ /dev/null @@ -1,392 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_CLOCKSOURCE_INIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_RV64I=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ASN1=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_ATA=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CAVIUM_PTP=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y -CONFIG_CLK_SIFIVE=y -CONFIG_CLK_SIFIVE_PRCI=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_CMODEL_MEDANY=y -# CONFIG_CMODEL_MEDLOW is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_COMPAT_BRK=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC7=y -CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EDAC=y -# CONFIG_EDAC_DEBUG is not set -CONFIG_EDAC_LEGACY_SYSFS=y -CONFIG_EDAC_SIFIVE=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EFI=y -CONFIG_EFIVAR_FS=m -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_COCO_SECRET is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# CONFIG_EFI_DISABLE_RUNTIME is not set -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_ESRT=y -CONFIG_EFI_GENERIC_STUB=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_STUB=y -# CONFIG_EFI_TEST is not set -# CONFIG_EFI_ZBOOT is not set -CONFIG_ELF_CORE=y -CONFIG_ERRATA_SIFIVE=y -CONFIG_ERRATA_SIFIVE_CIP_1200=y -CONFIG_ERRATA_SIFIVE_CIP_453=y -# CONFIG_ERRATA_THEAD is not set -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_FAILOVER=y -CONFIG_FAT_FS=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_AUTOSELECT=y -CONFIG_FONT_SUPPORT=y -CONFIG_FPU=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_INJECTION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_CDEV_V1=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_SIFIVE=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_CPCI is not set -CONFIG_HOTPLUG_PCI_PCIE=y -CONFIG_HOTPLUG_PCI_SHPC=y -CONFIG_HVC_DRIVER=y -CONFIG_HVC_RISCV_SBI=y -CONFIG_HW_CONSOLE=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_OCORES=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KEYS=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_MACB=y -# CONFIG_MACB_PCI is not set -CONFIG_MACB_USE_HWSTAMP=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MICROSEMI_PHY=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_CADENCE=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SPI=y -CONFIG_MMIOWB=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MODULE_SECTIONS=y -CONFIG_MPILIB=y -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FAILOVER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_NONPORTABLE is not set -CONFIG_NR_CPUS=8 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DMA_DEFAULT_COHERENT=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OID_REGISTRY=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xff60000000000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_REPORTING=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEAER_INJECT=m -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DPC=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_ECRC=y -CONFIG_PCIE_FU740=y -CONFIG_PCIE_PTM=y -CONFIG_PCIE_XILINX=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_ECAM=y -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_SW_SWITCHTEC=y -CONFIG_PGTABLE_LEVELS=5 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PORTABLE=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_RESTART=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_PPS=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_SIFIVE=y -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RCU_TRACE=y -CONFIG_RD_GZIP=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -# CONFIG_RESET_ATTACK_MITIGATION is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SIMPLE=y -CONFIG_RFS_ACCEL=y -CONFIG_RISCV=y -CONFIG_RISCV_ALTERNATIVE=y -# CONFIG_RISCV_BOOT_SPINWAIT is not set -CONFIG_RISCV_DMA_NONCOHERENT=y -CONFIG_RISCV_INTC=y -CONFIG_RISCV_ISA_C=y -CONFIG_RISCV_ISA_SVPBMT=y -CONFIG_RISCV_ISA_ZICBOM=y -CONFIG_RISCV_SBI=y -CONFIG_RISCV_SBI_V01=y -CONFIG_RISCV_TIMER=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_EFI is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_DEBUG=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_EARLYCON_RISCV_SBI=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_SIFIVE=y -CONFIG_SERIAL_SIFIVE_CONSOLE=y -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SIFIVE_CCACHE=y -CONFIG_SIFIVE_PLIC=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -# CONFIG_SOC_MICROCHIP_POLARFIRE is not set -CONFIG_SOC_SIFIVE=y -# CONFIG_SOC_STARFIVE is not set -# CONFIG_SOC_VIRT is not set -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_SIFIVE=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_SYSFB_SIMPLEFB is not set -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOOLCHAIN_HAS_ZICBOM=y -CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y -CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y -CONFIG_TRACE_CLOCK=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TUNE_GENERIC=y -CONFIG_UCS2_STRING=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_EHCI_PCI=y -CONFIG_USB_HID=y -CONFIG_USB_NET_DRIVERS=y -CONFIG_USB_PCI=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_VFAT_FS=y -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch b/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch deleted file mode 100644 index 9a1c96813907bf..00000000000000 --- a/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch +++ /dev/null @@ -1,49 +0,0 @@ -From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Wed, 17 Feb 2021 06:06:14 -0800 -Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to - sifive,u74-mc - -Signed-off-by: David Abdurachmanov ---- - arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi -+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi -@@ -39,7 +39,7 @@ - }; - }; - cpu1: cpu@1 { -- compatible = "sifive,bullet0", "riscv"; -+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; -@@ -63,7 +63,7 @@ - }; - }; - cpu2: cpu@2 { -- compatible = "sifive,bullet0", "riscv"; -+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; -@@ -87,7 +87,7 @@ - }; - }; - cpu3: cpu@3 { -- compatible = "sifive,bullet0", "riscv"; -+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; -@@ -111,7 +111,7 @@ - }; - }; - cpu4: cpu@4 { -- compatible = "sifive,bullet0", "riscv"; -+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; diff --git a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch b/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch deleted file mode 100644 index 07170d7c769fcf..00000000000000 --- a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Mon, 13 Sep 2021 02:18:30 -0700 -Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node - -Add gpio-poweroff node to allow powering off the system. - -Signed-off-by: David Abdurachmanov ---- - arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -86,6 +86,11 @@ - }; - }; - }; -+ -+ gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>; -+ }; - }; - - &uart0 { diff --git a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch b/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch deleted file mode 100644 index c4242c6f07d804..00000000000000 --- a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch +++ /dev/null @@ -1,116 +0,0 @@ -From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Fri, 14 May 2021 05:27:51 -0700 -Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq) - -Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4 - -Signed-off-by: David Abdurachmanov ---- - arch/riscv/Kconfig | 8 +++++ - arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++ - .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++ - 3 files changed, 47 insertions(+) - ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -711,6 +711,14 @@ config PORTABLE - select OF - select MMU - -+menu "CPU Power Management" -+ -+source "drivers/cpuidle/Kconfig" -+ -+source "drivers/cpufreq/Kconfig" -+ -+endmenu -+ - menu "Power management options" - - source "kernel/power/Kconfig" ---- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi -+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi -@@ -30,6 +30,7 @@ - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; -@@ -54,6 +55,7 @@ - reg = <1>; - riscv,isa = "rv64imafdc"; - tlb-split; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - next-level-cache = <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; -@@ -78,6 +80,7 @@ - reg = <2>; - riscv,isa = "rv64imafdc"; - tlb-split; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - next-level-cache = <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; -@@ -102,6 +105,7 @@ - reg = <3>; - riscv,isa = "rv64imafdc"; - tlb-split; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - next-level-cache = <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; -@@ -126,6 +130,7 @@ - reg = <4>; - riscv,isa = "rv64imafdc"; - tlb-split; -+ clocks = <&prci FU540_PRCI_CLK_COREPLL>; - next-level-cache = <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; ---- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts -@@ -80,6 +80,40 @@ - label = "d4"; - }; - }; -+ -+ fu540_c000_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-350000000 { -+ opp-hz = /bits/ 64 <350000000>; -+ }; -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ }; -+ opp-999999999 { -+ opp-hz = /bits/ 64 <999999999>; -+ }; -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ }; -+ }; -+}; -+ -+&cpu0 { -+ operating-points-v2 = <&fu540_c000_opp_table>; -+}; -+&cpu1 { -+ operating-points-v2 = <&fu540_c000_opp_table>; -+}; -+&cpu2 { -+ operating-points-v2 = <&fu540_c000_opp_table>; -+}; -+&cpu3 { -+ operating-points-v2 = <&fu540_c000_opp_table>; -+}; -+&cpu4 { -+ operating-points-v2 = <&fu540_c000_opp_table>; - }; - - &uart0 { diff --git a/target/linux/sunxi/Makefile b/target/linux/sunxi/Makefile index 3982b763fb1be0..d91e5c5a3e6756 100644 --- a/target/linux/sunxi/Makefile +++ b/target/linux/sunxi/Makefile @@ -10,8 +10,7 @@ BOARDNAME:=Allwinner ARM SoCs FEATURES:=usb ext4 display rootfs-part rtc squashfs SUBTARGETS:=cortexa8 cortexa7 cortexa53 -KERNEL_PATCHVER:=6.1 -KERNEL_TESTING_PATCHVER:=6.6 +KERNEL_PATCHVER:=6.6 KERNELNAME:=zImage dtbs diff --git a/target/linux/sunxi/config-6.1 b/target/linux/sunxi/config-6.1 deleted file mode 100644 index a76834c13a9978..00000000000000 --- a/target/linux/sunxi/config-6.1 +++ /dev/null @@ -1,524 +0,0 @@ -# CONFIG_AHCI_SUNXI is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=416 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUNXI=y -CONFIG_ARCH_SUNXI_MC_SMP=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -CONFIG_ARM_CCI=y -CONFIG_ARM_CCI400_COMMON=y -CONFIG_ARM_CCI400_PORT_CTRL=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_ERRATA_643719=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_LPAE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PSCI=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_AXP20X_POWER=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -CONFIG_CACHE_L2X0=y -CONFIG_CAN=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_SUNXI=y -CONFIG_CLK_SUNXI_CLOCKS=y -CONFIG_CLK_SUNXI_PRCM_SUN6I=y -CONFIG_CLK_SUNXI_PRCM_SUN8I=y -CONFIG_CLK_SUNXI_PRCM_SUN9I=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONNECTOR=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_ALLWINNER=y -CONFIG_CRYPTO_DEV_SUN4I_SS=y -# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set -CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y -# CONFIG_CRYPTO_DEV_SUN8I_CE is not set -# CONFIG_CRYPTO_DEV_SUN8I_SS is not set -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA1=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SUN4I=y -CONFIG_DMA_SUN6I=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DVB_CORE=y -CONFIG_DWMAC_GENERIC=y -# CONFIG_DWMAC_SUN8I is not set -CONFIG_DWMAC_SUNXI=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ELF_CORE=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FAT_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_FOREIGN_ENDIAN=y -CONFIG_FB_LITTLE_ENDIAN=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_SIMPLE=y -CONFIG_FB_TILEBLITTING=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_WARN=2048 -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_TIMERIOMEM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_MV64XXX=y -CONFIG_I2C_SUN6I_P2WI=y -CONFIG_IIO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_AXP20X_PEK=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KEYBOARD_SUN4I_LRADC=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_KSM=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_MACH_SUN4I=y -CONFIG_MACH_SUN5I=y -CONFIG_MACH_SUN6I=y -CONFIG_MACH_SUN7I=y -CONFIG_MACH_SUN8I=y -CONFIG_MACH_SUN9I=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_SUN4I=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_TEST_SUPPORT=y -CONFIG_MEDIA_TUNER=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_AXP20X=y -CONFIG_MFD_AXP20X_I2C=y -CONFIG_MFD_AXP20X_RSB=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SUN6I_PRCM=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SUNXI=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_VENDOR_ALLWINNER=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=8 -CONFIG_NVMEM=y -CONFIG_NVMEM_SUNXI_SID=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PCS_XPCS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_SUN4I_USB=y -# CONFIG_PHY_SUN50I_USB3 is not set -# CONFIG_PHY_SUN6I_MIPI_DPHY is not set -CONFIG_PHY_SUN9I_USB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AXP209=y -# CONFIG_PINCTRL_SUN20I_D1 is not set -CONFIG_PINCTRL_SUN4I_A10=y -# CONFIG_PINCTRL_SUN50I_A100 is not set -# CONFIG_PINCTRL_SUN50I_A100_R is not set -# CONFIG_PINCTRL_SUN50I_A64 is not set -# CONFIG_PINCTRL_SUN50I_A64_R is not set -# CONFIG_PINCTRL_SUN50I_H5 is not set -# CONFIG_PINCTRL_SUN50I_H6 is not set -# CONFIG_PINCTRL_SUN50I_H616 is not set -# CONFIG_PINCTRL_SUN50I_H616_R is not set -# CONFIG_PINCTRL_SUN50I_H6_R is not set -CONFIG_PINCTRL_SUN5I=y -CONFIG_PINCTRL_SUN6I_A31=y -CONFIG_PINCTRL_SUN6I_A31_R=y -CONFIG_PINCTRL_SUN8I_A23=y -CONFIG_PINCTRL_SUN8I_A23_R=y -CONFIG_PINCTRL_SUN8I_A33=y -CONFIG_PINCTRL_SUN8I_A83T=y -CONFIG_PINCTRL_SUN8I_A83T_R=y -CONFIG_PINCTRL_SUN8I_H3=y -CONFIG_PINCTRL_SUN8I_H3_R=y -CONFIG_PINCTRL_SUN8I_V3S=y -CONFIG_PINCTRL_SUN9I_A80=y -CONFIG_PINCTRL_SUN9I_A80_R=y -CONFIG_PINCTRL_SUNXI=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PROC_EVENTS=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_SUN4I=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_SY8106A=y -CONFIG_RELAY=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SIMPLE=y -CONFIG_RESET_SUNXI=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SATA_HOST=y -CONFIG_SATA_PMP=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SDIO_UART=y -CONFIG_SECURITYFS=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=8 -CONFIG_SERIAL_8250_RUNTIME_UARTS=8 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SND=y -CONFIG_SND_COMPRESS_OFFLOAD=y -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -CONFIG_SND_PCM=y -CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_SIMPLE_CARD_UTILS=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SUN4I_I2S is not set -# CONFIG_SND_SUN4I_SPDIF is not set -# CONFIG_SND_SUN50I_DMIC is not set -# CONFIG_SND_SUN8I_CODEC is not set -# CONFIG_SND_SUN8I_CODEC_ANALOG is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_SUN4I=y -CONFIG_SPI_SUN6I=y -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -CONFIG_SUN4I_A10_CCU=y -# CONFIG_SUN4I_EMAC is not set -CONFIG_SUN4I_TIMER=y -CONFIG_SUN5I_CCU=y -CONFIG_SUN5I_HSTIMER=y -CONFIG_SUN6I_A31_CCU=y -# CONFIG_SUN6I_RTC_CCU is not set -CONFIG_SUN8I_A23_CCU=y -CONFIG_SUN8I_A33_CCU=y -CONFIG_SUN8I_A83T_CCU=y -CONFIG_SUN8I_DE2_CCU=y -CONFIG_SUN8I_H3_CCU=y -CONFIG_SUN8I_R40_CCU=y -CONFIG_SUN8I_R_CCU=y -CONFIG_SUN8I_THERMAL=y -CONFIG_SUN8I_V3S_CCU=y -CONFIG_SUN9I_A80_CCU=y -CONFIG_SUNXI_CCU=y -CONFIG_SUNXI_MBUS=y -CONFIG_SUNXI_RSB=y -CONFIG_SUNXI_SRAM=y -CONFIG_SUNXI_WATCHDOG=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TOUCHSCREEN_SUN4I=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC2=y -CONFIG_USB_DWC2_HOST=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_GADGET=y -CONFIG_USB_NET_DRIVERS=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USERIO=y -CONFIG_USE_OF=y -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VHOST=y -CONFIG_VHOST_IOTLB=y -CONFIG_VHOST_NET=y -# CONFIG_VIDEO_SUN4I_CSI is not set -# CONFIG_VIDEO_SUN6I_CSI is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/sunxi/cortexa53/config-6.1 b/target/linux/sunxi/cortexa53/config-6.1 deleted file mode 100644 index 55bcd4e8e544c5..00000000000000 --- a/target/linux/sunxi/cortexa53/config-6.1 +++ /dev/null @@ -1,109 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_2051678=y -CONFIG_ARM64_ERRATUM_2077057=y -CONFIG_ARM64_ERRATUM_2658417=y -CONFIG_ARM64_ERRATUM_2054223=y -CONFIG_ARM64_ERRATUM_2067961=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SIMD=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DWMAC_SUN8I=y -CONFIG_EEPROM_AT24=y -CONFIG_FRAME_POINTER=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_MDIO_BUS_MUX=y -CONFIG_MICREL_PHY=y -# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MOTORCOMM_PHY=y -CONFIG_MUSB_PIO_ONLY=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_IOPORT_MAP=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PHY_SUN50I_USB3=y -CONFIG_PINCTRL_SUN50I_A100=y -CONFIG_PINCTRL_SUN50I_A100_R=y -CONFIG_PINCTRL_SUN50I_A64=y -CONFIG_PINCTRL_SUN50I_A64_R=y -CONFIG_PINCTRL_SUN50I_H5=y -CONFIG_PINCTRL_SUN50I_H6=y -CONFIG_PINCTRL_SUN50I_H6_R=y -CONFIG_PINCTRL_SUN50I_H616=y -CONFIG_PINCTRL_SUN50I_H616_R=y -# CONFIG_PREEMPT_DYNAMIC is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -# CONFIG_SCHED_CLUSTER is not set -# CONFIG_SHADOW_CALL_STACK is not set -# CONFIG_SND_SUN50I_CODEC_ANALOG is not set -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SUN50I_A100_CCU=y -CONFIG_SUN50I_A100_R_CCU=y -CONFIG_SUN50I_A64_CCU=y -CONFIG_SUN50I_DE2_BUS=y -CONFIG_SUN50I_ERRATUM_UNKNOWN1=y -CONFIG_SUN50I_H616_CCU=y -CONFIG_SUN50I_H6_CCU=y -CONFIG_SUN50I_H6_R_CCU=y -# CONFIG_SUN6I_RTC_CCU is not set -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB_MUSB_DUAL_ROLE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_PHY=y -CONFIG_VMAP_STACK=y -CONFIG_ZONE_DMA32=y -CONFIG_SURFACE_PLATFORMS=y -# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set -# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set -# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set -# CONFIG_PAGE_TABLE_CHECK is not set -CONFIG_RANDOMIZE_KSTACK_OFFSET=y -# CONFIG_ARCH_NXP is not set diff --git a/target/linux/sunxi/cortexa7/config-6.1 b/target/linux/sunxi/cortexa7/config-6.1 deleted file mode 100644 index eaa6b037bed927..00000000000000 --- a/target/linux/sunxi/cortexa7/config-6.1 +++ /dev/null @@ -1,26 +0,0 @@ -CONFIG_B53=y -CONFIG_B53_MDIO_DRIVER=y -CONFIG_CRYPTO_BLAKE2S_ARM=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_DWMAC_SUN8I=y -CONFIG_GRO_CELLS=y -# CONFIG_HARDEN_BRANCH_HISTORY is not set -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -# CONFIG_MACH_SUN4I is not set -# CONFIG_MACH_SUN5I is not set -CONFIG_MDIO_BUS_MUX=y -CONFIG_MICREL_PHY=y -CONFIG_MUSB_PIO_ONLY=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_TAG_BRCM=y -CONFIG_NET_DSA_TAG_BRCM_COMMON=y -CONFIG_NET_DSA_TAG_BRCM_LEGACY=y -CONFIG_NET_DSA_TAG_BRCM_PREPEND=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_RTC_DRV_SUN6I=y -CONFIG_USB_MUSB_DUAL_ROLE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_PHY=y diff --git a/target/linux/sunxi/cortexa8/config-6.1 b/target/linux/sunxi/cortexa8/config-6.1 deleted file mode 100644 index b893b3142e0e11..00000000000000 --- a/target/linux/sunxi/cortexa8/config-6.1 +++ /dev/null @@ -1,12 +0,0 @@ -# CONFIG_ARM_LPAE is not set -CONFIG_CRYPTO_BLAKE2S_ARM=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -# CONFIG_MACH_SUN6I is not set -# CONFIG_MACH_SUN7I is not set -# CONFIG_MACH_SUN8I is not set -# CONFIG_MACH_SUN9I is not set -CONFIG_PGTABLE_LEVELS=2 -# CONFIG_PHY_SUN9I_USB is not set -# CONFIG_SPI_SUN6I is not set -# CONFIG_SUN8I_A83T_CCU is not set -# CONFIG_SUN8I_THERMAL is not set diff --git a/target/linux/sunxi/image/Makefile b/target/linux/sunxi/image/Makefile index fc1359d173cf12..ee36df598af965 100644 --- a/target/linux/sunxi/image/Makefile +++ b/target/linux/sunxi/image/Makefile @@ -34,9 +34,7 @@ define Device/Default KERNEL := kernel-bin | uImage none IMAGES := sdcard.img.gz IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip -ifdef CONFIG_LINUX_6_6 SUNXI_DTS_DIR :=allwinner/ -endif SUNXI_DTS = $$(SUNXI_DTS_DIR)$$(SOC)-$(lastword $(subst _, ,$(1))) endef diff --git a/target/linux/sunxi/image/cortexa7.mk b/target/linux/sunxi/image/cortexa7.mk index a85b20531d3af1..e2d83fa94f24b9 100644 --- a/target/linux/sunxi/image/cortexa7.mk +++ b/target/linux/sunxi/image/cortexa7.mk @@ -112,6 +112,14 @@ define Device/lemaker_bananapro endef TARGET_DEVICES += lemaker_bananapro +define Device/licheepi_licheepi-zero-dock + DEVICE_VENDOR := LicheePi + DEVICE_MODEL := Zero with Dock (V3s) + DEVICE_PACKAGES:=kmod-rtc-sunxi + SOC := sun8i-v3s +endef +TARGET_DEVICES += licheepi_licheepi-zero-dock + define Device/linksprite_pcduino3 DEVICE_VENDOR := LinkSprite DEVICE_MODEL := pcDuino3 diff --git a/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch b/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch deleted file mode 100644 index c24d479534d38c..00000000000000 --- a/target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 28a1a6474c5053bae01bd29946b4d5ede539176b Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 31 Oct 2022 11:13:52 +0000 -Subject: [PATCH] dt-bindings: usb: Add H616 compatible string - -The Allwinner H616 contains four fully OHCI/EHCI compatible USB host -controllers, so just add their compatible strings to the list of -generic OHCI/EHCI controllers. - -Signed-off-by: Andre Przywara -Acked-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20221031111358.3387297-2-andre.przywara@arm.com -Signed-off-by: Jernej Skrabec ---- - Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + - Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + - 2 files changed, 2 insertions(+) - ---- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml -+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml -@@ -30,6 +30,7 @@ properties: - - allwinner,sun4i-a10-ehci - - allwinner,sun50i-a64-ehci - - allwinner,sun50i-h6-ehci -+ - allwinner,sun50i-h616-ehci - - allwinner,sun5i-a13-ehci - - allwinner,sun6i-a31-ehci - - allwinner,sun7i-a20-ehci ---- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml -+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml -@@ -20,6 +20,7 @@ properties: - - allwinner,sun4i-a10-ohci - - allwinner,sun50i-a64-ohci - - allwinner,sun50i-h6-ohci -+ - allwinner,sun50i-h616-ohci - - allwinner,sun5i-a13-ohci - - allwinner,sun6i-a31-ohci - - allwinner,sun7i-a20-ohci diff --git a/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch b/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch deleted file mode 100644 index 5739172ceb5c32..00000000000000 --- a/target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 6964affe65066651eca21e97247d3b7cac5153dc Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 31 Oct 2022 11:13:53 +0000 -Subject: [PATCH] dt-bindings: phy: Add special clock for Allwinner H616 PHY - -The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves -some resources from port 2's PHY and HCI IP. In particular the PMU clock -for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL -register of port 2. To allow each USB port to be controlled -independently of port 2, we need a handle to that particular PMU clock -in the *PHY* node, as the HCI and PHY part might be handled by separate -drivers. - -Add that clock to the requirements of the H616 PHY binding, so that a -PHY driver can apply the quirk in isolation, without requiring help from -port 2's HCI driver. - -Signed-off-by: Andre Przywara -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20221031111358.3387297-3-andre.przywara@arm.com -Signed-off-by: Vinod Koul ---- - .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml -@@ -36,18 +36,22 @@ properties: - - const: pmu3 - - clocks: -+ minItems: 4 - items: - - description: USB OTG PHY bus clock - - description: USB Host 0 PHY bus clock - - description: USB Host 1 PHY bus clock - - description: USB Host 2 PHY bus clock -+ - description: PMU clock for host port 2 - - clock-names: -+ minItems: 4 - items: - - const: usb0_phy - - const: usb1_phy - - const: usb2_phy - - const: usb3_phy -+ - const: pmu2_clk - - resets: - items: -@@ -96,6 +100,28 @@ required: - - resets - - reset-names - -+allOf: -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - allwinner,sun50i-h616-usb-phy -+ then: -+ properties: -+ clocks: -+ minItems: 5 -+ -+ clock-names: -+ minItems: 5 -+ else: -+ properties: -+ clocks: -+ maxItems: 4 -+ -+ clock-names: -+ maxItems: 4 -+ - additionalProperties: false - - examples: diff --git a/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch b/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch deleted file mode 100644 index 6dc1cf2f36be2f..00000000000000 --- a/target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch +++ /dev/null @@ -1,188 +0,0 @@ -From f40cf244c3feb4e1a442f8029b691add2c65b3ab Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 31 Oct 2022 11:13:56 +0000 -Subject: [PATCH] arm64: dts: allwinner: h616: Add USB nodes - -Add the nodes for the MUSB and the four USB host controllers to the SoC -.dtsi, along with the PHY node needed to bind all of them together. - -EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires -some quirks (handled in the driver). - -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20221031111358.3387297-6-andre.przywara@arm.com -Signed-off-by: Jernej Skrabec ---- - .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++ - 1 file changed, 160 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -504,6 +504,166 @@ - }; - }; - -+ usbotg: usb@5100000 { -+ compatible = "allwinner,sun50i-h616-musb", -+ "allwinner,sun8i-h3-musb"; -+ reg = <0x05100000 0x0400>; -+ clocks = <&ccu CLK_BUS_OTG>; -+ resets = <&ccu RST_BUS_OTG>; -+ interrupts = ; -+ interrupt-names = "mc"; -+ phys = <&usbphy 0>; -+ phy-names = "usb"; -+ extcon = <&usbphy 0>; -+ status = "disabled"; -+ }; -+ -+ usbphy: phy@5100400 { -+ compatible = "allwinner,sun50i-h616-usb-phy"; -+ reg = <0x05100400 0x24>, -+ <0x05101800 0x14>, -+ <0x05200800 0x14>, -+ <0x05310800 0x14>, -+ <0x05311800 0x14>; -+ reg-names = "phy_ctrl", -+ "pmu0", -+ "pmu1", -+ "pmu2", -+ "pmu3"; -+ clocks = <&ccu CLK_USB_PHY0>, -+ <&ccu CLK_USB_PHY1>, -+ <&ccu CLK_USB_PHY2>, -+ <&ccu CLK_USB_PHY3>, -+ <&ccu CLK_BUS_EHCI2>; -+ clock-names = "usb0_phy", -+ "usb1_phy", -+ "usb2_phy", -+ "usb3_phy", -+ "pmu2_clk"; -+ resets = <&ccu RST_USB_PHY0>, -+ <&ccu RST_USB_PHY1>, -+ <&ccu RST_USB_PHY2>, -+ <&ccu RST_USB_PHY3>; -+ reset-names = "usb0_reset", -+ "usb1_reset", -+ "usb2_reset", -+ "usb3_reset"; -+ status = "disabled"; -+ #phy-cells = <1>; -+ }; -+ -+ ehci0: usb@5101000 { -+ compatible = "allwinner,sun50i-h616-ehci", -+ "generic-ehci"; -+ reg = <0x05101000 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI0>, -+ <&ccu CLK_BUS_EHCI0>, -+ <&ccu CLK_USB_OHCI0>; -+ resets = <&ccu RST_BUS_OHCI0>, -+ <&ccu RST_BUS_EHCI0>; -+ phys = <&usbphy 0>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci0: usb@5101400 { -+ compatible = "allwinner,sun50i-h616-ohci", -+ "generic-ohci"; -+ reg = <0x05101400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI0>, -+ <&ccu CLK_USB_OHCI0>; -+ resets = <&ccu RST_BUS_OHCI0>; -+ phys = <&usbphy 0>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci1: usb@5200000 { -+ compatible = "allwinner,sun50i-h616-ehci", -+ "generic-ehci"; -+ reg = <0x05200000 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI1>, -+ <&ccu CLK_BUS_EHCI1>, -+ <&ccu CLK_USB_OHCI1>; -+ resets = <&ccu RST_BUS_OHCI1>, -+ <&ccu RST_BUS_EHCI1>; -+ phys = <&usbphy 1>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci1: usb@5200400 { -+ compatible = "allwinner,sun50i-h616-ohci", -+ "generic-ohci"; -+ reg = <0x05200400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI1>, -+ <&ccu CLK_USB_OHCI1>; -+ resets = <&ccu RST_BUS_OHCI1>; -+ phys = <&usbphy 1>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci2: usb@5310000 { -+ compatible = "allwinner,sun50i-h616-ehci", -+ "generic-ehci"; -+ reg = <0x05310000 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI2>, -+ <&ccu CLK_BUS_EHCI2>, -+ <&ccu CLK_USB_OHCI2>; -+ resets = <&ccu RST_BUS_OHCI2>, -+ <&ccu RST_BUS_EHCI2>; -+ phys = <&usbphy 2>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci2: usb@5310400 { -+ compatible = "allwinner,sun50i-h616-ohci", -+ "generic-ohci"; -+ reg = <0x05310400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI2>, -+ <&ccu CLK_USB_OHCI2>; -+ resets = <&ccu RST_BUS_OHCI2>; -+ phys = <&usbphy 2>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ehci3: usb@5311000 { -+ compatible = "allwinner,sun50i-h616-ehci", -+ "generic-ehci"; -+ reg = <0x05311000 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI3>, -+ <&ccu CLK_BUS_EHCI3>, -+ <&ccu CLK_USB_OHCI3>; -+ resets = <&ccu RST_BUS_OHCI3>, -+ <&ccu RST_BUS_EHCI3>; -+ phys = <&usbphy 3>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ -+ ohci3: usb@5311400 { -+ compatible = "allwinner,sun50i-h616-ohci", -+ "generic-ohci"; -+ reg = <0x05311400 0x100>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_OHCI3>, -+ <&ccu CLK_USB_OHCI3>; -+ resets = <&ccu RST_BUS_OHCI3>; -+ phys = <&usbphy 3>; -+ phy-names = "usb"; -+ status = "disabled"; -+ }; -+ - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h616-rtc"; - reg = <0x07000000 0x400>; diff --git a/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch b/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch deleted file mode 100644 index a544e482f3603c..00000000000000 --- a/target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch +++ /dev/null @@ -1,81 +0,0 @@ -From db5f028309ede13767e2ba356c1975ac37a4fd6c Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 31 Oct 2022 11:13:57 +0000 -Subject: [PATCH] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes - -The OrangePi Zero 2 has one USB-A host port, VBUS is provided by -a GPIO controlled regulator. -The USB-C port is meant to power the board, but is also connected to -the USB 0 port, which we configure as an MUSB peripheral. - -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20221031111358.3387297-7-andre.przywara@arm.com -Signed-off-by: Jernej Skrabec ---- - .../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -@@ -49,8 +49,24 @@ - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -+ -+ reg_usb1_vbus: regulator-usb1-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb1-vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_vcc5v>; -+ enable-active-high; -+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ -+ }; -+}; -+ -+&ehci1 { -+ status = "okay"; - }; - -+/* USB 2 & 3 are on headers only. */ -+ - &emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; -@@ -76,6 +92,10 @@ - status = "okay"; - }; - -+&ohci1 { -+ status = "okay"; -+}; -+ - &r_rsb { - status = "okay"; - -@@ -211,3 +231,24 @@ - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; - }; -+ -+&usbotg { -+ /* -+ * PHY0 pins are connected to a USB-C socket, but a role switch -+ * is not implemented: both CC pins are pulled to GND. -+ * The VBUS pins power the device, so a fixed peripheral mode -+ * is the best choice. -+ * The board can be powered via GPIOs, in this case port0 *can* -+ * act as a host (with a cable/adapter ignoring CC), as VBUS is -+ * then provided by the GPIOs. Any user of this setup would -+ * need to adjust the DT accordingly: dr_mode set to "host", -+ * enabling OHCI0 and EHCI0. -+ */ -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ usb1_vbus-supply = <®_usb1_vbus>; -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-6.1/005-v6.6-arm64-dts-allwinner-h616-Split-Orange-Pi-Zero-2-DT.patch b/target/linux/sunxi/patches-6.1/005-v6.6-arm64-dts-allwinner-h616-Split-Orange-Pi-Zero-2-DT.patch deleted file mode 100644 index 0747e6a8e02ede..00000000000000 --- a/target/linux/sunxi/patches-6.1/005-v6.6-arm64-dts-allwinner-h616-Split-Orange-Pi-Zero-2-DT.patch +++ /dev/null @@ -1,305 +0,0 @@ -From 322bf103204b8f786547acbeed85569254e7088f Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Fri, 4 Aug 2023 18:08:54 +0100 -Subject: [PATCH] arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT - -The Orange Pi Zero 2 got a successor (Zero 3), which shares quite some -DT nodes with the Zero 2, but comes with a different PMIC. - -Move the common parts (except the PMIC) into a new shared file, and -include that from the existing board .dts file. - -No functional change, the generated DTB is the same, except for some -phandle numbering differences. - -Signed-off-by: Andre Przywara -Acked-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20230804170856.1237202-2-andre.przywara@arm.com -Signed-off-by: Jernej Skrabec ---- - .../allwinner/sun50i-h616-orangepi-zero.dtsi | 134 ++++++++++++++++++ - .../allwinner/sun50i-h616-orangepi-zero2.dts | 119 +--------------- - 2 files changed, 135 insertions(+), 118 deletions(-) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi -@@ -0,0 +1,134 @@ -+// SPDX-License-Identifier: (GPL-2.0+ or MIT) -+/* -+ * Copyright (C) 2020 Arm Ltd. -+ * -+ * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3. -+ * Excludes PMIC nodes and properties, since they are different between the two. -+ */ -+ -+#include "sun50i-h616.dtsi" -+ -+#include -+#include -+#include -+ -+/ { -+ aliases { -+ ethernet0 = &emac0; -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-0 { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ -+ default-state = "on"; -+ }; -+ -+ led-1 { -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ -+ }; -+ }; -+ -+ reg_vcc5v: vcc5v { -+ /* board wide 5V supply directly from the USB-C socket */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-5v"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb1_vbus: regulator-usb1-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb1-vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_vcc5v>; -+ enable-active-high; -+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ -+ }; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+/* USB 2 & 3 are on headers only. */ -+ -+&emac0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ext_rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ allwinner,rx-delay-ps = <3100>; -+ allwinner,tx-delay-ps = <700>; -+ status = "okay"; -+}; -+ -+&mdio0 { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; -+}; -+ -+&mmc0 { -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&spi0 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <40000000>; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_ph_pins>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ /* -+ * PHY0 pins are connected to a USB-C socket, but a role switch -+ * is not implemented: both CC pins are pulled to GND. -+ * The VBUS pins power the device, so a fixed peripheral mode -+ * is the best choice. -+ * The board can be powered via GPIOs, in this case port0 *can* -+ * act as a host (with a cable/adapter ignoring CC), as VBUS is -+ * then provided by the GPIOs. Any user of this setup would -+ * need to adjust the DT accordingly: dr_mode set to "host", -+ * enabling OHCI0 and EHCI0. -+ */ -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ usb1_vbus-supply = <®_usb1_vbus>; -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -@@ -5,95 +5,19 @@ - - /dts-v1/; - --#include "sun50i-h616.dtsi" -- --#include --#include --#include -+#include "sun50i-h616-orangepi-zero.dtsi" - - / { - model = "OrangePi Zero2"; - compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; -- -- aliases { -- ethernet0 = &emac0; -- serial0 = &uart0; -- }; -- -- chosen { -- stdout-path = "serial0:115200n8"; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- led-0 { -- function = LED_FUNCTION_POWER; -- color = ; -- gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ -- default-state = "on"; -- }; -- -- led-1 { -- function = LED_FUNCTION_STATUS; -- color = ; -- gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ -- }; -- }; -- -- reg_vcc5v: vcc5v { -- /* board wide 5V supply directly from the USB-C socket */ -- compatible = "regulator-fixed"; -- regulator-name = "vcc-5v"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- regulator-always-on; -- }; -- -- reg_usb1_vbus: regulator-usb1-vbus { -- compatible = "regulator-fixed"; -- regulator-name = "usb1-vbus"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <®_vcc5v>; -- enable-active-high; -- gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ -- }; --}; -- --&ehci1 { -- status = "okay"; - }; - --/* USB 2 & 3 are on headers only. */ -- - &emac0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&ext_rgmii_pins>; -- phy-mode = "rgmii"; -- phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dcdce>; -- allwinner,rx-delay-ps = <3100>; -- allwinner,tx-delay-ps = <700>; -- status = "okay"; --}; -- --&mdio0 { -- ext_rgmii_phy: ethernet-phy@1 { -- compatible = "ethernet-phy-ieee802.3-c22"; -- reg = <1>; -- }; - }; - - &mmc0 { - vmmc-supply = <®_dcdce>; -- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -- bus-width = <4>; -- status = "okay"; --}; -- --&ohci1 { -- status = "okay"; - }; - - &r_rsb { -@@ -211,44 +135,3 @@ - vcc-ph-supply = <®_aldo1>; - vcc-pi-supply = <®_aldo1>; - }; -- --&spi0 { -- status = "okay"; -- pinctrl-names = "default"; -- pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; -- -- flash@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "jedec,spi-nor"; -- reg = <0>; -- spi-max-frequency = <40000000>; -- }; --}; -- --&uart0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&uart0_ph_pins>; -- status = "okay"; --}; -- --&usbotg { -- /* -- * PHY0 pins are connected to a USB-C socket, but a role switch -- * is not implemented: both CC pins are pulled to GND. -- * The VBUS pins power the device, so a fixed peripheral mode -- * is the best choice. -- * The board can be powered via GPIOs, in this case port0 *can* -- * act as a host (with a cable/adapter ignoring CC), as VBUS is -- * then provided by the GPIOs. Any user of this setup would -- * need to adjust the DT accordingly: dr_mode set to "host", -- * enabling OHCI0 and EHCI0. -- */ -- dr_mode = "peripheral"; -- status = "okay"; --}; -- --&usbphy { -- usb1_vbus-supply = <®_usb1_vbus>; -- status = "okay"; --}; diff --git a/target/linux/sunxi/patches-6.1/006-v6.6-arm64-dts-allwinner-h616-Add-OrangePi-Zero-3-board.patch b/target/linux/sunxi/patches-6.1/006-v6.6-arm64-dts-allwinner-h616-Add-OrangePi-Zero-3-board.patch deleted file mode 100644 index 4081a82d524446..00000000000000 --- a/target/linux/sunxi/patches-6.1/006-v6.6-arm64-dts-allwinner-h616-Add-OrangePi-Zero-3-board.patch +++ /dev/null @@ -1,140 +0,0 @@ -From f1b3ddb3ecc2eec1f912383e01156c226daacfab Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Fri, 4 Aug 2023 18:08:56 +0100 -Subject: [PATCH] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board - support - -The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC, -which seems to be just an H616 with more L2 cache. The board itself is a -slightly updated version of the Orange Pi Zero 2. It features: -- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU -- 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2) -- AXP313a PMIC (more capable AXP305 on the Zero2) -- Raspberry-Pi-1 compatible GPIO header -- extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports -- 1 USB 2.0 host port -- 1 USB 2.0 type C port (power supply + OTG) -- MicroSD slot -- on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2) -- 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2) -- micro-HDMI port -- (yet) unsupported Allwinner WiFi/BT chip - -Add the devicetree file describing the currently supported features, -namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at -the moment, though the basic functionality works. - -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20230804170856.1237202-4-andre.przywara@arm.com -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/Makefile | 1 + - .../allwinner/sun50i-h618-orangepi-zero3.dts | 94 +++++++++++++++++++ - 2 files changed, 95 insertions(+) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts - ---- a/arch/arm64/boot/dts/allwinner/Makefile -+++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-ta - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb -+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts -@@ -0,0 +1,94 @@ -+// SPDX-License-Identifier: (GPL-2.0+ or MIT) -+/* -+ * Copyright (C) 2023 Arm Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "sun50i-h616-orangepi-zero.dtsi" -+ -+/ { -+ model = "OrangePi Zero3"; -+ compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; -+}; -+ -+&emac0 { -+ phy-supply = <®_dldo1>; -+}; -+ -+&ext_rgmii_phy { -+ motorcomm,clk-out-frequency-hz = <125000000>; -+}; -+ -+&mmc0 { -+ /* -+ * The schematic shows the card detect pin wired up to PF6, via an -+ * inverter, but it just doesn't work. -+ */ -+ broken-cd; -+ vmmc-supply = <®_dldo1>; -+}; -+ -+&r_i2c { -+ status = "okay"; -+ -+ axp313: pmic@36 { -+ compatible = "x-powers,axp313a"; -+ reg = <0x36>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ interrupt-parent = <&pio>; -+ interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ -+ -+ vin1-supply = <®_vcc5v>; -+ vin2-supply = <®_vcc5v>; -+ vin3-supply = <®_vcc5v>; -+ -+ regulators { -+ /* Supplies VCC-PLL, so needs to be always on. */ -+ reg_aldo1: aldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8"; -+ }; -+ -+ /* Supplies VCC-IO, so needs to be always on. */ -+ reg_dldo1: dldo1 { -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3"; -+ }; -+ -+ reg_dcdc1: dcdc1 { -+ regulator-always-on; -+ regulator-min-microvolt = <810000>; -+ regulator-max-microvolt = <990000>; -+ regulator-name = "vdd-gpu-sys"; -+ }; -+ -+ reg_dcdc2: dcdc2 { -+ regulator-always-on; -+ regulator-min-microvolt = <810000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-cpu"; -+ }; -+ -+ reg_dcdc3: dcdc3 { -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-name = "vdd-dram"; -+ }; -+ }; -+ }; -+}; -+ -+&pio { -+ vcc-pc-supply = <®_dldo1>; -+ vcc-pf-supply = <®_dldo1>; -+ vcc-pg-supply = <®_aldo1>; -+ vcc-ph-supply = <®_dldo1>; -+ vcc-pi-supply = <®_dldo1>; -+}; diff --git a/target/linux/sunxi/patches-6.1/007-v6.7-arm64-dts-allwinner-h616-update-emac-for-Orange-Pi.patch b/target/linux/sunxi/patches-6.1/007-v6.7-arm64-dts-allwinner-h616-update-emac-for-Orange-Pi.patch deleted file mode 100644 index a492eed5512470..00000000000000 --- a/target/linux/sunxi/patches-6.1/007-v6.7-arm64-dts-allwinner-h616-update-emac-for-Orange-Pi.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b9622937d95809ef89904583191571a9fa326402 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 29 Oct 2023 15:40:09 +0800 -Subject: [PATCH] arm64: dts: allwinner: h616: update emac for Orange Pi Zero 3 - -The current emac setting is not suitable for Orange Pi Zero 3, -move it back to Orange Pi Zero 2 DT. Also update phy mode and -delay values for emac on Orange Pi Zero 3. -With these changes, Ethernet now looks stable. - -Fixes: 322bf103204b ("arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT") -Signed-off-by: Chukun Pan -Reviewed-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20231029074009.7820-2-amadeus@jmu.edu.cn -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 3 --- - arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 3 +++ - arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 2 ++ - 3 files changed, 5 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi -@@ -68,10 +68,7 @@ - &emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; -- phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; -- allwinner,rx-delay-ps = <3100>; -- allwinner,tx-delay-ps = <700>; - status = "okay"; - }; - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts -@@ -13,6 +13,9 @@ - }; - - &emac0 { -+ allwinner,rx-delay-ps = <3100>; -+ allwinner,tx-delay-ps = <700>; -+ phy-mode = "rgmii"; - phy-supply = <®_dcdce>; - }; - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts -@@ -13,6 +13,8 @@ - }; - - &emac0 { -+ allwinner,tx-delay-ps = <700>; -+ phy-mode = "rgmii-rxid"; - phy-supply = <®_dldo1>; - }; - diff --git a/target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch b/target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch deleted file mode 100644 index ce8add18ab4347..00000000000000 --- a/target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 951992797378a2177946400438f4d23c9fceae5b Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Tue, 12 Sep 2023 14:25:13 +0200 -Subject: [PATCH] arm64: dts: allwinner: h616: Add SID controller node - -Add node for the H616 SID controller - -Signed-off-by: Martin Botka -Acked-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20230912-sid-h616-v3-2-ee18e1c5bbb5@somainline.org -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -133,6 +133,13 @@ - #reset-cells = <1>; - }; - -+ sid: efuse@3006000 { -+ compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; -+ reg = <0x03006000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ }; -+ - watchdog: watchdog@30090a0 { - compatible = "allwinner,sun50i-h616-wdt", - "allwinner,sun6i-a31-wdt"; diff --git a/target/linux/sunxi/patches-6.1/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch b/target/linux/sunxi/patches-6.1/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch deleted file mode 100644 index 3453e2aa5330ff..00000000000000 --- a/target/linux/sunxi/patches-6.1/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 19 Feb 2024 15:36:33 +0000 -Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616 - -The Allwinner H616 SoC contains a mysterious bit at register offset 0x0 -in the SRAM control block. If bit 16 is set (the reset value), the -temperature readings of the THS are way off, leading to reports about -200C, at normal ambient temperatures. Clearing this bits brings the -reported values down to the expected values. -The BSP code clears this bit in firmware (U-Boot), and has an explicit -comment about this, but offers no real explanation. - -Experiments in U-Boot show that register 0x0 has no effect on the SRAM C -visibility: all tested bit settings still allow full read and write -access by the CPU to the whole of SRAM C. Only bit 24 of the register at -offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling -the THS switch functionality as an SRAM region would not reflect reality. - -Since we should not rely on firmware settings, allow other code (the THS -driver) to access this register, by exporting it through the already -existing regmap. This mimics what we already do for the LDO control and -the EMAC register. - -To avoid concurrent accesses to the same register at the same time, by -the SRAM switch code and the regmap code, use the same lock to protect -the access. The regmap subsystem allows to use an existing lock, so we -just need to hook in there. - -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com ---- - drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/drivers/soc/sunxi/sunxi_sram.c -+++ b/drivers/soc/sunxi/sunxi_sram.c -@@ -284,6 +284,7 @@ EXPORT_SYMBOL(sunxi_sram_release); - struct sunxi_sramc_variant { - int num_emac_clocks; - bool has_ldo_ctrl; -+ bool has_ths_offset; - }; - - static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { -@@ -305,8 +306,10 @@ static const struct sunxi_sramc_variant - - static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = { - .num_emac_clocks = 2, -+ .has_ths_offset = true, - }; - -+#define SUNXI_SRAM_THS_OFFSET_REG 0x0 - #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 - #define SUNXI_SYS_LDO_CTRL_REG 0x150 - -@@ -315,6 +318,8 @@ static bool sunxi_sram_regmap_accessible - { - const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev); - -+ if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset) -+ return true; - if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG && - reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4) - return true; -@@ -324,6 +329,20 @@ static bool sunxi_sram_regmap_accessible - return false; - } - -+static void sunxi_sram_lock(void *_lock) -+{ -+ spinlock_t *lock = _lock; -+ -+ spin_lock(lock); -+} -+ -+static void sunxi_sram_unlock(void *_lock) -+{ -+ spinlock_t *lock = _lock; -+ -+ spin_unlock(lock); -+} -+ - static struct regmap_config sunxi_sram_regmap_config = { - .reg_bits = 32, - .val_bits = 32, -@@ -333,6 +352,9 @@ static struct regmap_config sunxi_sram_r - /* other devices have no business accessing other registers */ - .readable_reg = sunxi_sram_regmap_accessible_reg, - .writeable_reg = sunxi_sram_regmap_accessible_reg, -+ .lock = sunxi_sram_lock, -+ .unlock = sunxi_sram_unlock, -+ .lock_arg = &sram_lock, - }; - - static int __init sunxi_sram_probe(struct platform_device *pdev) diff --git a/target/linux/sunxi/patches-6.1/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch b/target/linux/sunxi/patches-6.1/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch deleted file mode 100644 index 8b199891184fef..00000000000000 --- a/target/linux/sunxi/patches-6.1/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch +++ /dev/null @@ -1,47 +0,0 @@ -From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001 -From: Maxim Kiselev -Date: Mon, 18 Dec 2023 00:06:23 +0300 -Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support - -This patch adds a thermal sensor controller support for the D1/T113s, -which is similar to the one on H6, but with only one sensor and -different scale and offset values. - -Signed-off-by: Maxim Kiselev -Acked-by: Jernej Skrabec -Reviewed-by: Andre Przywara -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20231217210629.131486-3-bigunclemax@gmail.com ---- - drivers/thermal/sun8i_thermal.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -610,6 +610,18 @@ static const struct ths_thermal_chip sun - .calc_temp = sun8i_ths_calc_temp, - }; - -+static const struct ths_thermal_chip sun20i_d1_ths = { -+ .sensor_num = 1, -+ .has_bus_clk_reset = true, -+ .offset = 188552, -+ .scale = 673, -+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA, -+ .calibrate = sun50i_h6_ths_calibrate, -+ .init = sun50i_h6_thermal_init, -+ .irq_ack = sun50i_h6_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ - static const struct of_device_id of_ths_match[] = { - { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, - { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, -@@ -618,6 +630,7 @@ static const struct of_device_id of_ths_ - { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths }, - { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, - { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, -+ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, of_ths_match); diff --git a/target/linux/sunxi/patches-6.1/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch b/target/linux/sunxi/patches-6.1/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch deleted file mode 100644 index b8138a3870375d..00000000000000 --- a/target/linux/sunxi/patches-6.1/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 19 Feb 2024 15:36:35 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value - -So far we were ORing in some "unknown" value into the THS control -register on the Allwinner H6. This part of the register is not explained -in the H6 manual, but the H616 manual details those bits, and on closer -inspection the THS IP blocks in both SoCs seem very close: -- The BSP code for both SoCs writes the same values into THS_CTRL. -- The reset values of at least the first three registers are the same. - -Replace the "unknown" value with its proper meaning: "acquire time", -most probably the sample part of the sample & hold circuit of the ADC, -according to its explanation in the H616 manual. - -No functional change, just a macro rename and adjustment. - -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Acked-by: Vasily Khoruzhick -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com ---- - drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++------------- - 1 file changed, 16 insertions(+), 13 deletions(-) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -50,7 +50,8 @@ - #define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16) - #define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8) - --#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16) -+#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1)) -+#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16) - #define SUN50I_THS_FILTER_EN BIT(2) - #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) - #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) -@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct - return 0; - } - --/* -- * Without this undocumented value, the returned temperatures would -- * be higher than real ones by about 20C. -- */ --#define SUN50I_H6_CTRL0_UNK 0x0000002f -- - static int sun50i_h6_thermal_init(struct ths_device *tmdev) - { - int val; - - /* -- * T_acq = 20us -- * clkin = 24MHz -- * -- * x = T_acq * clkin - 1 -- * = 479 -+ * The manual recommends an overall sample frequency of 50 KHz (20us, -+ * 480 cycles at 24 MHz), which provides plenty of time for both the -+ * acquisition time (>24 cycles) and the actual conversion time -+ * (>14 cycles). -+ * The lower half of the CTRL register holds the "acquire time", in -+ * clock cycles, which the manual recommends to be 2us: -+ * 24MHz * 2us = 48 cycles. -+ * The high half of THS_CTRL encodes the sample frequency, in clock -+ * cycles: 24MHz * 20us = 480 cycles. -+ * This is explained in the H616 manual, but apparently wrongly -+ * described in the H6 manual, although the BSP code does the same -+ * for both SoCs. - */ - regmap_write(tmdev->regmap, SUN50I_THS_CTRL0, -- SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479)); -+ SUN50I_THS_CTRL0_T_ACQ(48) | -+ SUN50I_THS_CTRL0_T_SAMPLE_PER(480)); - /* average over 4 samples */ - regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC, - SUN50I_THS_FILTER_EN | diff --git a/target/linux/sunxi/patches-6.1/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch b/target/linux/sunxi/patches-6.1/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch deleted file mode 100644 index 3d01a507fac395..00000000000000 --- a/target/linux/sunxi/patches-6.1/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001 -From: Maksim Kiselev -Date: Mon, 19 Feb 2024 15:36:36 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4 - sensors - -The H616 SoC resembles the H6 thermal sensor controller, with a few -changes like four sensors. - -Extend sun50i_h6_ths_calibrate() function to support calibration of -these sensors. - -Co-developed-by: Martin Botka -Signed-off-by: Martin Botka -Signed-off-by: Maksim Kiselev -Reviewed-by: Andre Przywara -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Acked-by: Vasily Khoruzhick -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-5-andre.przywara@arm.com ---- - drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++-------- - 1 file changed, 20 insertions(+), 8 deletions(-) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -224,16 +224,21 @@ static int sun50i_h6_ths_calibrate(struc - struct device *dev = tmdev->dev; - int i, ft_temp; - -- if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num) -+ if (!caldata[0]) - return -EINVAL; - - /* - * efuse layout: - * -- * 0 11 16 32 -- * +-------+-------+-------+ -- * |temp| |sensor0|sensor1| -- * +-------+-------+-------+ -+ * 0 11 16 27 32 43 48 57 -+ * +----------+-----------+-----------+-----------+ -+ * | temp | |sensor0| |sensor1| |sensor2| | -+ * +----------+-----------+-----------+-----------+ -+ * ^ ^ ^ -+ * | | | -+ * | | sensor3[11:8] -+ * | sensor3[7:4] -+ * sensor3[3:0] - * - * The calibration data on the H6 is the ambient temperature and - * sensor values that are filled during the factory test stage. -@@ -246,9 +251,16 @@ static int sun50i_h6_ths_calibrate(struc - ft_temp = (caldata[0] & FT_TEMP_MASK) * 100; - - for (i = 0; i < tmdev->chip->sensor_num; i++) { -- int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK; -- int cdata, offset; -- int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); -+ int sensor_reg, sensor_temp, cdata, offset; -+ -+ if (i == 3) -+ sensor_reg = (caldata[1] >> 12) -+ | ((caldata[2] >> 12) << 4) -+ | ((caldata[3] >> 12) << 8); -+ else -+ sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK; -+ -+ sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); - - /* - * Calibration data is CALIBRATE_DEFAULT - (calculated diff --git a/target/linux/sunxi/patches-6.1/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch b/target/linux/sunxi/patches-6.1/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch deleted file mode 100644 index 6db1e32cfb5a30..00000000000000 --- a/target/linux/sunxi/patches-6.1/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch +++ /dev/null @@ -1,126 +0,0 @@ -From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Mon, 19 Feb 2024 15:36:37 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code - -The Allwinner H616 SoC needs to clear a bit in one register in the SRAM -controller, to report reasonable temperature values. On reset, bit 16 in -register 0x3000000 is set, which leads to the driver reporting -temperatures around 200C. Clearing this bit brings the values down to the -expected range. The BSP code does a one-time write in U-Boot, with a -comment just mentioning the effect on the THS, but offering no further -explanation. - -To not rely on firmware to set things up for us, add code that queries -the SRAM controller device via a DT phandle link, then clear just this -single bit. - -Signed-off-by: Andre Przywara -Acked-by: Vasily Khoruzhick -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-6-andre.przywara@arm.com ---- - drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++ - 1 file changed, 51 insertions(+) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -68,6 +69,7 @@ struct tsensor { - struct ths_thermal_chip { - bool has_mod_clk; - bool has_bus_clk_reset; -+ bool needs_sram; - int sensor_num; - int offset; - int scale; -@@ -85,12 +87,16 @@ struct ths_device { - const struct ths_thermal_chip *chip; - struct device *dev; - struct regmap *regmap; -+ struct regmap_field *sram_regmap_field; - struct reset_control *reset; - struct clk *bus_clk; - struct clk *mod_clk; - struct tsensor sensor[MAX_SENSOR_NUM]; - }; - -+/* The H616 needs to have a bit 16 in the SRAM control register cleared. */ -+static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16); -+ - /* Temp Unit: millidegree Celsius */ - static int sun8i_ths_calc_temp(struct ths_device *tmdev, - int id, int reg) -@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse - reset_control_assert(data); - } - -+static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node) -+{ -+ struct device_node *sram_node; -+ struct platform_device *sram_pdev; -+ struct regmap *regmap = NULL; -+ -+ sram_node = of_parse_phandle(node, "allwinner,sram", 0); -+ if (!sram_node) -+ return ERR_PTR(-ENODEV); -+ -+ sram_pdev = of_find_device_by_node(sram_node); -+ if (!sram_pdev) { -+ /* platform device might not be probed yet */ -+ regmap = ERR_PTR(-EPROBE_DEFER); -+ goto out_put_node; -+ } -+ -+ /* If no regmap is found then the other device driver is at fault */ -+ regmap = dev_get_regmap(&sram_pdev->dev, NULL); -+ if (!regmap) -+ regmap = ERR_PTR(-EINVAL); -+ -+ platform_device_put(sram_pdev); -+out_put_node: -+ of_node_put(sram_node); -+ return regmap; -+} -+ - static int sun8i_ths_resource_init(struct ths_device *tmdev) - { - struct device *dev = tmdev->dev; -@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc - if (ret) - return ret; - -+ if (tmdev->chip->needs_sram) { -+ struct regmap *regmap; -+ -+ regmap = sun8i_ths_get_sram_regmap(dev->of_node); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ tmdev->sram_regmap_field = devm_regmap_field_alloc(dev, -+ regmap, -+ sun8i_ths_sram_reg_field); -+ if (IS_ERR(tmdev->sram_regmap_field)) -+ return PTR_ERR(tmdev->sram_regmap_field); -+ } -+ - ret = sun8i_ths_calibrate(tmdev); - if (ret) - return ret; -@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct - { - int val; - -+ /* The H616 needs to have a bit in the SRAM control register cleared. */ -+ if (tmdev->sram_regmap_field) -+ regmap_field_write(tmdev->sram_regmap_field, 0); -+ - /* - * The manual recommends an overall sample frequency of 50 KHz (20us, - * 480 cycles at 24 MHz), which provides plenty of time for both the diff --git a/target/linux/sunxi/patches-6.1/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch b/target/linux/sunxi/patches-6.1/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch deleted file mode 100644 index e743d344c6e97d..00000000000000 --- a/target/linux/sunxi/patches-6.1/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch +++ /dev/null @@ -1,50 +0,0 @@ -From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Mon, 19 Feb 2024 15:36:38 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller - -Add support for the thermal sensor found in H616 SoCs, is the same as -the H6 thermal sensor controller, but with four sensors. -Also the registers readings are wrong, unless a bit in the first SYS_CFG -register cleared, so set exercise the SRAM regmap to take care of that. - -Signed-off-by: Martin Botka -Signed-off-by: Andre Przywara -Acked-by: Vasily Khoruzhick -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240219153639.179814-7-andre.przywara@arm.com ---- - drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -688,6 +688,20 @@ static const struct ths_thermal_chip sun - .calc_temp = sun8i_ths_calc_temp, - }; - -+static const struct ths_thermal_chip sun50i_h616_ths = { -+ .sensor_num = 4, -+ .has_bus_clk_reset = true, -+ .needs_sram = true, -+ .ft_deviation = 8000, -+ .offset = 263655, -+ .scale = 810, -+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA, -+ .calibrate = sun50i_h6_ths_calibrate, -+ .init = sun50i_h6_thermal_init, -+ .irq_ack = sun50i_h6_irq_ack, -+ .calc_temp = sun8i_ths_calc_temp, -+}; -+ - static const struct of_device_id of_ths_match[] = { - { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, - { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, -@@ -697,6 +711,7 @@ static const struct of_device_id of_ths_ - { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, - { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, - { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths }, -+ { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, of_ths_match); diff --git a/target/linux/sunxi/patches-6.1/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch b/target/linux/sunxi/patches-6.1/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch deleted file mode 100644 index 384bf55084f307..00000000000000 --- a/target/linux/sunxi/patches-6.1/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001 -From: Mark Brown -Date: Tue, 23 Jan 2024 23:33:07 +0000 -Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone - registration failure - -Currently the sun8i thermal driver will fail to probe if any of the -thermal zones it is registering fails to register with the thermal core. -Since we currently do not define any trip points for the GPU thermal -zones on at least A64 or H5 this means that we have no thermal support -on these platforms: - -[ 1.698703] thermal_sys: Failed to find 'trips' node -[ 1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1 - -even though the main CPU thermal zone on both SoCs is fully configured. -This does not seem ideal, while we may not be able to use all the zones -it seems better to have those zones which are usable be operational. -Instead just carry on registering zones if we get any non-deferral -error, allowing use of those zones which are usable. - -This means that we also need to update the interrupt handler to not -attempt to notify the core for events on zones which we have not -registered, I didn't see an ability to mask individual interrupts and -I would expect that interrupts would still be indicated in the ISR even -if they were masked. - -Reviewed-by: Vasily Khoruzhick -Acked-by: Jernej Skrabec -Signed-off-by: Mark Brown -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/20240123-thermal-sun8i-registration-v3-1-3e5771b1bbdd@kernel.org ---- - drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++-- - 1 file changed, 14 insertions(+), 2 deletions(-) - ---- a/drivers/thermal/sun8i_thermal.c -+++ b/drivers/thermal/sun8i_thermal.c -@@ -197,6 +197,9 @@ static irqreturn_t sun8i_irq_thread(int - int i; - - for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) { -+ /* We allow some zones to not register. */ -+ if (IS_ERR(tmdev->sensor[i].tzd)) -+ continue; - thermal_zone_device_update(tmdev->sensor[i].tzd, - THERMAL_EVENT_UNSPECIFIED); - } -@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths - i, - &tmdev->sensor[i], - &ths_ops); -- if (IS_ERR(tmdev->sensor[i].tzd)) -- return PTR_ERR(tmdev->sensor[i].tzd); -+ -+ /* -+ * If an individual zone fails to register for reasons -+ * other than probe deferral (eg, a bad DT) then carry -+ * on, other zones might register successfully. -+ */ -+ if (IS_ERR(tmdev->sensor[i].tzd)) { -+ if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER) -+ return PTR_ERR(tmdev->sensor[i].tzd); -+ continue; -+ } - - if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd)) - dev_warn(tmdev->dev, diff --git a/target/linux/sunxi/patches-6.1/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch b/target/linux/sunxi/patches-6.1/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch deleted file mode 100644 index cd6542bf14419d..00000000000000 --- a/target/linux/sunxi/patches-6.1/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch +++ /dev/null @@ -1,138 +0,0 @@ -From f4318af40544b8e7ff5a6b667ede60e6cf808262 Mon Sep 17 00:00:00 2001 -From: Martin Botka -Date: Mon, 19 Feb 2024 15:36:39 +0000 -Subject: [PATCH] arm64: dts: allwinner: h616: Add thermal sensor and zones - -There are four thermal sensors: -- CPU -- GPU -- VE -- DRAM - -Add the thermal sensor configuration and the thermal zones. - -Signed-off-by: Martin Botka -Signed-off-by: Andre Przywara -Reviewed-by: Jernej Skrabec -Link: https://lore.kernel.org/r/20240219153639.179814-8-andre.przywara@arm.com -Signed-off-by: Jernej Skrabec ---- - .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++ - 1 file changed, 88 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - - / { - interrupt-parent = <&gic>; -@@ -138,6 +139,10 @@ - reg = <0x03006000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ ths_calibration: thermal-sensor-calibration@14 { -+ reg = <0x14 0x8>; -+ }; - }; - - watchdog: watchdog@30090a0 { -@@ -511,6 +516,19 @@ - }; - }; - -+ ths: thermal-sensor@5070400 { -+ compatible = "allwinner,sun50i-h616-ths"; -+ reg = <0x05070400 0x400>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_THS>; -+ clock-names = "bus"; -+ resets = <&ccu RST_BUS_THS>; -+ nvmem-cells = <&ths_calibration>; -+ nvmem-cell-names = "calibration"; -+ allwinner,sram = <&syscon>; -+ #thermal-sensor-cells = <1>; -+ }; -+ - usbotg: usb@5100000 { - compatible = "allwinner,sun50i-h616-musb", - "allwinner,sun8i-h3-musb"; -@@ -755,4 +773,74 @@ - #size-cells = <0>; - }; - }; -+ -+ thermal-zones { -+ cpu-thermal { -+ polling-delay-passive = <500>; -+ polling-delay = <1000>; -+ thermal-sensors = <&ths 2>; -+ sustainable-power = <1000>; -+ -+ trips { -+ cpu_threshold: cpu-trip-0 { -+ temperature = <60000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ cpu_target: cpu-trip-1 { -+ temperature = <70000>; -+ type = "passive"; -+ hysteresis = <0>; -+ }; -+ cpu_critical: cpu-trip-2 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ -+ gpu-thermal { -+ polling-delay-passive = <500>; -+ polling-delay = <1000>; -+ thermal-sensors = <&ths 0>; -+ sustainable-power = <1100>; -+ -+ trips { -+ gpu_temp_critical: gpu-trip-0 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ -+ ve-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 1>; -+ -+ trips { -+ ve_temp_critical: ve-trip-0 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ -+ ddr-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&ths 3>; -+ -+ trips { -+ ddr_temp_critical: ddr-trip-0 { -+ temperature = <110000>; -+ type = "critical"; -+ hysteresis = <0>; -+ }; -+ }; -+ }; -+ }; - }; diff --git a/target/linux/sunxi/patches-6.1/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch b/target/linux/sunxi/patches-6.1/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch deleted file mode 100644 index 30c98aa7378835..00000000000000 --- a/target/linux/sunxi/patches-6.1/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch +++ /dev/null @@ -1,30 +0,0 @@ -From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 10 Oct 2021 21:50:17 +0800 -Subject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5 - -This adds the OF node for the USB3 ethernet adapter on the FriendlyARM -NanoPi R1S H5. Add the correct value for the RTL8153 LED configuration -register to match the blink behavior of the other port on the device. - -Signed-off-by: Chukun Pan ---- - arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -@@ -116,6 +116,13 @@ - - &ehci1 { - status = "okay"; -+ -+ usb-eth@1 { -+ compatible = "realtek,rtl8153"; -+ reg = <1>; -+ -+ realtek,led-data = <0x78>; -+ }; - }; - - &ehci2 { diff --git a/target/linux/sunxi/patches-6.1/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-6.1/301-orangepi_pc2_usb_otg_to_host_key_power.patch deleted file mode 100644 index 2c5ccd7d96deb0..00000000000000 --- a/target/linux/sunxi/patches-6.1/301-orangepi_pc2_usb_otg_to_host_key_power.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -@@ -59,7 +59,7 @@ - - key-sw4 { - label = "sw4"; -- linux,code = ; -+ linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; -@@ -220,7 +220,7 @@ - }; - - &usb_otg { -- dr_mode = "otg"; -+ dr_mode = "host"; - status = "okay"; - }; - diff --git a/target/linux/sunxi/patches-6.1/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-6.1/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch deleted file mode 100644 index a8dfcd9dbce10c..00000000000000 --- a/target/linux/sunxi/patches-6.1/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001 -From: Oskari Lemmela -Date: Mon, 31 Dec 2018 07:44:49 +0200 -Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions. - -First 896kB to u-boot. Enough space for SPL, u-boot and ATF. -Next 128kB to u-boot environment and rest to firmware. - -Firmware partition is compatible FIT image dynamic splitting. - -Signed-off-by: Oskari Lemmela ---- - .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -@@ -58,6 +58,28 @@ - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x000000 0x0E0000>; -+ }; -+ -+ partition@e0000 { -+ label = "u-boot-env"; -+ reg = <0x0E0000 0x020000>; -+ }; -+ -+ partition@100000 { -+ compatible = "denx,fit"; -+ label = "firmware"; -+ reg = <0x100000 0xF00000>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/sunxi/patches-6.1/410-sunxi-add-bananapi-p2-zero.patch b/target/linux/sunxi/patches-6.1/410-sunxi-add-bananapi-p2-zero.patch deleted file mode 100644 index 5b8dd170c59ffb..00000000000000 --- a/target/linux/sunxi/patches-6.1/410-sunxi-add-bananapi-p2-zero.patch +++ /dev/null @@ -1,292 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -1352,6 +1352,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a83t-cubietruck-plus.dtb \ - sun8i-a83t-tbs-a711.dtb \ - sun8i-h2-plus-bananapi-m2-zero.dtb \ -+ sun8i-h2-plus-bananapi-p2-zero.dtb \ - sun8i-h2-plus-libretech-all-h3-cc.dtb \ - sun8i-h2-plus-orangepi-r1.dtb \ - sun8i-h2-plus-orangepi-zero.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-p2-zero.dts -@@ -0,0 +1,279 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2023 Zoltan HERPAI -+ * -+ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is: -+ * Copyright (C) 2017 Icenowy Zheng -+ */ -+ -+/dts-v1/; -+#include "sun8i-h3.dtsi" -+#include "sunxi-common-regulators.dtsi" -+ -+#include -+#include -+ -+/ { -+ model = "Banana Pi BPI-P2-Zero"; -+ compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus"; -+ -+ aliases { -+ serial0 = &uart0; -+ serial1 = &uart1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ connector { -+ compatible = "hdmi-connector"; -+ type = "c"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ pwr_led { -+ label = "bananapi-p2-zero:red:pwr"; -+ gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */ -+ default-state = "on"; -+ }; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ -+ sw4 { -+ label = "power"; -+ linux,code = ; -+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ reg_vdd_cpux: vdd-cpux-regulator { -+ compatible = "regulator-gpio"; -+ regulator-name = "vdd-cpux"; -+ regulator-type = "voltage"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-ramp-delay = <50>; /* 4ms */ -+ -+ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */ -+ enable-active-high; -+ gpios-states = <0x1>; -+ states = <1100000 0>, <1300000 1>; -+ }; -+ -+ reg_vcc_dram: vcc-dram { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-dram"; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-always-on; -+ regulator-boot-on; -+ enable-active-high; -+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ -+ vin-supply = <®_vcc5v0>; -+ }; -+ -+ reg_vcc1v2: vcc1v2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc1v2"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-always-on; -+ regulator-boot-on; -+ enable-active-high; -+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ -+ vin-supply = <®_vcc5v0>; -+ }; -+ -+ poweroff { -+ compatible = "regulator-poweroff"; -+ cpu-supply = <®_vcc1v2>; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <®_vdd_cpux>; -+}; -+ -+&de { -+ status = "okay"; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&emac { -+ phy-handle = <&int_mii_phy>; -+ phy-mode = "mii"; -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ -+&mmc0 { -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ /* -+ * On the production batch of this board the card detect GPIO is -+ * high active (card inserted), although on the early samples it's -+ * low active. -+ */ -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ -+ status = "okay"; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&pio>; -+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pa_pins>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ max-speed = <1500000>; -+ clocks = <&rtc 1>; -+ clock-names = "lpo"; -+ vbat-supply = <®_vcc3v3>; -+ vddio-supply = <®_vcc3v3>; -+ device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ -+ host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ -+ shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -+ }; -+ -+}; -+ -+&pio { -+ gpio-line-names = -+ /* PA */ -+ "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15", -+ "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29", -+ "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05", -+ "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16", -+ "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27", -+ "CON2-P40", "CON2-P38", "", "", -+ "", "", "", "", "", "", "", "", -+ -+ /* PB */ -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ -+ /* PC */ -+ "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24", -+ "CON2-P18", "", "", "CON2-P26", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ -+ /* PD */ -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "CSI-PWR-EN", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ -+ /* PE */ -+ "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07", -+ "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20", -+ "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12", -+ "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ -+ /* PF */ -+ "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", -+ "SDC0-D2", "SDC0-DET", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ -+ /* PG */ -+ "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1", -+ "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX", -+ "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP", -+ "BT-RST-N", "AP-WAKE-BT", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&r_pio { -+ gpio-line-names = -+ /* PL */ -+ "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36", -+ "VCC-IO-EN", "USB0-ID", "WL-PWR-EN", -+ "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "", -+ "", "", "", "", "", "", "", "", -+ "", "", "", "", "", "", "", ""; -+}; -+ -+&usb_otg { -+ dr_mode = "otg"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ -+ /* -+ * There're two micro-USB connectors, one is power-only and another is -+ * OTG. The Vbus of these two connectors are connected together, so -+ * the external USB device will be powered just by the power input -+ * from the power-only USB port. -+ */ -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-6.1/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch b/target/linux/sunxi/patches-6.1/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch deleted file mode 100644 index 68ec333e3742f5..00000000000000 --- a/target/linux/sunxi/patches-6.1/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Petr=20=C5=A0tetiar?= -Date: Thu, 26 Mar 2020 10:09:19 +0100 -Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Petr Štetiar - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -@@ -15,6 +15,10 @@ - aliases { - ethernet0 = &emac; - serial0 = &uart0; -+ led-boot = &led_user; -+ led-failsafe = &led_user; -+ led-running = &led_user; -+ led-upgrade = &led_user; - }; - - chosen { -@@ -35,7 +39,7 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ led_user: led-0 { - label = "a64-olinuxino:red:user"; - gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - }; diff --git a/target/linux/sunxi/patches-6.1/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch b/target/linux/sunxi/patches-6.1/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch deleted file mode 100644 index 8670d06109b285..00000000000000 --- a/target/linux/sunxi/patches-6.1/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 10 Oct 2021 21:50:18 +0800 -Subject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases - -Use the SYS LED on the casing for showing system status. - -Signed-off-by: Chukun Pan ---- - arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -@@ -23,6 +23,11 @@ - ethernet0 = &emac; - ethernet1 = &rtl8189etv; - serial0 = &uart0; -+ -+ led-boot = &led_sys; -+ led-failsafe = &led_sys; -+ led-running = &led_sys; -+ led-upgrade = &led_sys; - }; - - chosen { -@@ -38,7 +43,7 @@ - gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; - }; - -- led-1 { -+ led_sys: led-1 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; diff --git a/target/linux/sunxi/patches-6.1/442-arm64-dts-orangepi-one-plus-enable-PWM.patch b/target/linux/sunxi/patches-6.1/442-arm64-dts-orangepi-one-plus-enable-PWM.patch deleted file mode 100644 index 76a73ee1f0d673..00000000000000 --- a/target/linux/sunxi/patches-6.1/442-arm64-dts-orangepi-one-plus-enable-PWM.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -@@ -41,3 +41,7 @@ - reg = <1>; - }; - }; -+ -+&pwm { -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-6.1/450-arm64-dts-enable-wifi-on-pine64-boards.patch b/target/linux/sunxi/patches-6.1/450-arm64-dts-enable-wifi-on-pine64-boards.patch deleted file mode 100644 index 3876852c2bca76..00000000000000 --- a/target/linux/sunxi/patches-6.1/450-arm64-dts-enable-wifi-on-pine64-boards.patch +++ /dev/null @@ -1,72 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -@@ -42,6 +42,11 @@ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -+ }; - }; - - &ac_power_supply { -@@ -102,6 +107,21 @@ - reg = <1>; - }; - }; -+ -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ vmmc-supply = <®_dldo4>; -+ vqmmc-supply = <®_eldo1>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8723cs: wifi@1 { -+ reg = <1>; -+ }; -+}; - - &mmc2 { - pinctrl-names = "default"; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -@@ -35,6 +35,11 @@ - }; - }; - }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -+ }; - }; - - &codec { -@@ -124,6 +129,21 @@ - status = "okay"; - }; - -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ vmmc-supply = <®_dldo4>; -+ vqmmc-supply = <®_eldo1>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8723cs: wifi@1 { -+ reg = <1>; -+ }; -+}; -+ - &ohci0 { - status = "okay"; - }; diff --git a/target/linux/x86/config-6.1 b/target/linux/x86/config-6.1 index 20feecafd050cf..6c9f30cf91740e 100644 --- a/target/linux/x86/config-6.1 +++ b/target/linux/x86/config-6.1 @@ -236,6 +236,7 @@ CONFIG_MICROCODE_INTEL=y CONFIG_MICROCODE_LATE_LOADING=y CONFIG_MIGRATION=y CONFIG_MITIGATION_RFDS=y +CONFIG_MITIGATION_SPECTRE_BHI=y # CONFIG_MK6 is not set # CONFIG_MK7 is not set # CONFIG_MK8 is not set @@ -351,9 +352,6 @@ CONFIG_SG_POOL=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_SPARSEMEM_STATIC=y CONFIG_SPARSE_IRQ=y -# CONFIG_SPECTRE_BHI_AUTO is not set -# CONFIG_SPECTRE_BHI_OFF is not set -CONFIG_SPECTRE_BHI_ON=y CONFIG_SPECULATION_MITIGATIONS=y CONFIG_SRCU=y # CONFIG_STATIC_CALL_SELFTEST is not set diff --git a/target/linux/zynq/Makefile b/target/linux/zynq/Makefile index 7e4ff3288136fe..90e49df87892db 100644 --- a/target/linux/zynq/Makefile +++ b/target/linux/zynq/Makefile @@ -18,8 +18,7 @@ define Target/Description Build firmware image for Zynq 7000 SoC devices. endef -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/zynq/config-5.15 b/target/linux/zynq/config-5.15 deleted file mode 100644 index d1d73924400040..00000000000000 --- a/target/linux/zynq/config-5.15 +++ /dev/null @@ -1,552 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ALTERA_FREEZE_BRIDGE is not set -# CONFIG_ALTERA_PR_IP_CORE is not set -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=1024 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_VEXPRESS=y -CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y -# CONFIG_ARCH_VEXPRESS_SPC is not set -CONFIG_ARCH_ZYNQ=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_ERRATA_643719=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_754327=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GLOBAL_TIMER=y -CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2 -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_PL172_MPMC is not set -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_TIMER_SP804=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ARM_ZYNQ_CPUIDLE=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -# CONFIG_AXI_DMAC is not set -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -CONFIG_CACHE_L2X0=y -CONFIG_CADENCE_TTC_TIMER=y -CONFIG_CADENCE_WATCHDOG=y -CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLKSRC_VERSATILE=y -CONFIG_CLK_SP810=y -CONFIG_CLK_VEXPRESS_OSC=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SYSFS is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_SI570=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONNECTOR=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_COREDUMP=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_RNG2=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_E1000E=y -CONFIG_EDAC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -# CONFIG_EDAC_DEBUG is not set -CONFIG_EDAC_LEGACY_SYSFS=y -CONFIG_EDAC_SUPPORT=y -# CONFIG_EDAC_SYNOPSYS is not set -CONFIG_EEPROM_AT24=y -CONFIG_EEPROM_AT25=y -CONFIG_ELF_CORE=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_XILINX is not set -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FPGA=y -CONFIG_FPGA_BRIDGE=y -# CONFIG_FPGA_DFL is not set -# CONFIG_FPGA_MGR_ALTERA_CVP is not set -# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set -# CONFIG_FPGA_MGR_ICE40_SPI is not set -# CONFIG_FPGA_MGR_MACHXO2_SPI is not set -# CONFIG_FPGA_MGR_XILINX_SPI is not set -CONFIG_FPGA_MGR_ZYNQ_FPGA=y -CONFIG_FPGA_REGION=y -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_ZYNQ=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HID_MICROSOFT=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CADENCE=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_ICST=y -CONFIG_IIO=y -CONFIG_IIO_BUFFER=y -CONFIG_IIO_KFIFO_BUF=y -CONFIG_IIO_TRIGGER=y -CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_SPARSEKMAP=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_RARP=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISDN is not set -CONFIG_JBD2=y -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_KCMP=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_XZ is not set -CONFIG_KEYBOARD_ATKBD=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_GPIO_POLLED=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_CAMERA=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_TRANSIENT=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_MACB=y -# CONFIG_MACB_PCI is not set -CONFIG_MACB_USE_HWSTAMP=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_GPIO is not set -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MFD_VEXPRESS_SYSREG=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODULE_STRIPPED is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_CYPRESS=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -CONFIG_MOUSE_PS2_FOCALTECH=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SMBUS=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_VIA is not set -CONFIG_NLS=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NO_IOPORT_MAP=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -# CONFIG_OF_FPGA_REGION is not set -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PCI=y -CONFIG_PCIE_XILINX=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_ZYNQ=y -CONFIG_PL310_ERRATA_588369=y -CONFIG_PL310_ERRATA_727915=y -CONFIG_PL310_ERRATA_753970=y -CONFIG_PL310_ERRATA_769419=y -CONFIG_PL330_DMA=y -# CONFIG_PL353_SMC is not set -CONFIG_PLAT_VERSATILE=y -CONFIG_PM=y -CONFIG_PMBUS=y -CONFIG_PM_CLK=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_VEXPRESS=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PROC_EVENTS=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_R8169=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_VEXPRESS is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_ZYNQ=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_PCF8563=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SCHED_CORE is not set -CONFIG_SCHED_MC=y -CONFIG_SCHED_SMT=y -CONFIG_SENSORS_PMBUS=y -CONFIG_SENSORS_UCD9000=y -CONFIG_SENSORS_UCD9200=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOC_BUS=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_CADENCE=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_XILINX=y -CONFIG_SPI_ZYNQ_QSPI=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TEXTSEARCH is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UIO=y -# CONFIG_UIO_AEC is not set -# CONFIG_UIO_CIF is not set -# CONFIG_UIO_DMEM_GENIRQ is not set -# CONFIG_UIO_MF624 is not set -# CONFIG_UIO_NETX is not set -# CONFIG_UIO_PCI_GENERIC is not set -CONFIG_UIO_PDRV_GENIRQ=y -# CONFIG_UIO_PRUSS is not set -# CONFIG_UIO_SERCOS3 is not set -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_CHIPIDEA=y -CONFIG_USB_CHIPIDEA_HOST=y -CONFIG_USB_CHIPIDEA_UDC=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_XILINX=y -CONFIG_USB_HID=y -CONFIG_USB_NET_DRIVERS=y -CONFIG_USB_OTG=y -CONFIG_USB_OTG_FSM=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USE_OF=y -CONFIG_VEXPRESS_CONFIG=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_VITESSE_PHY=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XILINX_EMACLITE=y -# CONFIG_XILINX_INTC is not set -# CONFIG_XILINX_PR_DECOUPLER is not set -CONFIG_XILINX_WATCHDOG=y -CONFIG_XILINX_XADC=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/toolchain/Config.in b/toolchain/Config.in index 24caecccb3ee73..b4ba5b3b677cf9 100644 --- a/toolchain/Config.in +++ b/toolchain/Config.in @@ -97,6 +97,7 @@ menuconfig EXTERNAL_TOOLCHAIN default "arm-unknown-linux-gnu" if arm default "armeb-unknown-linux-gnu" if armeb default "i486-unknown-linux-gnu" if i386 + default "loongarch64-unknown-linux-gnu" if loongarch64 default "mips-unknown-linux-gnu" if mips default "mipsel-unknown-linux-gnu" if mipsel default "powerpc-unknown-linux-gnu" if powerpc @@ -111,6 +112,7 @@ menuconfig EXTERNAL_TOOLCHAIN default "arm-unknown-linux-gnu-" if arm default "armeb-unknown-linux-gnu-" if armeb default "i486-unknown-linux-gnu-" if i386 + default "loongarch64-unknown-linux-gnu-" if loongarch64 default "mips-unknown-linux-gnu-" if mips default "mipsel-unknown-linux-gnu-" if mipsel default "powerpc-unknown-linux-gnu-" if powerpc @@ -125,6 +127,7 @@ menuconfig EXTERNAL_TOOLCHAIN default "/opt/cross/arm-unknown-linux-gnu" if arm default "/opt/cross/armeb-unknown-linux-gnu" if armeb default "/opt/cross/i486-unknown-linux-gnu" if i386 + default "/opt/cross/loongarch64-unknown-linux-gnu" if loongarch64 default "/opt/cross/mips-unknown-linux-gnu" if mips default "/opt/cross/mipsel-unknown-linux-gnu" if mipsel default "/opt/cross/powerpc-unknown-linux-gnu" if powerpc diff --git a/toolchain/gcc/patches-13.x/400-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch b/toolchain/gcc/patches-13.x/400-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch new file mode 100644 index 00000000000000..4fddc3f77e72d5 --- /dev/null +++ b/toolchain/gcc/patches-13.x/400-LoongArch-Fix-MUSL_DYNAMIC_LINKER.patch @@ -0,0 +1,41 @@ +From a80c68a08604b0ac625ac7fc59eae40b551b1176 Mon Sep 17 00:00:00 2001 +From: Peng Fan +Date: Wed, 19 Apr 2023 16:23:42 +0800 +Subject: [PATCH] LoongArch: Fix MUSL_DYNAMIC_LINKER + +The system based on musl has no '/lib64', so change it. + +https://wiki.musl-libc.org/guidelines-for-distributions.html, +"Multilib/multi-arch" section of this introduces it. + +gcc/ + * config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER): Redefine. + +Signed-off-by: Peng Fan +Suggested-by: Xi Ruoyao +--- + gcc/config/loongarch/gnu-user.h | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h +index aecaa02a199..fa1a5211419 100644 +--- a/gcc/config/loongarch/gnu-user.h ++++ b/gcc/config/loongarch/gnu-user.h +@@ -33,9 +33,14 @@ along with GCC; see the file COPYING3. If not see + #define GLIBC_DYNAMIC_LINKER \ + "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1" + ++#define MUSL_ABI_SPEC \ ++ "%{mabi=lp64d:-lp64d}" \ ++ "%{mabi=lp64f:-lp64f}" \ ++ "%{mabi=lp64s:-lp64s}" ++ + #undef MUSL_DYNAMIC_LINKER + #define MUSL_DYNAMIC_LINKER \ +- "/lib" ABI_GRLEN_SPEC "/ld-musl-loongarch-" ABI_SPEC ".so.1" ++ "/lib/ld-musl-loongarch" ABI_GRLEN_SPEC MUSL_ABI_SPEC ".so.1" + + #undef GNU_USER_TARGET_LINK_SPEC + #define GNU_USER_TARGET_LINK_SPEC \ +-- +2.39.3 diff --git a/toolchain/gcc/patches-13.x/401-LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch b/toolchain/gcc/patches-13.x/401-LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch new file mode 100644 index 00000000000000..218a6925784198 --- /dev/null +++ b/toolchain/gcc/patches-13.x/401-LoongArch-Modify-MUSL_DYNAMIC_LINKER.patch @@ -0,0 +1,43 @@ +From 8bccee51f0deac64b79cd9ad75df599422f4c8ff Mon Sep 17 00:00:00 2001 +From: Lulu Cheng +Date: Sat, 18 Nov 2023 11:04:42 +0800 +Subject: [PATCH] LoongArch: Modify MUSL_DYNAMIC_LINKER. + +Use no suffix at all in the musl dynamic linker name for hard +float ABI. Use -sf and -sp suffixes in musl dynamic linker name +for soft float and single precision ABIs. The following table +outlines the musl interpreter names for the LoongArch64 ABI names. + +musl interpreter | LoongArch64 ABI +--------------------------- | ----------------- +ld-musl-loongarch64.so.1 | loongarch64-lp64d +ld-musl-loongarch64-sp.so.1 | loongarch64-lp64f +ld-musl-loongarch64-sf.so.1 | loongarch64-lp64s + +gcc/ChangeLog: + + * config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix. +--- + gcc/config/loongarch/gnu-user.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h +index 9616d6e8a0b..e9f4bcef1d4 100644 +--- a/gcc/config/loongarch/gnu-user.h ++++ b/gcc/config/loongarch/gnu-user.h +@@ -34,9 +34,9 @@ along with GCC; see the file COPYING3. If not see + "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1" + + #define MUSL_ABI_SPEC \ +- "%{mabi=lp64d:-lp64d}" \ +- "%{mabi=lp64f:-lp64f}" \ +- "%{mabi=lp64s:-lp64s}" ++ "%{mabi=lp64d:}" \ ++ "%{mabi=lp64f:-sp}" \ ++ "%{mabi=lp64s:-sf}" + + #undef MUSL_DYNAMIC_LINKER + #define MUSL_DYNAMIC_LINKER \ +-- +2.39.3 + diff --git a/toolchain/glibc/common.mk b/toolchain/glibc/common.mk index 79a7a0131df34f..28beda04ebdcc3 100644 --- a/toolchain/glibc/common.mk +++ b/toolchain/glibc/common.mk @@ -12,8 +12,8 @@ PKG_RELEASE:=1 PKG_SOURCE_PROTO:=git PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION) -PKG_SOURCE_VERSION:=cfe121910013a46e2477562282c56ae8062089aa -PKG_MIRROR_HASH:=99b9beb283d644caacea12fe87dd7f0a0141ff26349ee500a78047aba3f5be5c +PKG_SOURCE_VERSION:=e9f05fa1c62c8044ff025963498063f73eb51c5f +PKG_MIRROR_HASH:=fd61eb2caea0d4100638b8aa8285b0f1bc23af921c376516307c9ab8ac307739 PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.zst PKG_CPE_ID:=cpe:/a:gnu:glibc diff --git a/toolchain/musl/patches/400-fix-loongarch64-ldso-file-name.patch b/toolchain/musl/patches/400-fix-loongarch64-ldso-file-name.patch new file mode 100644 index 00000000000000..a19ceb4583d7fe --- /dev/null +++ b/toolchain/musl/patches/400-fix-loongarch64-ldso-file-name.patch @@ -0,0 +1,10 @@ +--- a/Makefile ++++ b/Makefile +@@ -218,6 +218,7 @@ $(DESTDIR)$(includedir)/%: $(srcdir)/inc + + $(DESTDIR)$(LDSO_PATHNAME): $(DESTDIR)$(libdir)/libc.so + $(INSTALL) -D -l libc.so $@ || true ++ $(if $(filter loongarch64,$(ARCH)$(SUBARCH)),$(INSTALL) -D -l libc.so $(subst $(ARCH)$(SUBARCH).so.1,loongarch-lp64d.so.1,$@) || true) + + install-libs: $(ALL_LIBS:lib/%=$(DESTDIR)$(libdir)/%) $(if $(SHARED_LIBS),$(DESTDIR)$(LDSO_PATHNAME),) + diff --git a/tools/elfutils/Makefile b/tools/elfutils/Makefile index 140250801c9d30..466fc312711bc7 100644 --- a/tools/elfutils/Makefile +++ b/tools/elfutils/Makefile @@ -4,7 +4,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=elfutils PKG_VERSION:=0.191 -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:=https://sourceware.org/$(PKG_NAME)/ftp/$(PKG_VERSION) @@ -41,7 +41,6 @@ PKG_GNULIB_ARGS = \ PKG_GNULIB_MODS = \ argp \ - dirname \ fts \ obstack \ progname \ diff --git a/tools/elfutils/patches/100-portability.patch b/tools/elfutils/patches/100-portability.patch index 1a61455f483c76..6f7564731b6acb 100644 --- a/tools/elfutils/patches/100-portability.patch +++ b/tools/elfutils/patches/100-portability.patch @@ -346,12 +346,11 @@ +} --- a/libdwfl/libdwflP.h +++ b/libdwfl/libdwflP.h -@@ -31,6 +31,8 @@ +@@ -31,6 +31,7 @@ #include #include +#include -+#include #include #include #include @@ -366,17 +365,18 @@ +#endif --- a/libdw/libdwP.h +++ b/libdw/libdwP.h -@@ -32,8 +32,10 @@ +@@ -32,10 +32,10 @@ #include #include +#include #include #include -+#include - +- /* Known location expressions already decoded. */ + struct loc_s + { --- a/libdw/Makefile.am +++ b/libdw/Makefile.am @@ -34,14 +34,12 @@ endif diff --git a/tools/gengetopt/patches/001-gm_utils.cpp-Call-clear-instead-of-empty.patch b/tools/gengetopt/patches/001-gm_utils.cpp-Call-clear-instead-of-empty.patch new file mode 100644 index 00000000000000..6aa3f549da0bf3 --- /dev/null +++ b/tools/gengetopt/patches/001-gm_utils.cpp-Call-clear-instead-of-empty.patch @@ -0,0 +1,25 @@ +From bfba6445a778007f40af5cbfbe725e12c0fcafc6 Mon Sep 17 00:00:00 2001 +From: Tomas Volf <~@wolfsden.cz> +Date: Tue, 5 Mar 2024 22:25:20 +0100 +Subject: [PATCH] gm_utils.cpp: Call clear instead of empty. + +Since the intention seem to be to erase the next word, I believe calling empty +was a mistake and it should have been clear. Empty does nothing in this +context. + +* src/gm_utils.cpp (wrap_cstr): Call clear. +--- + src/gm_utils.cpp | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/src/gm_utils.cpp ++++ b/src/gm_utils.cpp +@@ -311,7 +311,7 @@ void wrap_cstr(string& wrapped, unsigned + // trim leading spaces + std::size_t pos = next_word.find_first_not_of(' '); + if( pos == std::string::npos ) +- next_word.empty(); ++ next_word.clear(); + else if( pos ) + next_word.erase( 0, pos ); + diff --git a/tools/gengetopt/patches/002-gm_utils.h-Drop-std-unary_function.patch b/tools/gengetopt/patches/002-gm_utils.h-Drop-std-unary_function.patch new file mode 100644 index 00000000000000..ce997f4505e572 --- /dev/null +++ b/tools/gengetopt/patches/002-gm_utils.h-Drop-std-unary_function.patch @@ -0,0 +1,33 @@ +From a3d0a0419a35bef9b80a6a12432ab30e2d1e0f5a Mon Sep 17 00:00:00 2001 +From: Tomas Volf <~@wolfsden.cz> +Date: Tue, 5 Mar 2024 22:27:42 +0100 +Subject: [PATCH] gm_utils.h: Drop std::unary_function. + +I am not sure what it does, it is deprecated/removed (depending on C++ version) +and the advice seems to be that is just is not necessary. So just remove it. + +* src/gm_utils.h (print_f, pair_print_f): Drop std::unary_function. +--- + src/gm_utils.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/src/gm_utils.h ++++ b/src/gm_utils.h +@@ -117,7 +117,7 @@ bool string_contains(const char *s, cons + * Function object to print something into a stream (to be used with for_each) + */ + template +-struct print_f : public std::unary_function ++struct print_f + { + print_f(std::ostream& out, const string &s = ", ") : os(out), sep(s) {} + void operator() (T x) { os << x << sep; } +@@ -129,7 +129,7 @@ struct print_f : public std::unary_funct + * Function object to print a pair into two streams (to be used with for_each) + */ + template +-struct pair_print_f : public std::unary_function ++struct pair_print_f + { + pair_print_f(std::ostream& out1, std::ostream& out2, const string &s = ", ") : + os1(out1), os2(out2), sep(s) {}