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SMT target and SystemVerilog target? #511
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It seems that
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In the Makefile, I see there is the
riscv.smt_model
target, I was hoping it can generate models in SMT-LIB2 format (is that what it means to be?), but it seems that does not work for me.The error message is:
Can anyone help explain how to fix this?
Meanwhile, I was wondering, how to generate the reference ISA model in System Verilog?
Thanks!
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