From de38540a2b45a24c369be383960dab03b3bf6d4e Mon Sep 17 00:00:00 2001 From: Gilbert Chen Date: Mon, 18 Mar 2019 11:22:11 +0800 Subject: [PATCH 1/3] Update RISCV-SMBIOS.md update processor-specific block standard header --- RISCV-SMBIOS.md | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/RISCV-SMBIOS.md b/RISCV-SMBIOS.md index 1c3b467..f5294c4 100644 --- a/RISCV-SMBIOS.md +++ b/RISCV-SMBIOS.md @@ -48,40 +48,48 @@ The information in this structure defines the processor additional information i Below is the standard header of SMBIOS type 44 defined in SMBIOS spec v3.3.0, the total length of entire SMBIOS type 44 is indicated in *offset 01h* and the value must be less than or equal to 255 in bytes according to section 6.1.2 in SMBIOS spec 3.2.0 spec. | **Offset** | **Name** | **Length** | **Value** | **Description** | -|------------|-----------------------------------------------------|------------|-----------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +|------------|-----------------------------------------------------|------------|-----------|------------------| | 00h | Type | BYTE | 44 | Processor Additional Information.| | 01h | Length | BYTE | 4+Y | Length of the structure. Y is the length of Processor-specific Block specified at offset 06h.| | 02h | Handle | WORD | Varies | Handle, or instance number, associated with the structure.| | 04h | Referenced Handle | WORD | Varies | Handle, or instance number, associated with the processor (SMBIOS type 4) which the processor additional information describes.| -| 06h | Processor-specific Block | Varies (Y) | Varies | Processor-specific block. (See below section)| +| 06h | Processor-specific Block | Varies (Y) | Varies | [Processor-specific block](#processor-specific_block)| -### Standard Processor-specific Block Structure +### Processor-specific Block ---------------------------------------------------------- Processor-specific block is the standard header of processor-specific data as defined in SMBIOS section 7.45.1. -| **Offset** |**Name**| **Length** | **Value** | **Description** | +| **Offset** |**Name**| **Length** | **Value** | **Description**| |------------|--------|------------|-----------|---------------| -|00h|Revision|WORD|Varies|Bit 15:8 Major revision
Bit 7:0 Minor revision -|02h|Structure Length|BYTE|N|Length of Processor-specific Data -|03h|Processor-specific Data|N BYTEs|Varies|Processor-specific Data - -### RISC-V Processor-specific Block Structure +|00h|Structure Length|BYTE|N|Length of Processor-specific Data +|01h|Processor Type|BYTE|Varies|The processor architecture delineated by this Processor-specific Block. (see [processor architectures types](#processor_architectures_types)) +|02h|Processor-specific Data|N BYTEs|Varies|[ RISC-V Processor-specific Data](#risc-v_processor-specific_data) + + +### Processor Architecture Types +| **Byte value** |**Meaing**| **Reference** | +|----------------|----------|---------------| +|01h|IA32(x86)|None| +|02h|x64(x86064, Intel64, AMD64, EM64T)|None| +|03h|Intel® Itanium® architecture|None| +|04h|32-bit ARM(Aarch32)|None| +|05h|64-bit ARM(Aarch64)|None| +|06h|32-bit RISC-V(RV32)|None| +|07h|64-bit RISC-V(RV64)|None| +|08h|128-bit RISCV(RV64)|None| + +### RISC-V Processor-specific Data ---------------------------------------------------------- RISC-V processor-specific additional information is constructed by RISC-V boot loader such as uboot, coreboot, UEFI edk2 firmware, etc. SMBIOS Type 44 is referred by RISC-V software for recognizing RISC-V hart capability. RISC-V SMBIOS Type 44 Processor-specific Block is version controlled which use major and minor versioning in 16-bit value at *offset 0*. The new fields must be added to the end of this table for the backward compatible. -| **Offset** | **Additional Info. Version** | **Name** | **Length** | **Value** | **Description** | +| **Offset** | **Additional Info. Version** | **Name**| **Length** | **Value** | **Description**| |------------|------------------------------|-----------------------------------------------------------------------|------------|-----------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 00h | 000Ah (v0.10) | Revision of RISC-V Processor-specific Block Structure | WORD | Varies | Bit 15:8 Major revision Bit 7:0 Minor revision The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure.| +| 00h | 000Ah (v0.10)| Revision of RISC-V Processor-specific Block Structure | WORD | Varies | Bit 15:8 Major revision Bit 7:0 Minor revision The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure.| | 02h | 000Ah (v0.10) | Structure Length | Byte | 110 | Length of Processor-specific Data | - -#### RISC-V Processor-specific Data Structure (follows Processor-specific Block Structure above) - -| **Offset** | **Additional Info. Version** | **Name** | **Length** | **Value** | **Description** | -|------------|------------------------------|-----------------------------------------------------------------------|------------|-----------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 03h | 000Ah (v0.10) | Hart ID | DQWORD | Varies | The ID of this RISC-V Hart | -| 13h | 000Ah (v0.10) | Boot Hart | BYTE | Boolean | 1: This is boot hart to boot system
0: This is not the boot hart | +| 13h | 000Ah (v0.10) | Boot Hart | BYTE | Boolean | 1: This is boot hart to boot system
0: This is not the boot hart | | 14h | 000Ah (v0.10) | Machine Vendor ID | DQWORD | Varies | The vendor ID of this RISC-V Hart | | 24h | 000Ah (v0.10) | Machine Architecture ID | DQWORD | Varies | Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. | | 34h | 000Ah (v0.10) | Machine Implementation ID | DQWORD | Varies | Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. | @@ -113,3 +121,4 @@ SMBIOS Spec - https://www.dmtf.org/standards/smbios ---------------------------------------------------------- #### All contributors are listed as below, Abner Chang , **Hewlett Packard Enterprise (HPE)**
Gilbert Chen , **Hewlett Packard Enterprise (HPE)** + From ad6d1060055a1cf25f4c657fb7024d845db69429 Mon Sep 17 00:00:00 2001 From: Gilbert Chen Date: Mon, 18 Mar 2019 15:02:59 +0800 Subject: [PATCH 2/3] Update RISCV-SMBIOS.md update version fix the value of length(offset 2) in SMBIOS type 44 add reference link in Processor Architecture Types table. --- RISCV-SMBIOS.md | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/RISCV-SMBIOS.md b/RISCV-SMBIOS.md index f5294c4..ad749fd 100644 --- a/RISCV-SMBIOS.md +++ b/RISCV-SMBIOS.md @@ -50,7 +50,7 @@ Below is the standard header of SMBIOS type 44 defined in SMBIOS spec v3.3.0, th | **Offset** | **Name** | **Length** | **Value** | **Description** | |------------|-----------------------------------------------------|------------|-----------|------------------| | 00h | Type | BYTE | 44 | Processor Additional Information.| -| 01h | Length | BYTE | 4+Y | Length of the structure. Y is the length of Processor-specific Block specified at offset 06h.| +| 01h | Length | BYTE | 6+Y | Length of the structure. Y is the length of Processor-specific Block specified at offset 06h.| | 02h | Handle | WORD | Varies | Handle, or instance number, associated with the structure.| | 04h | Referenced Handle | WORD | Varies | Handle, or instance number, associated with the processor (SMBIOS type 4) which the processor additional information describes.| | 06h | Processor-specific Block | Varies (Y) | Varies | [Processor-specific block](#processor-specific_block)| @@ -75,9 +75,9 @@ Processor-specific block is the standard header of processor-specific data as de |03h|Intel® Itanium® architecture|None| |04h|32-bit ARM(Aarch32)|None| |05h|64-bit ARM(Aarch64)|None| -|06h|32-bit RISC-V(RV32)|None| -|07h|64-bit RISC-V(RV64)|None| -|08h|128-bit RISCV(RV64)|None| +|06h|32-bit RISC-V(RV32)|see [ RISC-V Processor-specific Data](#risc-v_processor-specific_data)| +|07h|64-bit RISC-V(RV64)|see [ RISC-V Processor-specific Data](#risc-v_processor-specific_data)| +|08h|128-bit RISCV(RV64)|see [ RISC-V Processor-specific Data](#risc-v_processor-specific_data)| ### RISC-V Processor-specific Data ---------------------------------------------------------- @@ -87,21 +87,21 @@ RISC-V processor-specific additional information is constructed by RISC-V boot l | **Offset** | **Additional Info. Version** | **Name**| **Length** | **Value** | **Description**| |------------|------------------------------|-----------------------------------------------------------------------|------------|-----------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | 00h | 000Ah (v0.10)| Revision of RISC-V Processor-specific Block Structure | WORD | Varies | Bit 15:8 Major revision Bit 7:0 Minor revision The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure.| -| 02h | 000Ah (v0.10) | Structure Length | Byte | 110 | Length of Processor-specific Data | -| 03h | 000Ah (v0.10) | Hart ID | DQWORD | Varies | The ID of this RISC-V Hart | -| 13h | 000Ah (v0.10) | Boot Hart | BYTE | Boolean | 1: This is boot hart to boot system
0: This is not the boot hart | -| 14h | 000Ah (v0.10) | Machine Vendor ID | DQWORD | Varies | The vendor ID of this RISC-V Hart | -| 24h | 000Ah (v0.10) | Machine Architecture ID | DQWORD | Varies | Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. | -| 34h | 000Ah (v0.10) | Machine Implementation ID | DQWORD | Varies | Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. | -| 44h | 000Ah (v0.10) | Instruction set supported | DWORD | Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. | -| 48h | 000Ah (v0.10) | Privilege Level Supported | BYTE | Varies | The privilege levels supported by this RISC-V Hart. Bit 0 Machine Mode
BIT 1 Reserved
BIT 2 Supervisor Mode
Bit 3 User Mode
BIT 6:4 Reserved
BIT 7 Debug Mode | -| 49H | 000Ah (v0.10) | Machine Exception Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call.| -| 59H | 000Ah (v0.10) | Machine Interrupt Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. | -| 69h | 000Ah (v0.10) | The register width (XLEN) | BYTE | ENUM | The width of register supported by this RISC-V Hart | -| 6Ah | 000Ah (v0.10) | Machine Mode native base integer ISA width (M-XLEN) | BYTE | ENUM | The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart | -| 6Bh | 000Ah (v0.10) | Reserved | BYTE | ENUM | Placeholder for Hypervisor Mode | -| 6Ch | 000Ah (v0.10) | Supervisor Mode native base integer ISA width (S-XLEN) | BYTE | ENUM | The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart | -| 6Dh | 0000Ah (v0.10) | User Mode native base integer ISA width (U-XLEN) | BYTE | ENUM | The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart | +| 02h | 0001h (v1.0) | Structure Length | Byte | 110 | Length of Processor-specific Data | +| 03h | 0001h (v1.0) | Hart ID | DQWORD | Varies | The ID of this RISC-V Hart | +| 13h | 0001h (v1.0) | Boot Hart | BYTE | Boolean | 1: This is boot hart to boot system
0: This is not the boot hart | +| 14h | 0001h (v1.0) | Machine Vendor ID | DQWORD | Varies | The vendor ID of this RISC-V Hart | +| 24h | 0001h (v1.0) | Machine Architecture ID | DQWORD | Varies | Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. | +| 34h | 0001h (v1.0) | Machine Implementation ID | DQWORD | Varies | Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. | +| 44h | 0001h (v1.0) | Instruction set supported | DWORD | Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. | +| 48h | 0001h (v1.0) | Privilege Level Supported | BYTE | Varies | The privilege levels supported by this RISC-V Hart. Bit 0 Machine Mode
BIT 1 Reserved
BIT 2 Supervisor Mode
Bit 3 User Mode
BIT 6:4 Reserved
BIT 7 Debug Mode | +| 49H | 0001h (v1.0) | Machine Exception Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call.| +| 59H | 0001h (v1.0) | Machine Interrupt Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. | +| 69h | 0001h (v1.0) | The register width (XLEN) | BYTE | ENUM | The width of register supported by this RISC-V Hart | +| 6Ah | 0001h (v1.0) | Machine Mode native base integer ISA width (M-XLEN) | BYTE | ENUM | The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart | +| 6Bh | 0001h (v1.0) | Reserved | BYTE | ENUM | Placeholder for Hypervisor Mode | +| 6Ch | 0001h (v1.0) | Supervisor Mode native base integer ISA width (S-XLEN) | BYTE | ENUM | The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart | +| 6Dh | 00001h (v1.0) | User Mode native base integer ISA width (U-XLEN) | BYTE | ENUM | The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart | ### Encoding of RISC-V Native Base Integer ISA Width ---------------------------------------------------------- From 17240088a3cccab147f41ce0ada1e67ba4e84413 Mon Sep 17 00:00:00 2001 From: Gilbert Chen Date: Mon, 18 Mar 2019 15:09:51 +0800 Subject: [PATCH 3/3] Update RISCV-SMBIOS.md correct the additional info version --- RISCV-SMBIOS.md | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/RISCV-SMBIOS.md b/RISCV-SMBIOS.md index ad749fd..2e0030c 100644 --- a/RISCV-SMBIOS.md +++ b/RISCV-SMBIOS.md @@ -86,22 +86,22 @@ RISC-V processor-specific additional information is constructed by RISC-V boot l | **Offset** | **Additional Info. Version** | **Name**| **Length** | **Value** | **Description**| |------------|------------------------------|-----------------------------------------------------------------------|------------|-----------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| 00h | 000Ah (v0.10)| Revision of RISC-V Processor-specific Block Structure | WORD | Varies | Bit 15:8 Major revision Bit 7:0 Minor revision The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure.| -| 02h | 0001h (v1.0) | Structure Length | Byte | 110 | Length of Processor-specific Data | -| 03h | 0001h (v1.0) | Hart ID | DQWORD | Varies | The ID of this RISC-V Hart | -| 13h | 0001h (v1.0) | Boot Hart | BYTE | Boolean | 1: This is boot hart to boot system
0: This is not the boot hart | -| 14h | 0001h (v1.0) | Machine Vendor ID | DQWORD | Varies | The vendor ID of this RISC-V Hart | -| 24h | 0001h (v1.0) | Machine Architecture ID | DQWORD | Varies | Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. | -| 34h | 0001h (v1.0) | Machine Implementation ID | DQWORD | Varies | Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. | -| 44h | 0001h (v1.0) | Instruction set supported | DWORD | Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. | -| 48h | 0001h (v1.0) | Privilege Level Supported | BYTE | Varies | The privilege levels supported by this RISC-V Hart. Bit 0 Machine Mode
BIT 1 Reserved
BIT 2 Supervisor Mode
Bit 3 User Mode
BIT 6:4 Reserved
BIT 7 Debug Mode | -| 49H | 0001h (v1.0) | Machine Exception Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call.| -| 59H | 0001h (v1.0) | Machine Interrupt Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. | -| 69h | 0001h (v1.0) | The register width (XLEN) | BYTE | ENUM | The width of register supported by this RISC-V Hart | -| 6Ah | 0001h (v1.0) | Machine Mode native base integer ISA width (M-XLEN) | BYTE | ENUM | The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart | -| 6Bh | 0001h (v1.0) | Reserved | BYTE | ENUM | Placeholder for Hypervisor Mode | -| 6Ch | 0001h (v1.0) | Supervisor Mode native base integer ISA width (S-XLEN) | BYTE | ENUM | The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart | -| 6Dh | 00001h (v1.0) | User Mode native base integer ISA width (U-XLEN) | BYTE | ENUM | The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart | +| 00h | 0100h (v1.0)| Revision of RISC-V Processor-specific Block Structure | WORD | 0100h | Bit 15:8 Major revision Bit 7:0 Minor revision The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure.| +| 02h | 0100h (v1.0) | Structure Length | Byte | 110 | Length of Processor-specific Data | +| 03h | 0100h (v1.0) | Hart ID | DQWORD | Varies | The ID of this RISC-V Hart | +| 13h | 0100h (v1.0) | Boot Hart | BYTE | Boolean | 1: This is boot hart to boot system
0: This is not the boot hart | +| 14h | 0100h (v1.0) | Machine Vendor ID | DQWORD | Varies | The vendor ID of this RISC-V Hart | +| 24h | 0100h (v1.0) | Machine Architecture ID | DQWORD | Varies | Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. | +| 34h | 0100h (v1.0) | Machine Implementation ID | DQWORD | Varies | Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. | +| 44h | 0100h (v1.0) | Instruction set supported | DWORD | Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. | +| 48h | 0100h (v1.0) | Privilege Level Supported | BYTE | Varies | The privilege levels supported by this RISC-V Hart. Bit 0 Machine Mode
BIT 1 Reserved
BIT 2 Supervisor Mode
Bit 3 User Mode
BIT 6:4 Reserved
BIT 7 Debug Mode | +| 49H | 0100h (v1.0) | Machine Exception Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call.| +| 59H | 0100h (v1.0) | Machine Interrupt Trap Delegation Information | DQWORD | Varies | Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. | +| 69h | 0100h (v1.0) | The register width (XLEN) | BYTE | ENUM | The width of register supported by this RISC-V Hart | +| 6Ah | 0100h (v1.0) | Machine Mode native base integer ISA width (M-XLEN) | BYTE | ENUM | The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart | +| 6Bh | 0100h (v1.0) | Reserved | BYTE | ENUM | Placeholder for Hypervisor Mode | +| 6Ch | 0100h (v1.0) | Supervisor Mode native base integer ISA width (S-XLEN) | BYTE | ENUM | The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart | +| 6Dh | 0100h (v1.0) | User Mode native base integer ISA width (U-XLEN) | BYTE | ENUM | The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart | ### Encoding of RISC-V Native Base Integer ISA Width ----------------------------------------------------------