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Pointer Masking in M Mode with VM enabled not Working as intended #1817

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MuhammadHammad001 opened this issue Sep 26, 2024 · 0 comments
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@MuhammadHammad001
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Context:

Hi, I am writing the test for Pointer Masking in M Mode. I have enabled the pointer Masking by setting up the mseccfg and also enabled the virtualization by selecting the SV-48 address translation scheme with MPP as M Mode and MPRV enabled in mstatus register. (hence, returning to M Mode with address translation enabled for data accesses)
The test.S, spike.log and the sail log is attached as well for the reference.

Issue:

When I switch from M to M, at the following instruction, the spike gives a load-page-fauit which is not intended because with pointer masking enabled, this address should be masked and this instruction should be accessed properly as done in the sail log.

May be the reason:

The pointer Masking is enabled when the test is in the M Mode but it may be falsely considering the address as a physical address and masking it accordingly (i.e., setting the upper 16 bits (SV48) equal to zero) because of the current privilege mode = M.

Spike Log on lb with PMM enabled with SV48 address translation scheme in M Mode with MPRV set:

(spike) core   0: 0x0080000000000804 (0x00040483) lb      s1, 0(s0)
core   0: exception trap_load_page_fault, epc 0x0080000000000804
core   0:           tval 0x0000900000000000

Sail Log on lb with PMM enabled with SV48 address translation scheme in M Mode with MPRV set:

mem[X,0x00800000000007F8] -> 0x1413
mem[X,0x00800000000007FA] -> 0x02C4
[2026] [M]: 0x00800000000007F8 (0x02C41413) slli fp, fp, 0x2c
x8 <- 0x0000900000000000

mem[X,0x0080000000000804] -> 0x0483
mem[X,0x0080000000000806] -> 0x0004
[2029] [M]: 0x0080000000000804 (0x00040483) lb s1, 0x0(fp)
mem[R,0x0080000000006900] -> 0x00200000000000DF
mem[R,0x0080000000000000] -> 0x17
x9 <- 0x0000000000000017

Attached files for reference:

spike.log
The following Test File is attached with the .txt extension because github does not allow to upload with .S extension, Please change this after downloading :)
PMM_atomic_01_M_sv48_tag00.txt
PMM_atomic_01_M_sv48_tag00.log

@MuhammadHammad001 MuhammadHammad001 changed the title Pointer Masking in M Mode not Working as intended Pointer Masking in M Mode with VM enabled not Working as intended Sep 26, 2024
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