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Hi, I am writing the test for Pointer Masking in M Mode. I have enabled the pointer Masking by setting up the mseccfg and also enabled the virtualization by selecting the SV-48 address translation scheme with MPP as M Mode and MPRV enabled in mstatus register. (hence, returning to M Mode with address translation enabled for data accesses)
The test.S, spike.log and the sail log is attached as well for the reference.
Issue:
When I switch from M to M, at the following instruction, the spike gives a load-page-fauit which is not intended because with pointer masking enabled, this address should be masked and this instruction should be accessed properly as done in the sail log.
May be the reason:
The pointer Masking is enabled when the test is in the M Mode but it may be falsely considering the address as a physical address and masking it accordingly (i.e., setting the upper 16 bits (SV48) equal to zero) because of the current privilege mode = M.
Spike Log on lb with PMM enabled with SV48 address translation scheme in M Mode with MPRV set:
The text was updated successfully, but these errors were encountered:
MuhammadHammad001
changed the title
Pointer Masking in M Mode not Working as intended
Pointer Masking in M Mode with VM enabled not Working as intended
Sep 26, 2024
Context:
Hi, I am writing the test for Pointer Masking in M Mode. I have enabled the pointer Masking by setting up the
mseccfg
and also enabled the virtualization by selecting theSV-48
address translation scheme with MPP as M Mode and MPRV enabled in mstatus register. (hence, returning to M Mode with address translation enabled for data accesses)The test.S, spike.log and the sail log is attached as well for the reference.
Issue:
When I switch from M to M, at the following instruction, the spike gives a
load-page-fauit
which is not intended because with pointer masking enabled, this address should be masked and this instruction should be accessed properly as done in the sail log.May be the reason:
The pointer Masking is enabled when the test is in the M Mode but it may be falsely considering the address as a physical address and masking it accordingly (i.e., setting the upper 16 bits (SV48) equal to zero) because of the current privilege mode = M.
Spike Log on lb with PMM enabled with SV48 address translation scheme in M Mode with MPRV set:
Sail Log on lb with PMM enabled with SV48 address translation scheme in M Mode with MPRV set:
Attached files for reference:
spike.log
The following Test File is attached with the .txt extension because github does not allow to upload with .S extension, Please change this after downloading :)
PMM_atomic_01_M_sv48_tag00.txt
PMM_atomic_01_M_sv48_tag00.log
The text was updated successfully, but these errors were encountered: