From 9a975bd1673ea8322b0f285ac5547ee304d83ed5 Mon Sep 17 00:00:00 2001 From: Afonso Oliveira Date: Fri, 25 Oct 2024 14:43:56 +0100 Subject: [PATCH 1/2] Add V pseudoinstrutions #110 Signed-off-by: Afonso Oliveira --- src/asm-manual.adoc | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/asm-manual.adoc b/src/asm-manual.adoc index d7e5cf2..d45dc1c 100644 --- a/src/asm-manual.adoc +++ b/src/asm-manual.adoc @@ -1079,6 +1079,32 @@ srli rd, rd, XLEN - 32 |jr rs | jalr x0, rs, 0 | Jump register | |jalr rs | jalr x1, rs, 0 | Jump and link register | |ret | jalr x0, x1, 0 | Return from subroutine | +|vfneg.v vd, vs | vfsgnjn.vv vd, vs, vs | Floating-point vector negate | +|vfabs.v vd, vs | vfsgnjx.vv vd, vs, vs | Floating-point vector absolute value | +|vmclr.m vd | vmxor.mm vd, vd, vd | Vector clear mask register | +|vmfge.vv vd, va, vb, vm | vmfle.vv vd, vb, va, vm | Vector Floating-point >=| +|vmfgt.vv vd, va, vb, vm | vmflt.vv vd, vb, va, vm | Vector Floating-point >| +|vmmv.m vd, vs | vmand.mm vd, vs, vs | Vector copy mask register | +|vmnot.m vd, vs | vmnand.mm vd, vs, vs | Vector invert mask bits| +|vmset.m vd | vmxnor.mm vd, vd, vd | Vector set all mask bits| +|vmsge.vi vd, va, i, vm | vmsgt.vi vd, va, i-1, vm | Vector >= Immediate| +|vmsgeu.vi vd, va, i, vm | vmsgtu.vi vd, va, i-1, vm | Vector >= Immediate, unsigned| +|vmsge.vv vd, va, vb, vm | vmsle.vv vd, vb, va, vm | Vector >= Vector| +|vmsgeu.vv vd, va, vb, vm | vmsleu.vv vd, vb, va, vm | Vector >= Vector, unsigned | +|vmsge.vx vd, va, x, vm | vmsle.vx vd, x, va, vm | Vector >= scalar| +|vmsgeu.vx vd, va, x, vm | vmsleu.vx vd, x, va, vm | Vector >= scalar, unsigned| +|vmsgt.vv vd, va, vb, vm | vmslt.vv vd, vb, va, vm | Vector > Vector| +|vmsgtu.vv vd, va, vb, vm | vmsltu.vv vd, vb, va, vm | Vector > Vector, unsigned| +|vmslt.vi vd, va, i, vm | vmsle.vi vd, va, i-1, vm | Vector < immediate| +|vmsltu.vi vd, va, i, vm | vmsleu.vi vd, va, i-1, vm | Vector < immediate, unsigned | +|vneg.v vd,vs | vrsub.vx vd,vs,x0 | Vector negate | +|vnot.v vd,vs,vm | vxor.vi vd, vs, -1, vm | Vector not | +|vwcvt.x.x.v vd,vs,vm | vwadd.vx vd,vs,x0,vm | Vector widen convert, integer-integer| +|vwcvtu.x.x.v vd,vs,vm | vwaddu.vx vd,vs,x0,vm | Vector widen convert, integer-integer, unsigned| + + + + |call offset |auipc x1, offset[31:12] + From a8b3580da411d08c11aa66b3e8a5b8051545bde5 Mon Sep 17 00:00:00 2001 From: Afonso Oliveira Date: Fri, 25 Oct 2024 16:16:46 +0100 Subject: [PATCH 2/2] Complete V pseudoinstrutions Signed-off-by: Afonso Oliveira --- src/asm-manual.adoc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/asm-manual.adoc b/src/asm-manual.adoc index d45dc1c..84f8c2f 100644 --- a/src/asm-manual.adoc +++ b/src/asm-manual.adoc @@ -1099,8 +1099,13 @@ srli rd, rd, XLEN - 32 |vmsltu.vi vd, va, i, vm | vmsleu.vi vd, va, i-1, vm | Vector < immediate, unsigned | |vneg.v vd,vs | vrsub.vx vd,vs,x0 | Vector negate | |vnot.v vd,vs,vm | vxor.vi vd, vs, -1, vm | Vector not | +|vncvt.x.x.w vd,vs,vm | vnsrl.wx vd,vs,x0,vm | Vector narrow convert element | |vwcvt.x.x.v vd,vs,vm | vwadd.vx vd,vs,x0,vm | Vector widen convert, integer-integer| |vwcvtu.x.x.v vd,vs,vm | vwaddu.vx vd,vs,x0,vm | Vector widen convert, integer-integer, unsigned| +|vl1r.v v3, x0 | vl1re8.v v3, x0 | Equal to vl1re8.v | +|vl2r.v v2,x0 | vl2re8.v v2, x0 | Equal to vl2re8.v | +|vl4r.v v4,x0 | vl4re8.v v4, x0 | Equal to vl4re8.v | +|vl8r.v v8,x0 | vl8re8.v v8, x0 | Equal to vl8re8.v |