diff --git a/AArch64_boot/boot_mon.h b/AArch64_boot/boot_mon.h index 44749c5..656b44d 100644 --- a/AArch64_boot/boot_mon.h +++ b/AArch64_boot/boot_mon.h @@ -1,34 +1,25 @@ -;/* -; * Copyright (c) 2015-2016, Renesas Electronics Corporation -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * -; * - Redistributions of source code must retain the above copyright notice, -; * this list of conditions and the following disclaimer. -; * -; * - Redistributions in binary form must reproduce the above copyright -; * notice, this list of conditions and the following disclaimer in the -; * documentation and/or other materials provided with the distribution. -; * -; * - Neither the name of Renesas nor the names of its contributors may be -; * used to endorse or promote products derived from this software without -; * specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; * POSSIBILITY OF SUCH DAMAGE. -; */ - +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ ;#RWDT .EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter .EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A diff --git a/AArch64_boot/boot_mon.s b/AArch64_boot/boot_mon.s index c78a08b..742f989 100644 --- a/AArch64_boot/boot_mon.s +++ b/AArch64_boot/boot_mon.s @@ -1,189 +1,193 @@ -;/* -; * Copyright (c) 2015-2018, Renesas Electronics Corporation -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * -; * - Redistributions of source code must retain the above copyright notice, -; * this list of conditions and the following disclaimer. -; * -; * - Redistributions in binary form must reproduce the above copyright -; * notice, this list of conditions and the following disclaimer in the -; * documentation and/or other materials provided with the distribution. -; * -; * - Neither the name of Renesas nor the names of its contributors may be -; * used to endorse or promote products derived from this software without -; * specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; * POSSIBILITY OF SUCH DAMAGE. -; */ - -;# W0-W30 : 32bit Register (W30=Link Register) -;# X0-X30 : 64bit Register (X30=Link Register) -;# WZR : 32bit Zero Register -;# XZR : 64bit Zero Register -;# WSP : 32bit Stack Pointer -;# SP : 64bit Stack Pointer - - .INCLUDE "boot_mon.h" - .ALIGN 4 - -;# Initialize registers -Register_init: - LDR X0, =0 - LDR X1, =0 - LDR X2, =0 - LDR X3, =0 - LDR X4, =0 - LDR X5, =0 - LDR X6, =0 - LDR X7, =0 - LDR X8, =0 - LDR X9, =0 - LDR X10, =0 - LDR X11, =0 - LDR X12, =0 - LDR X13, =0 - LDR X14, =0 - LDR X15, =0 - LDR X16, =0 - LDR X17, =0 - LDR X18, =0 - LDR X19, =0 - LDR X20, =0 - LDR X21, =0 - LDR X22, =0 - LDR X23, =0 - LDR X24, =0 - LDR X25, =0 - LDR X26, =0 - LDR X27, =0 - LDR X28, =0 - LDR X29, =0 - LDR X30, =0 - -Set_EnableRAM: - LDR X0, =0xE67F0018 - LDR W1, =0x00000001 ;#Enable DRAM/SECRAM/PUBRAM - STR W1, [X0] - -;# Loader - LDR x0, =__STACKS_END__ - MSR SP_EL0,x0 - MSR SP_EL1,x0 - MSR SP_EL2,x0 - MOV sp,x0 - MSR ELR_EL1,x0 - MSR ELR_EL2,x0 - MSR ELR_EL3,x0 - MSR SPSR_EL1,x0 - MSR SPSR_EL2,x0 - MSR SPSR_EL3,x0 - - -;# Board Initialize -.ifdef Area0Boot - -Init_set_WDT: - LDR W0, =RWDT_RWTCSRA - LDR W1, =0xA5A5A500 ;#Timer disabled - STR W1, [X0] - -Init_set_SYSWDT: - LDR W0, =SYSWDT_WTCSRA - LDR W1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled) - STR W1, [X0] - -.endif - - - -;# Enable cache -;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) - mrs x0, sctlr_el3 - orr x0, x0, #(0x1 << 12) - orr x0, x0, #(0x1 << 1) - orr x0, x0, #(0x1 << 3) - msr sctlr_el3, x0 - isb - - - /* clear bss section */ - mov X0, #0x0 - ldr X1, =__BSS_START__ - ldr X2, =__BSS_SIZE__ -bss_loop: - subs X2, X2, #4 - bcc bss_end - str W0, [X1, X2] - b bss_loop -bss_end: - -.ifdef Area0Boot - /* copy data section */ - ldr X0, =__DATA_COPY_START__ - ldr X1, =__DATA_START__ - ldr X2, =__DATA_SIZE__ -data_loop: - subs X2, X2, #4 - bcc data_end - ldr W3, [X0, X2] - str W3, [X1, X2] - b data_loop -.endif - -data_end: - - BL InitPORT - BL InitGPIO - BL InitLBSC - BL InitScif - BL InitDram - - cmp x0, #0 - beq 2f /* InitDram success */ - mov x19, x0 - - ldr x0, =dram_err_msg - mov x1, #0 - bl PutStr - - mov x0, x19 /* return value of InitDram */ - ldr x1, =str_buf - ldr x2, =cnt - bl Hex2Ascii - mov x0, x1 - mov x1, #1 - bl PutStr -1: - wfi /* InitDram fail */ - b 1b - -2: - BL Main - - - .section .rodata -dram_err_msg: - .asciz "InitDram error=0x" - - .section .bss - .align 4 -cnt: - .space 4 -str_buf: - .space 16 - - .END - +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +#define CONFIG_ARM_ERRATA_855873 1 + +#define EL3 1 + +.global _prestart +.global _boot + +.global __el3_stack +.global _vector_table + +.set EL3_stack, __el3_stack + +.set TT_S1_FAULT, 0x0 +.set TT_S1_TABLE, 0x3 + +.set vector_base, _vector_table +.set rvbar_base, 0xA3F02020 // CA53_RVA0CRL + +.set counterfreq, 24000000 +.set MODE_EL1, 0x5 +.set DAIF_BIT, 0x1C0 + +.section .boot,"ax" + + +/* this initializes the various processor modes */ + +_prestart: +_boot: + mov x0, #0 + mov x1, #0 + mov x2, #0 + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + mov x7, #0 + mov x8, #0 + mov x9, #0 + mov x10, #0 + mov x11, #0 + mov x12, #0 + mov x13, #0 + mov x14, #0 + mov x15, #0 + mov x16, #0 + mov x17, #0 + mov x18, #0 + mov x19, #0 + mov x20, #0 + mov x21, #0 + mov x22, #0 + mov x23, #0 + mov x24, #0 + mov x25, #0 + mov x26, #0 + mov x27, #0 + mov x28, #0 + mov x29, #0 + mov x30, #0 + +OKToRun: + + mrs x0, currentEL + cmp x0, #0xC + beq InitEL3 + + b error // go to error if current exception level is neither EL3 +InitEL3: + /*Set vector table base address*/ + ldr x1, =vector_base + msr VBAR_EL3,x1 + + /* Set reset vector address */ + /* Get the cpu ID */ + mrs x0, MPIDR_EL1 + and x0, x0, #0xFF + mov w0, w0 + ldr w2, =rvbar_base + /* calculate the rvbar base address for particular CPU core */ + mov w3, #0x8 + mul w0, w0, w3 + add w2, w2, w0 + /* store vector base address to RVBAR */ + mov w3, w1 + str w3, [x2] + lsr x3, x1, #32 + mov w3, w3 + str w3, [x2, #4] + + /*Define stack pointer for current exception level*/ + ldr x2,=EL3_stack + mov sp,x2 + + /* Enable Trapping of SIMD/FPU register for standalone BSP */ + mov x0, #0 + msr CPTR_EL3, x0 + isb + + /* program the counter frequency */ + bl SYC_enable + bl CMN_InitSysCnt + ldr x0, =counterfreq + msr CNTFRQ_EL0, x0 + + /*Enable hardware coherency between cores*/ + mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register + orr x0, x0, #(1 << 6) //Set the SMPEN bit + msr S3_1_c15_c2_1, x0 //Write EL1 CPU Extended Control Register + isb + + /********************************************** + * Set up memory attributes + * This equates to: + * 0 = b01000100 = Normal, Inner/Outer Non-Cacheable + * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA + * 2 = b00000000 = Device-nGnRnE + * 3 = b00000100 = Device-nGnRE + * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA + **********************************************/ + ldr x1, =0x000000BB0400FF44 + msr MAIR_EL3, x1 + + /********************************************** + * Set up TCR_EL3 + * Physical Address Size PS = 001 -> 36bits 64GB + * Granual Size TG0 = 00 -> 4KB + * size offset of the memory region T0SZ = 30 -> (region size 2^(64-30) = 2^34) + ***************************************************/ + ldr x1,=0x8081351E + msr TCR_EL3, x1 + isb + + /* Enable SError Exception for asynchronous abort */ + mrs x1,DAIF + bic x1,x1,#(0x1<<8) + msr DAIF,x1 + + /* Configure SCTLR_EL3 */ + ldr x1, = 0x30C50830 + orr x1, x1, #(1 << 3) //Enable SP alignment check + msr SCTLR_EL3, x1 + dsb sy + isb + + b _startup //jump to start + + b error // present exception level and selected exception level mismatch + +error: b error + +_startup: + + /* clear bss section */ + mov X0, #0x0 + ldr X1, =__bss_start + ldr X2, =__bss_end +bss_loop: + cmp X1,X2 + bge bss_end + str X0, [X1], #8 + b bss_loop +bss_end: + + bl Main + +exit: /* should never get here */ + bl exit + +.end + diff --git a/AArch64_boot/stack.s b/AArch64_boot/stack.s index 2065a18..500a85c 100644 --- a/AArch64_boot/stack.s +++ b/AArch64_boot/stack.s @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ .section writer_stack, "aw", %nobits diff --git a/AArch64_boot/vectors.S b/AArch64_boot/vectors.S new file mode 100644 index 0000000..8834b2f --- /dev/null +++ b/AArch64_boot/vectors.S @@ -0,0 +1,96 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : vectors.s + * Version : 0.9 + * Description : vector table for the Cortex A53 processor + ******************************************************************************/ + +.org 0 +.text + +.globl _boot +.globl _vector_table + +.org 0 + +.section .vectors, "a" + +_vector_table: + +.set VBAR, _vector_table + +.org VBAR + b _boot + +.org (VBAR + 0x80) + b . + +.org (VBAR + 0x100) + b . + +.org (VBAR + 0x180) + b . + + +.org (VBAR + 0x200) + b . + +.org (VBAR + 0x280) + b . + +.org (VBAR + 0x300) + b . + +.org (VBAR + 0x380) + b . + + + +.org (VBAR + 0x400) + b . + +.org (VBAR + 0x480) + b . + +.org (VBAR + 0x500) + b . + +.org (VBAR + 0x580) + b . + +.org (VBAR + 0x600) + b . + +.org (VBAR + 0x680) + b . + +.org (VBAR + 0x700) + b . + +.org (VBAR + 0x780) + b . + +.org (VBAR + 0x1000) + +.end diff --git a/AArch64_lib/libusb.a b/AArch64_lib/libusb.a deleted file mode 100755 index 58c0b91..0000000 Binary files a/AArch64_lib/libusb.a and /dev/null differ diff --git a/HardwareSetup.c b/HardwareSetup.c new file mode 100644 index 0000000..1f0e70f --- /dev/null +++ b/HardwareSetup.c @@ -0,0 +1,188 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : HardwareSetup.c + * Description : + ******************************************************************************/ + + +#include +#include + +#include "rdk_common.h" +#include "rdk_cmn_cpg.h" +#include "rdk_cmn_pmc.h" +#include "rdk_pfc.h" + +#include "HardwareSetup.h" + +#define UART_BAUDRATE 115200 + + +void InitPFC(void){ + /* set select function for URT */ + PFC_SetPinFunc(PFC_SELECT_URT0); + /* set select function for EMM */ + PFC_SetPinFunc(PFC_SELECT_EMM); +} + +void InitCPG(void) +{ + int t; + uint32_t clock_sts = (CPG_CLKSTATUS_DIVA | CPG_CLKSTATUS_DIVD | CPG_CLKSTATUS_DIVE); + t = 0; + + //Check complete status + while (1000000 > t++) //1sec time out + { + if (0 == (CPG_ReadReg(CPG_CLKSTATUS) & clock_sts)) { + break; + } + CMN_DelayInUS(10); + } + + //Set dividor and selector for CA53 clock and UART0, eMM + CPG_WriteReg(CPG_CA53_DDIV, (CPG_CA53_DDIV_WEN_DIVA | CPG_CA53_DDIV_DIVA_SET_MIN)); //CA53 clock:996MHz + + CPG_WriteReg(CPG_SYS_DDIV, + (CPG_SYS_DDIV_WEN_DIVD) | (CPG_SYS_DDIV_DIVD_SET_MIN << CPG_SYS_DDIV_DIVD_SET_SHIFT) | //CPG_MPCLK:200MHz + (CPG_SYS_DDIV_WEN_DIVE) | (CPG_SYS_DDIV_DIVE_SET_MIN << CPG_SYS_DDIV_DIVE_SET_SHIFT) //CPG_SPCLK:100MHz + ); + + CPG_WriteReg(CPG_CLK48_DSEL, + (CPG_CLK48_DSEL_WEN_SELD | CPG_CLK48_DSEL_SELD) | //Set Selector D clcok + (CPG_CLK48_DSEL_WEN_SELE | CPG_CLK48_DSEL_SELE) //Set Selector E clcok + ); + + CPG_WriteReg(CPG_SDIEMM_SSEL, (CPG_SDIEMM_SSEL_WEN_SELSDI | CPG_SDIEMM_SSEL_SELSDI)); //SDI/EMM core clock: 200MHz + CPG_WriteReg(CPG_URT_RCLK_SSEL, (CPG_URT_RCLK_SSEL_WEN_SELW0 | 0x0)); //Set UART0 clock : 48MHz + + //Check complete status + t = 0; + while (1000000 > t++) //1sec time out + { + if (0 == (CPG_ReadReg(CPG_CLKSTATUS) & clock_sts)) { + break; + } + CMN_DelayInUS(10); + } + + /* enable supply clock to URT(URT_CLK[0]/URT_PCLK) and eMMC(EMM_CLK_HS/EMM_IMCLK2/EMM_IMCLK/EMM_ACLK) */ + CPG_SetClockCtrl(15, 0x0030, 0x0030); //UART + CPG_SetClockCtrl(3, 0x0f00, 0x0f00); //eMMC + + /* asset RESET to URT0 and eMMC */ + CPG_SetResetCtrl(6, 0x0400, 0x0000); //UART + CPG_SetResetCtrl(3, 0x0004, 0x0000); //eMMC + + CPG_WaitResetMon(0, (CPG_RST_MON_URT|CPG_RST_MON_EMM), (CPG_RST_MON_URT|CPG_RST_MON_EMM)); + + /* deasset RESET to URT0 and eMMC */ + CPG_SetResetCtrl(6, 0x0400, 0x0400); //UART + CPG_SetResetCtrl(3, 0x0004, 0x0004); //eMMC + + CPG_WaitResetMon(0, (CPG_RST_MON_URT|CPG_RST_MON_EMM), 0); + + return; +} + +void SYC_enable(void) +{ + uint32_t tmp; + + /* enable SYC_CNT_CLK */ + CPG_SetClockCtrl(8, (1<<12), (1<<12)); + + /* enable ICB_SYC_CNT_CLK */ + CPG_SetClockCtrl(16, (1<<15), (1<<15)); + + do{ + CPG_GetClockCtrl(8, &tmp); + } while((tmp & (1<<12)) == 0); + + /* SYC_RST_N(TYPE-B) OFF */ + CPG_SetResetCtrl(5, (1<<9), (1<<9)); +} + +void PowerOnRAMB(void) +{ + + uint32_t value; + + /** A */ + /** A-1) Set power on time to register */ + /** Use the initial value */ + + /** A-2) Start sequence to power on PD_RFX */ + PMC_WriteReg(PMC_SPLY_ENA,(PMC_SPLY_ENA_PD_ON|PMC_SPLY_ENA_PD_RFX)); + /** A-3) Wait for Power on process */ + while (0 == (PMC_INT_STS_PD_DONE & PMC_ReadReg(PMC_INT_STS))) + ; + + /** A-4) Clear to interrupt status */ + PMC_WriteReg(PMC_INT_CLR, PMC_INT_CLR_PD_DONE); + /** B) release RESET and start supplies clock */ + /** B-1) release RESET for PD_RFX */ + CPG_WriteReg(CPG_PD_RST, + (CPG_PD_RST_WEN_RFX_RSTB | CPG_PD_RST_RFX_RSTB)); + + /** B-2) start supplies clock for target IPs */ + + + /** CPG_CLK_ON23 : CLK0, 1 */ + CPG_SetClockCtrl(23, 0x0003, 0x0003); + + /** B-3) turn off isolation for PD_RFX */ + /** B-4) check turned off isolation */ + PMC_WriteReg(PMC_PD_RFX_ISOEN, PMC_PD_ISO_DONE); + while (0 == (PMC_PD_ISO_DONE & PMC_ReadReg(PMC_PD_RFX_ISOEN))) + ; + + /** B-5) release RESET for target IPs */ + /** CPG_RST12 : UNIT0, 1, 2, 3 */ + CPG_SetResetCtrl(12,0x0001, 0x0001); + /** B-6) 50nsec wait */ + CMN_DelayInUS(1); + + /** B-9) release RESET for PD_RFX ICB */ + /** CPG_RST7 : UNIT4 */ + CPG_SetResetCtrl(7, 0x0010, 0x0010); + + /** B-10) 50nsec wait */ + CMN_DelayInUS(1); + + /** B-11) start supply clock for PD_RFX ICB */ + /** CPG_CLK_ON16 : CLK9 */ + CPG_SetClockCtrl(16, 0x0200, 0x0200); + + /** CPG_CLK_ON17 : CLK4 */ + CPG_SetClockCtrl(17, 0x0010, 0x0010); + + /** C) connecting bus */ + /** C-1) setting connecting bus */ + PMC_WriteReg(PMC_IDLE_REQ, (PMC_IDLE_RAW_IDLE_PD_RFX)); + + /** C-2) check connecting bus */ + while (0 == (PMC_IDLE_STS_PD_RFX_ACT_DONE & PMC_ReadReg(PMC_IDLE_STS))) + ; +} diff --git a/LICENSE.md b/LICENSE.md index 4966428..f79c663 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -1,6 +1,6 @@ BSD 3-Clause License -Copyright (c) 2015-2019, Renesas Electronics Corporation +Copyright (c) 2021, Renesas Electronics Corporation All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/Message.c b/Message.c index 041e557..034abee 100644 --- a/Message.c +++ b/Message.c @@ -1,33 +1,26 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + #include "dgtable.h" /********************** @@ -35,13 +28,6 @@ ***********************/ const char *const AllHelpMess[ALL_HELP_MESS_LINE] = { -#if SERIAL_FLASH == 1 - " SPI Flash write command", - " XCS erase program to SPI Flash", - " XLS2 write program to SPI Flash", - " XLS3 write program to SPI Flash(Binary)", - "", -#endif /* SERIAL_FLASH == 1 */ #if EMMC == 1 " eMMC write command", " EM_DCID display register CID", diff --git a/README.md b/README.md index 0dcf658..1bca59d 100644 --- a/README.md +++ b/README.md @@ -1,640 +1,275 @@ -# README of the RZ/G2 Flash Writer - -
-Renesas Electronics Corporation - -Dec-02-2020 -
- -The RZ/G2 flash writer is sample software for Renesas RZ/G2 Group MPUs. -The RZ/G2 flash writer downloads binary images from Host PC via SCIF or USB and writes those binary images to Serial NOR Flash or eMMC. - -## 1. Overview - -This document explains about the RZ/G2 flash writer sample software for Renesas RZ/G2 Group MPUs. - -The RZ/G2 flash writer is downloaded from the Host PC via SCIF or USB by the boot ROM container within the RZ/G2 device. - -The RZ/G2 flash writer downloads binary images from Host PC via SCIF or USB, and writes those binary images to Serial NOR Flash (hereafter referred to as “Serial Flash”) or eMMC. - -The RZ/G2 flash writer's Serial Flash writing support is for on-board Serial NOR Flash devices (i.e. W25M512JW and others). - -The RZ/G2 flash writer eMMC writing support is for High Speed SDR (i.e. 50MHz) and x8 bus width mode. - -[Chapter 2](#2-operating-environment) describes the operating environment. - -[Chapter 3](#3-software) describes the software. - -[Chapter 4](#4-how-to-build-the-rzg2-flash-writer) explains example of how to build the RZ/G2 flash writer. - -[Chapter 5](#5-how-to-run-the-rzg2-flash-writer) explains example of how to perform the RZ/G2 flash writer. - -[Chapter 6](#6-error-case-to-handle) explains how to handle error case. - -[Chapter 7](#7-revision-history) explains revision history. - -*Note) This sample software does not support file systems. Therefore, only raw binary images can be downloaded and programmed into Serial NOR Flash or eMMC.* - -## 1.2. License - -BSD-3-Clause (please see file [LICENSE.md](LICENSE.md) for the details) - -## 1.3. Notice - -The RZ/G2 flash writer is distributed as a sample software from Renesas without any warranty or support. - -## 1.4. Contributing - -To contribute to this software, you should email patches to renesas-rz@renesas.com. Please send .patch files as email attachments, not embedded in the email body. - -## 1.5. References - -The following table shows the document related to this function. - -### Related Document - -| Number | Issuer | Title | Edition | -|--------|---------|----------------------------------------------------------------|-------------------| -| 1 | JEDEC | Embedded Multi-Media Card (eMMC) Electrical Standard (5.01) | JESD84-B50.1 | -| 2 | Renesas | Release Note for Verified Linux Package for 64bit kernel | Rev.1.01 or later | -| 3 | Renesas | RZ/G2 Yocto recipe Start-Up Guide | Rev.1.01 or later | -| 4 | Renesas | RZ/G2 Reference Boards Start-up Guide | Rev.1.01 or later | - -## 2. Operating Environment - -### 2.1. Hardware Environment - -The following table lists the hardware needed to use this utility. - -#### Hardware environment - -| Name | Note | -|--------------|---------------------------------------------| -| Target board | Hoperun HiHope RZ/G2[M,N,H] platform | -| | Silicon Linux RZ/G2E evaluation kit (EK874) | -| Host PC | Ubuntu Desktop 14.04(64bit) or later | - -The following table shows Serial Flash and eMMC support for each MPU. - -##### Serial Flash / eMMC support status of each MPU - -| MPU | Read/Write the Serial Flash | Boot from the Serial Flash | Read/Write the eMMC | Boot from the eMMC | MMC interface | -|--------|-----------------------------|----------------------------|---------------------|--------------------|---------------| -| RZ/G2H | Support | Support | Support | Support | MMC1 | -| RZ/G2M | Support | Support | Support | Support *1 | MMC1 | -| RZ/G2N | Support | Support | Support | Support | MMC1 | -| RZ/G2E | Support | Support | Support *2 | Support *2 | MMC1 | - -\*1: Some early samples are not support booting from the eMMC. Please contact to Renesas sales for further details. - -\*2: eMMC is not implemented on the Silicon Linux RZ/G2E evaluation kit Rev.A - C boards. -Rev.D or later boards can use eMMC, but note that the support is disabled in default settings. - -## 2.2. Software Environment - -The following table lists the software required to use this sample software. - -### Software environment - -| Name | Note | -|---------------------|------------------------------------------------------------------| -| Linaro Toolchain *1 | Linaro Binary Toolchain Release GCC 7.3-2018.05 for aarch64-elf. | -| Yocto SDK *1 *2 | Yocto SDK built from Yocto environment for RZ/G2 Group | - -\*1: One of the above toolchains are required. - -\*2: Regarding how to get the Yocto SDK, refer to [Related Document](#related-document) No.2 or No.3. - -## 3. Software - -### 3.1. Function - -This package has the following capabilities: - -- Write binary images to the Serial Flash. -- Erase the Serial Flash. -- Display the CID/CSD/EXT_CSD registers of an eMMC. -- Modify the EXT_CSD registers of an eMMC. -- Write binary images to the boot partition of an eMMC. -- Write binary images to the user data area of an eMMC. -- Erase the boot partition of an eMMC. -- Erase the user data area of an eMMC. -- Change the SCIF baud rate setting. -- Display the command help. - -### 3.3. Option setting - -The RZ/G2 flash writer support the following build options. - -#### 3.3.2. BOARD - -Select from the following table according to the board settings. - -If this option is not selected, the default value is HIHOPE. - -| BOARD | BOARD setting | -|----------|----------------------------------------------------------------------------| -| HIHOPE | Generate binary that works on Hoperun HiHope RZ/G2[MN] platform. (default) | -| EK874 | Generate binary that works on Silicon Linux RZ/G2E evaluation kit. | - -#### 3.3.5. SERIAL_FLASH - -Select from the following table according to the Serial Flash writing function. - -If this option is not selected, the default value is ENABLE. - -##### Association table for the SERIAL_FLASH value and valid Serial Flash writing function settings - -| SERIAL_FLASH | Serial Flash writing setting | -|--------------|-------------------------------------------------------| -| ENABLE | Serial Flash writing function is available. (default) | -| DISABLE | Serial Flash writing function is not available. | - -#### 3.3.6 eMMC - -Select from the following table according to the eMMC writing function. - -If this option is not selected, the default value is ENABLE. - -##### Association table for the eMMC value and valid eMMC writing function settings - -| EMMC | Serial Flash writing setting | -|---------|-------------------------------------------------------------| -| ENABLE | eMMC writing function is available. (default for HIHOPE) | -| DISABLE | eMMC writing function is not available. (default for EK874) | - -#### 3.3.7 USB - -Select from the following table according to the USB download mode support. - -If this option is not selected, the default value is ENABLE. - -##### Association table for the USB communications values - -| USB | USB Communications | -|---------|--------------------------------------------------------------------| -| ENABLE | USB communication to Host PC is available. (default for HIHOPE) | -| DISABLE | USB communication to Host PC is not available. (default for EK874) | - -### 3.4. Command specification - -The following table shows the command list. - -#### Command list - -| Command | Description | -|----------|----------------------------------------------------------------------------------------------------| -| XLS2 | Write the S-record format images to the Serial Flash. | -| XCS | Erase the Serial Flash. | -| EM_DCID | Display the CID registers of eMMC. | -| EM_DCSD | Display the CSD registers of eMMC. | -| EM_DECSD | Display the EXT_CSD registers of eMMC. | -| EM_SECSD | Modify the EXT_CSD registers of eMMC. | -| EM_W | Write to the S-record format images to the user data area of eMMC, and the boot partition of eMMC. | -| EM_WB | Write to the raw binary images to the user data area of eMMC, and the boot partition of eMMC. | -| EM_E | Erase the user data area of eMMC, and the boot partition of eMMC. | -| SUP | Change the SCIF baud rate setting. | -| H | Display the command help. | - -#### 3.4.1. Write to the S-record format images to the Serial Flash - -This command writes the S-record format image to Serial Flash. - -##### Example of writing data for the Serial Flash boot - -| Filename | Program Top Address | Flash Save Address | Description | -|--------------------------------|---------------------|--------------------|------------------------| -| bootparam_sa0.srec | H'E6320000 | H'000000 | Loader(Boot parameter) | -| bl2-``.srec | H'E6304000 | H'040000 | Loader | -| cert_header_sa6.srec | H'E6320000 | H'180000 | Loader(Certification) | -| bl31-``.srec | H'44000000 | H'1C0000 | ARM Trusted Firmware | -| u-boot-elf-``.srec | H'50000000 | H'300000 | U-boot | - -The following shows the procedure of this command. -The values must be entered as **hexadecimal**. - -*Note) The following procedure is an example on HiHope RZ/G2M board.* - -*Note) If Flash is already blank, you will not be asked to erase* - -```text ->XLS2 -===== Qspi writing of RZ/G2 Board Command ============= -Load Program to Spiflash -Writes to any of SPI address. - Winbond : W25M512JW -Program Top Address & Qspi Save Address -===== Please Input Program Top Address ============ - Please Input : H'e6304000 <<<< Enter "e6304000" here - -===== Please Input Qspi Save Address === - Please Input : H'40000 <<<< Enter "40000" here -SPI Data Clear(H'FF) Check :H'00040000-0005FFFF,Clear OK?(y/n) <<<< Enter "y" here -Work RAM(H'50000000-H'53FFFFFF) Clear.... -please send ! ('.' & CR stop load) -SPI Data Clear(H'FF) Check :H'00040000-0005FFFF Erasing...Erase Completed -SAVE SPI-FLASH....... -======= Qspi Save Information ================= - SpiFlashMemory Stat Address : H'00040000 - SpiFlashMemory End Address : H'0005B0E3 -=========================================================== -> -``` - -Image writing has been completed. - -#### 3.4.3. Erase the Serial NOR Flash - -This command erases all sectors of Serial Flash. - -The following shows the procedure of this command. - -*Note) The following procedure is an example on HiHope RZ/G2M board.* - -```text ->XCS -ALL ERASE SpiFlash memory -Clear OK?(y/n) -``` - -Please enter the 'y' key. - -```text ->XCS -ALL ERASE SpiFlash memory - Winbond : W25M512JW - ERASE QSPI-FLASH (60sec[typ]).... complete! -> -``` - -Selected Serial Flash has been erased. - -#### 3.4.4. Display the CID registers command - -This command displays the contents of the CID registers of the eMMC. - -The following shows the procedure of this command. - -```text -EM_DCID - -[CID Field Data] -[127:120] MID 0x13 -[113:112] CBX 0x01 -[111:104] OID 0x4E -[103: 56] PNM 0x52314A35374C -[ 55: 48] PRV 0x10 -[ 47: 16] PSN 0x18E3D660 -[ 15: 8] MDT 0x73 -[ 7: 1] CRC 0x00 -``` - -#### 3.4.5. Display the CSD registers command - -This command displays the contents of the CSD registers of eMMC. - -The following shows the procedure of this command. - -```text ->EM_DCSD - -[CSD Field Data] -[127:126] CSD_STRUCTURE 0x03 -[125:122] SPEC_VERS 0x04 -[119:112] TAAC 0x7F -... -[ 11: 10] FILE_FORMAT 0x00 -[ 9: 8] ECC 0x00 -[ 7: 1] CRC 0x00 -``` - -#### 3.4.6. Display the EXT_CSD registers command - -This command displays the contents of the EXT_CSD registers of the eMMC. - -The following shows the procedure of this command. - -```text ->EM_DECSD - -[EXT_CSD Field Data] -[505:505] EXT_SECURITY_ERR 0x00 -[504:504] S_CMD_SET 0x01 -[503:503] HPI_FEATURES 0x01 -... -[142:140] ENH_SIZE_MULT 0x000000 -[139:136] ENH_START_ADDR 0x00000000 -[134:134] SEC_BAD_BLK_MGMNT 0x00 -``` - -#### 3.4.7. Modify the EXT_CSD registers of eMMC command - -This command modifies the contents of the EXT_CSD registers in the eMMC. - -The values must be entered as **hexadecimal**. - -Example: - -```text ->EM_SECSD - Please Input EXT_CSD Index(H'00 - H'1FF) :b1 - EXT_CSD[B1] = 0x00 - Please Input Value(H'00 - H'FF) :a - EXT_CSD[B1] = 0x0A -``` - -#### eMMC Boot Settings - -Please note that for eMMC booting, the following EXT_CSD registers need to be modified: - - EXT_CSD[**B1**] = **0x0A** - - EXT_CSD[**B3**] = **0x08** - - -#### 3.4.8. Write to the S-record format images to the eMMC - -This command writes the S-record format image to any partition of the eMMC. - -##### Example of writing data for the eMMC boot - -| Filename | Program Top Address | eMMC Save Partition | eMMC Save Sectors | Description | -|--------------------------------|---------------------|---------------------|-------------------|------------------------| -| bootparam_sa0.srec | H'E6320000 | boot partition1 | H'000000 | Loader(Boot parameter) | -| bl2-``.srec | H'E6304000 | boot partition1 | H'00001E | Loader | -| cert_header_sa6.srec | H'E6320000 | boot partition1 | H'000180 | Loader(Certification) | -| bl31-``.srec | H'44000000 | boot partition1 | H'000200 | ARM Trusted Firmware | -| u-boot-elf-``.srec | H'50000000 | boot partition2 | H'000000 | U-boot | - -The following shows the procedure of this command. -The values must be entered as **hexadecimal**. -Please enter the start sector number of the write image in hexadecimal. Sector size is 512 bytes. -Please enter the program top address of the write image in hexadecimal. -Please download the write image in S-record format. - -```text ->EM_W -EM_W Start -------------- ---------------------------------------------------------- -Please select,eMMC Partition Area. - 0:User Partition Area : 30535680 KBytes - eMMC Sector Cnt : H'0 - H'03A3DFFF - 1:Boot Partition 1 : 16384 KBytes - eMMC Sector Cnt : H'0 - H'00007FFF - 2:Boot Partition 2 : 16384 KBytes - eMMC Sector Cnt : H'0 - H'00007FFF ---------------------------------------------------------- - Select area(0-2)>1 <<<< Enter "1" here --- Boot Partition 1 Program ----------------------------- -Please Input Start Address in sector :0000 <<<< Enter "0000" here -Please Input Program Start Address : E6320000 <<<< Enter "E6320000" here -Work RAM(H'50000000-H'50FFFFFF) Clear.... -please send ! ('.' & CR stop load) -SAVE -FLASH....... -EM_W Complete! -``` - -Image writing has been completed. - -#### 3.4.10. Erase the eMMC - -This command erases any partition of the eMMC. - -The following shows the procedure of this command. - -```text ->EM_E -EM_E Start -------------- ---------------------------------------------------------- -Please select,eMMC Partition Area. - 0:User Partition Area : 30539776 KBytes - eMMC Sector Cnt : H'0 - H'03A3FFFF - 1:Boot Partition 1 : 8192 KBytes - eMMC Sector Cnt : H'0 - H'00003FFF - 2:Boot Partition 2 : 8192 KBytes - eMMC Sector Cnt : H'0 - H'00003FFF ---------------------------------------------------------- - Select area(0-2)>0 <<<< Enter "0" here --- User Partition Area Program -------------------------- -EM_E Complete! -``` - -Selected partition has been erased. - -#### 3.4.11. Change the SCIF baud rate setting - -This command will change the baud rate of the SCIF. - -Baud rate depends on the MPU and the SCIF clock setting on the board. - -##### Baud rate settings after command execution - -| Board | Baud rate at startup | Baud rate at After command execution | -|---------------|---------------------:|-------------------------------------:| -| HIHOPE, EK874 | 115200bps | 921600bps | - -*Note) The baud rate that has been changed in this command cannot be undone until the power is turned off.* - -The following shows the procedure of this command. - -```text ->SUP -Scif speed UP -Please change to 921.6Kbps baud rate setting of the terminal. -``` - -#### 3.4.12. Display the command help - -Displays a description of the commands. - -The following shows the procedure of this command. - -```text ->H - HyperFlash/SPI Flash write command - XCS erase program to HyperFlash/SPI Flash - XLS2 write program to HyperFlash/SPI Flash - XLS3 write program to HyperFlash/SPI Flash(Binary) - - eMMC write command - EM_DCID display register CID - EM_DCSD display register CSD - EM_DECSD display register EXT_CSD - EM_SECSD change register EXT_CSD byte - EM_W write program to eMMC - EM_WB write program to eMMC (Binary) - EM_E erase program to eMMC - SUP Scif speed UP (Change to speed up baud rate setting) - H help -> -``` - -## 4. How to build the RZ/G2 flash writer - -This chapter is described how to build the RZ/G2 flash writer. -Command is executed in the user's home directory (~ /). - -### 4.1. Prepare the compiler - -Gets cross compiler for linaro or setup the Yocto SDK. - -Linaro toolchain: - -```shell -cd ~/ -wget https://releases.linaro.org/components/toolchain/binaries/7.3-2018.05/aarch64-elf/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-elf.tar.xz -tar xvf gcc-linaro-7.3.1-2018.05-x86_64_aarch64-elf.tar.xz -``` - -Yocto SDK: - -```shell -source /opt/poky/2.4.3/environment-setup-aarch64-poky-linux -``` - -### 4.2. Prepare the source code - -Get the source code of RZ/G2 flash writer. - -```shell -cd ~/ -git clone https://github.com/renesas-rz/rzg2_flash_writer.git -cd rzg2_flash_writer -git checkout -b v1.04 v1.04 -``` - -### 4.3. Build the RZ/G2 flash writer - -S-record file will be built by the following command. - -Linaro toolchain: - -```shell -make -f makefile.linaro clean -CROSS_COMPILE=~/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-elf/bin/aarch64-elf- make -f makefile.linaro BOARD=HIHOPE -``` - -*Note) Makefile for linaro toolchain is changed from `makefile` to `makefile.linaro` at v1.01.* - -Yocto SDK: - -```shell -make clean -make BOARD=HIHOPE -``` - -Output image will be available in the following directory. - -* ./AArch64_output/AArch64_Flash_writer_SCIF_DUMMY_CERT_E6300400_hihope.mot - -The target file name changes depending on the build options. - -The following table lists the relationship between build option and target files. - -#### Description of build options and target files - -| Build options | Target filename | -|---------------|----------------------------------------------------------| -| HIHOPE | AArch64_Flash_writer_SCIF_DUMMY_CERT_E6300400_hihope.mot | -| EK874 | AArch64_Flash_writer_SCIF_DUMMY_CERT_E6300400_ek874.mot | - -## 5. How to run the RZ/G2 flash writer - -### 5.1. Prepare for write to the Serial Flash and eMMC - -Start the target in the SCIF download mode and run the RZ/G2 flash writer sample code. - -Regarding the DIP switch configuration on the board, refer to [Related Document](#related-document) No.4. - -The following table shows the setting of terminal software. - -#### Terminal software configuration - -| Baud rate | Data bit length | Parity check | Stop bits | Flow control | -|-----------:|-----------------|--------------|-----------|--------------| -| 115200bps | 8bits | none | 1bit | none | - -Terminal software outputs the following log at power ON the target. - -```text -SCIF Download mode (w/o verification) -(C) Renesas Electronics Corp. - --- Load Program to SystemRAM --------------- -please send ! -``` - -Transfer S-record file after the log output. - -S-record file: - -- AArch64_output/AArch64_Flash_writer_SCIF_DUMMY_CERT_E6300400_``.mot - -After the transfer has succeeded, the following log will be shown. - -```text -Flash writer for RZ/G2M V1.01 Jan.08,2020 -> -``` - -Please enter the any key from the console to continue. - -For details on how to write to the Serial Flash and eMMC, please refer to [Section 3.4](#34-command-specification). - -### 5.2. Prepare for boot from the Serial Flash and eMMC - -To boot from the eMMC, need to change the DIP switch setting. - -Regarding the DIP switch configuration on the board, refer to [Related Document](#related-document) No.4. - -## 6. Error case to handle - -### 6.1. EXT_CSD incorrect setting case - -If error of eMMC command is occurred, please check the following description and restart. - -- Please Check the correct setting of EXT_CSD. If the wrong setting is present, to set the correct setting using EM_SECSD command. -- Program start address error of S-record file. - -The following shows the setting of High speed SDR(50MHz) x8 bus width mode, Boot partition 1 enable. - -| Address | Register Name | Filed name | Bit filed | Settings | -|--------------|---------------------|------------------------|-----------|----------| -| EXT_CSD[179] | PARTITION_CONFIG | BOOT_ACK | [6] | 0x0 | -| | | BOOT_PARTITION_ENABLE | [5:3] | 0x1 | -| EXT_CSD[177] | BOOT_BUS_CONDITIONS | BOOT_MODE | [4:3] | 0x1 | -| | | BOOT_BUS_WIDTH | [1:0] | 0x2 | - -For details of EXT_CSD, please refer to [Related Document](#related-document) No.1. - -### 6.2. Program start address error of S-record format file - -After the message "Please Input User Program Start Address" has been displayed, input a start address of the S-record format file to be loaded (smallest value) as the start address of the program. (This address is treated as the start address and branch address of the data transfer destination from the eMMC device in the program.) - -Please check the program start address and write again program using EM_W command. - -## 7. Revision history - -Describe the revision history of RZ/G2 flash writer. - -### 7.1. v1.00 - -- First release. - -### 7.2. v1.01 - -- Support HiHope RZ/G2[MN] Rev.3/Rev.4 boards -- Improve makefile to support the build by bitbake -- Add new makefile for the linaro toolchain build - -### 7.3. v1.02 - -- Support HiHope RZ/G2[H] Rev.4 boards -- Support USB Download mode -- List register configurations needed eMMC boot - -### 7.4. v1.03 - -- Support QSPI Flash devices smaller than 16MB - -### 7.5. v1.04 - -- Support SiLinux EK874 Rev.D/Rev.E boards +# RZ/V2M Flash Writer + +
+Renesas Electronics Corporation + +July 30, 2021 +
+ +RZ/V2M flash writer is a sample software to write loader binary images to eMMC on RZ/V2M. + +## 1. Overview + +This README explains how to use RZ/V2M flash writer. +Refer to "RZ/V2M Linux Package Yocto recipe Start-Up Guide" for the detail. + +## 1.1. README Contents + +[Chapter 2](#2-operating-environment) describes the operating environment. + +[Chapter 3](#3-software) describes the software. + +[Chapter 4](#4-how-to-build-the-rzv2m-flash-writer) explains an example of how to build the RZ/V2M flash writer. + +[Chapter 5](#5-how-to-run-the-rzv2m-flash-writer) explains an example of how to perform the RZ/V2M flash writer. + +*Note) This sample software does not support file systems. Therefore, only raw binary images can be downloaded and programmed into eMMC.* + +## 1.2. License + +BSD-3-Clause (See file [LICENSE.md](LICENSE.md) for details.) + +## 1.3. Notice + +RZ/V2M flash writer is distributed by Renesas Electronics Corporation as a sample software without any warranty or support. + +## 1.4. Contributing + +To contribute to this software, you should email patches to renesas-rz@renesas.com. Send .patch files as email attachments, not embedded in the email body. + +## 1.5. References + +The following table shows the document related to this function. + +### Related Document + +| Number | Issuer | Title | Edition | +|--------|---------|----------------------------------------------------------------|-------------------| +| 1 | JEDEC | Embedded Multi-Media Card (eMMC) Electrical Standard (5.01) | JESD84-B50.1 | +| 2 | Renesas | RZ/V2M Linux Package Relese Note | Rev.1.00 or later | +| 3 | Renesas | RZ/V2M Linux Package Start-Up Guide | Rev.1.00 or later | +| 4 | Renesas | RZ/V2M Linux Package Yocto recipe Start-Up Guide | Rev.1.00 or later | + +## 2. Operating Environment + +### 2.1. Hardware Environment + +The following table lists the hardware needed to use this utility. + +#### Hardware environment + +| Name | Note | +|------------------------|--------------------------------------------------------------------------------------| +| Target board | RZ/V2M Evaluation Kit. | +| Linux Host PC | Build and debug environment. Ubuntu Desktop 16.04(64bit). | +| Windows PC | Use to control serial console of the target board. | +| micro SDHC card | Use for writing flash writer. The card should have 1 partition formatted with FAT32. | +| micro USB serial cable | Connect between the target board and Host PC. | + +The eMMC support status of RZ/V2M is as follows. + +#### eMMC support status + +| MPU | eMMC | Read/Write the eMMC | Boot from the eMMC | MMC interface | +|--------|-----------------|---------------------|--------------------|---------------| +| RZ/V2M | THGBMJG7C1LBAIL | Support | Support | MMC1 | + +## 2.2. Software Environment + +The following table lists the software required to use this sample software. + +### Compile + +| Name | Note | +|---------------------|------------------------------------------------------------------| +| Linaro Toolchain *1 | Linaro Binary Toolchain Release GCC 7.3-2018.05 for aarch64-elf. | + +### Software on Windows PC + +| Name | Note | +|---------------------|------------------------------------------------------------------| +| Terminal software | Control serial console of the target board. | + +## 3. Software + +### 3.1. Function + +This package has the following capabilities: + +- Write binary images to the boot partition of an eMMC. +- Erase the boot partition of an eMMC. + +### 3.2 Command specification + +The following table shows the command list. + +#### Command list + +| Command | Description | +|----------|------------------------------------------------------------------| +| EM_WB | Write the raw binary images to the boot partition of eMMC. | +| EM_E | Erase the user data area of eMMC and the boot partition of eMMC. | + +#### 3.2.1 Write the loader binary images to the eMMC + +This command writes the loader binary images to any partition of the eMMC. + +##### Example of writing data for the eMMC boot + +| Filename | Program Top Address | eMMC save partition | eMMC save sectors *1 | File size (byte) *2 | Description | +|----------------------|---------------------|---------------------|----------------------|---------------------|-------------------------------| +| loader_1st_128kb.bin | Hf80100000 | boot partition1 | H'000000 | H'20000 | 1st loader binary | +| loader_2nd_param.bin | On RAMA area *3 | boot partition1 | H'000100 | H'8 | Boot parameter for 2nd loader | +| loader_2nd.bin | HfB6000000 | boot partition1 | H'000101 | *2 | 2nd loader binary | +| u-boot_param.bin | On RAMB area *3 | boot partition1 | H'000901 | H'8 | Boot parameter for u-boot | +| u-boot.bin | Hf57F00000 | boot partition1 | H'000902 | *2 | U-Boot binary | + +*1: The sector size is 512bytes. +*2: These file sizes may be different from the loader binary files generated by bitbake. Also, the size of these files may change in future versions. Check the size of each file on your PC. +*3: These RAM areas are not fixed because these binaries are stored in the local memory. + +The following shows the procedure of this command with the binary file loader_1st_128kb.bin. +Note that the values of eMMC save sector and file size must be entered as **hexadecimal**. + +```text +>EM_WB + +EM_W Start -------------- +--------------------------------------------------------- +Please select,eMMC Partition Area. + 0:User Partition Area : 15388672 KBytes + eMMC Sector Cnt : H'0 - H'01D59FFF + 1:Boot Partition 1 : 4096 KBytes + eMMC Sector Cnt : H'0 - H'00001FFF + 2:Boot Partition 2 : 4096 KBytes + eMMC Sector Cnt : H'0 - H'00001FFF +--------------------------------------------------------- + Select area(0-2)>1 <<<< Enter the boot partition to write. + +-- Boot Partition 1 Program ----------------------------- +Please Input Start Address in sector :000 <<<< Enter the start address in the sector in hexadecimal. + +Work RAM(H'B6000000-H'B60FFFFF) Clear.... +Please Input File size(byte) : 20000 <<<< Enter the file size in hexiadecimal. + +please send binary file! <<<< Send the file via the terminal software. +SAVE -FLASH....... +EM_WB Complete! +>EM_WB +``` + +Image writing has been completed. + +#### 3.2.2 Erase the eMMC + +This command erases any partition of the eMMC. + +The following shows the procedure of this command. + +```text +>EM_E + +EM_E Start -------------- +--------------------------------------------------------- +Please select,eMMC Partition Area. + 0:User Partition Area : 15388672 KBytes + eMMC Sector Cnt : H'0 - H'01D59FFF + 1:Boot Partition 1 : 4096 KBytes + eMMC Sector Cnt : H'0 - H'00001FFF + 2:Boot Partition 2 : 4096 KBytes + eMMC Sector Cnt : H'0 - H'00001FFF +--------------------------------------------------------- + Select area(0-2)>1 <<<< Enter the boot partition to erase + +-- Boot Partition 1 Program ----------------------------- +EM_E Complete! +``` +After running the above command, the selected partition will be erased. + +## 4. How to build the RZ/V2M flash writer + +This chapter describes how to build the RZ/V2M flash writer. The following commands should be executed in your work directory {$WORK} on your Host PC. + +### 4.1. Prepare the compiler + +Get the cross compiler for linaro. + +Linaro toolchain: + +```shell +$ cd {$WORK} +$ wget https://releases.linaro.org/components/toolchain/binaries/7.3-2018.05/aarch64-elf/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-elf.tar.xz +$ tar xvf gcc-linaro-7.3.1-2018.05-x86_64_aarch64-elf.tar.xz +``` + +### 4.2. Prepare the source code + +Get the source code of the RZ/V2M flash writer from this repository as follows. + +```shell +cd ${WORK} +git clone -b rz_v2m https://github.com/renesas-rz/rzg2_flash_writer.git rzv2m_flash_writer +``` + +### 4.3. Build the RZ/V2M flash writer + +The RZ/V2M flash writer will be built by the following command. + +Linaro toolchain: + +```shell +$ cd ${WORK} +$ make -f makefile.linaro clean +$ CROSS_COMPILE=../gcc-linaro-7.3.1-2018.05-x86_64_aarch64-elf/bin/aarch64-elf- make -f makefile.linaro +``` + +### 4.4. Check the output file +The output image will be available in the following directory. + +| Generated files | File name | File stored path | +|-----------------|--------------|--------------------------------------------| +| Flash writer | B2_intSW.bin | ${WORK}/rzv2m_flash_writer /AArch64_output | + +## 5. How to run the RZ/V2M flash writer +### Step.1 Equipment setting +Connect your PC and the target board via a serial to micro-USB cable. +Start a terminal software on your PC. Set the configuration of terminal software is as follows and select the Standard COM port. +| Baud rate | Data bit | Parity bit | Stop bit | Flow control | +|------------|----------|------------|----------|--------------| +| 115200bps | 8bits | none | 1bit | none | + +### Step.2 Write the flash writer to the eMMC +Store the Flash writer binary (B2_intSW.bin) in a micro-SDHC Card that has 1 partition formatted with FAT32. +Insert the micro-SD card into the micro-SD card slot on the RZ/V2M Evaluation Kit. +Set the Main SW2 on the RZ/V2M Evaluation Kit is as the following table to change the board operation mode to "forced write mode". +| SW1 | SW2 | SW3 | SW4 | +|-----|-----|-----|-----| +| OFF | OFF | OFF | ON | + +Power on the RZ/V2M Evaluation Kit. +Start RZ/V2M in forced write mode and write the Flash writer binary from the micro-SD card to eMMC. +Check the lighting of Main LED 2.Note that if the LED is blinking, writing the Flash writer binary is failed. +After checking the LED, power off the RZ/V2M Evaluation Kit. + + +### Step.3 Start the flash writer +Set the Main SW2 on the RZ/V2M Evaluation Kit is as the following table to change the board operation mode to "normal mode". + +| SW1 | SW2 | SW3 | SW4 | +|-----|-----|-----|-----| +| OFF | OFF | OFF | OFF | + +Power on the RZ/V2M Evaluation Kit. The following log will appear if RZ/V2M starts in normal mode and run Flash writer successfully. + +```text +Flash writer for RZ/V2M V1.00 Jul 9, 2021 +> +``` + +### Step.4 Write loader binaries to eMMC with Flash writer +Please enter any key from the console to continue. +For details on how to write to the eMMC, please refer to 3.2 Command specification. +After completing the writing, turn off the board. + +### Step.5 Confirm booting by the boot loader and U-boot +Power on the RZ/V2M Evaluation Kit with the normal mode. And then, confirm that the boot loader and U-boot run normally. diff --git a/boardid.c b/boardid.c deleted file mode 100644 index 390b16c..0000000 --- a/boardid.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "reg_rzg2.h" -#include "boardid.h" - -uint32_t gBoardFlag; - -void CheckBoard(void) -{ -#if defined (RZG2_EK874) - gBoardFlag = BD_EK874; -#elif defined (RZG2_HIHOPE) - gBoardFlag = BD_HIHOPE; -#endif -} diff --git a/boot_init_gpio.c b/boot_init_gpio.c deleted file mode 100644 index bfa208e..0000000 --- a/boot_init_gpio.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "reg_rzg2.h" -#include "boot_init_gpio.h" - -static void InitPOSNEG(void); -static void InitIOINTSEL(void); -static void InitOUTDT(void); -static void InitINOUTSEL(void); - -void InitGPIO(void) -{ - InitPOSNEG(); - InitIOINTSEL(); - InitOUTDT(); - InitINOUTSEL(); -} - -static void InitPOSNEG(void) -{ - *((volatile uint32_t*)GPIO_POSNEG0)=0x00000000; - *((volatile uint32_t*)GPIO_POSNEG1)=0x00000000; - *((volatile uint32_t*)GPIO_POSNEG2)=0x00000000; - *((volatile uint32_t*)GPIO_POSNEG3)=0x00000000; - *((volatile uint32_t*)GPIO_POSNEG4)=0x00000000; - *((volatile uint32_t*)GPIO_POSNEG5)=0x00000000; - *((volatile uint32_t*)GPIO_POSNEG6)=0x00000000; -} - -static void InitIOINTSEL(void) -{ - *((volatile uint32_t*)GPIO_IOINTSEL0)=0x00000000; - *((volatile uint32_t*)GPIO_IOINTSEL1)=0x00000000; - *((volatile uint32_t*)GPIO_IOINTSEL2)=0x00000000; - *((volatile uint32_t*)GPIO_IOINTSEL3)=0x00000000; - *((volatile uint32_t*)GPIO_IOINTSEL4)=0x00000000; - *((volatile uint32_t*)GPIO_IOINTSEL5)=0x00000000; - *((volatile uint32_t*)GPIO_IOINTSEL6)=0x00000000; -} - -static void InitOUTDT(void) -{ - uint32_t product; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - switch (product) - { -#ifdef RZG2_HIHOPE - case PRR_PRODUCT_G2H: - case PRR_PRODUCT_G2M: - case PRR_PRODUCT_G2N: - *((volatile uint32_t*)GPIO_OUTDT1)=0x00000000; - *((volatile uint32_t*)GPIO_OUTDT2)=0x00000400; - *((volatile uint32_t*)GPIO_OUTDT3)=0x0000C000; - *((volatile uint32_t*)GPIO_OUTDT5)=0x00000006; - *((volatile uint32_t*)GPIO_OUTDT6)=0x00003880; - break; -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - case PRR_PRODUCT_G2E: - break; -#endif /* RZG2_EK874 */ - default: - break; - } -} - -static void InitINOUTSEL(void) -{ - uint32_t product; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - switch (product) - { -#ifdef RZG2_HIHOPE - case PRR_PRODUCT_G2H: - case PRR_PRODUCT_G2M: - case PRR_PRODUCT_G2N: - *((volatile uint32_t*)GPIO_INOUTSEL0)=0x00000000; - *((volatile uint32_t*)GPIO_INOUTSEL1)=0x01000A00; - *((volatile uint32_t*)GPIO_INOUTSEL2)=0x00000400; - *((volatile uint32_t*)GPIO_INOUTSEL3)=0x0000C000; - *((volatile uint32_t*)GPIO_INOUTSEL4)=0x00000000; - *((volatile uint32_t*)GPIO_INOUTSEL5)=0x0000020E; - *((volatile uint32_t*)GPIO_INOUTSEL6)=0x00013880; - break; -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - case PRR_PRODUCT_G2E: - break; -#endif /* RZG2_EK874*/ - default: - break; - } -} diff --git a/boot_init_lbsc.c b/boot_init_lbsc.c deleted file mode 100644 index 24e5614..0000000 --- a/boot_init_lbsc.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "reg_rzg2.h" -#include "boot_init_lbsc.h" - -void InitLBSC(void) -{ - InitCSCTRL(); - InitCSWCR(); - InitCSPWCR(); - InitEXWTSYNC(); -} - -void InitCSCTRL(void) -{ - *((volatile uint32_t*)LBSC_CS0CTRL)=0x00000020; - *((volatile uint32_t*)LBSC_CS1CTRL)=0x00000020; -} - -void InitCSWCR(void) -{ -#ifdef RZG2_HIHOPE - *((volatile uint32_t*)LBSC_CSWCR0)=0x2A103320; - *((volatile uint32_t*)LBSC_CSWCR1)=0x2A103320; -#endif /* RZG2_HIHOPE */ -} - -void InitCSPWCR(void) -{ - *((volatile uint32_t*)LBSC_CSPWCR0)=0x00000000; - *((volatile uint32_t*)LBSC_CSPWCR1)=0x00000000; -} - -void InitEXWTSYNC(void) -{ - *((volatile uint32_t*)LBSC_EXWTSYNC)=0x00000000; - *((volatile uint32_t*)LBSC_CS1GDST) =0x00000000; -} diff --git a/boot_init_port.c b/boot_init_port.c deleted file mode 100644 index 3dadb25..0000000 --- a/boot_init_port.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "reg_rzg2.h" -#include "boot_init_port.h" - -#define PFC_WR(m,n) *((volatile uint32_t*)PFC_PMMR)=~(n);*((volatile uint32_t*)(m))=(n); - -/* SCIF3 Registers for Dummy write */ -#define SCIF3_BASE (0xE6C50000U) -#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) -#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) -#define SCFCR_DATA (0x0000U) - -/* Realtime module stop control */ -#define RMSTPCR0_RTDMAC (0x00200000U) - -/* RT-DMAC Registers */ -#define RTDMAC_CH (0U) /* choose 0 to 15 */ - -#define RTDMAC_BASE (0xFFC10000U) -#define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U) -#define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U) -#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x))) -#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x))) -#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x))) -#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x))) -#define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x))) -#define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x))) -#define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U) -#define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U) -#define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U) -#define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U) - -#define RDMOR_DME (0x0001U) /* DMA Master Enable */ -#define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */ -#define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */ -#define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */ -#define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */ -#define RDMCHCR_DE (0x00000001U) /* DMA Enable */ -#define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */ -#define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */ -#define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */ - -#ifdef RZG2_HIHOPE -static void InitMODSEL(void); -static void InitIPSR_G2M(void); -static void InitGPSR_G2M(void); -static void InitPOCCTRL(void); -static void InitDRVCTRL(void); -static void InitPUD(void); -static void InitPUEN(void); -#endif /* RZG2_HIHOPE */ - -#ifdef RZG2_EK874 -static void InitMODSEL_G2E(void); -static void InitIPSR_G2E(void); -static void InitGPSR_G2E(void); -static void InitIOCTRL_G2E(void); -static void InitPUD_G2E(void); -static void InitPUEN_G2E(void); -#endif /* RZG2_EK874 */ - -#ifdef RZG2_HIHOPE -static void StartRtDma0_Descriptor(void); -#endif /* RZG2_HIHOPE */ - -void InitPORT(void) -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - switch (product) - { -#ifdef RZG2_HIHOPE - case PRR_PRODUCT_G2M: - StartRtDma0_Descriptor(); - /* no break */ - case PRR_PRODUCT_G2N: - case PRR_PRODUCT_G2H: - InitMODSEL(); - InitIPSR_G2M(); - InitGPSR_G2M(); - InitPOCCTRL(); - InitDRVCTRL(); - InitPUD(); - InitPUEN(); - break; -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - case PRR_PRODUCT_G2E: - InitMODSEL_G2E(); - InitIPSR_G2E(); - InitGPSR_G2E(); - InitIOCTRL_G2E(); - InitPUD_G2E(); - InitPUEN_G2E(); - break; -#endif /* RZG2_EK874*/ - default: - break; - } -} - -#ifdef RZG2_HIHOPE -static void InitMODSEL(void) -{ - PFC_WR(PFC_MOD_SEL0,0x00000000); - PFC_WR(PFC_MOD_SEL1,0x00000000); - PFC_WR(PFC_MOD_SEL2,0x00000000); -} - -static void InitIPSR_G2M(void) -{ - PFC_WR(PFC_IPSR17,0x00000010); // selcet SCIF_CLK_A -} - -static void InitGPSR_G2M(void) -{ - PFC_WR(PFC_GPSR4, 0x0003FF80); // SD3_DS, SD3_DAT7, - // SD3_DAT6, SD3_DAT5, SD3_DAT4, SD3_DAT3, SD2_DAT2, SD3_DAT1, SD3_DAT0, SD3_CMD - // SD3_CLK - PFC_WR(PFC_GPSR5, 0x00000C00); // TX2_A, RX2_A - PFC_WR(PFC_GPSR6, 0x00800000); // SCIF_CLK_A - PFC_WR(PFC_GPSR7, 0x00000000); -} - -static void InitPOCCTRL(void) -{ - PFC_WR(PFC_POCCTRL0, 0x0007FFFF); // SD3_xx 1.8V -} - -static void InitDRVCTRL(void) -{ - PFC_WR(PFC_DRVCTRL15,0xFFFFFCCC); - PFC_WR(PFC_DRVCTRL16,0xCCCCCCCC); -} - -static void InitPUD(void) -{ -} - -static void InitPUEN(void) -{ -} -#endif /* RZG2_HIHOPE */ - -#ifdef RZG2_EK874 -static void InitMODSEL_G2E(void) -{ -} - -static void InitIPSR_G2E(void) -{ -} - -static void InitGPSR_G2E(void) -{ - PFC_WR(PFC_GPSR2,0x3f); -#if EMMC == 1 - PFC_WR(PFC_GPSR4,0x000007FF); -#endif /* EMMC == 1 */ -} - -static void InitIOCTRL_G2E(void) -{ -#if EMMC == 1 - PFC_WR(PFC_IOCTRL30,0x0007FFFF); -#endif /* EMMC == 1 */ -} - -static void InitPUD_G2E(void) -{ -#if EMMC == 1 - PFC_WR(PFC_PUD3, 0x001FF79FU); -#endif -} - -static void InitPUEN_G2E(void) -{ -#if EMMC == 1 - PFC_WR(PFC_PUEN3, 0x001FF800U); -#endif -} -#endif /* RZG2_EK874*/ - -#ifdef RZG2_HIHOPE -static void StartRtDma0_Descriptor(void) -{ - uint32_t reg; - - reg = *((volatile uint32_t *)PRR); - reg &= (PRR_CUT_MASK); - if (reg == (PRR_CUT_10)) - { - /* Module stop clear */ - while((*((volatile uint32_t *)CPG_RMSTPCR0) & RMSTPCR0_RTDMAC) != 0U) - { - reg = *((volatile uint32_t *)CPG_RMSTPCR0); - reg &= ~RMSTPCR0_RTDMAC; - *((volatile uint32_t *)CPG_CPGWPR) = ~reg; - *((volatile uint32_t *)CPG_RMSTPCR0) = reg; - } - - /* Initialize ch0, Reset Descriptor */ - *((volatile uint32_t *)RTDMAC_RDMCHCLR) = ((uint32_t)1U << RTDMAC_CH); - *((volatile uint32_t *)RTDMAC_RDMCHCRB(RTDMAC_CH)) = RDMCHCRB_DRST; - - /* Enable DMA */ - *((volatile uint16_t *)RTDMAC_RDMOR) = RDMOR_DME; - - /* Set first transfer */ - *((volatile uint32_t *)RTDMAC_RDMSAR(RTDMAC_CH)) = PRR; - *((volatile uint32_t *)RTDMAC_RDMDAR(RTDMAC_CH)) = SCIF3_SCFDR; - *((volatile uint32_t *)RTDMAC_RDMTCR(RTDMAC_CH)) = 0x00000001U; - - /* Set descriptor */ - *((volatile uint32_t *)RTDMAC_DESC_RDMSAR) = 0x00000000U; - *((volatile uint32_t *)RTDMAC_DESC_RDMDAR) = 0x00000000U; - *((volatile uint32_t *)RTDMAC_DESC_RDMTCR) = 0x00200000U; - *((volatile uint32_t *)RTDMAC_RDMCHCRB(RTDMAC_CH)) = RDMCHCRB_SLM_256; - *((volatile uint32_t *)RTDMAC_RDMDPBASE(RTDMAC_CH)) = (RTDMAC_DESC_BASE | RDMDPBASE_SEL_EXT); - - /* Set transfer parameter, Start transfer */ - *((volatile uint32_t *)RTDMAC_RDMCHCR(RTDMAC_CH)) = (RDMCHCR_DPM_INFINITE - | RDMCHCR_RPT_TCR - | RDMCHCR_TS_2 - | RDMCHCR_RS_AUTO - | RDMCHCR_DE - ); - } -} -#endif /* RZG2_HIHOPE */ diff --git a/cert_param.c b/cert_param.c deleted file mode 100644 index 67ef9dd..0000000 --- a/cert_param.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* 0xE6300400 */ -const unsigned int __attribute__ ((section (".boot_param"))) boot_param = 0x00000000; -/* 0xE630048C */ -const unsigned int __attribute__ ((section (".cert_offset"))) reserved = 0x00000000; -/* 0xE63005D4 */ -const unsigned int __attribute__ ((section (".cert_addr"))) cert_addr = 0xE6304000; -/* 0xE63006E4 */ -const unsigned int __attribute__ ((section (".cert_size"))) cert_size = 0x00001000; -/* 0xE6301154 */ -const unsigned int __attribute__ ((section (".cert_addr2"))) cert_addr2 = 0xE6304000; -/* 0xE6301264 */ -const unsigned int __attribute__ ((section (".cert_size2"))) cert_size2 = 0x00001000; diff --git a/common.c b/common.c index 91302ae..2645f9a 100644 --- a/common.c +++ b/common.c @@ -1,71 +1,33 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #include #include "types.h" #include "common.h" #include "devdrv.h" -#if USB_ENABLE == 1 -#include "usb_lib.h" -#endif /* USB_ENABLE == 1 */ __attribute__((aligned(32))) uint8_t gCOMMAND_Area[COMMAND_BUFFER_SIZE]; -/************************************************************************/ -/*NAME : PutMes */ -/************************************************************************/ -int32_t PutMess(const char *const mess[]) -{ - int32_t i = 0; - while(mess[i]) - { - PutStr(mess[i],ENB_RTN); - i++; - } - return(0); -} - -#if USB_ENABLE == 1 -int32_t PutMessUSB(const char *const mess[]) -{ - int32_t i=0; - while(mess[i]) - { - PutStrUSB(mess[i],ENB_RTN); - i++; - } - return(0); -} -#endif /* USB_ENABLE == 1 */ - /************************************************************************/ /*NAME : PutStr */ /************************************************************************/ @@ -85,56 +47,6 @@ int32_t PutStr(const char *str,char rtn) } -#if USB_ENABLE == 1 -int32_t PutStrUSB(const char *str,char rtn) -{ - while(*str) - { - PutCharUSB(*str); - str++; - } - if (rtn == 1) - { - PutCharUSB(CR_CODE); - PutCharUSB(LF_CODE); - } - return(0); - -} - -int32_t PutCharUSB(char outChar) -{ - char outCh; - outCh = outChar; - - (void)USB_WriteData(&outCh, 1); - USB_IntCheck(); - return(0); -} - -int32_t GetCharUSB(char *inChar) -{ - static int32_t numOfChar = 0; - static int32_t index = 0; - int32_t length = 0; - - while(numOfChar == 0) - { - numOfChar = USB_ReadCount(); - length = USB_ReadData(gCOMMAND_Area, numOfChar); - USB_IntCheck(); - } - *inChar = *((char*)(gCOMMAND_Area + index)); - index++; - if (numOfChar == index) - { - index = 0; - numOfChar = 0; - } - return(0); -} -#endif /* USB_ENABLE == 1 */ - /************************************************************************/ /*NAME : GetStr */ /************************************************************************/ diff --git a/cpudrv.c b/cpudrv.c deleted file mode 100644 index 6bb3624..0000000 --- a/cpudrv.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "bit.h" -#include "reg_rzg2.h" -#include "cpudrv.h" - -/* TMU ch0-2 : CP-Clock */ -/* TMU ch3-11 : S3D2_PERE-Clock */ -/* TMU ch12-14 : S3D2_RT-Clock */ -void StartTMU0(uint32_t tenmSec) -{ - uint16_t dataW; - uint32_t cnt,dataL; - - PowerOnTmu0(); - - *((volatile uint16_t*)TMU_TCR0) = 0x0000U; /* TCNT_count_clock=(Input-Clock)/4 */ - -#ifdef RZG2_HIHOPE - *((volatile uint32_t*)TMU_TCNT0) = 20833U; /* [G2M/G2N](8.3333MHz/4)*20833=9.999880ms (-0.000012s/100s) */ - *((volatile uint32_t*)TMU_TCOR0) = 20833U; /* Input-Clock=CP-Clock=16.6666/2=8.3333MHz */ -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - *((volatile uint32_t*)TMU_TCNT0) = 60000U; /* [G2E](24.0000MHz/4)*60000=10.00ms */ - *((volatile uint32_t*)TMU_TCOR0) = 60000U; /* Input-Clock=CP-Clock=48.0000/2=24.0000MHz */ -#endif /* RZG2_EK874 */ - - *((volatile uint8_t*)TMU_TSTR0) |= BIT0; /* TMU0 Start */ - for (cnt = 0; cnt < tenmSec; cnt++) - { - while(1) - { - dataW = *((volatile uint16_t*)TMU_TCR0); - if (dataW & BIT8) - { - /* UNF(under-flow-flag) clear */ - *((volatile uint16_t*)TMU_TCR0) &= ~BIT8; - break; - } - } - } - *((volatile uint8_t*)TMU_TSTR0) &= ~BIT0; /* TMU0 Stop */ -} - -void StartTMU0usec(uint32_t tenuSec) -{ - uint16_t dataW; - uint32_t cnt,dataL; - - PowerOnTmu0(); - - *((volatile uint16_t*)TMU_TCR0) = 0x0000U; /* TCNT_count_clock=(Input-Clock)/4 */ - -#ifdef RZG2_HIHOPE - *((volatile uint32_t*)TMU_TCNT0) = 21U; /* [G2M/G2N](8.3333MHz/4)*21=10.08004us (+0.8004s/100s) */ - *((volatile uint32_t*)TMU_TCOR0) = 21U; /* Input-Clock=CP-Clock=16.6666/2=8.3333MHz */ -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - *((volatile uint32_t*)TMU_TCNT0) = 60U; /* [G2E](24.0000MHz/4)*60=10.00us */ - *((volatile uint32_t*)TMU_TCOR0) = 60U; /* Input-Clock=CP-Clock=48.0000/2=24.0000MHz */ -#endif /* RZG2_EK874 */ - - *((volatile uint8_t*)TMU_TSTR0) |= BIT0; /* TMU0 Start */ - for (cnt = 0; cnt < tenuSec; cnt++) - { - while(1) - { - dataW = *((volatile uint16_t*)TMU_TCR0); - if (dataW & BIT8) - { - /* UNF(under-flow-flag) clear */ - *((volatile uint16_t*)TMU_TCR0) &= ~BIT8; - break; - } - } - } - *((volatile uint8_t*)TMU_TSTR0) &= ~BIT0; /* TMU0 Stop */ -} - -void PowerOnTmu0(void) -{ - uint32_t dataL; - - dataL = *((volatile uint32_t*)CPG_MSTPSR1); - if (dataL & BIT25) - { - dataL &= ~BIT25; - *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; - *((volatile uint32_t*)CPG_SMSTPCR1) = dataL; - while( (BIT25) & *((volatile uint32_t*)CPG_MSTPSR1) ); /* wait bit=0 */ - } -} - -const void* const GPIO_INDT[8]= -{ - (void*)GPIO_INDT0, - (void*)GPIO_INDT1, - (void*)GPIO_INDT2, - (void*)GPIO_INDT3, - (void*)GPIO_INDT4, - (void*)GPIO_INDT5, - (void*)GPIO_INDT6, - (void*)GPIO_INDT7, -}; - -uint32_t GetGpioInputLevel( uint32_t gp, uint32_t bit ) -{ - uint32_t dataL; - dataL = *((volatile uint32_t*)GPIO_INDT[gp]); - if (dataL & (1< -#include - -#include "boot_init_dram_regdef_g2e.h" -#include "ddr_init_g2e.h" - -#include "../dram_sub_func.h" - -// rev.0.04 add variables -/******************************************************************************* - * variables - ******************************************************************************/ -uint32_t ddrBackup; - -// rev.0.03 add Prototypes -/******************************************************************************* - * Prototypes - ******************************************************************************/ -//static uint32_t init_ddr(void); // rev.0.04 -//static uint32_t recovery_from_backup_mode(void); // rev.0.04 -//int32_t dram_update_boot_status(uint32_t status); // rev.0.04 - -// rev.0.03 add Comment -/******************************************************************************* - * register write/read function - ******************************************************************************/ -static void WriteReg_32(uint32_t a, uint32_t v) -{ - (*(volatile uint32_t*)(uintptr_t)a) = v; -} // WriteReg_32 - -static uint32_t ReadReg_32(uint32_t a) -{ - uint32_t w = (*(volatile uint32_t*)(uintptr_t)a); - return w; -} // ReadReg_32 - -// rev.0.04 add Comment -/******************************************************************************* - * Initialize ddr - ******************************************************************************/ -uint32_t init_ddr(void) -{ - - uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; - uint32_t ddr_md; - -//rev.0.08 - uint32_t RegVal, j; - uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; - uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; - uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; -//rev.0.10 - uint32_t pdr_ctl; -//rev.0.11 - uint32_t byp_ctl; - -//rev.0.08 - if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) - { - pdqsr_ctl = 1; - lcdl_ctl = 1; - pdr_ctl = 1; //rev.0.10 - byp_ctl = 1; //rev.0.11 - } - else - { - pdqsr_ctl = 0; - lcdl_ctl = 0; - pdr_ctl = 0; //rev.0.10 - byp_ctl = 0; //rev.0.11 - } - - // Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) - ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0; - - // 1584Mbps setting - if (ddr_md == 0) - { - /* CPG setting ===============================================*/ - WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF); - WriteReg_32(CPG_CPGWPCR, 0xA5A50000); - - WriteReg_32(CPG_SRCR4, 0x20000000); - - WriteReg_32(0xE61500DC, 0xe2200000); // Change to 1584Mbps - while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0) - { - ; - } - WriteReg_32(CPG_SRSTCLR4, 0x20000000); - - WriteReg_32(CPG_CPGWPCR, 0xA5A50001); - - /* CPG setting ===============================================*/ - } // ddr_md - - WriteReg_32(DBSC_G2E_DBSYSCNT0, 0x00001234); - WriteReg_32(DBSC_G2E_DBKIND, 0x00000007); - - -#if RZG2E_DRAM_DDR3L_MEMCONF == 0 - WriteReg_32(DBSC_G2E_DBMEMCONF00, 0x0f030a02); // 1GB -#elif RZG2E_DRAM_DDR3L_MEMCONF == 1 - WriteReg_32(DBSC_G2E_DBMEMCONF00, 0x10030a02); // 2GB(default) -#else - WriteReg_32(DBSC_G2E_DBMEMCONF00, 0x10030a02); // 2GB -#endif - -#if RZG2E_DRAM_DDR3L_MEMDUAL == 1 - RegVal_R2 = (ReadReg_32(0xE6790614)); - WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); // MCS1_N/MODT1 are activated. -#endif - - WriteReg_32(DBSC_G2E_DBPHYCONF0, 0x00000001); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBTR0, 0x0000000B); - WriteReg_32(DBSC_G2E_DBTR1, 0x00000008); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBTR0, 0x0000000D); - WriteReg_32(DBSC_G2E_DBTR1, 0x00000009); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBTR2, 0x00000000); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBTR3, 0x0000000B); - WriteReg_32(DBSC_G2E_DBTR4, 0x000B000B); - WriteReg_32(DBSC_G2E_DBTR5, 0x00000027); - WriteReg_32(DBSC_G2E_DBTR6, 0x0000001C); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBTR3, 0x0000000D); - WriteReg_32(DBSC_G2E_DBTR4, 0x000D000D); - WriteReg_32(DBSC_G2E_DBTR5, 0x0000002D); - WriteReg_32(DBSC_G2E_DBTR6, 0x00000020); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBTR7, 0x00060006); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBTR8, 0x00000020); - WriteReg_32(DBSC_G2E_DBTR9, 0x00000006); - WriteReg_32(DBSC_G2E_DBTR10, 0x0000000C); - WriteReg_32(DBSC_G2E_DBTR11, 0x0000000A); - WriteReg_32(DBSC_G2E_DBTR12, 0x00120012); - WriteReg_32(DBSC_G2E_DBTR13, 0x000000CE); - WriteReg_32(DBSC_G2E_DBTR14, 0x00140005); - WriteReg_32(DBSC_G2E_DBTR15, 0x00050004); - WriteReg_32(DBSC_G2E_DBTR16, 0x071F0305); - WriteReg_32(DBSC_G2E_DBTR17, 0x040C0000); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBTR8, 0x00000021); - WriteReg_32(DBSC_G2E_DBTR9, 0x00000007); - WriteReg_32(DBSC_G2E_DBTR10, 0x0000000E); - WriteReg_32(DBSC_G2E_DBTR11, 0x0000000C); - WriteReg_32(DBSC_G2E_DBTR12, 0x00140014); - WriteReg_32(DBSC_G2E_DBTR13, 0x000000F2); - WriteReg_32(DBSC_G2E_DBTR14, 0x00170006); - WriteReg_32(DBSC_G2E_DBTR15, 0x00060005); - WriteReg_32(DBSC_G2E_DBTR16, 0x09210507); - WriteReg_32(DBSC_G2E_DBTR17, 0x040E0000); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBTR18, 0x00000200); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBTR19, 0x01000040); - WriteReg_32(DBSC_G2E_DBTR20, 0x020000D6); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBTR19, 0x0129004B); - WriteReg_32(DBSC_G2E_DBTR20, 0x020000FB); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBTR21, 0x00040004); - WriteReg_32(DBSC_G2E_DBBL, 0x00000000); - WriteReg_32(DBSC_G2E_DBODT0, 0x00000001); - WriteReg_32(DBSC_G2E_DBADJ0, 0x00000001); - WriteReg_32(DBSC_G2E_DBSYSCONF1, 0x00000002); - WriteReg_32(DBSC_G2E_DBDFICNT0, 0x00000010); - WriteReg_32(DBSC_G2E_DBBCAMDIS, 0x00000001); - WriteReg_32(DBSC_G2E_DBSCHRW1, 0x00000046); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_SCFCTST0, 0x0D050B03); - WriteReg_32(DBSC_G2E_SCFCTST1, 0x0306030C); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_SCFCTST0, 0x0C050B03); - WriteReg_32(DBSC_G2E_SCFCTST1, 0x0305030C); - } // ddr_md - - // rev.0.03 add Comment - /*********************************************************************** - * Initial_Step0( INITBYP ) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDLK0, 0x0000A55A); - WriteReg_32(DBSC_G2E_DBCMD, 0x01840001); - WriteReg_32(DBSC_G2E_DBCMD, 0x08840000); - NOTICE("BL2: [COLD_BOOT]\n"); // rev.0.11 - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x80010000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - // rev.0.03 add Comment - /*********************************************************************** - * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000B8000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000090); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058904); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058A04); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000091); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0007BB6B); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000095); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0007BBAD); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000099); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0007BB6B); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000090); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058900); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058A00); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000021); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0024641E); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010073); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - ; - - // rev.0.03 add Comment - /*********************************************************************** - * Initial_Step2( DRAMRST/DRAMINT training ) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000090); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0C058900); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0C058A00); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000090); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058900); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058A00); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000003); - if (byp_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0780C720); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0780C700); - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000007); - while ((BIT30 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000004); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, (uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, (uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000022); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x1000040B); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000023); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x2D9C0B66); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x35A00D77); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000024); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x2A88B400); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x2A8A2C28); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000025); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x30005200); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x30005E00); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000026); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0014A9C9); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0014CB49); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000027); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000D70); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000F14); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000028); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000046); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000029); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - if (REFRESH_RATE > 3900) - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000018); // [7]SRT=0 - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000098); // [7]SRT=1 - } - } - else - { // 1856Mbps - if (REFRESH_RATE > 3900) - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000020); // [7]SRT=0 - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000000A0); // [7]SRT=1 - } - // REFRESH_RATE - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000002C); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x81003047); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000020); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00181884); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000001A); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x33C03C10); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A7); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A8); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A9); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C7); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C8); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C9); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E7); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E8); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E9); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000107); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000108); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000109); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000D0D0D); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010181); - WriteReg_32(DBSC_G2E_DBCMD, 0x08840001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - // rev.0.03 add Comment - /*********************************************************************** - * Initial_Step3( WL/QSG training ) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010601); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - for (i = 0; i < 4; i++) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B1 + i*0x20); - RegVal_R5 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x0000FF00) >> 0x8; - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x00000007); - if (RegVal_R6 > 0) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | RegVal_R6); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | RegVal_R7); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); - } // RegVal_R6 - } // for i - - // rev.0.10 move Comment - /*********************************************************************** - * Initial_Step4( WLADJ training ) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000005); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0xC1AA00C0); - - //rev.0.08 - if (pdqsr_ctl == 1) - { - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - - } - - // PDR always off // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010801); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - /*********************************************************************** - * Initial_Step5(Read Data Bit Deskew) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000005); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0xC1AA00D8); - - //rev.0.08 - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00011001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - if (pdqsr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - } - - // PDR dynamic // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - } - - /*********************************************************************** - * Initial_Step6(Write Data Bit Deskew) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00012001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - /*********************************************************************** - * Initial_Step7(Read Data Eye Training) - **********************************************************************/ - if (pdqsr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - } - - // PDR always off // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00014001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - if (pdqsr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - } - - // PDR dynamic // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - } - - /*********************************************************************** - * Initial_Step8(Write Data Eye Training) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00018001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - // rev.0.03 add Comment - /*********************************************************************** - * Initial_Step3_2( DQS Gate Training ) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000002C); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x81003087); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010401); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - for (i = 0; i < 4; i++) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B1 + i*0x20); - RegVal_R5 = ((ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x0000FF00) >> 0x8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x00000007); - RegVal_R12 = (RegVal_R5 >> 0x2); - if (RegVal_R12 < RegVal_R6) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007)); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); - } // RegVal_R12 < RegVal_R6 - } // for i - - // rev.0.10 move Comment - /*********************************************************************** - * Initial_Step5-2_7-2( Rd bit Rd eye ) - **********************************************************************/ -//rev.0.08 - if (pdqsr_ctl == 1) - { - } - else - { - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - } - - // PDR always off // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00015001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - //rev.0.08 - if (lcdl_ctl == 1) - { - for (i = 0; i < 4; i++) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - dqsgd_0c = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B1 + i*0x20); - bdlcount_0c = ((ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x0000FF00) >> 8); - bdlcount_0c_div2 = (bdlcount_0c >> 1); - bdlcount_0c_div4 = (bdlcount_0c >> 2); - bdlcount_0c_div8 = (bdlcount_0c >> 3); - bdlcount_0c_div16 = (bdlcount_0c >> 4); - - if (ddr_md == 0) - { - // 1584Mbps - lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8; - lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16; - } - else - { - // 1856Mbps - lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4; - lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4; - } // ddr_md - - if (dqsgd_0c > lcdl_judge1) - { - if (dqsgd_0c <= lcdl_judge2) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal)); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i * 0x20); - gatesl_0c = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x00000007); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGD0, (RegVal|(gatesl_0c + 1))); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AF + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0)); - rdqsd_0c = (RegVal & 0x0000FF00) >> 8; - rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AF + i * 0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16))); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AA + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0)); - rbd_0c[0] = (RegVal) & 0x0000001f; - rbd_0c[1] = (RegVal >> 8) & 0x0000001f; - rbd_0c[2] = (RegVal >> 16) & 0x0000001f; - rbd_0c[3] = (RegVal >> 24) & 0x0000001f; - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AA + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xE0E0E0E0); - for (j = 0; j < 4; j++) - { - rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); - if (rbd_0c[j] > 0x1F) - { - rbd_0c[j] = 0x1F; - } - RegVal = RegVal | (rbd_0c[j] << 8*j); - } - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AB + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0)); - rbd_0c[0] = (RegVal) & 0x0000001f; - rbd_0c[1] = (RegVal >> 8) & 0x0000001f; - rbd_0c[2] = (RegVal >> 16) & 0x0000001f; - rbd_0c[3] = (RegVal >> 24) & 0x0000001f; - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AB + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xE0E0E0E0); - for (j = 0; j < 4; j++) - { - rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); - if (rbd_0c[j] > 0x1F) - { - rbd_0c[j] = 0x1F; - } - RegVal = RegVal | (rbd_0c[j] << 8*j); - } - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal); - } - } - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000002); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x07D81E37); - } - - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000003); - if (byp_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0380C720); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0380C700); - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000007); - while ((BIT30 & ReadReg_32(DBSC_G2E_DBPDRGD0)) != 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000021); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0024643E); - - WriteReg_32(DBSC_G2E_DBBUS0CNF1, 0x00000010); - WriteReg_32(DBSC_G2E_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000); - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBRFCNF2, 0x00010000); - WriteReg_32(DBSC_G2E_DBDFICUPDCNF, 0x40100001); - WriteReg_32(DBSC_G2E_DBRFEN, 0x00000001); - WriteReg_32(DBSC_G2E_DBACEN, 0x00000001); - -//rev.0.08 - if (pdqsr_ctl == 1) - { - WriteReg_32(0xE67F0018, 0x00000001); - RegVal = ReadReg_32(0x40000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - } - - // PDR dynamic // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - } - - // rev.0.03 add Comment - /*********************************************************************** - * Initial_Step9( Initial End ) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDLK0, 0x00000000); - WriteReg_32(DBSC_G2E_DBSYSCNT0, 0x00000000); - -#ifdef ddr_qos_init_setting // only for non qos_init - WriteReg_32(DBSC_G2E_DBSYSCNT0, 0x00001234); - WriteReg_32(DBSC_G2E_DBCAM0CNF1, 0x00043218); - WriteReg_32(DBSC_G2E_DBCAM0CNF2, 0x000000F4); - WriteReg_32(DBSC_G2E_DBSCHCNT0, 0x000f0037); - WriteReg_32(DBSC_G2E_DBSCHSZ0, 0x00000001); - WriteReg_32(DBSC_G2E_DBSCHRW0, 0x22421111); - WriteReg_32(DBSC_G2E_SCFCTST2, 0x012F1123); - WriteReg_32(DBSC_G2E_DBSCHQOS00, 0x00000F00); - WriteReg_32(DBSC_G2E_DBSCHQOS01, 0x00000B00); - WriteReg_32(DBSC_G2E_DBSCHQOS02, 0x00000000); - WriteReg_32(DBSC_G2E_DBSCHQOS03, 0x00000000); - WriteReg_32(DBSC_G2E_DBSCHQOS40, 0x00000300); - WriteReg_32(DBSC_G2E_DBSCHQOS41, 0x000002F0); - WriteReg_32(DBSC_G2E_DBSCHQOS42, 0x00000200); - WriteReg_32(DBSC_G2E_DBSCHQOS43, 0x00000100); - WriteReg_32(DBSC_G2E_DBSCHQOS90, 0x00000100); - WriteReg_32(DBSC_G2E_DBSCHQOS91, 0x000000F0); - WriteReg_32(DBSC_G2E_DBSCHQOS92, 0x000000A0); - WriteReg_32(DBSC_G2E_DBSCHQOS93, 0x00000040); - WriteReg_32(DBSC_G2E_DBSCHQOS130, 0x00000100); - WriteReg_32(DBSC_G2E_DBSCHQOS131, 0x000000F0); - WriteReg_32(DBSC_G2E_DBSCHQOS132, 0x000000A0); - WriteReg_32(DBSC_G2E_DBSCHQOS133, 0x00000040); - WriteReg_32(DBSC_G2E_DBSCHQOS140, 0x000000C0); - WriteReg_32(DBSC_G2E_DBSCHQOS141, 0x000000B0); - WriteReg_32(DBSC_G2E_DBSCHQOS142, 0x00000080); - WriteReg_32(DBSC_G2E_DBSCHQOS143, 0x00000040); - WriteReg_32(DBSC_G2E_DBSCHQOS150, 0x00000040); - WriteReg_32(DBSC_G2E_DBSCHQOS151, 0x00000030); - WriteReg_32(DBSC_G2E_DBSCHQOS152, 0x00000020); - WriteReg_32(DBSC_G2E_DBSCHQOS153, 0x00000010); - -//rev.0.08 - if (pdqsr_ctl == 1) - { - ; - } - else - { - WriteReg_32(0xE67F0018, 0x00000001); - } - WriteReg_32(DBSC_G2E_DBSYSCNT0, 0x00000000); -#endif - - return 1; // rev.0.04 Restore the return code -// return 0; // rev.0.03 - -} // init_ddr - -// rev.0.04 add function -uint32_t recovery_from_backup_mode(void) -{ - /*********************************************************************** - * recovery_Step0(DBSC Setting 1) / same "init_ddr" - **********************************************************************/ - uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; - uint32_t ddr_md; - uint32_t err; - -//rev.0.08 - uint32_t RegVal, j; - uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; - uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; - uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; -//rev.0.10 - uint32_t pdr_ctl; -//rev.0.11 - uint32_t byp_ctl; - -//rev.0.08 - if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) - { - pdqsr_ctl = 1; - lcdl_ctl = 1; - pdr_ctl = 1; //rev.0.10 - byp_ctl = 1; //rev.0.11 - } - else - { - pdqsr_ctl = 0; - lcdl_ctl = 0; - pdr_ctl = 0; //rev.0.10 - byp_ctl = 0; //rev.0.11 - } - - // Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) - ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0; - - // 1584Mbps setting - if (ddr_md == 0) - { - /* CPG setting ===============================================*/ - WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF); - WriteReg_32(CPG_CPGWPCR, 0xA5A50000); - - WriteReg_32(CPG_SRCR4, 0x20000000); - - WriteReg_32(0xE61500DC, 0xe2200000); // Change to 1584Mbps - while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0) - { - ; - } - WriteReg_32(CPG_SRSTCLR4, 0x20000000); - - WriteReg_32(CPG_CPGWPCR, 0xA5A50001); - - /* CPG setting ===============================================*/ - } // ddr_md - - WriteReg_32(DBSC_G2E_DBSYSCNT0, 0x00001234); - WriteReg_32(DBSC_G2E_DBKIND, 0x00000007); - -#if RZG2E_DRAM_DDR3L_MEMCONF == 0 - WriteReg_32(DBSC_G2E_DBMEMCONF00, 0x0f030a02); -#elif RZG2E_DRAM_DDR3L_MEMCONF == 1 - WriteReg_32(DBSC_G2E_DBMEMCONF00, 0x10030a02); -#else - WriteReg_32(DBSC_G2E_DBMEMCONF00, 0x10030a02); -#endif - -//rev.0.08 -#if RZG2E_DRAM_DDR3L_MEMDUAL == 1 - RegVal_R2 = (ReadReg_32(0xE6790614)); - WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); // MCS1_N/MODT1 are activated. -#endif - - WriteReg_32(DBSC_G2E_DBPHYCONF0, 0x00000001); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBTR0, 0x0000000B); - WriteReg_32(DBSC_G2E_DBTR1, 0x00000008); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBTR0, 0x0000000D); - WriteReg_32(DBSC_G2E_DBTR1, 0x00000009); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBTR2, 0x00000000); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBTR3, 0x0000000B); - WriteReg_32(DBSC_G2E_DBTR4, 0x000B000B); - WriteReg_32(DBSC_G2E_DBTR5, 0x00000027); - WriteReg_32(DBSC_G2E_DBTR6, 0x0000001C); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBTR3, 0x0000000D); - WriteReg_32(DBSC_G2E_DBTR4, 0x000D000D); - WriteReg_32(DBSC_G2E_DBTR5, 0x0000002D); - WriteReg_32(DBSC_G2E_DBTR6, 0x00000020); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBTR7, 0x00060006); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBTR8, 0x00000020); - WriteReg_32(DBSC_G2E_DBTR9, 0x00000006); - WriteReg_32(DBSC_G2E_DBTR10, 0x0000000C); - WriteReg_32(DBSC_G2E_DBTR11, 0x0000000A); - WriteReg_32(DBSC_G2E_DBTR12, 0x00120012); - WriteReg_32(DBSC_G2E_DBTR13, 0x000000CE); - WriteReg_32(DBSC_G2E_DBTR14, 0x00140005); - WriteReg_32(DBSC_G2E_DBTR15, 0x00050004); - WriteReg_32(DBSC_G2E_DBTR16, 0x071F0305); - WriteReg_32(DBSC_G2E_DBTR17, 0x040C0000); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBTR8, 0x00000021); - WriteReg_32(DBSC_G2E_DBTR9, 0x00000007); - WriteReg_32(DBSC_G2E_DBTR10, 0x0000000E); - WriteReg_32(DBSC_G2E_DBTR11, 0x0000000C); - WriteReg_32(DBSC_G2E_DBTR12, 0x00140014); - WriteReg_32(DBSC_G2E_DBTR13, 0x000000F2); - WriteReg_32(DBSC_G2E_DBTR14, 0x00170006); - WriteReg_32(DBSC_G2E_DBTR15, 0x00060005); - WriteReg_32(DBSC_G2E_DBTR16, 0x09210507); - WriteReg_32(DBSC_G2E_DBTR17, 0x040E0000); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBTR18, 0x00000200); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBTR19, 0x01000040); - WriteReg_32(DBSC_G2E_DBTR20, 0x020000D6); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBTR19, 0x0129004B); - WriteReg_32(DBSC_G2E_DBTR20, 0x020000FB); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBTR21, 0x00040004); - WriteReg_32(DBSC_G2E_DBBL, 0x00000000); - WriteReg_32(DBSC_G2E_DBODT0, 0x00000001); - WriteReg_32(DBSC_G2E_DBADJ0, 0x00000001); - WriteReg_32(DBSC_G2E_DBSYSCONF1, 0x00000002); - WriteReg_32(DBSC_G2E_DBDFICNT0, 0x00000010); - WriteReg_32(DBSC_G2E_DBBCAMDIS, 0x00000001); - WriteReg_32(DBSC_G2E_DBSCHRW1, 0x00000046); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_SCFCTST0, 0x0D050B03); - WriteReg_32(DBSC_G2E_SCFCTST1, 0x0306030C); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_SCFCTST0, 0x0C050B03); - WriteReg_32(DBSC_G2E_SCFCTST1, 0x0305030C); - } // ddr_md - - /*********************************************************************** - * recovery_Step1(PHY setting 1) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDLK0, 0x0000A55A); - WriteReg_32(DBSC_G2E_DBCMD, 0x01840001); - WriteReg_32(DBSC_G2E_DBCMD, 0x0A840000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000008); // DDR_PLLCR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000B8000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000003); // DDR_PGCR1 - if (byp_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0780C720); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0780C700); - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000020); // DDR_DXCCR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00181884); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000001A); // DDR_ACIOCR0 - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x33C03C10); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000007); - while ((BIT30 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - ; - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000004); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, (uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, (uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000022); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x1000040B); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000023); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x2D9C0B66); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x35A00D77); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000024); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x2A88B400); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x2A8A2C28); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000025); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x30005200); - } - else - { // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x30005E00); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000026); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0014A9C9); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0014CB49); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000027); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000D70); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000F14); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000028); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000046); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000029); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - if (REFRESH_RATE > 3900) - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000018); // [7]SRT=0 - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000098); // [7]SRT=1 - } - } - else - { - // 1856Mbps - if (REFRESH_RATE > 3900) - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000020); // [7]SRT=0 - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000000A0); // [7]SRT=1 - } - // REFRESH_RATE - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000002C); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x81003047); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000091); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0007BB6B); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000095); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0007BBAD); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000099); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0007BB6B); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000021); // DDR_DSGCR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0024641E); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); // DDR_PGSR0 - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); // DDR_PIR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x40010000); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); // DDR_PGSR0 - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000092); // DDR_ZQ0DR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0xC2C59AB5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000096); // DDR_ZQ1DR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0xC4285FBF); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000009A); // DDR_ZQ2DR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0xC2C59AB5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000090); // DDR_ZQCR - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0C058900); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0C058A00); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000090); // DDR_ZQCR - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058900); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058A00); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); // DDR_PIR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00050001); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); // DDR_PGSR0 - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - // ddr backupmode end - if (ddrBackup) - { - NOTICE("BL2: [WARM_BOOT]\n"); - } - else - { - NOTICE("BL2: [COLD_BOOT]\n"); - } - // ddrBackup - err = dram_update_boot_status(ddrBackup); - if (err) - { - NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); - return INITDRAM_ERR_I; - } // err - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000092); // DDR_ZQ0DR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x02C59AB5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000096); // DDR_ZQ1DR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04285FBF); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000009A); // DDR_ZQ2DR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x02C59AB5); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); // DDR_PIR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x08000000); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); // DDR_PIR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000003); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); // DDR_PGSR0 - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); // DDR_PIR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x80010000); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); // DDR_PGSR0 - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); // DDR_PIR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010073); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); // DDR_PGSR0 - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000090); // DDR_ZQCR - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0C058900); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0C058A00); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000090); // DDR_ZQCR - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058900); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x04058A00); - } // ddr_md - -//rev0.08 - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000000C); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x18000040); - - /*********************************************************************** - * recovery_Step2(PHY setting 2) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A7); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A8); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A9); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C7); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C8); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C9); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E7); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E8); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E9); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000107); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000108); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000109); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x000D0D0D); - - WriteReg_32(DBSC_G2E_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000); - WriteReg_32(DBSC_G2E_DBBUS0CNF1, 0x00000010); - - // Select setting value in bps - if (ddr_md == 0) - { - // 1584Mbps - WriteReg_32(DBSC_G2E_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000); - } - else - { - // 1856Mbps - WriteReg_32(DBSC_G2E_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000); - } // ddr_md - - WriteReg_32(DBSC_G2E_DBRFCNF2, 0x00010000); - WriteReg_32(DBSC_G2E_DBRFEN, 0x00000001); - WriteReg_32(DBSC_G2E_DBCMD, 0x0A840001); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBWAIT)) != 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBCMD, 0x00000000); - - WriteReg_32(DBSC_G2E_DBCMD, 0x04840010); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBWAIT)) != 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); // DDR_PGSR0 - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); // DDR_PIR - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010701); - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); // DDR_PGSR0 - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - for (i = 0; i < 4; i++) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B1 + i*0x20); - RegVal_R5 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x0000FF00) >> 0x8; - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x00000007); - - if (RegVal_R6 > 0) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | RegVal_R6); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | RegVal_R7); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); - } // RegVal_R6 - } // for i - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000005); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0xC1AA00C0); - - //rev.0.08 - if (pdqsr_ctl == 1) - { - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - - } - - // PDR always off // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010801); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000005); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0xC1AA00D8); - - - //rev.0.08 - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00011001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - if (pdqsr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - } - - // PDR dynamic // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - } - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00012001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - if (pdqsr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - } - - // PDR always off // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00014001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - if (pdqsr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - } - - // PDR dynamic // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - } - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00018001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x0000002C); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x81003087); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00010401); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - for (i = 0; i < 4; i++) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B1 + i*0x20); - RegVal_R5 = ((ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x0000FF00) >> 0x8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x00000007); - RegVal_R12 = (RegVal_R5 >> 0x2); - - if (RegVal_R12 < RegVal_R6) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); - }else - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007)); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); - } // RegVal_R12 < RegVal_R6 - } // for i - -//rev.0.08 - if (pdqsr_ctl == 1) - { - } - else - { - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - - } - - // PDR always off // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00015001); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_G2E_DBPDRGD0)) == 0) - { - ; - } - -//rev.0.08 - if (lcdl_ctl == 1) - { - for (i = 0; i < 4; i++) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i*0x20); - dqsgd_0c = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B1 + i*0x20); - bdlcount_0c = ((ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x0000FF00) >> 8); - bdlcount_0c_div2 = (bdlcount_0c >> 1); - bdlcount_0c_div4 = (bdlcount_0c >> 2); - bdlcount_0c_div8 = (bdlcount_0c >> 3); - bdlcount_0c_div16 = (bdlcount_0c >> 4); - - if (ddr_md == 0) - { - // 1584Mbps - lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8; - lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16; - } - else - { - // 1856Mbps - lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4; - lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4; - } // ddr_md - - if (dqsgd_0c > lcdl_judge1) - { - if (dqsgd_0c <= lcdl_judge2) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal)); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i * 0x20); - gatesl_0c = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0x00000007); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_G2E_DBPDRGD0, (RegVal|(gatesl_0c + 1))); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AF + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0)); - rdqsd_0c = (RegVal & 0x0000FF00) >> 8; - rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AF + i * 0x20); - WriteReg_32(DBSC_G2E_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16))); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AA + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0)); - rbd_0c[0] = (RegVal) & 0x0000001f; - rbd_0c[1] = (RegVal >> 8) & 0x0000001f; - rbd_0c[2] = (RegVal >> 16) & 0x0000001f; - rbd_0c[3] = (RegVal >> 24) & 0x0000001f; - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AA + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xE0E0E0E0); - for (j = 0; j < 4; j++) - { - rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); - if (rbd_0c[j] > 0x1F) - { - rbd_0c[j] = 0x1F; - } - RegVal = RegVal | (rbd_0c[j] << 8*j); - } - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AB + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0)); - rbd_0c[0] = (RegVal) & 0x0000001f; - rbd_0c[1] = (RegVal >> 8) & 0x0000001f; - rbd_0c[2] = (RegVal >> 16) & 0x0000001f; - rbd_0c[3] = (RegVal >> 24) & 0x0000001f; - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000AB + i * 0x20); - RegVal = (ReadReg_32(DBSC_G2E_DBPDRGD0) & 0xE0E0E0E0); - for (j = 0; j < 4; j++) - { - rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); - if (rbd_0c[j] > 0x1F) - { - rbd_0c[j] = 0x1F; - } - RegVal = RegVal | (rbd_0c[j] << 8*j); - } - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal); - } - } - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000002); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x07D81E37); - } - - - - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000003); - if (byp_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0380C720); - } - else - { - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0380C700); - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000007); - while ((BIT30 & ReadReg_32(DBSC_G2E_DBPDRGD0)) != 0) - { - ; - } - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000021); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x0024643E); - - /*********************************************************************** - * recovery_Step3(DBSC Setting 2) - **********************************************************************/ - WriteReg_32(DBSC_G2E_DBDFICUPDCNF, 0x40100001); - WriteReg_32(DBSC_G2E_DBACEN, 0x00000001); - -//rev.0.08 - if (pdqsr_ctl == 1) - { - WriteReg_32(0xE67F0018, 0x00000001); - RegVal = ReadReg_32(0x40000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGD0, RegVal); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x7C0002C5); - - } - - // PDR dynamic // rev.0.10 add - if (pdr_ctl == 1) - { - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_G2E_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_G2E_DBPDRGD0, 0x00000000); - } - - - WriteReg_32(DBSC_G2E_DBPDLK0, 0x00000000); - WriteReg_32(DBSC_G2E_DBSYSCNT0, 0x00000000); - -#ifdef ddr_qos_init_setting // only for non qos_init - WriteReg_32(DBSC_G2E_DBSYSCNT0, 0x00001234); - WriteReg_32(DBSC_G2E_DBCAM0CNF1, 0x00043218); - WriteReg_32(DBSC_G2E_DBCAM0CNF2, 0x000000F4); - WriteReg_32(DBSC_G2E_DBSCHCNT0, 0x000f0037); - WriteReg_32(DBSC_G2E_DBSCHSZ0, 0x00000001); - WriteReg_32(DBSC_G2E_DBSCHRW0, 0x22421111); - WriteReg_32(DBSC_G2E_SCFCTST2, 0x012F1123); - WriteReg_32(DBSC_G2E_DBSCHQOS00, 0x00000F00); - WriteReg_32(DBSC_G2E_DBSCHQOS01, 0x00000B00); - WriteReg_32(DBSC_G2E_DBSCHQOS02, 0x00000000); - WriteReg_32(DBSC_G2E_DBSCHQOS03, 0x00000000); - WriteReg_32(DBSC_G2E_DBSCHQOS40, 0x00000300); - WriteReg_32(DBSC_G2E_DBSCHQOS41, 0x000002F0); - WriteReg_32(DBSC_G2E_DBSCHQOS42, 0x00000200); - WriteReg_32(DBSC_G2E_DBSCHQOS43, 0x00000100); - WriteReg_32(DBSC_G2E_DBSCHQOS90, 0x00000100); - WriteReg_32(DBSC_G2E_DBSCHQOS91, 0x000000F0); - WriteReg_32(DBSC_G2E_DBSCHQOS92, 0x000000A0); - WriteReg_32(DBSC_G2E_DBSCHQOS93, 0x00000040); - WriteReg_32(DBSC_G2E_DBSCHQOS130, 0x00000100); - WriteReg_32(DBSC_G2E_DBSCHQOS131, 0x000000F0); - WriteReg_32(DBSC_G2E_DBSCHQOS132, 0x000000A0); - WriteReg_32(DBSC_G2E_DBSCHQOS133, 0x00000040); - WriteReg_32(DBSC_G2E_DBSCHQOS140, 0x000000C0); - WriteReg_32(DBSC_G2E_DBSCHQOS141, 0x000000B0); - WriteReg_32(DBSC_G2E_DBSCHQOS142, 0x00000080); - WriteReg_32(DBSC_G2E_DBSCHQOS143, 0x00000040); - WriteReg_32(DBSC_G2E_DBSCHQOS150, 0x00000040); - WriteReg_32(DBSC_G2E_DBSCHQOS151, 0x00000030); - WriteReg_32(DBSC_G2E_DBSCHQOS152, 0x00000020); - WriteReg_32(DBSC_G2E_DBSCHQOS153, 0x00000010); - -//rev.0.08 - if (pdqsr_ctl == 1) - { - ; - } - else - { - WriteReg_32(0xE67F0018, 0x00000001); - } - WriteReg_32(DBSC_G2E_DBSYSCNT0, 0x00000000); -#endif - - return 1; - -} // recovery_from_backup_mode - -/******************************************************************************* - * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps - ******************************************************************************/ - -/******************************************************************************* - * DDR Initialize entry for IPL - ******************************************************************************/ -int32_t InitDram(void) -{ - uint32_t dataL; - uint32_t failcount; - uint32_t md = 0; - uint32_t ddr = 0; - - md = *((volatile uint32_t*)RST_MODEMR); - ddr = (md & 0x00080000) >> 19; - if (ddr == 0x0) - { - NOTICE("BL2: DDR1584(%s)\n", RZG2E_DDR_VERSION); - } - else if (ddr == 0x1) - { - NOTICE("BL2: DDR1856(%s)\n", RZG2E_DDR_VERSION); - } - // ddr - - dram_get_boot_status(&ddrBackup); - - if (ddrBackup == DRAM_BOOT_STATUS_WARM) - { - dataL = recovery_from_backup_mode(); // WARM boot - } - else - { - dataL = init_ddr(); // COLD boot - } - // ddrBackup - - if (dataL == 1) - { - failcount = 0; - } - else - { - failcount = 1; - } - // dataL - - if (failcount == 0) - { - return INITDRAM_OK; - } - else - { - return INITDRAM_NG; - } - // failcount -} // InitDram - -/******************************************************************************* - * END - ******************************************************************************/ diff --git a/ddr/ddr3l/ddr_init_g2e.h b/ddr/ddr3l/ddr_init_g2e.h deleted file mode 100644 index f71f70c..0000000 --- a/ddr/ddr3l/ddr_init_g2e.h +++ /dev/null @@ -1,28 +0,0 @@ -#pragma once -#include - -#ifndef __DDR_INIT_G2E_ -#define __DDR_INIT_G2E_ - -#define RZG2E_DDR_VERSION "rev.0.12" - -#ifdef ddr_qos_init_setting - #define REFRESH_RATE 3900 // Average periodic refresh interval[ns]. Support 3900,7800 -#else - #if RZG2_REF_INT == 0 - #define REFRESH_RATE 3900 - #elif RZG2_REF_INT == 1 - #define REFRESH_RATE 7800 - #else - #define REFRESH_RATE 3900 - #endif -#endif - -extern int32_t InitDram(void); -#define INITDRAM_OK (0) -#define INITDRAM_NG (0xffffffff) -#define INITDRAM_ERR_I (0xffffffff) -#define INITDRAM_ERR_O (0xfffffffe) -#define INITDRAM_ERR_T (0xfffffff0) - -#endif /* __DDR_INIT_G2E_ */ diff --git a/ddr/dram_sub_func.c b/ddr/dram_sub_func.c deleted file mode 100644 index d69865f..0000000 --- a/ddr/dram_sub_func.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include "dram_sub_func.h" - - -void dram_get_boot_status(uint32_t *status) -{ - *status = DRAM_BOOT_STATUS_COLD; -} - -int32_t dram_update_boot_status(uint32_t status) -{ - int32_t ret = 0; - - return ret; -} diff --git a/ddr/dram_sub_func.h b/ddr/dram_sub_func.h deleted file mode 100644 index 5131508..0000000 --- a/ddr/dram_sub_func.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DRAM_SUB_FUNC_H_ -#define DRAM_SUB_FUNC_H_ - -#define DRAM_BOOT_STATUS_COLD (0U) -#define DRAM_BOOT_STATUS_WARM (1U) - -#define DRAM_UPDATE_STATUS_ERR (-1) - -void dram_get_boot_status(uint32_t *status); -int32_t dram_update_boot_status(uint32_t status); - -#endif /* DRAM_SUB_FUNC_H_ */ diff --git a/ddr/lpddr4/boot_init_dram.c b/ddr/lpddr4/boot_init_dram.c deleted file mode 100644 index 44bef6d..0000000 --- a/ddr/lpddr4/boot_init_dram.c +++ /dev/null @@ -1,4401 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include "ddr_regdef.h" -#include "init_dram_tbl_g2h.h" -#include "init_dram_tbl_g2m.h" -#include "init_dram_tbl_g2n.h" -#include "boot_init_dram_regdef.h" -#include "boot_init_dram.h" -#include "dram_sub_func.h" -#include "micro_wait.h" - -//#define DDR_BACKUPMODE -#define FATAL_MSG(x) NOTICE(x) - -/******************************************************************************* - * variables - ******************************************************************************/ -static uint32_t Prr_Product; -static uint32_t Prr_Cut; - -char *pRZG_DDR_VERSION; -uint32_t _cnf_BOARDTYPE; -static const uint32_t *pDDR_REGDEF_TBL; -static uint32_t brd_clk; -static uint32_t brd_clkdiv; -static uint32_t brd_clkdiva; -static uint32_t ddr_mbps; -static uint32_t ddr_mbpsdiv; -static uint32_t ddr_tccd; -static uint32_t ddr_phycaslice; -static const struct _boardcnf *Boardcnf; -static uint32_t ddr_phyvalid; -static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; -static uint32_t ch_have_this_cs[CS_CNT]__attribute__ ((aligned(64))); -static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT*2][9]; -static uint32_t max_density; -static uint32_t ddr0800_mul; -static uint32_t ddr_mul; -static uint32_t DDR_PHY_SLICE_REGSET_OFS; -static uint32_t DDR_PHY_ADR_V_REGSET_OFS; -static uint32_t DDR_PHY_ADR_I_REGSET_OFS; -static uint32_t DDR_PHY_ADR_G_REGSET_OFS; -static uint32_t DDR_PI_REGSET_OFS; -static uint32_t DDR_PHY_SLICE_REGSET_SIZE; -static uint32_t DDR_PHY_ADR_V_REGSET_SIZE; -static uint32_t DDR_PHY_ADR_I_REGSET_SIZE; -static uint32_t DDR_PHY_ADR_G_REGSET_SIZE; -static uint32_t DDR_PI_REGSET_SIZE; -static uint32_t DDR_PHY_SLICE_REGSET_NUM; -static uint32_t DDR_PHY_ADR_V_REGSET_NUM; -static uint32_t DDR_PHY_ADR_I_REGSET_NUM; -static uint32_t DDR_PHY_ADR_G_REGSET_NUM; -static uint32_t DDR_PI_REGSET_NUM; -static uint32_t DDR_PHY_ADR_I_NUM; -#define DDR_PHY_REGSET_MAX 128 -#define DDR_PI_REGSET_MAX 320 -static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; -static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; -static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; -static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; -static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; -static uint32_t Pll3Mode; -static uint32_t loop_max; -#ifdef DDR_BACKUPMODE -uint32_t ddrBackup; -/* #define DDR_BACKUPMODE_HALF //for Half channel(ch0, 1 only) */ -#endif - -#ifdef ddr_qos_init_setting /* only for non qos_init */ -#define OPERATING_FREQ (400U) /* Mhz */ -#define BASE_SUB_SLOT_NUM (0x6U) -#define SUB_SLOT_CYCLE (0x7EU) /* 126 */ -#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) /* unit:ns */ - -uint32_t get_refperiod(void) -{ - return (uint32_t)QOSWT_WTSET0_CYCLE; -} -#else /* ddr_qos_init_setting // only for non qos_init */ -extern uint32_t get_refperiod(void); -#endif /* ddr_qos_init_setting // only for non qos_init */ - -#define _reg_PHY_RX_CAL_X_NUM 11 -static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { - _reg_PHY_RX_CAL_DQ0, - _reg_PHY_RX_CAL_DQ1, - _reg_PHY_RX_CAL_DQ2, - _reg_PHY_RX_CAL_DQ3, - _reg_PHY_RX_CAL_DQ4, - _reg_PHY_RX_CAL_DQ5, - _reg_PHY_RX_CAL_DQ6, - _reg_PHY_RX_CAL_DQ7, - _reg_PHY_RX_CAL_DM, - _reg_PHY_RX_CAL_DQS, - _reg_PHY_RX_CAL_FDBK -}; - -#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 -static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { - _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ3_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ4_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ5_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ6_SLAVE_DELAY, - _reg_PHY_CLK_WRDQ7_SLAVE_DELAY, - _reg_PHY_CLK_WRDM_SLAVE_DELAY, - _reg_PHY_CLK_WRDQS_SLAVE_DELAY -}; - -#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 -static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { - _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY, - _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY -}; - -#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 -static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { - _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY, - _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY -}; - -#define _reg_PHY_PAD_TERM_X_NUM 8 -static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { - _reg_PHY_PAD_FDBK_TERM, - _reg_PHY_PAD_DATA_TERM, - _reg_PHY_PAD_DQS_TERM, - _reg_PHY_PAD_ADDR_TERM, - _reg_PHY_PAD_CLK_TERM, - _reg_PHY_PAD_CKE_TERM, - _reg_PHY_PAD_RST_TERM, - _reg_PHY_PAD_CS_TERM -}; - -#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 -static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { - _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY, - _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY, - - _reg_PHY_GRP_SLAVE_DELAY_0, - _reg_PHY_GRP_SLAVE_DELAY_1, - _reg_PHY_GRP_SLAVE_DELAY_2, - _reg_PHY_GRP_SLAVE_DELAY_3 -}; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -static inline uint32_t vch_nxt(uint32_t pos); -static void cpg_write_32(uint32_t a, uint32_t v); -static void pll3_control(uint32_t high); -static inline void dsb_sev(void); -static void wait_dbcmd(void); -static void send_dbcmd(uint32_t cmd); -static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); -static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); -static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); -static inline uint32_t ddr_regdef(uint32_t _regdef); -static inline uint32_t ddr_regdef_adr(uint32_t _regdef); -static inline uint32_t ddr_regdef_lsb(uint32_t _regdef); -static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, uint32_t val); -static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); -static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); -static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); -static void ddr_setval_ach(uint32_t regdef, uint32_t val); -static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); -static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); -static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); -static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); -static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); -static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); -static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); -static uint32_t ddrphy_regif_chk(void); -static inline void ddrphy_regif_idle(void); -static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, uint16_t cyc); -static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint16_t *js2); -static int16_t _f_scale_adj(int16_t ps); -static void ddrtbl_load(void); -static void ddr_config_sub(void); -static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); -static void ddr_config(void); -static void dbsc_regset(void); -static void dbsc_regset_post(void); -static uint32_t dfi_init_start(void); -static void change_lpddr4_en(uint32_t mode); -static uint32_t set_term_code(void); -static void ddr_register_set(void); -static inline uint32_t wait_freqchgreq(uint32_t assert); -static inline void set_freqchgack(uint32_t assert); -static inline void set_dfifrequency(uint32_t freq); -static uint32_t pll3_freq(uint32_t on); -static void update_dly(void); -static uint32_t pi_training_go(void); -static uint32_t init_ddr(void); -static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick); -static uint32_t wdqdm_man1(void); -static uint32_t wdqdm_man(void); -static uint32_t rdqdm_man1(void); -static uint32_t rdqdm_man(void); - -static int32_t _find_change(uint64_t val, uint32_t dir); -static uint32_t _rx_offset_cal_updn(uint32_t code); -static uint32_t rx_offset_cal(void); -static uint32_t rx_offset_cal_hw(void); -static void adjust_rddqs_latency(void); -static void adjust_wpath_latency(void); - -struct DdrtData { - int32_t init_temp; /* Initial Temperature (do) */ - uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ - uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ -}; -struct DdrtData tcal; - -static void pvtcode_update(void); -static void pvtcode_update2(void); -static void ddr_padcal_tcompensate_getinit(uint32_t override); - -/******************************************************************************* - * load board configuration - ******************************************************************************/ -#include "boot_init_dram_config.c" - -#ifndef DDR_FAST_INIT -static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; -static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; -static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; -static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; -static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2]; -static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn); -static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn); - -static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; -static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; -static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; -static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; -static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; -static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); -static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); -#endif /* DDR_FAST_INIT */ - -/******************************************************************************* - * macro for channel selection loop - ******************************************************************************/ -static inline uint32_t vch_nxt(uint32_t pos) -{ - uint32_t posn; - - for (posn = pos; posn < DRAM_CH_CNT; posn++) - { - if (ddr_phyvalid & (1U << posn)) - { - break; - } - } - return posn; -} - -#define foreach_vch(ch) \ -for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) - -#define foreach_ech(ch) \ -for (ch = 0; ch < DRAM_CH_CNT; ch++) - -/******************************************************************************* - * Printing functions - ******************************************************************************/ -#define MSG_LF(...) - -/******************************************************************************* - * clock settings, reset control - ******************************************************************************/ -static void cpg_write_32(uint32_t a, uint32_t v) -{ - mmio_write_32(CPG_CPGWPR, ~v); - mmio_write_32(a, v); -} - -static void pll3_control(uint32_t high) -{ - uint32_t dataL, dataDIV, dataMUL, tmpDIV; - - if (high) - { - tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr_mul) / 2; - dataMUL = (((ddr_mul * tmpDIV) - 1) << 24); - Pll3Mode = 1; - loop_max = 2; - } - else - { - tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr0800_mul) / 2; - dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24); - Pll3Mode = 0; - loop_max = 8; - } - switch (tmpDIV) - { - case 1: - dataDIV = 0; - break; - case 2: - dataDIV = 2; - break; - case 3: - dataDIV = 3; - break; - case 4: - dataDIV = 4; - break; - default: - dataDIV = 6; - dataMUL = (dataMUL * tmpDIV) / 3; - break; - } - dataMUL = dataMUL | (brd_clkdiva << 7); - - /* PLL3 disable */ - dataL = (~CPG_PLLECR_PLL3E_BIT) & mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, dataL); - dsb_sev(); - - if (Prr_Product == PRR_PRODUCT_G2M) - { - /* PLL3 DIV resetting(Lowest value:3) */ - dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); - dsb_sev(); - - /* zb3 clk stop */ - dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); - cpg_write_32(CPG_ZB3CKCR, dataL); - dsb_sev(); - - /* PLL3 enable */ - dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, dataL); - dsb_sev(); - - do - { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); - dsb_sev(); - - /* PLL3 DIV resetting (Highest value:0) */ - dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); - dsb_sev(); - - /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); - dsb_sev(); - - /* PLL3 multiplie set */ - cpg_write_32(CPG_PLL3CR, dataMUL); - dsb_sev(); - - do - { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); - dsb_sev(); - - /* PLL3 DIV resetting(Target value) */ - dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); - dsb_sev(); - - /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); - dsb_sev(); - - do - { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); - dsb_sev(); - - /* zb3 clk start */ - dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); - cpg_write_32(CPG_ZB3CKCR, dataL); - dsb_sev(); - - } - else - { - /* PLL3 multiplie set */ - cpg_write_32(CPG_PLL3CR, dataMUL); - dsb_sev(); - - /* PLL3 DIV set(Target value) */ - dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); - cpg_write_32(CPG_FRQCRD, dataL); - - /* DIV SET KICK */ - dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); - cpg_write_32(CPG_FRQCRB, dataL); - dsb_sev(); - - /* PLL3 enable */ - dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); - cpg_write_32(CPG_PLLECR, dataL); - dsb_sev(); - - do - { - dataL = mmio_read_32(CPG_PLLECR); - } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); - dsb_sev(); - } -} - -/******************************************************************************* - * barrier - ******************************************************************************/ -static inline void dsb_sev(void) -{ - __asm__ __volatile__ ("dsb sy"); -} - -/******************************************************************************* - * DDR memory register access - ******************************************************************************/ -static void wait_dbcmd(void) -{ - uint32_t dataL; - - /* dummy read */ - dataL = mmio_read_32(DBSC_DBCMD); - dsb_sev(); - while (1) - { - /* wait DBCMD 1 = busy, 0 = ready */ - dataL = mmio_read_32(DBSC_DBWAIT); - dsb_sev(); - if ((dataL & 0x00000001) == 0x00) - { - break; - } - } -} - -static void send_dbcmd(uint32_t cmd) -{ - /* dummy read */ - wait_dbcmd(); - mmio_write_32(DBSC_DBCMD, cmd); - dsb_sev(); -} - -static void dbwait_loop(uint32_t wait_loop) -{ - uint32_t i; - - for (i = 0; wait_loop> i; i++) - { - wait_dbcmd(); - } -} - -/******************************************************************************* - * DDRPHY register access (raw) - ******************************************************************************/ -static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) -{ - uint32_t val; - uint32_t loop; - - val = 0; - if (Prr_Product != PRR_PRODUCT_G2N) - { - mmio_write_32(DBSC_DBPDRGA(phyno), regadd); - dsb_sev(); - - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) - { - dsb_sev(); - } - dsb_sev(); - - for (loop = 0; loop < loop_max; loop++) - { - val = mmio_read_32(DBSC_DBPDRGD(phyno)); - dsb_sev(); - } - (void)val; - } - else - { - mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000); - dsb_sev(); - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000)) - { - dsb_sev(); - } - val = mmio_read_32(DBSC_DBPDRGA(phyno)); - mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) - { - dsb_sev(); - } - dsb_sev(); - - mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) - { - dsb_sev(); - } - dsb_sev(); - val = mmio_read_32(DBSC_DBPDRGD(phyno)); - dsb_sev(); - (void)val; - } - return val; -} - -static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) -{ - uint32_t val; - uint32_t loop; - - if (Prr_Product != PRR_PRODUCT_G2N) - { - mmio_write_32(DBSC_DBPDRGA(phyno), regadd); - dsb_sev(); - for (loop = 0; loop < loop_max; loop++) - { - val = mmio_read_32(DBSC_DBPDRGA(phyno)); - dsb_sev(); - } - mmio_write_32(DBSC_DBPDRGD(phyno), regdata); - dsb_sev(); - - for (loop = 0; loop < loop_max; loop++) - { - val = mmio_read_32(DBSC_DBPDRGD(phyno)); - dsb_sev(); - } - } - else - { - mmio_write_32(DBSC_DBPDRGA(phyno), regadd); - dsb_sev(); - - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) - { - dsb_sev(); - } - dsb_sev(); - - mmio_write_32(DBSC_DBPDRGD(phyno), regdata); - dsb_sev(); - - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000)) - { - dsb_sev(); - } - mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); - - while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) - { - dsb_sev(); - } - dsb_sev(); - - mmio_write_32(DBSC_DBPDRGA(phyno), regadd); - } - (void)val; -} - -static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) -{ - uint32_t ch; - uint32_t val; - uint32_t loop; - - if (Prr_Product != PRR_PRODUCT_G2N) - { - foreach_vch(ch) - { - mmio_write_32(DBSC_DBPDRGA(ch), regadd); - dsb_sev(); - } - - foreach_vch(ch) - { - mmio_write_32(DBSC_DBPDRGD(ch), regdata); - dsb_sev(); - } - - for (loop = 0; loop < loop_max; loop++) - { - val = mmio_read_32(DBSC_DBPDRGD(0)); - dsb_sev(); - } - (void)val; - } - else - { - foreach_vch(ch) - { - reg_ddrphy_write(ch, regadd, regdata); - dsb_sev(); - } - } -} - -static inline void ddrphy_regif_idle(void) -{ - uint32_t val; - - val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS)); - dsb_sev(); - (void)val; -} - -/******************************************************************************* - * DDRPHY register access (field modify) - ******************************************************************************/ -static inline uint32_t ddr_regdef(uint32_t _regdef) -{ - return pDDR_REGDEF_TBL[_regdef]; -} - -static inline uint32_t ddr_regdef_adr(uint32_t _regdef) -{ - return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]); -} - -static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) -{ - return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]); -} - -static inline uint32_t ddr_regdef_len(uint32_t _regdef) -{ - return DDR_REGDEF_LEN(pDDR_REGDEF_TBL[_regdef]); -} - -static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, uint32_t val) -{ - uint32_t adr; - uint32_t lsb; - uint32_t len; - uint32_t msk; - uint32_t tmp; - uint32_t regdef; - - regdef = ddr_regdef(_regdef); - adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; - len = DDR_REGDEF_LEN(regdef); - lsb = DDR_REGDEF_LSB(regdef); - if (len == 0x20) - { - msk = 0xffffffff; - } - else - { - msk = ((1U << len) - 1) << lsb; - } - tmp = reg_ddrphy_read(ch, adr); - tmp = (tmp & (~msk)) | ((val << lsb) & msk); - reg_ddrphy_write(ch, adr, tmp); -} - -static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) -{ - uint32_t adr; - uint32_t lsb; - uint32_t len; - uint32_t msk; - uint32_t tmp; - uint32_t regdef; - - regdef = ddr_regdef(_regdef); - adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; - len = DDR_REGDEF_LEN(regdef); - lsb = DDR_REGDEF_LSB(regdef); - if (len == 0x20) - { - msk = 0xffffffff; - } - else - { - msk = ((1U << len) - 1); - } - tmp = reg_ddrphy_read(ch, adr); - tmp = (tmp >> lsb) & msk; - - return tmp; -} - -static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) -{ - ddr_setval_s(ch, 0, regdef, val); -} - -static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) -{ - uint32_t ch; - - foreach_vch(ch) - { - ddr_setval_s(ch, slice, regdef, val); - } -} - -static void ddr_setval_ach(uint32_t regdef, uint32_t val) -{ - ddr_setval_ach_s(0, regdef, val); -} - -static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) -{ - uint32_t slice; - - for (slice = 0; slice < SLICE_CNT; slice++) - { - ddr_setval_ach_s(slice, regdef, val); - } -} - -static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) -{ - return ddr_getval_s(ch, 0, regdef); -} - -static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p) -{ - uint32_t ch; - - foreach_vch(ch) - { - p[ch] = ddr_getval_s(ch, 0, regdef); - } - return p[0]; -} - -static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) -{ - uint32_t ch, slice; - uint32_t *pp; - - pp = p; - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - *pp++ = ddr_getval_s(ch, slice, regdef); - } - } - return p[0]; -} - -/******************************************************************************* - * handling functions for setteing ddrphy value table - ******************************************************************************/ -static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) -{ - uint32_t i; - - for (i = 0; i < size; i++) - { - to[i] = from[i]; - } -} - -static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) -{ - uint32_t adr; - uint32_t lsb; - uint32_t len; - uint32_t msk; - uint32_t tmp; - uint32_t adrmsk; - uint32_t regdef; - - regdef = ddr_regdef(_regdef); - adr = DDR_REGDEF_ADR(regdef); - len = DDR_REGDEF_LEN(regdef); - lsb = DDR_REGDEF_LSB(regdef); - if (len == 0x20) - { - msk = 0xffffffff; - } - else - { - msk = ((1U << len) - 1) << lsb; - } - if (adr < 0x400) - { - adrmsk = 0xff; - } - else - { - adrmsk = 0x7f; - } - tmp = tbl[adr & adrmsk]; - tmp = (tmp & (~msk)) | ((val << lsb) & msk); - tbl[adr & adrmsk] = tmp; -} - -static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) -{ - uint32_t adr; - uint32_t lsb; - uint32_t len; - uint32_t msk; - uint32_t tmp; - uint32_t adrmsk; - uint32_t regdef; - - regdef = ddr_regdef(_regdef); - adr = DDR_REGDEF_ADR(regdef); - len = DDR_REGDEF_LEN(regdef); - lsb = DDR_REGDEF_LSB(regdef); - if (len == 0x20) - { - msk = 0xffffffff; - } - else - { - msk = ((1U << len) - 1); - } - if (adr < 0x400) - { - adrmsk = 0xff; - } - else - { - adrmsk = 0x7f; - } - tmp = tbl[adr & adrmsk]; - tmp = (tmp >> lsb) & msk; - - return tmp; -} - -/******************************************************************************* - * DDRPHY register access handling - ******************************************************************************/ -static uint32_t ddrphy_regif_chk(void) -{ - uint32_t tmp_ach[DRAM_CH_CNT]; - uint32_t ch; - uint32_t err; - uint32_t PI_VERSION_CODE; - - if (Prr_Product == PRR_PRODUCT_G2M) - { - PI_VERSION_CODE = 0x2041; /* RZ/G2M */ - } - else - { - PI_VERSION_CODE = 0x2040; /* RZ/G2N, RZ/G2H */ - } - ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); - err = 0; - foreach_vch(ch) - { - if (tmp_ach[ch] != PI_VERSION_CODE) - { - err = 1; - } - } - return err; -} - -/******************************************************************************* - * functions and parameters for timing setting - ******************************************************************************/ -struct _jedec_spec1 { - uint16_t fx3; - uint8_t RLwoDBI; - uint8_t RLwDBI; - uint8_t WL; - uint8_t nWR; - uint8_t nRTP; - uint8_t ODTLon; - uint8_t MR1; - uint8_t MR2; -}; -#define JS1_USABLEC_SPEC_LO 2 -#define JS1_USABLEC_SPEC_HI 5 -#define JS1_FREQ_TBL_NUM 8 -#define JS1_MR1(f) (0x04 | ((f) << 4)) -#define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) -const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { - { 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0)|0x40 }, /* 533.333Mbps */ - { 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1)|0x40 }, /* 1066.666Mbps */ - { 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2)|0x40 }, /* 1600.000Mbps */ - { 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) }, /* 2133.333Mbps */ - { 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) }, /* 2666.666Mbps */ - { 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) }, /* 3200.000Mbps */ - { 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) }, /* 3733.333Mbps */ - { 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) } /* 4266.666Mbps */ -}; - -struct _jedec_spec2 { - uint16_t ps; - uint16_t cyc; -}; - -#define JS2_tSR 0 -#define JS2_tXP 1 -#define JS2_tRTP 2 -#define JS2_tRCD 3 -#define JS2_tRPpb 4 -#define JS2_tRPab 5 -#define JS2_tRAS 6 -#define JS2_tWR 7 -#define JS2_tWTR 8 -#define JS2_tRRD 9 -#define JS2_tPPD 10 -#define JS2_tFAW 11 -#define JS2_tDQSCK 12 -#define JS2_tCKEHCMD 13 -#define JS2_tCKELCMD 14 -#define JS2_tCKELPD 15 -#define JS2_tMRR 16 -#define JS2_tMRW 17 -#define JS2_tMRD 18 -#define JS2_tZQCALns 19 -#define JS2_tZQLAT 20 -#define JS2_tIEdly 21 -#define JS2_tODTon_min 22 -#define JS2_TBLCNT 23 - -#define JS2_tRCpb (JS2_TBLCNT) -#define JS2_tRCab (JS2_TBLCNT + 1) -#define JS2_tRFCab (JS2_TBLCNT + 2) -#define JS2_CNT (JS2_TBLCNT + 3) - -#ifndef JS2_DERATE -#define JS2_DERATE 0 -#endif -const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { - { -/*tSR */ { 15000, 3 }, -/*tXP */ { 7500, 3 }, -/*tRTP */ { 7500, 8 }, -/*tRCD */ { 18000, 4 }, -/*tRPpb */ { 18000, 3 }, -/*tRPab */ { 21000, 3 }, -/*tRAS */ { 42000, 3 }, -/*tWR */ { 18000, 4 }, -/*tWTR */ { 10000, 8 }, -/*tRRD */ { 10000, 4 }, -/*tPPD */ { 0, 0 }, -/*tFAW */ { 40000, 0 }, -/*tDQSCK*/ { 3500, 0 }, -/*tCKEHCMD*/ { 7500, 3 }, -/*tCKELCMD*/ { 7500, 3 }, -/*tCKELPD*/ { 7500, 3 }, -/*tMRR*/ { 0, 8 }, -/*tMRW*/ { 10000, 10 }, -/*tMRD*/ { 14000, 10 }, -/*tZQCALns*/ {1000*10, 0 }, -/*tZQLAT*/ { 30000, 10 }, -/*tIEdly*/ { 12500, 0 }, -/*tODTon_min*/ { 1500, 0 } - }, { -/*tSR */ { 15000, 3 }, -/*tXP */ { 7500, 3 }, -/*tRTP */ { 7500, 8 }, -/*tRCD */ { 19875, 4 }, -/*tRPpb */ { 19875, 3 }, -/*tRPab */ { 22875, 3 }, -/*tRAS */ { 43875, 3 }, -/*tWR */ { 18000, 4 }, -/*tWTR */ { 10000, 8 }, -/*tRRD */ { 11875, 4 }, -/*tPPD */ { 0, 0 }, -/*tFAW */ { 40000, 0 }, -/*tDQSCK*/ { 3600, 0 }, -/*tCKEHCMD*/ { 7500, 3 }, -/*tCKELCMD*/ { 7500, 3 }, -/*tCKELPD*/ { 7500, 3 }, -/*tMRR*/ { 0, 8 }, -/*tMRW*/ { 10000, 10 }, -/*tMRD*/ { 14000, 10 }, -/*tZQCALns*/ {1000*10, 0 }, -/*tZQLAT*/ { 30000, 10 }, -/*tIEdly*/ { 12500, 0 }, -/*tODTon_min*/ { 1500, 0 } - } -}; - -const uint16_t jedec_spec2_tRFC_ab[7] = { -/* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ - 130, 180, 180, 280, 280, 560, 560 -}; - -static uint32_t js1_ind; -static uint16_t js2[JS2_CNT]; -static uint8_t RL; -static uint8_t WL; - -static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, uint16_t cyc) -{ - uint32_t tmp; - uint32_t div; - - tmp = (((uint32_t)(ps) + 9) / 10) * ddr_mbps; - div = tmp / (200000 * ddr_mbpsdiv); - if (tmp != (div * 200000 * ddr_mbpsdiv)) - { - div = div + 1; - } - if (div > cyc) - { - return (uint16_t)div; - } - return cyc; -} - -static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint16_t *js2) -{ - int i; - - for (i = 0; i < JS2_TBLCNT; i++) - { - js2[i] = _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL*jedec_spec2[JS2_DERATE][i].ps, - jedec_spec2[JS2_DERATE][i].cyc); - } - - js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb]; - js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab]; -} - -/* scaler for DELAY value */ -static int16_t _f_scale_adj(int16_t ps) -{ - int32_t tmp; - - tmp = (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / (int32_t)ddr_mbpsdiv; - tmp = (int32_t)tmp / (int32_t)15625; - - return (int16_t)tmp; -} - -const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { - { - _reg_PI_MR1_DATA_F0_0, - _reg_PI_MR1_DATA_F0_1, - _reg_PI_MR1_DATA_F0_2, - _reg_PI_MR1_DATA_F0_3 - }, - { - _reg_PI_MR1_DATA_F1_0, - _reg_PI_MR1_DATA_F1_1, - _reg_PI_MR1_DATA_F1_2, - _reg_PI_MR1_DATA_F1_3 - } -}; - -const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = { - { - _reg_PI_MR2_DATA_F0_0, - _reg_PI_MR2_DATA_F0_1, - _reg_PI_MR2_DATA_F0_2, - _reg_PI_MR2_DATA_F0_3 - }, - { - _reg_PI_MR2_DATA_F1_0, - _reg_PI_MR2_DATA_F1_1, - _reg_PI_MR2_DATA_F1_2, - _reg_PI_MR2_DATA_F1_3 - } -}; - -const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = { - { - _reg_PI_MR3_DATA_F0_0, - _reg_PI_MR3_DATA_F0_1, - _reg_PI_MR3_DATA_F0_2, - _reg_PI_MR3_DATA_F0_3 - }, - { - _reg_PI_MR3_DATA_F1_0, - _reg_PI_MR3_DATA_F1_1, - _reg_PI_MR3_DATA_F1_2, - _reg_PI_MR3_DATA_F1_3 - } -}; - -const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = { - { - _reg_PI_MR11_DATA_F0_0, - _reg_PI_MR11_DATA_F0_1, - _reg_PI_MR11_DATA_F0_2, - _reg_PI_MR11_DATA_F0_3 - }, - { - _reg_PI_MR11_DATA_F1_0, - _reg_PI_MR11_DATA_F1_1, - _reg_PI_MR11_DATA_F1_2, - _reg_PI_MR11_DATA_F1_3 - } -}; - -const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = { - { - _reg_PI_MR12_DATA_F0_0, - _reg_PI_MR12_DATA_F0_1, - _reg_PI_MR12_DATA_F0_2, - _reg_PI_MR12_DATA_F0_3 - }, - { - _reg_PI_MR12_DATA_F1_0, - _reg_PI_MR12_DATA_F1_1, - _reg_PI_MR12_DATA_F1_2, - _reg_PI_MR12_DATA_F1_3 - } -}; - -const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = { - { - _reg_PI_MR14_DATA_F0_0, - _reg_PI_MR14_DATA_F0_1, - _reg_PI_MR14_DATA_F0_2, - _reg_PI_MR14_DATA_F0_3 - }, - { - _reg_PI_MR14_DATA_F1_0, - _reg_PI_MR14_DATA_F1_1, - _reg_PI_MR14_DATA_F1_2, - _reg_PI_MR14_DATA_F1_3 - } -}; - -/******************************************************************************* - * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) - *******************************************************************************/ -static void regif_pll_wa(void) -{ - uint32_t ch; - - /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */ - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), (0x5064U << ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), - (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL_TOP) << 16) | - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL)); - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL_CA)); - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), - (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) | - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_PLL_CTRL)); - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), - ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_TOP_PLL_CTRL)); - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), - _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); - - /* protect register interface */ - ddrphy_regif_idle(); - pll3_control(0); - - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), (0x01U << ddr_regdef_lsb(_reg_PHY_DLL_RST_EN))); - ddrphy_regif_idle(); - - /*********************************************************************** - * init start - ***********************************************************************/ - /* dbdficnt0: - * dfi_dram_clk_disable = 1 - * dfi_frequency = 0 - * freq_ratio = 01 (2:1) - * init_start = 0 - */ - foreach_vch(ch) - { - mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); - } - dsb_sev(); - - /* dbdficnt0: - * dfi_dram_clk_disable = 1 - * dfi_frequency = 0 - * freq_ratio = 01 (2:1) - * init_start = 1 - */ - foreach_vch(ch) - { - mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); - } - dsb_sev(); - - foreach_ech(ch) - { - if (((Boardcnf->phyvalid) & (1U << ch))) - { - while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) - { - ; - } - } - } - dsb_sev(); -} - -/******************************************************************************* - * load table data into DDR registers - ******************************************************************************/ -static void ddrtbl_load(void) -{ - uint32_t i; - uint32_t slice; - uint32_t csab; - uint32_t adr; - uint32_t dataL; - uint32_t tmp[3]; - uint16_t dataS; - - /*********************************************************************** - * TIMING REGISTERS - ***********************************************************************/ - /* search jedec_spec1 index */ - for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) - { - if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) - { - break; - } - } - if (i > JS1_USABLEC_SPEC_HI) - { - js1_ind = JS1_USABLEC_SPEC_HI; - } - else - { - js1_ind = i; - } - if (Boardcnf->dbi_en) - { - RL = js1[js1_ind].RLwDBI; - } - else - { - RL = js1[js1_ind].RLwoDBI; - } - WL = js1[js1_ind].WL; - - /* calculate jedec_spec2 */ - _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); - - /*********************************************************************** - * PREPARE TBL - ***********************************************************************/ - if (Prr_Product == PRR_PRODUCT_G2H) - { - _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, - DDR_PHY_SLICE_REGSET_G2H, DDR_PHY_SLICE_REGSET_NUM_G2H); - _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, - DDR_PHY_ADR_V_REGSET_G2H, DDR_PHY_ADR_V_REGSET_NUM_G2H); - _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, - DDR_PHY_ADR_G_REGSET_G2H, DDR_PHY_ADR_G_REGSET_NUM_G2H); - _tblcopy(_cnf_DDR_PI_REGSET, - DDR_PI_REGSET_G2H, DDR_PI_REGSET_NUM_G2H); - - DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_G2H; - DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_G2H; - DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_G2H; - DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_G2H; - DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_G2H; - DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_G2H; - DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_G2H; - DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_G2H; - DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_G2H; - DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_G2H; - DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_G2H; - DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_G2H; - - DDR_PHY_ADR_I_NUM = 0; - } - else if (Prr_Product == PRR_PRODUCT_G2M) - { - _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, - DDR_PHY_SLICE_REGSET_G2M, DDR_PHY_SLICE_REGSET_NUM_G2M); - _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, - DDR_PHY_ADR_V_REGSET_G2M, DDR_PHY_ADR_V_REGSET_NUM_G2M); - _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, - DDR_PHY_ADR_I_REGSET_G2M, DDR_PHY_ADR_I_REGSET_NUM_G2M); - _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, - DDR_PHY_ADR_G_REGSET_G2M, DDR_PHY_ADR_G_REGSET_NUM_G2M); - _tblcopy(_cnf_DDR_PI_REGSET, - DDR_PI_REGSET_G2M, DDR_PI_REGSET_NUM_G2M); - - DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_G2M; - DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_G2M; - DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_G2M; - DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_G2M; - DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_G2M; - DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_G2M; - DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_G2M; - DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_G2M; - DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_G2M; - DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_G2M; - DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_G2M; - DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_G2M; - DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_G2M; - DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_G2M; - DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_G2M; - - DDR_PHY_ADR_I_NUM = 2; - } - else - { - _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, - DDR_PHY_SLICE_REGSET_G2N, DDR_PHY_SLICE_REGSET_NUM_G2N); - _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, - DDR_PHY_ADR_V_REGSET_G2N, DDR_PHY_ADR_V_REGSET_NUM_G2N); - _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, - DDR_PHY_ADR_I_REGSET_G2N, DDR_PHY_ADR_I_REGSET_NUM_G2N); - _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, - DDR_PHY_ADR_G_REGSET_G2N, DDR_PHY_ADR_G_REGSET_NUM_G2N); - _tblcopy(_cnf_DDR_PI_REGSET, - DDR_PI_REGSET_G2N, DDR_PI_REGSET_NUM_G2N); - - DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_G2N; - DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_G2N; - DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_G2N; - DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_G2N; - DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_G2N; - DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_G2N; - DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_G2N; - DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_G2N; - DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_G2N; - DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_G2N; - DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_G2N; - DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_G2N; - DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_G2N; - DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_G2N; - DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_G2N; - - DDR_PHY_ADR_I_NUM = 2; - } - - /*********************************************************************** - * on fly gate adjust - ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut == PRR_PRODUCT_10)) - { - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_ON_FLY_GATE_ADJUST_EN, 0x00); - } - /*********************************************************************** - * Adjust PI parameters - ***********************************************************************/ -#ifdef _def_LPDDR4_ODT - for (i = 0; i < 2; i++) - { - for (csab = 0; csab < CSAB_CNT; csab++) - { - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[i][csab], _def_LPDDR4_ODT); - } - } -#endif /* _def_LPDDR4_ODT */ - -#ifdef _def_LPDDR4_VREFCA - for (i = 0; i < 2; i++) - { - for (csab = 0; csab < CSAB_CNT; csab++) - { - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_Fx_CSx[i][csab], _def_LPDDR4_VREFCA); - } - } -#endif /* _def_LPDDR4_VREFCA */ - if (Prr_Product == PRR_PRODUCT_G2N) - { - js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; - if (js2[JS2_tIEdly] > (RL)) - { - js2[JS2_tIEdly] = RL; - } - } - else if (Prr_Product == PRR_PRODUCT_G2H) - { - js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; - } - - if ((Prr_Product == PRR_PRODUCT_G2N) || (Prr_Product == PRR_PRODUCT_G2H)) - { - if ((js2[JS2_tIEdly]) >= 0x1e) - { - dataS = 0x1e; - } - else - { - dataS = js2[JS2_tIEdly]; - } - } - else - { - if ((js2[JS2_tIEdly]) >= 0x0e) - { - dataS = 0x0e; - } - else - { - dataS = js2[JS2_tIEdly]; - } - } - - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, (dataS - 2)); - if (Prr_Product == PRR_PRODUCT_G2N) - { - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_OE_DLY, (dataS - 2)); - } - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS); - - if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) - { - dataL = WL - 1; - } - else - { - dataL = WL; - } - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2); - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL); - - if (Boardcnf->dbi_en) - { - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 0x01); - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WDQLVL_DATADM_MASK, 0x000); - } - else - { - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 0x00); - ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WDQLVL_DATADM_MASK, 0x100); - } - - tmp[0] = js1[js1_ind].MR1; - tmp[1] = js1[js1_ind].MR2; - dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); - if (Boardcnf->dbi_en) - { - tmp[2] = dataL | 0xc0; - } - else - { - tmp[2] = dataL & (~0xc0); - } - for (i = 0; i < 2; i++) - { - for (csab = 0; csab < CSAB_CNT; csab++) - { - ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]); - ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]); - ddrtbl_setval(_cnf_DDR_PI_REGSET, - _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]); - } - } - - /*********************************************************************** - * DDRPHY INT START - ***********************************************************************/ - regif_pll_wa(); - dbwait_loop(5); - - /*********************************************************************** - * FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) - ***********************************************************************/ - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); - - /*********************************************************************** - * SET DATA SLICE TABLE - ***********************************************************************/ - for (slice = 0; slice < SLICE_CNT; slice++) - { - adr = DDR_PHY_SLICE_REGSET_OFS + DDR_PHY_SLICE_REGSET_SIZE * slice; - for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) - { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_SLICE_REGSET[i]); - } - } - - /*********************************************************************** - * SET ADR SLICE TABLE - ***********************************************************************/ - adr = DDR_PHY_ADR_V_REGSET_OFS; - for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) - { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); - } - if (((Prr_Product == PRR_PRODUCT_G2M) || (Prr_Product == PRR_PRODUCT_G2N)) && - ((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40)) != 0x00)) - { - adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; - for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) - { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); - } - ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_ADR_DISABLE, 0x02); - DDR_PHY_ADR_I_NUM -= 1; - ddr_phycaslice = 1; - -#ifndef _def_LPDDR4_ODT - for (i = 0; i < 2; i++) - { - for (csab = 0; csab < CSAB_CNT; csab++) - { - ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[i][csab], 0x66); - } - } -#endif /* _def_LPDDR4_ODT */ - } - else - { - ddr_phycaslice = 0; - } - - if (DDR_PHY_ADR_I_NUM > 0) - { - for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) - { - adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE * slice; - for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) - { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_I_REGSET[i]); - } - } - } - - /*********************************************************************** - * SET ADRCTRL SLICE TABLE - ***********************************************************************/ - adr = DDR_PHY_ADR_G_REGSET_OFS; - for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) - { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); - } - /*********************************************************************** - * SET PI REGISTERS - ***********************************************************************/ - adr = DDR_PI_REGSET_OFS; - for (i = 0; i < DDR_PI_REGSET_NUM; i++) - { - reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); - } -} - -/******************************************************************************* - * CONFIGURE DDR REGISTERS - ******************************************************************************/ -static void ddr_config_sub(void) -{ - uint32_t i; - uint32_t ch, slice; - uint32_t dataL; - uint32_t tmp; - uint8_t high_byte[SLICE_CNT]; - const uint32_t _par_CALVL_DEVICE_MAP = 1; - - foreach_vch(ch) - { - /*********************************************************************** - * BOARD SETTINGS (DQ, DM, VREF_DRIVING) - ***********************************************************************/ - for (slice = 0; slice < SLICE_CNT; slice++) - { - high_byte[slice] = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2; - ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].dq_swap[slice]); - ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, Boardcnf->ch[ch].dm_swap[slice]); - if (high_byte[slice]) - { - /* HIGHER 16 BYTE */ - ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x00); - } - else - { - /* LOWER 16 BYTE */ - ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x01); - } - } - - /*********************************************************************** - * BOARD SETTINGS (CA, ADDR_SEL) - ***********************************************************************/ - dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) | 0x00888888; - - /* --- ADR_CALVL_SWIZZLE --- */ - if (Prr_Product == PRR_PRODUCT_G2M) - { - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); - ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); - } - else - { - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); - ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); - ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); - } - - /* --- ADR_ADDR_SEL --- */ - if (Prr_Product == PRR_PRODUCT_G2H) - { - dataL = 0x00FFFFFF & (uint32_t)(Boardcnf->ch[ch].ca_swap); - } - else - { - dataL = 0; - tmp = (uint32_t)(Boardcnf->ch[ch].ca_swap); - for (i = 0; i < 6; i++) - { - dataL |= ((tmp & 0x0f) << (i * 5)); - tmp = tmp >> 4; - } - } - ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL); - if (ddr_phycaslice == 1) - { - /* ----------- adr slice2 swap ----------- */ - tmp = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40); - dataL = (tmp & 0x00ffffff) | 0x00888888; - - /* --- ADR_CALVL_SWIZZLE --- */ - if (Prr_Product == PRR_PRODUCT_G2M) - { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); - } - else - { - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); - ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); - ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); - } - - /* --- ADR_ADDR_SEL --- */ - dataL = 0; - for (i = 0; i < 6; i++) - { - dataL |= ((tmp & 0x0f) << (i * 5)); - tmp = tmp >> 4; - } - ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL); - } - - /*********************************************************************** - * BOARD SETTINGS (BYTE_ORDER_SEL) - ***********************************************************************/ - if (Prr_Product == PRR_PRODUCT_G2M) - { - /* --- DATA_BYTE_SWAP --- */ - dataL = 0; - tmp = Boardcnf->ch[ch].dqs_swap; - for (i = 0; i < 4; i++) - { - dataL |= ((tmp & 0x03) << (i * 2)); - tmp = tmp >> 4; - } - } - else - { - /* --- DATA_BYTE_SWAP --- */ - dataL = Boardcnf->ch[ch].dqs_swap; - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, (dataL) & 0x0f); - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4 * 1) & 0x0f); - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, (dataL >> 4 * 2) & 0x0f); - ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, (dataL >> 4 * 3) & 0x0f); - - ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); - } - ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL); - } -} - -static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) -{ - uint32_t slice; - uint32_t tmp; - uint32_t tgt; - - if (ddr_csn / 2) - { - tgt = 3; - } - else - { - tgt = 1; - } - for (slice = 0; slice < SLICE_CNT; slice++) - { - tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (tgt == tmp) - { - break; - } - } - tmp = 0x00FFFFFF & (uint32_t)(Boardcnf->ch[ch].ca_swap); - if (slice % 2) - { - tmp |= 0x00888888; - } - *p_swz = tmp; -} - -static void ddr_config(void) -{ - int32_t i; - uint32_t ch, slice; - uint32_t dataL; - uint32_t tmp; - int8_t _adj; - int16_t adj; - uint32_t dq; - union { - uint32_t ui32[4]; - uint8_t ui8[16]; - } patt; - uint16_t patm; - - /*********************************************************************** - * configure ddrphy registers - ***********************************************************************/ - ddr_config_sub(); - - /*********************************************************************** - * WDQ_USER_PATT - ***********************************************************************/ - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - patm = 0; - for (i = 0; i < 16; i++) - { - tmp = Boardcnf->ch[ch].wdqlvl_patt[i]; - patt.ui8[i] = tmp & 0xff; - if (tmp & 0x100) - { - patm |= (1U << i); - } - } - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0, patt.ui32[0]); - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1, patt.ui32[1]); - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2, patt.ui32[2]); - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3, patt.ui32[3]); - ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm); - } - } - - /*********************************************************************** - * CACS DLY - ***********************************************************************/ - dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U); - foreach_vch(ch) - { - for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) - { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); - ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), - _cnf_DDR_PHY_ADR_V_REGSET[ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_V_REGSET_OFS]); - } - for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) - { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); - ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), - _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_G_REGSET_OFS]); - } - if (ddr_phycaslice == 1) - { - for (i = 0; i < 6; i++) - { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); - ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 0x0100, - _cnf_DDR_PHY_ADR_V_REGSET[ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_V_REGSET_OFS]); - } - } - } - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), - (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); - - /*********************************************************************** - * WDQDM DLY - ***********************************************************************/ - dataL = Boardcnf->dqdm_dly_w; - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - for (i = 0; i <= 8; i++) - { - dq = slice * 8 + i; - if (i == 8) - { - _adj = Boardcnf->ch[ch].dm_adj_w[slice]; - } - else - { - _adj = Boardcnf->ch[ch].dq_adj_w[dq]; - } - adj = _f_scale_adj(_adj); - ddr_setval_s(ch, slice, - _reg_PHY_CLK_WRX_SLAVE_DELAY[i], - dataL + adj - ); - } - } - } - - /*********************************************************************** - * RDQDM DLY - ***********************************************************************/ - dataL = Boardcnf->dqdm_dly_r; - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - for (i = 0; i <= 8; i++) - { - dq = slice * 8 + i; - if (i == 8) - { - _adj = Boardcnf->ch[ch].dm_adj_r[slice]; - } - else - { - _adj = Boardcnf->ch[ch].dq_adj_r[dq]; - } - adj = _f_scale_adj(_adj); - ddr_setval_s(ch, slice, - _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], - dataL + adj - ); - ddr_setval_s(ch, slice, - _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], - dataL + adj - ); - } - } - } -} - -/******************************************************************************* - * DBSC register setting functions - ******************************************************************************/ -static void dbsc_regset_pre(void) -{ - uint32_t ch, csab; - uint32_t dataL; - - /*********************************************************************** - * PRIMARY SETTINGS - ***********************************************************************/ - /* LPDDR4, BL = 16, DFI interface */ - mmio_write_32(DBSC_DBKIND, 0x0000000a); - mmio_write_32(DBSC_DBBL, 0x00000002); - mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); - - /* FREQRATIO=2 */ - mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); - - /* DRAM SIZE REGISTER: - * set all ranks as density=0(4Gb) for PHY initialization - */ - foreach_vch(ch) - { - for (csab = 0; csab < 4; csab++) - { - mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); - } - } - if (Prr_Product == PRR_PRODUCT_G2M) - { - dataL = 0xe4e4e4e4; - foreach_ech(ch) - { - if ((ddr_phyvalid & (1U << ch))) - { - dataL = (dataL & (~(0x000000FF << (ch*8)))) - | (((Boardcnf->ch[ch].dqs_swap & 0x0003) - | ((Boardcnf->ch[ch].dqs_swap & 0x0030) >> 2) - | ((Boardcnf->ch[ch].dqs_swap & 0x0300) >> 4) - | ((Boardcnf->ch[ch].dqs_swap & 0x3000) >> 6)) << (ch*8)); - } - } - mmio_write_32(DBSC_DBBSWAP, dataL); - } -} - -static void dbsc_regset(void) -{ - int32_t i; - uint32_t ch; - uint32_t dataL; - uint32_t dataL2; - uint32_t tmp[4]; - - /* RFC */ - if ((Prr_Product == PRR_PRODUCT_G2H) && (Prr_Cut == PRR_PRODUCT_20) && (max_density == 0)) - { - js2[JS2_tRFCab] = _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL*jedec_spec2_tRFC_ab[1] * 1000, 0); - } - else - { - js2[JS2_tRFCab] = _f_scale(ddr_mbps, ddr_mbpsdiv, - 1UL*jedec_spec2_tRFC_ab[max_density] * 1000, 0); - } - - /* DBTR0.CL : RL */ - mmio_write_32(DBSC_DBTR(0), RL); - - /* DBTR1.CWL : WL */ - mmio_write_32(DBSC_DBTR(1), WL); - - /* DBTR2.AL : 0 */ - mmio_write_32(DBSC_DBTR(2), 0); - - /* DBTR3.TRCD: tRCD */ - mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]); - - /* DBTR4.TRPA, TRP: tRPab, tRPpb */ - mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); - - /* DBTR5.TRC : use tRCpb */ - mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]); - - /* DBTR6.TRAS : tRAS */ - mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]); - - /* DBTR7.TRRD : tRRD */ - mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); - - /* DBTR8.TFAW : tFAW */ - mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]); - - /* DBTR9.TRDPR : tRTP */ - mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]); - - /* DBTR10.TWR : nWR */ - mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR); - - /* DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff - ODTLon + tDQSCK - tODTon,min + PCB delay (out+in) + tPHY_ODToff */ - mmio_write_32(DBSC_DBTR(11), - RL + (16 / 2) + 1 + 2 - js1[js1_ind].ODTLon + js2[JS2_tDQSCK] - js2[JS2_tODTon_min] + _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0)); - - /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ - dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR]; - mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL); - - /* DBTR13.TRFCAB : tRFCab */ - mmio_write_32(DBSC_DBTR(13), - (js2[JS2_tRFCab])); - - /* DBTR14.TCKEHDLL, tCKEH : tCKEHCMD, tCKEHCMD */ - mmio_write_32(DBSC_DBTR(14), - (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD])); - - /* DBTR15.TCKESR, TCKEL : tSR, tCKELPD */ - mmio_write_32(DBSC_DBTR(15), - (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD])); - - /* DBTR16 */ - /* WDQL : tphy_wrlat + tphy_wrdata */ - tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); - /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0 - * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0 - */ - tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); - /* DQL : tphy_rdlat + trdata_en */ - /* it is not important for dbsc */ - tmp[2] = RL + 16; - /* DQIENLTNCY : trdata_en */ - tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1; - mmio_write_32(DBSC_DBTR(16), - (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* DBTR24 */ - /* WRCSLAT = WRLAT -5 */ - tmp[0] -= 5; - /* WRCSGAP = 5 */ - tmp[1] = 5; - /* RDCSLAT = RDLAT_ADJ +2 */ - if (Prr_Product == PRR_PRODUCT_G2M) - { - tmp[2] = tmp[3]; - } - else - { - tmp[2] = tmp[3] + 2; - } - /* RDCSGAP = 6 */ - if (Prr_Product == PRR_PRODUCT_G2M) - { - tmp[3] = 4; - } - else - { - tmp[3] = 6; - } - mmio_write_32(DBSC_DBTR(24), - (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* DBTR17.TMODRD, TMOD, TRDMR: tMRR, tMRD, (0) */ - mmio_write_32(DBSC_DBTR(17), (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16)); - - /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ - mmio_write_32(DBSC_DBTR(18), 0); - - /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ - mmio_write_32(DBSC_DBTR(19), 0); - - /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ - dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD]; - mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL); - - /* DBTR21.TCCD */ - /* DBTR23.TCCD */ - if (ddr_tccd == 8) - { - dataL = 8; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); - mmio_write_32(DBSC_DBTR(23), 0x00000002); - } - else if (ddr_tccd <= 11) - { - dataL = 11; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); - mmio_write_32(DBSC_DBTR(23), 0x00000000); - } - else - { - dataL = ddr_tccd; - mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); - mmio_write_32(DBSC_DBTR(23), 0x00000000); - } - - /* DBTR22.ZQLAT : */ - dataL = js2[JS2_tZQCALns]*100; /* 1000 * 1000 ps */ - dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20); - mmio_write_32(DBSC_DBTR(22), dataL); - - /* DBTR25 : do not use in LPDDR4 */ - mmio_write_32(DBSC_DBTR(25), 0); - - /* DBRNK : */ - /* - * DBSC_DBRNK2 rkrr - * DBSC_DBRNK3 rkrw - * DBSC_DBRNK4 rkwr - * DBSC_DBRNK5 rkww - */ - #define _par_DBRNK_VAL (0x7007) - - for (i = 0; i < 4; i++) - { - dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; - if ((Prr_Product == PRR_PRODUCT_G2H) && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) - { - dataL += 1; - } - dataL2 = 0; - foreach_vch(ch) - { - dataL2 = dataL2 | (dataL << (4 * ch)); - } - mmio_write_32(DBSC_DBRNK(2 + i), dataL2); - } - mmio_write_32(DBSC_DBADJ0, 0x00000000); - - /*********************************************************************** - * timing registers for Scheduler - ***********************************************************************/ - /* SCFCTST0 */ - /* SCFCTST0 ACT-ACT */ - tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST0 RDA-ACT */ - tmp[2] = 1UL * ((16 / 2) + js2[JS2_tRTP] - 8 + js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST0 WRA-ACT */ - tmp[1] = 1UL * (WL + 1 + (16 / 2) + js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST0 PRE-ACT */ - tmp[0] = 1UL * js2[JS2_tRPpb]; - mmio_write_32(DBSC_SCFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* SCFCTST1 */ - /* SCFCTST1 RD-WR */ - tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST1 WR-RD */ - tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST1 ACT-RD/WR */ - tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps; - /* SCFCTST1 ASYNCOFS */ - tmp[0] = 12; - mmio_write_32(DBSC_SCFCTST1, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* DBSCHRW1 */ - /* DBSCHRW1 SCTRFCAB */ - tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps; - dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) - + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; - if (tmp[0] < dataL) - { - tmp[0] = dataL; - } - if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut < PRR_PRODUCT_30)) - { - mmio_write_32(DBSC_DBSCHRW1, tmp[0] - + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3); - } - else - { - mmio_write_32(DBSC_DBSCHRW1, tmp[0] - + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) - * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps); - } - - /*********************************************************************** - * QOS and CAM - ***********************************************************************/ -#ifdef ddr_qos_init_setting /* only for non qos_init */ - /* wbkwait(0004), wbkmdhi(4, 2), wbkmdlo(1, 8) */ - mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); - /* 0(fillunit), 8(dirtymax), 4(dirtymin) */ - mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); - /* stop_tolerance */ - mmio_write_32(DBSC_DBSCHRW0, 0x22421111); - /* rd-wr/wr-rd toggle priority */ - mmio_write_32(DBSC_SCFCTST2, 0x012F1123); - mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); - mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037); - - /* QoS Settings */ - mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U); - mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U); - mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U); - mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U); - mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U); - mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U); - mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U); - mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U); - mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U); - mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U); - mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U); - mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U); - mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U); - mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U); - mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U); - mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U); - mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U); - mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U); - mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U); - mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U); - mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U); - mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U); - mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U); - mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U); - - mmio_write_32(QOSCTRL_RAEN, 0x00000001U); -#endif /* ddr_qos_init_setting */ - - if (Prr_Product == PRR_PRODUCT_G2H) - { - if (Prr_Cut < PRR_PRODUCT_30) - { - /* resrdis */ - mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); - } - else - { - /* exprespque */ - mmio_write_32(DBSC_DBBCAMDIS, 0x00000010); - } - } - else - { - /* resrdis */ - mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); - } -} - -static void dbsc_regset_post(void) -{ - uint32_t ch, cs; - uint32_t dataL; - uint32_t slice, rdlat_max, rdlat_min; - - rdlat_max = 0; - rdlat_min = 0xffff; - foreach_vch(ch) - { - for (cs = 0; cs < CS_CNT; cs++) - { - if ((ch_have_this_cs[cs] & (1U << ch)) != 0) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_LATENCY_ADJUST); - if (dataL > rdlat_max) - { - rdlat_max = dataL; - } - if (dataL < rdlat_min) - { - rdlat_min = dataL; - } - } - } - } - } - if ((Prr_Product == PRR_PRODUCT_G2H) && (Prr_Cut > PRR_PRODUCT_11)) - { -#if RZG_DRAM_SPLIT == 2 - if (Boardcnf->phyvalid == 0x05) - { - mmio_write_32(DBSC_DBTR(24), - ((rdlat_max) << 24) + ((rdlat_min) << 16) + mmio_read_32(DBSC_DBTR(24))); - } - else - { - mmio_write_32(DBSC_DBTR(24), - ((rdlat_max * 2 - rdlat_min + 4) << 24) + ((rdlat_min + 2) << 16) + mmio_read_32(DBSC_DBTR(24))); - } -#else /*RZG_DRAM_SPLIT == 2 */ - mmio_write_32(DBSC_DBTR(24), - ((rdlat_max * 2 - rdlat_min + 4) << 24) + ((rdlat_min + 2) << 16) + mmio_read_32(DBSC_DBTR(24))); -#endif /*RZG_DRAM_SPLIT == 2 */ - } - else - { - mmio_write_32(DBSC_DBTR(24), - ((rdlat_max + 2) << 24) + ((rdlat_max + 2) << 16) + mmio_read_32(DBSC_DBTR(24))); - } - - /* set ddr density information */ - foreach_ech(ch) - { - for (cs = 0; cs < CS_CNT; cs++) - { - if (ddr_density[ch][cs] == 0xff) - { - mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); - } - else - { - mmio_write_32(DBSC_DBMEMCONF(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); - } - } - mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000); - mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000); - } - - mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); - - /* set DBI */ - if (Boardcnf->dbi_en) - { - mmio_write_32(DBSC_DBDBICNT, 0x00000003); - } - - /* RZ/G2N, RZ/G2H DBI wa */ - if (((Prr_Product == PRR_PRODUCT_G2N) || (Prr_Product == PRR_PRODUCT_G2H)) && (Boardcnf->dbi_en)) - { - reg_ddrphy_write_a(0x00001010, 0x01000000); - } - /* set REFCYCLE */ - dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; - mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff)); - mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); - -#if RZG_REWT_TRAINING != 0 - /* Periodic-WriteDQ Training seeting */ - mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); - - ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04); - ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F); - ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50); - ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300); - - ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP, ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WDQLVL_CS_MAP)); - ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); - ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01); - ddr_setval_ach(_reg_PI_TREF_F0, 0x0000); - ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); - ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); - - if (Prr_Product == PRR_PRODUCT_G2M) - { - ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); - } - else - { - ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); - } - ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); - - /* DFI_PHYMSTR_ACK , WTmode setting */ - mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); /* DFI_PHYMSTR_ACK: WTmode = b'01 */ -#endif /* RZG_REWT_TRAINING */ - - /* periodic dram zqcal enable */ - mmio_write_32(DBSC_DBCALCNF, 0x01000010); - - /* periodic phy ctrl update enable */ - if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut < PRR_PRODUCT_30)) - { - /* non : RZ/G2M Ver.1.x not support */ - } - else - { -#if RZG_DRAM_SPLIT == 2 - if ((Prr_Product == PRR_PRODUCT_G2H) && (Boardcnf->phyvalid == 0x05)) - { - mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); - } - else - { - mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); - } -#else /* RZG_DRAM_SPLIT == 2 */ - mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); -#endif /* RZG_DRAM_SPLIT == 2 */ - } - -#ifdef DDR_BACKUPMODE - /* SRX */ - if (ddrBackup == DRAM_BOOT_STATUS_WARM) - { -#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */ - NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n"); - send_dbcmd(0x0A040001); - if (Prr_Product == PRR_PRODUCT_G2H) - { - send_dbcmd(0x0A140001); - } -#else /* DDR_BACKUPMODE_HALF */ /* for All channels */ - send_dbcmd(0x0A840001); -#endif /* DDR_BACKUPMODE_HALF */ - } -#endif /* DDR_BACKUPMODE */ - /* set Auto Refresh */ - mmio_write_32(DBSC_DBRFEN, 0x00000001); - -#if RZG_REWT_TRAINING != 0 - /* Periodic WriteDQ Traning */ - ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100); -#endif /* RZG_REWT_TRAINING */ - - /* dram access enable */ - mmio_write_32(DBSC_DBACEN, 0x00000001); - - MSG_LF("dbsc_regset_post(done)"); -} - -/******************************************************************************* - * DFI_INIT_START - ******************************************************************************/ -static uint32_t dfi_init_start(void) -{ - uint32_t ch; - uint32_t phytrainingok; - uint32_t retry; - uint32_t dataL; - const uint32_t RETRY_MAX = 0x10000; - - ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02); - dsb_sev(); - ddrphy_regif_idle(); - - /* dll_rst negate */ - foreach_vch(ch) - { - mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); - } - dsb_sev(); - - /*********************************************************************** - * wait init_complete - ***********************************************************************/ - phytrainingok = 0; - retry = 0; - while (retry++ < RETRY_MAX) - { - foreach_vch(ch) - { - dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); - if (dataL & 0x00000001) - { - phytrainingok |= (1U << ch); - } - } - dsb_sev(); - if (phytrainingok == ddr_phyvalid) - { - break; - } - if ((retry % 256) == 0) - { - ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); - } - } - /*********************************************************************** - * all ch ok? - ***********************************************************************/ - if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) - { - return 0xff; - } - /* dbdficnt0: - * dfi_dram_clk_disable = 0 - * dfi_frequency = 0 - * freq_ratio = 01 (2:1) - * init_start = 0 - */ - foreach_vch(ch) - { - mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010); - } - dsb_sev(); - - return 0; -} - -/******************************************************************************* - * drivablity setting : CMOS MODE ON/OFF - ******************************************************************************/ -static void change_lpddr4_en(uint32_t mode) -{ - uint32_t ch; - uint32_t i; - uint32_t dataL; - const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { - _reg_PHY_PAD_ADDR_DRIVE, - _reg_PHY_PAD_CLK_DRIVE, - _reg_PHY_PAD_CS_DRIVE - }; - - foreach_vch(ch) - { - for (i = 0; i < 3; i++) - { - dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); - if (mode) - { - dataL |= (1U << 14); - } - else - { - dataL &= ~(1U << 14); - } - ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL); - } - } -} - -/******************************************************************************* - * drivablity setting - ******************************************************************************/ -static uint32_t set_term_code(void) -{ - int32_t i; - uint32_t ch, index; - uint32_t dataL; - uint32_t chip_id[2]; - uint32_t term_code; - uint32_t override; - uint32_t pvtr; - uint32_t pvtp; - uint32_t pvtn; - - term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_DATA_TERM); - override = 0; - for (i = 0; i < 2; i++) - { - chip_id[i] = mmio_read_32(LIFEC_CHIPID(i)); - } - index = 0; - while (1) - { - if (TermcodeBySample[index][0] == 0xffffffff) - { - break; - } - if ((TermcodeBySample[index][0] == chip_id[0]) && (TermcodeBySample[index][1] == chip_id[1])) - { - term_code = TermcodeBySample[index][2]; - override = 1; - break; - } - index++; - } - - if (override) - { - for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) - { - dataL = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[index]); - dataL = (dataL & 0xfffe0000) | term_code; - ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL); - } - } - else if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut == PRR_PRODUCT_10)) - { - /* non */ - } - else - { - ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], - (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000)); - ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01); - ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); - foreach_vch(ch) - { - do - { - dataL = ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); - } while (!(dataL & 0x00800000)); - } - foreach_vch(ch) - { - for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) - { - dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[index]); - ddr_setval(ch, _reg_PHY_PAD_TERM_X[index], (dataL & 0xFFFE0FFF) | 0x00015000); - } - } - } - ddr_padcal_tcompensate_getinit(override); - - return 0; -} - -/******************************************************************************* - * DDR mode register setting - ******************************************************************************/ -static void ddr_register_set(void) -{ - int32_t fspwp; - uint32_t tmp; - - for (fspwp = 1; fspwp >= 0; fspwp--) - { - /* MR13, fspwp */ - send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]); - send_dbcmd(0x0e840100 | tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]); - send_dbcmd(0x0e840200 | tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]); - send_dbcmd(0x0e840300 | tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]); - send_dbcmd(0x0e840b00 | tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]); - send_dbcmd(0x0e840c00 | tmp); - - tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]); - send_dbcmd(0x0e840e00 | tmp); - /* MR22 */ - send_dbcmd(0x0e841616); - - /* ZQCAL start */ - send_dbcmd(0x0d84004F); - - /* ZQLAT */ - send_dbcmd(0x0d840051); - } - /* MR13, fspwp */ - send_dbcmd(0x0e840d08); -} - -/******************************************************************************* - * Training handshake functions - ******************************************************************************/ -static inline uint32_t wait_freqchgreq(uint32_t assert) -{ - uint32_t dataL; - uint32_t count; - uint32_t ch; - - count = 100000; - - if (assert) - { - do - { - dataL = 1; - foreach_vch(ch) - { - dataL &= mmio_read_32(DBSC_DBPDSTAT(ch)); - } - count = count - 1; - } while (((dataL & 0x01) != 0x01) & (count != 0)); - } - else - { - do - { - dataL = 0; - foreach_vch(ch) - { - dataL |= mmio_read_32(DBSC_DBPDSTAT(ch)); - } - count = count - 1; - } while (((dataL & 0x01) != 0x00) & (count != 0)); - } - - return (count == 0); -} - -static inline void set_freqchgack(uint32_t assert) -{ - uint32_t ch; - uint32_t dataL; - - if (assert) - { - dataL = 0x0CF20000; - } - else - { - dataL = 0x00000000; - } - foreach_vch(ch) - { - mmio_write_32(DBSC_DBPDCNT2(ch), dataL); - } -} - -static inline void set_dfifrequency(uint32_t freq) -{ - uint32_t ch; - - foreach_vch(ch) - { - mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, (freq << 24)); - } - dsb_sev(); -} - -static uint32_t pll3_freq(uint32_t on) -{ - uint32_t timeout; - - timeout = wait_freqchgreq(1); - - if (timeout) - { - return 1; - } - pll3_control(on); - set_dfifrequency(on); - - set_freqchgack(1); - timeout = wait_freqchgreq(0); - set_freqchgack(0); - - if (timeout) - { - FATAL_MSG("BL2: Time out[2]\n"); - return 1; - } - return 0; -} - -/******************************************************************************* - * update dly - ******************************************************************************/ -static void update_dly(void) -{ - ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); - ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); -} - -/******************************************************************************* - * training by pi - ******************************************************************************/ -static uint32_t pi_training_go(void) -{ - uint32_t flag; - uint32_t dataL; - uint32_t retry; - const uint32_t RETRY_MAX = 4096*16; - uint32_t ch; - - uint32_t mst_ch; - uint32_t cur_frq; - uint32_t complete; - uint32_t frqchg_req; - - /* ********************************************************************* */ - - /*********************************************************************** - * pi_start - ***********************************************************************/ - ddr_setval_ach(_reg_PI_START, 0x01); - foreach_vch(ch) - { - ddr_getval(ch, _reg_PI_INT_STATUS); - } - /* set dfi_phymstr_ack = 1 */ - mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); - dsb_sev(); - - /*********************************************************************** - * wait pi_int_status[0] - ***********************************************************************/ - mst_ch = 0; - flag = 0; - complete = 0; - cur_frq = 0; - retry = RETRY_MAX; - do - { - frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; - - if (frqchg_req) - { - if (cur_frq) - { - /* Low frequency */ - flag = pll3_freq(0); - cur_frq = 0; - } - else - { - /* High frequency */ - flag = pll3_freq(1); - cur_frq = 1; - } - if (flag) - { - break; - } - } - else - { - if (cur_frq) - { - foreach_vch(ch) - { - if (complete & (1U << ch)) - { - continue; - } - dataL = ddr_getval(ch, _reg_PI_INT_STATUS); - if (dataL & 0x01) - { - complete |= (1U << ch); - } - } - if (complete == ddr_phyvalid) - { - break; - } - } - } - } while (--retry); - foreach_vch(ch) - { - /* dummy read */ - dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); - dataL = ddr_getval(ch, _reg_PI_INT_STATUS); - ddr_setval(ch, _reg_PI_INT_ACK, dataL); - } - if (ddrphy_regif_chk()) - { - return 0xfd; - } - return complete; -} - -/******************************************************************************* - * Initialize ddr - ******************************************************************************/ -static uint32_t init_ddr(void) -{ - int32_t i; - uint32_t dataL; - uint32_t phytrainingok; - uint32_t ch, slice; - uint32_t err; - int16_t adj; - - MSG_LF("init_ddr:0\n"); - -#ifdef DDR_BACKUPMODE - dram_get_boot_status(&ddrBackup); -#endif - - /*********************************************************************** - * unlock phy - ***********************************************************************/ - /* Unlock DDRPHY register(AGAIN) */ - foreach_vch(ch) - { - mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); - } - dsb_sev(); - - if (((Prr_Product == PRR_PRODUCT_G2N) || (Prr_Product == PRR_PRODUCT_G2H)) && (Boardcnf->dbi_en)) - { - reg_ddrphy_write_a(0x00001010, 0x01000001); - } - else - { - reg_ddrphy_write_a(0x00001010, 0x00000001); - } - /*********************************************************************** - * dbsc register pre-setting - ***********************************************************************/ - dbsc_regset_pre(); - - /*********************************************************************** - * load ddrphy registers - ***********************************************************************/ - - ddrtbl_load(); - - /*********************************************************************** - * configure ddrphy registers - ***********************************************************************/ - ddr_config(); - - /*********************************************************************** - * dfi_reset assert - ***********************************************************************/ - foreach_vch(ch) - { - mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); - } - dsb_sev(); - - /*********************************************************************** - * dbsc register set - ***********************************************************************/ - dbsc_regset(); - MSG_LF("init_ddr:1\n"); - - /*********************************************************************** - * dfi_reset negate - ***********************************************************************/ - foreach_vch(ch) - { - mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); - } - dsb_sev(); - - /*********************************************************************** - * dfi_init_start (start ddrphy) - ***********************************************************************/ - err = dfi_init_start(); - if (err) - { - return INITDRAM_ERR_I; - } - MSG_LF("init_ddr:2\n"); - - /*********************************************************************** - * ddr backupmode end - ***********************************************************************/ -#ifdef DDR_BACKUPMODE - if (ddrBackup) - { - NOTICE("BL2: [WARM_BOOT]\n"); - } - else - { - NOTICE("BL2: [COLD_BOOT]\n"); - } - err = dram_update_boot_status(ddrBackup); - - if (err) - { - NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); - return INITDRAM_ERR_I; - } -#endif - MSG_LF("init_ddr:3\n"); - - /*********************************************************************** - * override term code after dfi_init_complete - ***********************************************************************/ - err = set_term_code(); - if (err) - { - return INITDRAM_ERR_I; - } - MSG_LF("init_ddr:4\n"); - - /*********************************************************************** - * rx offset calibration - ***********************************************************************/ - if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_G2N)) - { - err = rx_offset_cal_hw(); - } - else - { - err = rx_offset_cal(); - } - if (err) - { - return INITDRAM_ERR_O; - } - MSG_LF("init_ddr:5\n"); - - /* Dummy PDE */ - send_dbcmd(0x08840000); - - /* PDX */ - send_dbcmd(0x08840001); - - /*********************************************************************** - * check register i/f is alive - ***********************************************************************/ - err = ddrphy_regif_chk(); - if (err) - { - return INITDRAM_ERR_O; - } - MSG_LF("init_ddr:6\n"); - - /*********************************************************************** - * phy initialize end - ***********************************************************************/ - - /*********************************************************************** - * setup DDR mode registers - ***********************************************************************/ - /* CMOS MODE */ - change_lpddr4_en(0); - - /* MRS */ - ddr_register_set(); - - /*********************************************************************** - * Thermal sensor setting - ***********************************************************************/ - /* THCTR Bit6: PONM = 0 , Bit0: THSST = 1 */ - dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; - mmio_write_32(THS1_THCTR, dataL); - - /* LPDDR4 MODE */ - change_lpddr4_en(1); - - MSG_LF("init_ddr:7\n"); - - /*********************************************************************** - * mask CS_MAP if RANKx is not found - ***********************************************************************/ - foreach_vch(ch) - { - dataL = ddr_getval(ch, _reg_PI_CS_MAP); - if (!(ch_have_this_cs[1] & (1U << ch))) - { - dataL = dataL & 0x05; - } - ddr_setval(ch, _reg_PI_CS_MAP, dataL); - } - - /*********************************************************************** - * exec pi_training - ***********************************************************************/ - reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); - - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, ((ch_have_this_cs[1]) >> ch) & 0x01); - } - } - - phytrainingok = pi_training_go(); - - if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) - { - return INITDRAM_ERR_T | phytrainingok; - } - MSG_LF("init_ddr:8\n"); - - /*********************************************************************** - * CACS DLY ADJUST - ***********************************************************************/ - dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); - foreach_vch(ch) - { - for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) - { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); - ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj - ); - } - if (ddr_phycaslice == 1) - { - for (i = 0; i < 6; i++) - { - adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); - ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], - dataL + adj - ); - } - } - } - update_dly(); - MSG_LF("init_ddr:9\n"); - - /*********************************************************************** - * Adjust Write path latency - ***********************************************************************/ - if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) - { - adjust_wpath_latency(); - } - /*********************************************************************** - * RDQLVL Training - ***********************************************************************/ - if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) - { - ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); - } - err = rdqdm_man(); - - if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) - { - ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); - } - if (err) - { - return INITDRAM_ERR_T; - } - update_dly(); - MSG_LF("init_ddr:10\n"); - - /*********************************************************************** - * WDQLVL Training - ***********************************************************************/ - err = wdqdm_man(); - if (err) - { - return INITDRAM_ERR_T; - } - update_dly(); - MSG_LF("init_ddr:11\n"); - - /*********************************************************************** - * training complete, setup dbsc - ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_G2N) || (Prr_Product == PRR_PRODUCT_G2H)) - { - ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); - ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); - } - - dbsc_regset_post(); - MSG_LF("init_ddr:12\n"); - - return phytrainingok; -} - -/******************************************************************************* - * SW LEVELING COMMON - ******************************************************************************/ -static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) -{ - uint32_t ch; - uint32_t dataL; - uint32_t retry; - uint32_t waiting; - uint32_t err; - - const uint32_t RETRY_MAX = 0x1000; - - err = 0; - /* set EXIT -> OP_DONE is cleared */ - ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); - - /* kick */ - foreach_vch(ch) - { - if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) - { - ddr_setval(ch, reg_cs, ddr_csn); - ddr_setval(ch, reg_kick, 0x01); - } - } - foreach_vch(ch) - { - /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE)*/ - ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); - } - waiting = ch_have_this_cs[ddr_csn % 2]; - dsb_sev(); - retry = RETRY_MAX; - do - { - foreach_vch(ch) - { - if (!(waiting & (1U << ch))) - { - continue; - } - dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); - if (dataL & 0x01) - { - waiting &= ~(1U << ch); - } - } - retry--; - } while ((waiting) && (retry > 0)); - if (retry == 0) - { - err = 1; - } - dsb_sev(); - /* set EXIT -> OP_DONE is cleared */ - ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); - dsb_sev(); - - return err; -} - -/******************************************************************************* - * WDQ TRAINING - ******************************************************************************/ -#ifndef DDR_FAST_INIT -static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) -{ - int32_t i, k; - uint32_t cs, slice; - uint32_t dataL; - - /*********************************************************************** - * clr of training results buffer - ***********************************************************************/ - cs = ddr_csn % 2; - dataL = Boardcnf->dqdm_dly_w; - for (slice = 0; slice < SLICE_CNT; slice++) - { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) - { - continue; - } - for (i = 0; i <= 8; i++) - { - if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) - { - wdqdm_dly[ch][cs][slice][i] = wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; - } - else - { - wdqdm_dly[ch][cs][slice][i] = dataL; - } - wdqdm_le[ch][cs][slice][i] = 0; - wdqdm_te[ch][cs][slice][i] = 0; - } - wdqdm_st[ch][cs][slice] = 0; - wdqdm_win[ch][cs][slice] = 0; - } -} - -static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) -{ - int32_t i, k; - uint32_t cs, slice; - uint32_t dataL; - uint32_t err; - const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; - - int32_t min_win; - int32_t win; - int8_t _adj; - int16_t adj; - uint32_t dq; - - /*********************************************************************** - * analysis of training results - ***********************************************************************/ - err = 0; - for (slice = 0; slice < SLICE_CNT; slice += 1) - { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) - { - continue; - } - cs = ddr_csn % 2; - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - for (i = 0; i < 9; i++) - { - dq = slice * 8 + i; - if (i == 8) - { - _adj = Boardcnf->ch[ch].dm_adj_w[slice]; - } - else - { - _adj = Boardcnf->ch[ch].dq_adj_w[dq]; - } - adj = _f_scale_adj(_adj); - - dataL = ddr_getval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], dataL); - wdqdm_dly[ch][cs][slice][i] = dataL; - } - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); - dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); - wdqdm_st[ch][cs][slice] = dataL; - min_win = INT_LEAST32_MAX; - for (i = 0; i <= 8; i++) - { - ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, i); - - dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); - wdqdm_te[ch][cs][slice][i] = dataL; - dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); - wdqdm_le[ch][cs][slice][i] = dataL; - win = (int32_t)wdqdm_te[ch][cs][slice][i] - wdqdm_le[ch][cs][slice][i]; - if (min_win > win) - { - min_win = win; - } - if (dataL >= _par_WDQLVL_RETRY_THRES) - { - err = 2; - } - } - wdqdm_win[ch][cs][slice] = min_win; - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, ((ch_have_this_cs[1]) >> ch) & 0x01); - } - return err; -} -#endif /* DDR_FAST_INIT */ - -static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) -{ - uint32_t i; - uint32_t ch, slice; - uint32_t tgt_cs, src_cs; - uint32_t tmp_r; - - /*********************************************************************** - * copy of training results - ***********************************************************************/ - foreach_vch(ch) - { - for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, tgt_cs); - src_cs = ddr_csn % 2; - if (!(ch_have_this_cs[1] & (1U << ch))) - { - src_cs = 0; - } - for (i = 0; i <= 4; i += 4) - { - if (restore) - { - tmp_r = rdqdm_dly[ch][tgt_cs][slice][i]; - } - else - { - tmp_r = rdqdm_dly[ch][src_cs][slice][i]; - } - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], tmp_r); - } - } - } - } -} - -static uint32_t wdqdm_man1(void) -{ - int32_t k; - uint32_t ch, cs, slice; - uint32_t ddr_csn; - uint32_t dataL; - uint32_t err; - uint32_t high_dq[DRAM_CH_CNT]; - uint32_t mr14_csab0_bak[DRAM_CH_CNT]; -#ifndef DDR_FAST_INIT - uint32_t err_flg; -#endif /* DDR_FAST_INIT */ - - /*********************************************************************** - * manual execution of training - ***********************************************************************/ - err = 0; - /* CLEAR PREV RESULT */ - for (cs = 0; cs < CS_CNT; cs++) - { - ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); - if ((Prr_Product == PRR_PRODUCT_G2N) || (Prr_Product == PRR_PRODUCT_G2H)) - { - ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01); - } - else - { - ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01); - } - } - ddrphy_regif_idle(); - -#ifndef DDR_FAST_INIT - err_flg = 0; -#endif /* DDR_FAST_INIT */ - - for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) - { - if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut == PRR_PRODUCT_10)) - { - wdqdm_cp(ddr_csn, 0); - } - - foreach_vch(ch) - { - dataL = ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]); - ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL); - } - - /* KICK WDQLVL */ - err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ); - if (err) - { - goto err_exit; - } - if (ddr_csn == 0) - { - foreach_vch(ch) - { - mr14_csab0_bak[ch] = ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]); - } - } - else - { - foreach_vch(ch) - { - ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], mr14_csab0_bak[ch]); - } - } -#ifndef DDR_FAST_INIT - foreach_vch(ch) - { - if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) - { - wdqdm_clr1(ch, ddr_csn); - continue; - } - err = wdqdm_ana1(ch, ddr_csn); - if (err) - { - err_flg |= (1U << (ddr_csn * 4 + ch)); - } - ddrphy_regif_idle(); - } -#else /* DDR_FAST_INIT */ -#endif /* DDR_FAST_INIT */ - } -err_exit: -#ifndef DDR_FAST_INIT - err |= err_flg; -#endif /* DDR_FAST_INIT */ - return err; -} - -static uint32_t wdqdm_man(void) -{ - uint32_t err, retry_cnt; - uint32_t ch, ddr_csn, mr14_bkup[4][4]; - uint32_t dataL; - const uint32_t retry_max = 0x10; - - dataL = RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2 + 19; - if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > dataL) - { - dataL = (mmio_read_32(DBSC_DBTR(11)) & 0xFF); - } - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, dataL); - - if ((Prr_Product == PRR_PRODUCT_G2N) || (Prr_Product == PRR_PRODUCT_G2H)) - { - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); - } - else - { - ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); - } - ddr_setval_ach(_reg_PI_TRFC_F0, (mmio_read_32(DBSC_DBTR(13)) & 0x1FF)); - ddr_setval_ach(_reg_PI_TRFC_F1, (mmio_read_32(DBSC_DBTR(13)) & 0x1FF)); - - retry_cnt = 0; - err = 0; - do - { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01); - if (Prr_Product == PRR_PRODUCT_G2N) - { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x0C); - } - else - { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C); - } - dsb_sev(); - err = wdqdm_man1(); - foreach_vch(ch) - { - for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) - { - mr14_bkup[ch][ddr_csn] = ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]); - dsb_sev(); - } - } - - if (Prr_Product == PRR_PRODUCT_G2N) - { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x04); - } - else - { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04); - } - pvtcode_update(); - err = wdqdm_man1(); - foreach_vch(ch) - { - for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) - { - mr14_bkup[ch][ddr_csn] = (mr14_bkup[ch][ddr_csn] + ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn])) / 2; - ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn], mr14_bkup[ch][ddr_csn]); - } - } - - ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x00); - if (Prr_Product == PRR_PRODUCT_G2N) - { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x00); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1, 0x00); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, 0x00); - } - else - { - ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 0x00); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 0x00); - } - ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 0x00); - - pvtcode_update2(); - err = wdqdm_man1(); - ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); - } while (err && (++retry_cnt < retry_max)); - - if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut <= PRR_PRODUCT_10)) - { - wdqdm_cp(0, 1); - } - - return (retry_cnt >= retry_max); -} - -/******************************************************************************* - * RDQ TRAINING - ******************************************************************************/ -#ifndef DDR_FAST_INIT -static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) -{ - int32_t i, k; - uint32_t cs, slice; - uint32_t dataL; - - /*********************************************************************** - * clr of training results buffer - ***********************************************************************/ - cs = ddr_csn % 2; - dataL = Boardcnf->dqdm_dly_r; - for (slice = 0; slice < SLICE_CNT; slice++) - { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) - { - continue; - } - for (i = 0; i <= 8; i++) - { - if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) - { - rdqdm_dly[ch][cs][slice][i] = - rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = - rdqdm_dly[ch][CS_CNT - 1 - cs][slice + SLICE_CNT][i]; - } - else - { - rdqdm_dly[ch][cs][slice][i] = dataL; - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; - } - rdqdm_le[ch][cs][slice][i] = 0; - rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; - rdqdm_te[ch][cs][slice][i] = 0; - rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0; - rdqdm_nw[ch][cs][slice][i] = 0; - rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0; - } - rdqdm_st[ch][cs][slice] = 0; - rdqdm_win[ch][cs][slice] = 0; - } -} - -static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) -{ - int32_t i, k; - uint32_t cs, slice; - uint32_t dataL; - uint32_t err; - int8_t _adj; - int16_t adj; - uint32_t dq; - int32_t min_win; - int32_t win; - uint32_t rdq_status_obs_select; - - /*********************************************************************** - * analysis of training results - ***********************************************************************/ - err = 0; - for (slice = 0; slice < SLICE_CNT; slice++) - { - k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; - if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) - { - continue; - } - cs = ddr_csn % 2; - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - ddrphy_regif_idle(); - - ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); - ddrphy_regif_idle(); - - for (i = 0; i <= 8; i++) - { - dq = slice * 8 + i; - if (i == 8) - { - _adj = Boardcnf->ch[ch].dm_adj_r[slice]; - } - else - { - _adj = Boardcnf->ch[ch].dq_adj_r[dq]; - } - adj = _f_scale_adj(_adj); - - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL); - rdqdm_dly[ch][cs][slice][i] = dataL; - - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL); - rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; - } - min_win = INT_LEAST32_MAX; - for (i = 0; i <= 8; i++) - { - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); - rdqdm_st[ch][cs][slice] = dataL; - rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL; - /* k : rise/fall */ - for (k = 0; k < 2; k++) - { - if (i == 8) - { - rdq_status_obs_select = 16 + 8 * k; - } - else - { - rdq_status_obs_select = i + 8 * k; - } - ddr_setval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, rdq_status_obs_select); - - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = dataL; - - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); - rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = dataL; - - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); - rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = dataL; - - win = (int32_t)rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; - if (i != 8) - { - if (min_win > win) - { - min_win = win; - } - } - } - } - rdqdm_win[ch][cs][slice] = min_win; - if (min_win <= 0) - { - err = 2; - } - } - return(err); -} -#endif /* DDR_FAST_INIT */ - -static uint32_t rdqdm_man1(void) -{ - uint32_t ch; - uint32_t ddr_csn; -#ifdef DDR_FAST_INIT - uint32_t slice; - uint32_t i, adj, dataL; -#endif /* DDR_FAST_INIT */ - uint32_t err; - - /*********************************************************************** - * manual execution of training - ***********************************************************************/ - err = 0; - - for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) - { - /* KICK RDQLVL */ - err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ); - if (err) - { - goto err_exit; - } -#ifndef DDR_FAST_INIT - foreach_vch(ch) - { - if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) - { - rdqdm_clr1(ch, ddr_csn); - ddrphy_regif_idle(); - continue; - } - err = rdqdm_ana1(ch, ddr_csn); - ddrphy_regif_idle(); - if (err) - { - goto err_exit; - } - } -#else /* DDR_FAST_INIT */ - foreach_vch(ch) - { - if (ch_have_this_cs[ddr_csn] & (1U << ch)) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - if (ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS) != 0x0D00FFFF) - { - err = (1U << ch) | (0x10U << slice); - goto err_exit; - } - } - } - if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut <= PRR_PRODUCT_10)) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - for (i = 0; i <= 8; i++) - { - if (i == 8) - { - adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]); - } - else - { - adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]); - } - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL); - rdqdm_dly[ch][ddr_csn][slice][i] = dataL; - rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL; - - dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; - ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL); - rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL; - rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL; - } - } - } - } - ddrphy_regif_idle(); - -#endif /* DDR_FAST_INIT */ - } - -err_exit: - return err; -} - -static uint32_t rdqdm_man(void) -{ - uint32_t err, retry_cnt; - const uint32_t retry_max = 0x01; - - ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, - 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQ_TSEL_ENABLE)); - ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, - 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQS_TSEL_ENABLE)); - ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, - 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQ_TSEL_SELECT)); - ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, - 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQS_TSEL_SELECT)); - - retry_cnt = 0; - do - { - err = rdqdm_man1(); - ddrphy_regif_idle(); - } while (err && (++retry_cnt < retry_max)); - ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, - ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQ_TSEL_ENABLE)); - ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, - ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQS_TSEL_ENABLE)); - ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, - ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQ_TSEL_SELECT)); - ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, - ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQS_TSEL_SELECT)); - - return (retry_cnt >= retry_max); -} - -/******************************************************************************* - * rx offset calibration - ******************************************************************************/ -static int32_t _find_change(uint64_t val, uint32_t dir) -{ - int32_t i; - uint32_t startval; - uint32_t curval; - const int32_t VAL_END = 0x3f; - - if (dir == 0) - { - startval = (val & 0x01); - for (i = 1; i <= VAL_END; i++) - { - curval = (val >> i) & 0x01; - if (curval != startval) - { - return(i); - } - } - return(VAL_END); - } - else - { - startval = (val >> dir) & 0x01; - for (i = dir - 1; i >= 0; i--) - { - curval = (val >> i) & 0x01; - if (curval != startval) - { - return(i); - } - } - return 0; - } -} - -static uint32_t _rx_offset_cal_updn(uint32_t code) -{ - const uint32_t CODE_MAX = 0x40; - uint32_t tmp; - - if (code == 0) - { - tmp = (1U << 6) | (CODE_MAX - 1); - } - else - { - tmp = (code << 6) | (CODE_MAX - code); - } - return tmp; -} - -static uint32_t rx_offset_cal(void) -{ - uint32_t index; - uint32_t code; - const uint32_t CODE_MAX = 0x40; - const uint32_t CODE_STEP = 2; - uint32_t ch, slice; - uint32_t tmp; - uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; - uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM]; - uint64_t tmpval; - int32_t lsb, msb; - - ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) - { - val[ch][slice][index] = 0; - } - } - } - - for (code = 0; code < (CODE_MAX / CODE_STEP); code++) - { - tmp = _rx_offset_cal_updn(code * CODE_STEP); - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) - { - ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); - } - dsb_sev(); - ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); - - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - tmp = tmp_ach_as[ch][slice]; - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) - { - if (tmp & (1U << index)) - { - val[ch][slice][index] |= (1ULL << code); - } - else - { - val[ch][slice][index] &= ~(1ULL << code); - } - } - } - } - } - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) - { - tmpval = val[ch][slice][index]; - lsb = _find_change(tmpval, 0); - msb = _find_change(tmpval, (CODE_MAX / CODE_STEP) - 1); - tmp = (lsb + msb) >> 1; - - tmp = _rx_offset_cal_updn(tmp * CODE_STEP); - ddr_setval_s(ch, slice, _reg_PHY_RX_CAL_X[index], tmp); - } - } - } - ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); - - return 0; -} - -static uint32_t rx_offset_cal_hw(void) -{ - uint32_t ch, slice; - uint32_t retry; - uint32_t complete; - uint32_t tmp; - uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; - - ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00); - ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); - ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f); - - retry = 0; - while (retry < 4096) - { - if ((retry & 0xff) == 0) - { - ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); - } - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - tmp_ach_as[ch][slice] = ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); - } - } - complete = 1; - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice++) - { - tmp = tmp_ach_as[ch][slice]; - tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); - if ((Prr_Product == PRR_PRODUCT_G2N) || (Prr_Product == PRR_PRODUCT_G2H)) - { - if (tmp != 0x3E) - { - complete = 0; - } - } - else - { - if (tmp != 0x40) - { - complete = 0; - } - } - } - } - if (complete) - { - break; - } - retry++; - } - - return (complete == 0); -} - -/******************************************************************************* - * adjust rddqs latency - ******************************************************************************/ -static void adjust_rddqs_latency(void) -{ - uint32_t ch, slice; - uint32_t dly; - uint32_t maxlatx2; - uint32_t tmp; - uint32_t rdlat_adjx2[SLICE_CNT]; - - foreach_vch(ch) - { - maxlatx2 = 0; - for (slice = 0; slice < SLICE_CNT; slice++) - { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, 0x00); - - dly = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_GATE_SLAVE_DELAY); - tmp = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_LATENCY_ADJUST); - /* note gate_slave_delay[9] is always 0 */ - tmp = (tmp << 1) + (dly >> 8); - rdlat_adjx2[slice] = tmp; - if (maxlatx2 < tmp) - { - maxlatx2 = tmp; - } - } - maxlatx2 = ((maxlatx2 + 1) >> 1) << 1; - for (slice = 0; slice < SLICE_CNT; slice++) - { - tmp = maxlatx2 - rdlat_adjx2[slice]; - tmp = (tmp >> 1); - if (tmp) - { - ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE, - ddr_getval_s(ch, slice, _reg_PHY_RPTR_UPDATE) + 1); - } - } - } -} - -/******************************************************************************* - * adjust wpath latency - ******************************************************************************/ -static void adjust_wpath_latency(void) -{ - uint32_t ch, cs, slice; - uint32_t dly; - uint32_t wpath_add; - const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180; - - foreach_vch(ch) - { - for (slice = 0; slice < SLICE_CNT; slice += 1) - { - for (cs = 0; cs < CS_CNT; cs++) - { - ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); - ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); - dly = ddr_getval_s(ch, slice, _reg_PHY_CLK_WRDQS_SLAVE_DELAY); - if (dly <= _par_EARLY_THRESHOLD_VAL) - { - continue; - } - wpath_add = ddr_getval_s(ch, slice, _reg_PHY_WRITE_PATH_LAT_ADD); - ddr_setval_s(ch, slice, _reg_PHY_WRITE_PATH_LAT_ADD, wpath_add - 1); - } - } - } -} - -/******************************************************************************* - * DDR Initialize entry - ******************************************************************************/ -int32_t InitDram(void) -{ - uint32_t ch, cs; - uint32_t dataL; - uint32_t bus_mbps, bus_mbpsdiv; - uint32_t tmp_tccd; - uint32_t failcount; - - /*********************************************************************** - * Thermal sensor setting - ***********************************************************************/ - dataL = mmio_read_32(CPG_MSTPSR5); - if (dataL & (1 << 22)) - { - /* case THS/TSC Standby */ - dataL &= ~(1 << 22); - cpg_write_32(CPG_SMSTPCR5, dataL); - while ((1 << 22) & mmio_read_32(CPG_MSTPSR5)) /* wait bit = 0 */ - ; - } - - /* THCTR Bit6: PONM = 0 , Bit0: THSST = 0 */ - dataL = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; - mmio_write_32(THS1_THCTR, dataL); - - /*********************************************************************** - * Judge product and cut - ***********************************************************************/ - Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; - Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; - - if (Prr_Product == PRR_PRODUCT_G2H) - { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0]; - } - else if (Prr_Product == PRR_PRODUCT_G2M) - { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; - } - else if (Prr_Product == PRR_PRODUCT_G2N) - { - pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; - } - else - { - FATAL_MSG("BL2: DDR:Unknown Product\n"); - return 0xff; - } - - if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut < PRR_PRODUCT_30)) - { - /* non */ - } - else - { - mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); - } - - /*********************************************************************** - * Judge board type - ***********************************************************************/ - _cnf_BOARDTYPE = boardcnf_get_brd_type(); - if (_cnf_BOARDTYPE >= BOARDNUM) - { - FATAL_MSG("BL2: DDR:Unknown Board\n"); - return 0xff; - } - Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE]; - -/* RZG_DRAM_SPLIT_2CH (2U) */ -#if RZG_DRAM_SPLIT == 2 - /*********************************************************************** - * RZ/G2H: Swap ch2 and ch1 for 2ch-split - ***********************************************************************/ - if ((Prr_Product == PRR_PRODUCT_G2H) && (Boardcnf->phyvalid == 0x05)) - { - mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); - ddr_phyvalid = 0x03; - } - else - { - ddr_phyvalid = Boardcnf->phyvalid; - } -#else//RZG_DRAM_SPLIT_2CH - ddr_phyvalid = Boardcnf->phyvalid; -#endif//RZG_DRAM_SPLIT_2CH - - max_density = 0; - - for (cs = 0; cs < CS_CNT; cs++) - { - ch_have_this_cs[cs] = 0; - } - foreach_ech(ch) - { - for (cs = 0; cs < CS_CNT; cs++) - { - ddr_density[ch][cs] = 0xff; - } - } - - foreach_vch(ch) - { - for (cs = 0; cs < CS_CNT; cs++) - { - dataL = Boardcnf->ch[ch].ddr_density[cs]; - ddr_density[ch][cs] = dataL; - - if (dataL == 0xff) - { - continue; - } - if (dataL > max_density) - { - max_density = dataL; - } - ch_have_this_cs[cs] |= (1U << ch); - } - } - - /*********************************************************************** - * Judge board clock frequency (in MHz) - ***********************************************************************/ - boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv); - if ((brd_clk / brd_clkdiv) > 25) - { - brd_clkdiva = 1; - } - else - { - brd_clkdiva = 0; - } - /*********************************************************************** - * Judge ddr operating frequency clock(in Mbps) - ***********************************************************************/ - boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv); - - ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); - - ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); - - /*********************************************************************** - * Adjust tccd - ***********************************************************************/ - dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; - bus_mbps = 0; - bus_mbpsdiv = 0; - switch (dataL) - { - case 0: - bus_mbps = brd_clk * 0x60 * 2; - bus_mbpsdiv = brd_clkdiv * 1; - break; - case 1: - bus_mbps = brd_clk * 0x50 * 2; - bus_mbpsdiv = brd_clkdiv * 1; - break; - case 2: - bus_mbps = brd_clk * 0x40 * 2; - bus_mbpsdiv = brd_clkdiv * 1; - break; - case 3: - bus_mbps = brd_clk * 0x60 * 2; - bus_mbpsdiv = brd_clkdiv * 2; - break; - default: - bus_mbps = brd_clk * 0x60 * 2; - bus_mbpsdiv = brd_clkdiv * 2; - break; - } - tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv); - if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) - { - tmp_tccd = tmp_tccd + 1; - } - if (tmp_tccd < 8) - { - ddr_tccd = 8; - } - else - { - ddr_tccd = tmp_tccd; - } - NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RZG_DDR_VERSION); - - MSG_LF("Start\n"); - - /*********************************************************************** - * PLL Setting - ***********************************************************************/ - pll3_control(1); - - /*********************************************************************** - * initialize DDR - ***********************************************************************/ - dataL = init_ddr(); - if (dataL == ddr_phyvalid) - { - failcount = 0; - } - else - { - failcount = 1; - } - foreach_vch(ch) - { - mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); - } - if ((Prr_Product == PRR_PRODUCT_G2M) && (Prr_Cut < PRR_PRODUCT_30)) - { - /* non */ - } - else - { - mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); - } - - if (failcount == 0) - { - return INITDRAM_OK; - } - else - { - return INITDRAM_NG; - } -} - -void pvtcode_update(void) -{ - uint32_t ch; - uint32_t dataL; - uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; - int32_t pvtp_tmp, pvtn_tmp; - - foreach_vch(ch) - { - pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6; - pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0; - - if (8912 * pvtp_init > 44230) - { - pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000; - } - else - { - pvtp_tmp = -((-(5000 + 8912 * pvtp_init - 44230)) / 10000); - } - pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000; - - pvtn[ch] = pvtn_tmp + pvtn_init; - pvtp[ch] = pvtp_tmp + pvtp_init; - - if (pvtn[ch] > 63) - { - pvtn[ch] = 63; - pvtp[ch] = (pvtp_tmp) * (63 - 6 * pvtn_tmp - pvtn_init) / (pvtn_tmp) + 6 * pvtp_tmp + pvtp_init; - } - dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), dataL | 0x00020000); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), dataL); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), dataL); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), dataL); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), dataL); - } -} - -void pvtcode_update2(void) -{ - uint32_t ch; - - foreach_vch(ch) - { - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), tcal.init_cal[ch] | 0x00020000); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), tcal.init_cal[ch]); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), tcal.init_cal[ch]); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), tcal.init_cal[ch]); - reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), tcal.init_cal[ch]); - } -} - -void ddr_padcal_tcompensate_getinit(uint32_t override) -{ - uint32_t ch; - uint32_t dataL; - uint32_t pvtp, pvtn; - - tcal.init_temp = 0; - for (ch = 0; ch < 4; ch++) - { - tcal.init_cal[ch] = 0; - tcal.tcomp_cal[ch] = 0; - } - - foreach_vch(ch) - { - tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); - tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); - } - - if (!override) - { - dataL = mmio_read_32(THS1_TEMP); - if (dataL < 2800) - { - tcal.init_temp = (143 * (int32_t)dataL - 359000) / 1000; - } - else - { - tcal.init_temp = (121 * (int32_t)dataL - 296300) / 1000; - } - foreach_vch(ch) - { - pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; - pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; - if ((int32_t)pvtp > ((tcal.init_temp * 29 - 3625) / 1000)) - { - pvtp = (int32_t)pvtp + ((3625 - tcal.init_temp * 29) / 1000); - } - else - { - pvtp = 0; - } - if ((int32_t)pvtn > ((tcal.init_temp * 54 - 6750) / 1000)) - { - pvtn = (int32_t)pvtn + ((6750 - tcal.init_temp * 54) / 1000); - } - else - { - pvtn = 0; - } - tcal.init_cal[ch] = 0x00015000 | (pvtn << 6) | (pvtp); - } - tcal.init_temp = 125; - } -} - -#ifndef ddr_qos_init_setting -/* for QoS init */ -uint8_t get_boardcnf_phyvalid(void) -{ - return ddr_phyvalid; -} -#endif /* ddr_qos_init_setting */ - -/******************************************************************************* - * END - ******************************************************************************/ diff --git a/ddr/lpddr4/boot_init_dram_config.c b/ddr/lpddr4/boot_init_dram_config.c deleted file mode 100644 index 8247ddd..0000000 --- a/ddr/lpddr4/boot_init_dram_config.c +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define GPIO_INDT5 0xE605500C -#define LPDDR4_2RANK (0x01 << 25) - -/******************************************************************************* - * NUMBER OF BOARD CONFIGRATION - * PLEASE DEFINE - ******************************************************************************/ -#define BOARDNUM 6 -/******************************************************************************* - * PLEASE SET board number or board judge function - ******************************************************************************/ -static uint32_t boardcnf_get_brd_type(void) -{ - uint32_t Prr_Product; - uint32_t judge = 0; - uint32_t reg; - uint32_t boardInfo; - - reg = mmio_read_32(PRR); - Prr_Product = reg & PRR_PRODUCT_MASK; - if (Prr_Product == PRR_PRODUCT_G2M) - { - if (RZG2M_CUT_11 == (reg & PRR_CUT_MASK)) - { - judge = 1; /* 2rank setting */ - } - else - { - boardInfo = mmio_read_32(GPIO_INDT5); - if (boardInfo & LPDDR4_2RANK) - { - judge = 1; /* 2rank setting */ - } - else - { - judge = 0; /* 1rank setting */ - } - } - } - else if (Prr_Product == PRR_PRODUCT_G2N) - { - judge = 3; - } - else if (Prr_Product == PRR_PRODUCT_G2H) - { - judge = 5; /* 1rank setting */ - } - return (judge); -} - -/******************************************************************************* - * Set DRAM ODT , VREFca , Derating condtition - ******************************************************************************/ -/* #define _def_LPDDR4_ODT 0x36 // MR11 */ -/* #define _def_LPDDR4_ODT 0x66 // MR11 */ -/* #define _def_LPDDR4_VREFCA 0x11 // MR12 */ -/* #define JS2_DERATE 1 // 1: Temperature Derating */ -#define DDR_FAST_INIT - -/******************************************************************************* - * BOARD CONFIGRATION - * PLEASE DEFINE boardcnfs[] - ******************************************************************************/ -struct _boardcnf_ch { - /*0x00... 4Gbit/die ( 2Gb/channel) - *0x01... 6Gbit/die ( 3Gb/channel) - *0x02... 8Gbit/die ( 4Gb/channel) or 4Gb/die (4Gb/channel) - *0x03...12Gbit/die ( 6Gb/channel) or 6Gb/die (6Gb/channel) - *0x04...16Gbit/die ( 8Gb/channel) or 8Gb/die (8Gb/channel) -//non: *0x05...24Gbit/die (12Gb/channel) -//non: *0x06...32Gbit/die (16Gb/channel) - *0xff...NO_MEMORY - */ - uint8_t ddr_density[CS_CNT]; - /* SoC caX([15][14]....[3][2][1][0]) -> MEM caY: */ - uint64_t ca_swap; - /* SoC dqsX([3][2][1][0]) -> MEM dqsY: */ - uint16_t dqs_swap; - /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ - uint32_t dq_swap[SLICE_CNT]; - /* SoC dm -> MEM dqY/dm: (8 means DM) */ - uint8_t dm_swap[SLICE_CNT]; - /* write traing pattern - * (DM,DQ7,....DQ0) x BL16 - */ - uint16_t wdqlvl_patt[16]; - /* delay adjustment is ps */ - int8_t cacs_adj[16]; - int8_t dm_adj_w[SLICE_CNT]; - int8_t dq_adj_w[SLICE_CNT*8]; - int8_t dm_adj_r[SLICE_CNT]; - int8_t dq_adj_r[SLICE_CNT*8]; -}; - -struct _boardcnf { - /* ch in use */ - uint8_t phyvalid; - /* use dbi mode */ - uint8_t dbi_en; - /* default CA/CS delay value */ - uint16_t cacs_dly; - /* default CA/CS delay adjust value in ps*/ - int16_t cacs_dly_adj; - /* default DQ/DM delay value for write*/ - uint16_t dqdm_dly_w; - /* default DQ/DM delay value for read*/ - uint16_t dqdm_dly_r; - struct _boardcnf_ch ch[DRAM_CH_CNT]; -}; -/* write traing pattern - * (DM,DQ7,....DQ0) x BL16 - */ -#define WDQLVL_PAT {\ - 0x00AA,\ - 0x0055,\ - 0x00AA,\ - 0x0155,\ - 0x01CC,\ - 0x0133,\ - 0x00CC,\ - 0x0033,\ - 0x00F0,\ - 0x010F,\ - 0x01F0,\ - 0x010F,\ - 0x00F0,\ - 0x00F0,\ - 0x000F,\ - 0x010F} - -static const struct _boardcnf boardcnfs[BOARDNUM] = { -/* - * boardcnf[0] Jiangsu HopeRun Software Co., Ltd. HiHope RZ/G2M board 16Gbit/1rank/2ch board with G2M/SOC - */ -{ - 0x03, /* phyvalid */ - 0x01, /* dbi_en */ - 0x02c0, /* cacs_dly */ - 0, /* cacs_dly_adj */ - 0x0300, /* dqdm_dly_w */ - 0x00a0, /* dqdm_dly_r */ - { -/*ch[0]*/ { -/*ddr_density[]*/ { 0x04, 0xff }, -/*ca_swap*/ 0x00345201, -/*dqs_swap*/ 0x3201, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - }, -/*ch[1]*/ { -/*ddr_density[]*/ { 0x04, 0xff }, -/*ca_swap*/ 0x00302154, -/*dqs_swap*/ 0x2310, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - } - } -}, -/* - * boardcnf[1] Jiangsu HopeRun Software Co., Ltd. HiHope RZ/G2M board 8Gbit/2rank/2ch board with G2M/SOC - */ -{ - 0x03, /* phyvalid */ - 0x01, /* dbi_en */ - 0x02c0, /* cacs_dly */ - 0, /* cacs_dly_adj */ - 0x0300, /* dqdm_dly_w */ - 0x00a0, /* dqdm_dly_r */ - { -/*ch[0]*/ { -/*ddr_density[]*/ { 0x02, 0x02 }, -/*ca_swap*/ 0x00345201, -/*dqs_swap*/ 0x3201, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - }, -/*ch[1]*/ { -/*ddr_density[]*/ { 0x02, 0x02 }, -/*ca_swap*/ 0x00302154, -/*dqs_swap*/ 0x2310, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - } - } -}, -/* - * boardcnf[2] Jiangsu HopeRun Software Co., Ltd. HiHope RZ/G2N board 8Gbit/2rank/1ch board with G2N/SOC - */ -{ - 0x01, /* phyvalid */ - 0x01, /* dbi_en */ - 0x0300, /* cacs_dly */ - 0, /* cacs_dly_adj */ - 0x0300, /* dqdm_dly_w */ - 0x00a0, /* dqdm_dly_r */ - { -/*ch[0]*/ { -/*ddr_density[]*/ { 0x02, 0x02 }, -/*ca_swap*/ 0x00345201, -/*dqs_swap*/ 0x3201, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - } - } -}, -/* - * boardcnf[3] Jiangsu HopeRun Software Co., Ltd. HiHope RZ/G2N board 16Gbit/2rank/1ch board with G2N/SOC - */ -{ - 0x01, /* phyvalid */ - 0x01, /* dbi_en */ - 0x0300, /* cacs_dly */ - 0, /* cacs_dly_adj */ - 0x0300, /* dqdm_dly_w */ - 0x00a0, /* dqdm_dly_r */ - { -/*ch[0]*/ { -/*ddr_density[]*/ { 0x04, 0x04 }, -/*ca_swap*/ 0x00345201, -/*dqs_swap*/ 0x3201, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - } - } -}, -/* - * boardcnf[4] Jiangsu HopeRun Software Co., Ltd. HiHope RZ/G2H board 8Gbit/2rank/2ch board with G2M/SOC - */ -{ - 0x05, /* phyvalid */ - 0x01, /* dbi_en */ - 0x0300, /* cacs_dly */ - 0, /* cacs_dly_adj */ - 0x0300, /* dqdm_dly_w */ - 0x00a0, /* dqdm_dly_r */ - { -/*ch[0]*/ { -/*ddr_density[]*/ { 0x02, 0x02 }, -/*ca_swap*/ 0x00345201, -/*dqs_swap*/ 0x3201, -/*dq_swap[]*/ { 0x01672543, 0x45367012, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - }, -/*ch[1]*/ { // for DRAM_SPLIT_2CH -/*ddr_density[]*/ { 0x02, 0x02 }, -/*ca_swap*/ 0x00302154, -/*dqs_swap*/ 0x2310, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - }, -/*ch[2]*/ { // for DRAM_SPLIT_NON -/*ddr_density[]*/ { 0x02, 0x02 }, -/*ca_swap*/ 0x00302154, -/*dqs_swap*/ 0x2310, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - }, -/*ch[3]*/ { // Dummy -/*ddr_density[]*/ { 0xff, 0xff }, -/*ca_swap*/ 0, -/*dqs_swap*/ 0, -/*dq_swap[]*/ { 0, 0, 0, 0 }, -/*dm_swap[]*/ { 0, 0, 0, 0 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - } - } -}, -/* - * boardcnf[5] Jiangsu HopeRun Software Co., Ltd. HiHope RZ/G2H board 16Gbit/1rank/2ch board with G2H/SOC - */ -{ - 0x05, /* phyvalid */ - 0x01, /* dbi_en */ - 0x0300, /* cacs_dly */ - 0, /* cacs_dly_adj */ - 0x0300, /* dqdm_dly_w */ - 0x00a0, /* dqdm_dly_r */ - { -/*ch[0]*/ { -/*ddr_density[]*/ { 0x04, 0xff }, -/*ca_swap*/ 0x00345201, -/*dqs_swap*/ 0x3201, -/*dq_swap[]*/ { 0x01672543, 0x45367012, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - }, -/*ch[1]*/ { // for DRAM_SPLIT_2CH -/*ddr_density[]*/ { 0x04, 0xff }, -/*ca_swap*/ 0x00302154, -/*dqs_swap*/ 0x2310, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - }, -/*ch[2]*/ { // for DRAM_SPLIT_NON -/*ddr_density[]*/ { 0x04, 0xff }, -/*ca_swap*/ 0x00302154, -/*dqs_swap*/ 0x2310, -/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, -/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - }, -/*ch[3]*/ { // Dummy -/*ddr_density[]*/ { 0xff, 0xff }, -/*ca_swap*/ 0, -/*dqs_swap*/ 0, -/*dq_swap[]*/ { 0, 0, 0, 0 }, -/*dm_swap[]*/ { 0, 0, 0, 0 }, -/*wdqlvl_patt[]*/ WDQLVL_PAT, -/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0 }, -/*dm_adj_w*/ { 0, 0, 0, 0 }, -/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 }, -/*dm_adj_r*/ { 0, 0, 0, 0 }, -/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0 } - } - } -} -}; - -/******************************************************************************* - * EXTAL CLOCK DEFINITION - * PLEASE DEFINE HOW TO JUDGE BOARD CLK - ******************************************************************************/ -/* - * RENESAS SALVATOR/KRIEK BOARD EXAMPLE - * judge by md14/md13 - * - * 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0) - * 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1) - * 25.00MHz CLK,DIV= 75,3 (md14,md13==1,0) - * 33.33MHz CLK,DIV=100,3 (md14,md13==1,1) - */ -void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) -{ - uint32_t md; - - md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3; - switch (md) - { - case 0x0: - *clk = 50; - *div = 3; - break; - case 0x1: - *clk = 60; - *div = 3; - break; - case 0x2: - *clk = 75; - *div = 3; - break; - case 0x3: - *clk = 100; - *div = 3; - break; - } - (void)brd; -} - -/******************************************************************************* - * DDR MBPS TARGET - * PLEASE DEFINE HOW TO JUDGE DDR BPS - ******************************************************************************/ -/* - * DDRxxxx (judge_ by md19,17) : 0 - * DDR3200 (md19,17==0,0) : 3200 - * DDR2800 (md19,17==0,1) : 2800 - * DDR2400 (md19,17==1,0) : 2400 - * DDR1600 (md19,17==1,1) : 1600 - */ -void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) -{ - uint32_t md; - - md = (mmio_read_32(RST_MODEMR) >> 17) & 0x05; - md = (md | (md >> 1)) & 0x03; - switch (md) - { - case 0x0: - *mbps = 3200; - *div = 1; - break; - case 0x1: - *mbps = 2800; - *div = 1; - break; - case 0x2: - *mbps = 2400; - *div = 1; - break; - case 0x3: - *mbps = 1600; - *div = 1; - break; - } - (void)brd; -} - -/******************************************************************************* - * REFRESH TARGET DEFINITION - * PLEASE DEFINE _def_REFPERIOD (in ns) - ******************************************************************************/ -/* WARN: do not modify in this IPL version */ -/* #define _def_REFPERIOD 1890 */ - -/******************************************************************************* - * PREDEFINED TERM CODE by chip id - ******************************************************************************/ -#define M3_SAMPLE_TT_A84 0xB866CC10, 0x3B250421 -#define M3_SAMPLE_TT_A85 0xB866CC10, 0x3AA50421 -#define M3_SAMPLE_TT_A86 0xB866CC10, 0x3AA48421 -#define M3_SAMPLE_FF_B45 0xB866CC10, 0x3AB00C21 -#define M3_SAMPLE_FF_B49 0xB866CC10, 0x39B10C21 -#define M3_SAMPLE_FF_B56 0xB866CC10, 0x3AAF8C21 -#define M3_SAMPLE_SS_E24 0xB866CC10, 0x3BA39421 -#define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421 -#define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421 -static const uint32_t TermcodeBySample[20][3] = { - { M3_SAMPLE_TT_A84, 0x000158D5 }, - { M3_SAMPLE_TT_A85, 0x00015955 }, - { M3_SAMPLE_TT_A86, 0x00015955 }, - { M3_SAMPLE_FF_B45, 0x00015690 }, - { M3_SAMPLE_FF_B49, 0x00015753 }, - { M3_SAMPLE_FF_B56, 0x00015793 }, - { M3_SAMPLE_SS_E24, 0x00015996 }, - { M3_SAMPLE_SS_E28, 0x000159D7 }, - { M3_SAMPLE_SS_E32, 0x00015997 }, - { 0xFFFFFFFF, 0xFFFFFFFF, 0x0001554F } -}; diff --git a/ddr/lpddr4/boot_init_dram_regdef.h b/ddr/lpddr4/boot_init_dram_regdef.h deleted file mode 100644 index f05869a..0000000 --- a/ddr/lpddr4/boot_init_dram_regdef.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define RZG2_DDR_VERSION "rev.0.40" -#define DRAM_CH_CNT 0x04 -#define SLICE_CNT 0x04 -#define CS_CNT 0x02 -/* order : CS0A, CS0B, CS1A, CS1B */ -#define CSAB_CNT (CS_CNT * 2) -/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */ -#define CHAB_CNT (DRAM_CH_CNT * 2) - -/* for pll setting */ -#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) -#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) - -/* for ddr deisity setting */ -#define DBMEMCONF_REG(d3, row, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) -#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29 - 3 - 10 - 2), 3, 10, 2)) -#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) - -/* refresh mode */ -#define DBSC_REFINTS 0x0 /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */ - -/* system registers */ -#define CPG_BASE (0xE6150000U) -#define CPG_FRQCRB (CPG_BASE + 0x0004U) - -#define CPG_PLLECR (CPG_BASE + 0x00D0U) -#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) /* R 32 Module stop status register 5 */ -#define CPG_SRCR4 (CPG_BASE + 0x00BCU) -#define CPG_PLL3CR (CPG_BASE + 0x00DCU) -#define CPG_ZB3CKCR (CPG_BASE + 0x0380U) -#define CPG_FRQCRD (CPG_BASE + 0x00E4U) -#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) /* R/W 32 System module stop control register 5 */ -#define CPG_CPGWPR (CPG_BASE + 0x0900U) -#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) - -#define CPG_FRQCRB_KICK_BIT (1U<<31) -#define CPG_PLLECR_PLL3E_BIT (1U<<3) -#define CPG_PLLECR_PLL3ST_BIT (1U<<11) -#define CPG_ZB3CKCR_ZB3ST_BIT (1U<<11) - -#define RST_BASE (0xE6160000U) -#define RST_MODEMR (RST_BASE + 0x0060U) - -/* chip_id and calibration code */ -#define LIFEC_CHIPID(x) (0xE6110040U+0x04U*(x)) - -/* Product Register */ -#define PRR (0xFFF00044U) -#define PRR_PRODUCT_MASK (0x00007F00U) -#define PRR_CUT_MASK (0x000000FFU) - -#define PRR_PRODUCT_G2H (0x00004F00U) /* RZ/G2H */ -#define PRR_PRODUCT_G2M (0x00005200U) /* RZ/G2M */ -#define PRR_PRODUCT_G2N (0x00005500U) /* RZ/G2N */ -#define PRR_PRODUCT_10 (0x00U) /* Ver.1.0 */ -#define PRR_PRODUCT_11 (0x01U) /* Ver.1.1 */ -#define PRR_PRODUCT_20 (0x10U) /* Ver.2.0 */ -#define PRR_PRODUCT_30 (0x20U) /* Ver.3.0 */ - -#define RZG2M_CUT_11 (0x10) /* RZ/G2M Ver.1.1/1,2 */ - -/* DBSC registers */ -#define DBSC_DBSYSCONF1 0xE6790004U -#define DBSC_DBPHYCONF0 0xE6790010U -#define DBSC_DBKIND 0xE6790020U - -#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U+0x10U*ch+0x04U*cs) -#define DBSC_DBMEMCONF_0_0 0xE6790030U -#define DBSC_DBMEMCONF_0_1 0xE6790034U -#define DBSC_DBMEMCONF_0_2 0xE6790038U -#define DBSC_DBMEMCONF_0_3 0xE679003CU -#define DBSC_DBMEMCONF_1_2 0xE6790048U -#define DBSC_DBMEMCONF_1_3 0xE679004CU -#define DBSC_DBMEMCONF_1_0 0xE6790040U -#define DBSC_DBMEMCONF_1_1 0xE6790044U -#define DBSC_DBMEMCONF_2_0 0xE6790050U -#define DBSC_DBMEMCONF_2_1 0xE6790054U -#define DBSC_DBMEMCONF_2_2 0xE6790058U -#define DBSC_DBMEMCONF_2_3 0xE679005CU -#define DBSC_DBMEMCONF_3_0 0xE6790060U -#define DBSC_DBMEMCONF_3_1 0xE6790064U -#define DBSC_DBMEMCONF_3_2 0xE6790068U -#define DBSC_DBMEMCONF_3_3 0xE679006CU - -#define DBSC_DBSYSCNT0 0xE6790100U - -#define DBSC_DBACEN 0xE6790200U -#define DBSC_DBRFEN 0xE6790204U -#define DBSC_DBCMD 0xE6790208U -#define DBSC_DBWAIT 0xE6790210U -#define DBSC_DBSYSCTRL0 0xE6790280U - -#define DBSC_DBTR(x) (0xE6790300U+0x04U*(x)) -#define DBSC_DBTR0 0xE6790300U -#define DBSC_DBTR1 0xE6790304U -#define DBSC_DBTR3 0xE679030CU -#define DBSC_DBTR4 0xE6790310U -#define DBSC_DBTR5 0xE6790314U -#define DBSC_DBTR6 0xE6790318U -#define DBSC_DBTR7 0xE679031CU -#define DBSC_DBTR8 0xE6790320U -#define DBSC_DBTR9 0xE6790324U -#define DBSC_DBTR10 0xE6790328U -#define DBSC_DBTR11 0xE679032CU -#define DBSC_DBTR12 0xE6790330U -#define DBSC_DBTR13 0xE6790334U -#define DBSC_DBTR14 0xE6790338U -#define DBSC_DBTR15 0xE679033CU -#define DBSC_DBTR16 0xE6790340U -#define DBSC_DBTR17 0xE6790344U -#define DBSC_DBTR18 0xE6790348U -#define DBSC_DBTR19 0xE679034CU -#define DBSC_DBTR20 0xE6790350U -#define DBSC_DBTR21 0xE6790354U -#define DBSC_DBTR22 0xE6790358U -#define DBSC_DBTR23 0xE679035CU -#define DBSC_DBTR24 0xE6790360U -#define DBSC_DBTR25 0xE6790364U -#define DBSC_DBTR26 0xE6790368U - -#define DBSC_DBBL 0xE6790400U -#define DBSC_DBRFCNF1 0xE6790414U -#define DBSC_DBRFCNF2 0xE6790418U -#define DBSC_DBTSPCNF 0xE6790420U -#define DBSC_DBCALCNF 0xE6790424U -#define DBSC_DBRNK(x) (0xE6790430U+0x04U*(x)) -#define DBSC_DBRNK2 0xE6790438U -#define DBSC_DBRNK3 0xE679043CU -#define DBSC_DBRNK4 0xE6790440U -#define DBSC_DBRNK5 0xE6790444U -#define DBSC_DBODT(x) (0xE6790460U+0x04U*(x)) - -#define DBSC_DBADJ0 0xE6790500U -#define DBSC_DBDBICNT 0xE6790518U -#define DBSC_DBDFIPMSTRCNF 0xE6790520U -#define DBSC_DBDFICUPDCNF 0xE679052CU - -#define DBSC_DBDFISTAT(ch) (0xE6790600U+0x40U*(ch)) -#define DBSC_DBDFISTAT_0 0xE6790600U -#define DBSC_DBDFISTAT_1 0xE6790640U -#define DBSC_DBDFISTAT_2 0xE6790680U -#define DBSC_DBDFISTAT_3 0xE67906C0U - -#define DBSC_DBDFICNT(ch) (0xE6790604U+0x40U*(ch)) -#define DBSC_DBDFICNT_0 0xE6790604U -#define DBSC_DBDFICNT_1 0xE6790644U -#define DBSC_DBDFICNT_2 0xE6790684U -#define DBSC_DBDFICNT_3 0xE67906C4U - -#define DBSC_DBPDCNT0(ch) (0xE6790610U+0x40U*(ch)) -#define DBSC_DBPDCNT0_0 0xE6790610U -#define DBSC_DBPDCNT0_1 0xE6790650U -#define DBSC_DBPDCNT0_2 0xE6790690U -#define DBSC_DBPDCNT0_3 0xE67906D0U - -#define DBSC_DBPDCNT1(ch) (0xE6790614U+0x40U*(ch)) -#define DBSC_DBPDCNT1_0 0xE6790614U -#define DBSC_DBPDCNT1_1 0xE6790654U -#define DBSC_DBPDCNT1_2 0xE6790694U -#define DBSC_DBPDCNT1_3 0xE67906D4U - -#define DBSC_DBPDCNT2(ch) (0xE6790618U+0x40U*(ch)) -#define DBSC_DBPDCNT2_0 0xE6790618U -#define DBSC_DBPDCNT2_1 0xE6790658U -#define DBSC_DBPDCNT2_2 0xE6790698U -#define DBSC_DBPDCNT2_3 0xE67906D8U - -#define DBSC_DBPDCNT3(ch) (0xE679061CU+0x40U*(ch)) -#define DBSC_DBPDCNT3_0 0xE679061CU -#define DBSC_DBPDCNT3_1 0xE679065CU -#define DBSC_DBPDCNT3_2 0xE679069CU -#define DBSC_DBPDCNT3_3 0xE67906DCU - -#define DBSC_DBPDLK(ch) (0xE6790620U+0x40U*(ch)) -#define DBSC_DBPDLK_0 0xE6790620U -#define DBSC_DBPDLK_1 0xE6790660U -#define DBSC_DBPDLK_2 0xE67906a0U -#define DBSC_DBPDLK_3 0xE67906e0U - -#define DBSC_DBPDRGA(ch) (0xE6790624U+0x40U*(ch)) -#define DBSC_DBPDRGD(ch) (0xE6790628U+0x40U*(ch)) -#define DBSC_DBPDRGA_0 0xE6790624U -#define DBSC_DBPDRGD_0 0xE6790628U -#define DBSC_DBPDRGA_1 0xE6790664U -#define DBSC_DBPDRGD_1 0xE6790668U -#define DBSC_DBPDRGA_2 0xE67906A4U -#define DBSC_DBPDRGD_2 0xE67906A8U -#define DBSC_DBPDRGA_3 0xE67906E4U -#define DBSC_DBPDRGD_3 0xE67906E8U - -#define DBSC_DBPDSTAT(ch) (0xE6790630U+0x40U*(ch)) -#define DBSC_DBPDSTAT_0 0xE6790630U -#define DBSC_DBPDSTAT_1 0xE6790670U -#define DBSC_DBPDSTAT_2 0xE67906B0U -#define DBSC_DBPDSTAT_3 0xE67906F0U - -#define DBSC_DBBUS0CNF0 0xE6790800U -#define DBSC_DBBUS0CNF1 0xE6790804U - -#define DBSC_DBCAM0CNF1 0xE6790904U -#define DBSC_DBCAM0CNF2 0xE6790908U -#define DBSC_DBCAM0CNF3 0xE679090CU -#define DBSC_DBBSWAP 0xE67909F0U -#define DBSC_DBBCAMDIS 0xE67909FCU -#define DBSC_DBSCHCNT0 0xE6791000U -#define DBSC_DBSCHCNT1 0xE6791004U -#define DBSC_DBSCHSZ0 0xE6791010U -#define DBSC_DBSCHRW0 0xE6791020U -#define DBSC_DBSCHRW1 0xE6791024U - -#define DBSC_DBSCHQOS_0(x) (0xE6791030U+0x10U*(x)) -#define DBSC_DBSCHQOS_1(x) (0xE6791034U+0x10U*(x)) -#define DBSC_DBSCHQOS_2(x) (0xE6791038U+0x10U*(x)) -#define DBSC_DBSCHQOS_3(x) (0xE679103CU+0x10U*(x)) - -#define DBSC_DBSCTR0 0xE6791700U -#define DBSC_DBSCTR1 0xE6791708U -#define DBSC_DBSCHRW2 0xE679170CU - -#define DBSC_SCFCTST01(x) (0xE6791700U+0x08U*(x)) -#define DBSC_SCFCTST0 0xE6791700U -#define DBSC_SCFCTST1 0xE6791708U -#define DBSC_SCFCTST2 0xE679170CU - -#define DBSC_DBMRRDR(chab) (0xE6791800U+0x04U*(chab)) -#define DBSC_DBMRRDR_0 0xE6791800U -#define DBSC_DBMRRDR_1 0xE6791804U -#define DBSC_DBMRRDR_2 0xE6791808U -#define DBSC_DBMRRDR_3 0xE679180CU -#define DBSC_DBMRRDR_4 0xE6791810U -#define DBSC_DBMRRDR_5 0xE6791814U -#define DBSC_DBMRRDR_6 0xE6791818U -#define DBSC_DBMRRDR_7 0xE679181CU - -#define DBSC_DBMEMSWAPCONF0 0xE6792000U - -#define DBSC_DBMONCONF4 0xE6793010U - -#define DBSC_PLL_LOCK(ch) (0xE6794054U+0x100U*(ch)) -#define DBSC_PLL_LOCK_0 0xE6794054U -#define DBSC_PLL_LOCK_1 0xE6794154U -#define DBSC_PLL_LOCK_2 0xE6794254U -#define DBSC_PLL_LOCK_3 0xE6794354U - -/* STAT registers */ -#define MSTAT_SL_INIT 0xE67E8000U -#define MSTAT_REF_ARS 0xE67E8004U -#define MSTATQ_STATQC 0xE67E8008U -#define MSTATQ_WTENABLE 0xE67E8030U -#define MSTATQ_WTREFRESH 0xE67E8034U -#define MSTATQ_WTSETTING0 0xE67E8038U -#define MSTATQ_WTSETTING1 0xE67E803CU - -#define QOS_BASE1 (0xE67F0000U) -#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U) -#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U) -#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U) -#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U) -#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U) -#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U) -#define QOSCTRL_EC (QOS_BASE1 + 0x003CU) -#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U) -#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U) -#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U) -#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U) -#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U) - -/* other module */ -#define THS1_THCTR 0xE6198020U -#define THS1_TEMP 0xE6198028U - -#define DBSC_BASE (0xE6790000U) -#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U) -#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U) -#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U) -#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU) -#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U) -#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U) -#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U) -#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU) -#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U) -#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U) -#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U) -#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU) -#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U) -#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U) -#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U) -#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU) -#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U) -#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U) -#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U) -#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU) -#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U) -#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U) -#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U) -#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU) -#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U) -#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U) -#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U) -#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU) diff --git a/ddr/lpddr4/ddr.mk b/ddr/lpddr4/ddr.mk deleted file mode 100644 index 86fbd88..0000000 --- a/ddr/lpddr4/ddr.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright (c) 2015-2018, Renesas Electronics Corporation -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# - Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# - Neither the name of Renesas nor the names of its contributors may be -# used to endorse or promote products derived from this software without -# specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - - -SRC_FILE += ddr/lpddr4/boot_init_dram.c -SRC_FILE += ddr/dram_sub_func.c diff --git a/ddr/lpddr4/ddr_regdef.h b/ddr/lpddr4/ddr_regdef.h deleted file mode 100644 index b129a4f..0000000 --- a/ddr/lpddr4/ddr_regdef.h +++ /dev/null @@ -1,5886 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define _reg_PHY_DQ_DM_SWIZZLE0 0x00000000U -#define _reg_PHY_DQ_DM_SWIZZLE1 0x00000001U -#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY 0x00000002U -#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY 0x00000003U -#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE 0x00000004U -#define _reg_PHY_CLK_BYPASS_OVERRIDE 0x00000005U -#define _reg_PHY_SW_WRDQ0_SHIFT 0x00000006U -#define _reg_PHY_SW_WRDQ1_SHIFT 0x00000007U -#define _reg_PHY_SW_WRDQ2_SHIFT 0x00000008U -#define _reg_PHY_SW_WRDQ3_SHIFT 0x00000009U -#define _reg_PHY_SW_WRDQ4_SHIFT 0x0000000aU -#define _reg_PHY_SW_WRDQ5_SHIFT 0x0000000bU -#define _reg_PHY_SW_WRDQ6_SHIFT 0x0000000cU -#define _reg_PHY_SW_WRDQ7_SHIFT 0x0000000dU -#define _reg_PHY_SW_WRDM_SHIFT 0x0000000eU -#define _reg_PHY_SW_WRDQS_SHIFT 0x0000000fU -#define _reg_PHY_DQ_TSEL_ENABLE 0x00000010U -#define _reg_PHY_DQ_TSEL_SELECT 0x00000011U -#define _reg_PHY_DQS_TSEL_ENABLE 0x00000012U -#define _reg_PHY_DQS_TSEL_SELECT 0x00000013U -#define _reg_PHY_TWO_CYC_PREAMBLE 0x00000014U -#define _reg_PHY_DBI_MODE 0x00000015U -#define _reg_PHY_PER_RANK_CS_MAP 0x00000016U -#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN 0x00000017U -#define _reg_PHY_PER_CS_TRAINING_INDEX 0x00000018U -#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY 0x00000019U -#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY 0x0000001aU -#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY 0x0000001bU -#define _reg_PHY_LP4_BOOT_RPTR_UPDATE 0x0000001cU -#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY 0x0000001dU -#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST 0x0000001eU -#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE 0x0000001fU -#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY 0x00000020U -#define _reg_PHY_LPBK_CONTROL 0x00000021U -#define _reg_PHY_LPBK_DFX_TIMEOUT_EN 0x00000022U -#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL 0x00000023U -#define _reg_PHY_AUTO_TIMING_MARGIN_OBS 0x00000024U -#define _reg_PHY_SLICE_PWR_RDC_DISABLE 0x00000025U -#define _reg_PHY_PRBS_PATTERN_START 0x00000026U -#define _reg_PHY_PRBS_PATTERN_MASK 0x00000027U -#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY 0x00000028U -#define _reg_PHY_GATE_ERROR_DELAY_SELECT 0x00000029U -#define _reg_SC_PHY_SNAP_OBS_REGS 0x0000002aU -#define _reg_PHY_LPDDR 0x0000002bU -#define _reg_PHY_LPDDR_TYPE 0x0000002cU -#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY 0x0000002dU -#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY 0x0000002eU -#define _reg_ON_FLY_GATE_ADJUST_EN 0x0000002fU -#define _reg_PHY_GATE_TRACKING_OBS 0x00000030U -#define _reg_PHY_DFI40_POLARITY 0x00000031U -#define _reg_PHY_LP4_PST_AMBLE 0x00000032U -#define _reg_PHY_RDLVL_PATT8 0x00000033U -#define _reg_PHY_RDLVL_PATT9 0x00000034U -#define _reg_PHY_RDLVL_PATT10 0x00000035U -#define _reg_PHY_RDLVL_PATT11 0x00000036U -#define _reg_PHY_LP4_RDLVL_PATT8 0x00000037U -#define _reg_PHY_LP4_RDLVL_PATT9 0x00000038U -#define _reg_PHY_LP4_RDLVL_PATT10 0x00000039U -#define _reg_PHY_LP4_RDLVL_PATT11 0x0000003aU -#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE 0x0000003bU -#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE 0x0000003cU -#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT 0x0000003dU -#define _reg_PHY_RDDQ_ENC_OBS_SELECT 0x0000003eU -#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT 0x0000003fU -#define _reg_PHY_WR_ENC_OBS_SELECT 0x00000040U -#define _reg_PHY_WR_SHIFT_OBS_SELECT 0x00000041U -#define _reg_PHY_FIFO_PTR_OBS_SELECT 0x00000042U -#define _reg_PHY_LVL_DEBUG_MODE 0x00000043U -#define _reg_SC_PHY_LVL_DEBUG_CONT 0x00000044U -#define _reg_PHY_WRLVL_CAPTURE_CNT 0x00000045U -#define _reg_PHY_WRLVL_UPDT_WAIT_CNT 0x00000046U -#define _reg_PHY_WRLVL_DQ_MASK 0x00000047U -#define _reg_PHY_GTLVL_CAPTURE_CNT 0x00000048U -#define _reg_PHY_GTLVL_UPDT_WAIT_CNT 0x00000049U -#define _reg_PHY_RDLVL_CAPTURE_CNT 0x0000004aU -#define _reg_PHY_RDLVL_UPDT_WAIT_CNT 0x0000004bU -#define _reg_PHY_RDLVL_OP_MODE 0x0000004cU -#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x0000004dU -#define _reg_PHY_RDLVL_DATA_MASK 0x0000004eU -#define _reg_PHY_RDLVL_DATA_SWIZZLE 0x0000004fU -#define _reg_PHY_WDQLVL_BURST_CNT 0x00000050U -#define _reg_PHY_WDQLVL_PATT 0x00000051U -#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET 0x00000052U -#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT 0x00000053U -#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT 0x00000054U -#define _reg_PHY_WDQLVL_QTR_DLY_STEP 0x00000055U -#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000056U -#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000057U -#define _reg_PHY_WDQLVL_DATADM_MASK 0x00000058U -#define _reg_PHY_USER_PATT0 0x00000059U -#define _reg_PHY_USER_PATT1 0x0000005aU -#define _reg_PHY_USER_PATT2 0x0000005bU -#define _reg_PHY_USER_PATT3 0x0000005cU -#define _reg_PHY_USER_PATT4 0x0000005dU -#define _reg_PHY_DQ_SWIZZLING 0x0000005eU -#define _reg_PHY_CALVL_VREF_DRIVING_SLICE 0x0000005fU -#define _reg_SC_PHY_MANUAL_CLEAR 0x00000060U -#define _reg_PHY_FIFO_PTR_OBS 0x00000061U -#define _reg_PHY_LPBK_RESULT_OBS 0x00000062U -#define _reg_PHY_LPBK_ERROR_COUNT_OBS 0x00000063U -#define _reg_PHY_MASTER_DLY_LOCK_OBS 0x00000064U -#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS 0x00000065U -#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS 0x00000066U -#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS 0x00000067U -#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS 0x00000068U -#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS 0x00000069U -#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS 0x0000006aU -#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS 0x0000006bU -#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS 0x0000006cU -#define _reg_PHY_WR_SHIFT_OBS 0x0000006dU -#define _reg_PHY_WRLVL_HARD0_DELAY_OBS 0x0000006eU -#define _reg_PHY_WRLVL_HARD1_DELAY_OBS 0x0000006fU -#define _reg_PHY_WRLVL_STATUS_OBS 0x00000070U -#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS 0x00000071U -#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS 0x00000072U -#define _reg_PHY_WRLVL_ERROR_OBS 0x00000073U -#define _reg_PHY_GTLVL_HARD0_DELAY_OBS 0x00000074U -#define _reg_PHY_GTLVL_HARD1_DELAY_OBS 0x00000075U -#define _reg_PHY_GTLVL_STATUS_OBS 0x00000076U -#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x00000077U -#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00000078U -#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS 0x00000079U -#define _reg_PHY_RDLVL_STATUS_OBS 0x0000007aU -#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS 0x0000007bU -#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS 0x0000007cU -#define _reg_PHY_WDQLVL_STATUS_OBS 0x0000007dU -#define _reg_PHY_DDL_MODE 0x0000007eU -#define _reg_PHY_DDL_TEST_OBS 0x0000007fU -#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS 0x00000080U -#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD 0x00000081U -#define _reg_PHY_LP4_WDQS_OE_EXTEND 0x00000082U -#define _reg_SC_PHY_RX_CAL_START 0x00000083U -#define _reg_PHY_RX_CAL_OVERRIDE 0x00000084U -#define _reg_PHY_RX_CAL_SAMPLE_WAIT 0x00000085U -#define _reg_PHY_RX_CAL_DQ0 0x00000086U -#define _reg_PHY_RX_CAL_DQ1 0x00000087U -#define _reg_PHY_RX_CAL_DQ2 0x00000088U -#define _reg_PHY_RX_CAL_DQ3 0x00000089U -#define _reg_PHY_RX_CAL_DQ4 0x0000008aU -#define _reg_PHY_RX_CAL_DQ5 0x0000008bU -#define _reg_PHY_RX_CAL_DQ6 0x0000008cU -#define _reg_PHY_RX_CAL_DQ7 0x0000008dU -#define _reg_PHY_RX_CAL_DM 0x0000008eU -#define _reg_PHY_RX_CAL_DQS 0x0000008fU -#define _reg_PHY_RX_CAL_FDBK 0x00000090U -#define _reg_PHY_RX_CAL_OBS 0x00000091U -#define _reg_PHY_RX_CAL_LOCK_OBS 0x00000092U -#define _reg_PHY_RX_CAL_DISABLE 0x00000093U -#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY 0x00000094U -#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY 0x00000095U -#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY 0x00000096U -#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY 0x00000097U -#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY 0x00000098U -#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY 0x00000099U -#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY 0x0000009aU -#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY 0x0000009bU -#define _reg_PHY_CLK_WRDM_SLAVE_DELAY 0x0000009cU -#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY 0x0000009dU -#define _reg_PHY_WRLVL_THRESHOLD_ADJUST 0x0000009eU -#define _reg_PHY_RDDQ0_SLAVE_DELAY 0x0000009fU -#define _reg_PHY_RDDQ1_SLAVE_DELAY 0x000000a0U -#define _reg_PHY_RDDQ2_SLAVE_DELAY 0x000000a1U -#define _reg_PHY_RDDQ3_SLAVE_DELAY 0x000000a2U -#define _reg_PHY_RDDQ4_SLAVE_DELAY 0x000000a3U -#define _reg_PHY_RDDQ5_SLAVE_DELAY 0x000000a4U -#define _reg_PHY_RDDQ6_SLAVE_DELAY 0x000000a5U -#define _reg_PHY_RDDQ7_SLAVE_DELAY 0x000000a6U -#define _reg_PHY_RDDM_SLAVE_DELAY 0x000000a7U -#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY 0x000000a8U -#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY 0x000000a9U -#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY 0x000000aaU -#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY 0x000000abU -#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY 0x000000acU -#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY 0x000000adU -#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY 0x000000aeU -#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY 0x000000afU -#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY 0x000000b0U -#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY 0x000000b1U -#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY 0x000000b2U -#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY 0x000000b3U -#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY 0x000000b4U -#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY 0x000000b5U -#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY 0x000000b6U -#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY 0x000000b7U -#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 0x000000b8U -#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 0x000000b9U -#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY 0x000000baU -#define _reg_PHY_RDDQS_LATENCY_ADJUST 0x000000bbU -#define _reg_PHY_WRITE_PATH_LAT_ADD 0x000000bcU -#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD 0x000000bdU -#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD 0x000000beU -#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO 0x000000bfU -#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START 0x000000c0U -#define _reg_PHY_GTLVL_LAT_ADJ_START 0x000000c1U -#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START 0x000000c2U -#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START 0x000000c3U -#define _reg_PHY_FDBK_PWR_CTRL 0x000000c4U -#define _reg_PHY_DQ_OE_TIMING 0x000000c5U -#define _reg_PHY_DQ_TSEL_RD_TIMING 0x000000c6U -#define _reg_PHY_DQ_TSEL_WR_TIMING 0x000000c7U -#define _reg_PHY_DQS_OE_TIMING 0x000000c8U -#define _reg_PHY_DQS_TSEL_RD_TIMING 0x000000c9U -#define _reg_PHY_DQS_OE_RD_TIMING 0x000000caU -#define _reg_PHY_DQS_TSEL_WR_TIMING 0x000000cbU -#define _reg_PHY_PER_CS_TRAINING_EN 0x000000ccU -#define _reg_PHY_DQ_IE_TIMING 0x000000cdU -#define _reg_PHY_DQS_IE_TIMING 0x000000ceU -#define _reg_PHY_RDDATA_EN_IE_DLY 0x000000cfU -#define _reg_PHY_IE_MODE 0x000000d0U -#define _reg_PHY_RDDATA_EN_DLY 0x000000d1U -#define _reg_PHY_RDDATA_EN_TSEL_DLY 0x000000d2U -#define _reg_PHY_RDDATA_EN_OE_DLY 0x000000d3U -#define _reg_PHY_SW_MASTER_MODE 0x000000d4U -#define _reg_PHY_MASTER_DELAY_START 0x000000d5U -#define _reg_PHY_MASTER_DELAY_STEP 0x000000d6U -#define _reg_PHY_MASTER_DELAY_WAIT 0x000000d7U -#define _reg_PHY_MASTER_DELAY_HALF_MEASURE 0x000000d8U -#define _reg_PHY_RPTR_UPDATE 0x000000d9U -#define _reg_PHY_WRLVL_DLY_STEP 0x000000daU -#define _reg_PHY_WRLVL_RESP_WAIT_CNT 0x000000dbU -#define _reg_PHY_GTLVL_DLY_STEP 0x000000dcU -#define _reg_PHY_GTLVL_RESP_WAIT_CNT 0x000000ddU -#define _reg_PHY_GTLVL_BACK_STEP 0x000000deU -#define _reg_PHY_GTLVL_FINAL_STEP 0x000000dfU -#define _reg_PHY_WDQLVL_DLY_STEP 0x000000e0U -#define _reg_PHY_TOGGLE_PRE_SUPPORT 0x000000e1U -#define _reg_PHY_RDLVL_DLY_STEP 0x000000e2U -#define _reg_PHY_WRPATH_GATE_DISABLE 0x000000e3U -#define _reg_PHY_WRPATH_GATE_TIMING 0x000000e4U -#define _reg_PHY_ADR0_SW_WRADDR_SHIFT 0x000000e5U -#define _reg_PHY_ADR1_SW_WRADDR_SHIFT 0x000000e6U -#define _reg_PHY_ADR2_SW_WRADDR_SHIFT 0x000000e7U -#define _reg_PHY_ADR3_SW_WRADDR_SHIFT 0x000000e8U -#define _reg_PHY_ADR4_SW_WRADDR_SHIFT 0x000000e9U -#define _reg_PHY_ADR5_SW_WRADDR_SHIFT 0x000000eaU -#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY 0x000000ebU -#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE 0x000000ecU -#define _reg_SC_PHY_ADR_MANUAL_CLEAR 0x000000edU -#define _reg_PHY_ADR_LPBK_RESULT_OBS 0x000000eeU -#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS 0x000000efU -#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT 0x000000f0U -#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS 0x000000f1U -#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS 0x000000f2U -#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS 0x000000f3U -#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE 0x000000f4U -#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT 0x000000f5U -#define _reg_SC_PHY_ADR_SNAP_OBS_REGS 0x000000f6U -#define _reg_PHY_ADR_TSEL_ENABLE 0x000000f7U -#define _reg_PHY_ADR_LPBK_CONTROL 0x000000f8U -#define _reg_PHY_ADR_PRBS_PATTERN_START 0x000000f9U -#define _reg_PHY_ADR_PRBS_PATTERN_MASK 0x000000faU -#define _reg_PHY_ADR_PWR_RDC_DISABLE 0x000000fbU -#define _reg_PHY_ADR_TYPE 0x000000fcU -#define _reg_PHY_ADR_WRADDR_SHIFT_OBS 0x000000fdU -#define _reg_PHY_ADR_IE_MODE 0x000000feU -#define _reg_PHY_ADR_DDL_MODE 0x000000ffU -#define _reg_PHY_ADR_DDL_TEST_OBS 0x00000100U -#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS 0x00000101U -#define _reg_PHY_ADR_CALVL_START 0x00000102U -#define _reg_PHY_ADR_CALVL_COARSE_DLY 0x00000103U -#define _reg_PHY_ADR_CALVL_QTR 0x00000104U -#define _reg_PHY_ADR_CALVL_SWIZZLE0 0x00000105U -#define _reg_PHY_ADR_CALVL_SWIZZLE1 0x00000106U -#define _reg_PHY_ADR_CALVL_SWIZZLE0_0 0x00000107U -#define _reg_PHY_ADR_CALVL_SWIZZLE1_0 0x00000108U -#define _reg_PHY_ADR_CALVL_SWIZZLE0_1 0x00000109U -#define _reg_PHY_ADR_CALVL_SWIZZLE1_1 0x0000010aU -#define _reg_PHY_ADR_CALVL_DEVICE_MAP 0x0000010bU -#define _reg_PHY_ADR_CALVL_RANK_CTRL 0x0000010cU -#define _reg_PHY_ADR_CALVL_NUM_PATTERNS 0x0000010dU -#define _reg_PHY_ADR_CALVL_CAPTURE_CNT 0x0000010eU -#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT 0x0000010fU -#define _reg_PHY_ADR_CALVL_DEBUG_MODE 0x00000110U -#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT 0x00000111U -#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR 0x00000112U -#define _reg_PHY_ADR_CALVL_OBS_SELECT 0x00000113U -#define _reg_PHY_ADR_CALVL_OBS0 0x00000114U -#define _reg_PHY_ADR_CALVL_OBS1 0x00000115U -#define _reg_PHY_ADR_CALVL_RESULT 0x00000116U -#define _reg_PHY_ADR_CALVL_FG_0 0x00000117U -#define _reg_PHY_ADR_CALVL_BG_0 0x00000118U -#define _reg_PHY_ADR_CALVL_FG_1 0x00000119U -#define _reg_PHY_ADR_CALVL_BG_1 0x0000011aU -#define _reg_PHY_ADR_CALVL_FG_2 0x0000011bU -#define _reg_PHY_ADR_CALVL_BG_2 0x0000011cU -#define _reg_PHY_ADR_CALVL_FG_3 0x0000011dU -#define _reg_PHY_ADR_CALVL_BG_3 0x0000011eU -#define _reg_PHY_ADR_ADDR_SEL 0x0000011fU -#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY 0x00000120U -#define _reg_PHY_ADR_BIT_MASK 0x00000121U -#define _reg_PHY_ADR_SEG_MASK 0x00000122U -#define _reg_PHY_ADR_CALVL_TRAIN_MASK 0x00000123U -#define _reg_PHY_ADR_CSLVL_TRAIN_MASK 0x00000124U -#define _reg_PHY_ADR_SW_TXIO_CTRL 0x00000125U -#define _reg_PHY_ADR_TSEL_SELECT 0x00000126U -#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY 0x00000127U -#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY 0x00000128U -#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY 0x00000129U -#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY 0x0000012aU -#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY 0x0000012bU -#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY 0x0000012cU -#define _reg_PHY_ADR_SW_MASTER_MODE 0x0000012dU -#define _reg_PHY_ADR_MASTER_DELAY_START 0x0000012eU -#define _reg_PHY_ADR_MASTER_DELAY_STEP 0x0000012fU -#define _reg_PHY_ADR_MASTER_DELAY_WAIT 0x00000130U -#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE 0x00000131U -#define _reg_PHY_ADR_CALVL_DLY_STEP 0x00000132U -#define _reg_PHY_FREQ_SEL 0x00000133U -#define _reg_PHY_FREQ_SEL_FROM_REGIF 0x00000134U -#define _reg_PHY_FREQ_SEL_MULTICAST_EN 0x00000135U -#define _reg_PHY_FREQ_SEL_INDEX 0x00000136U -#define _reg_PHY_SW_GRP_SHIFT_0 0x00000137U -#define _reg_PHY_SW_GRP_SHIFT_1 0x00000138U -#define _reg_PHY_SW_GRP_SHIFT_2 0x00000139U -#define _reg_PHY_SW_GRP_SHIFT_3 0x0000013aU -#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY 0x0000013bU -#define _reg_PHY_SW_GRP_BYPASS_SHIFT 0x0000013cU -#define _reg_PHY_GRP_BYPASS_OVERRIDE 0x0000013dU -#define _reg_SC_PHY_MANUAL_UPDATE 0x0000013eU -#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE 0x0000013fU -#define _reg_PHY_LP4_BOOT_DISABLE 0x00000140U -#define _reg_PHY_CSLVL_ENABLE 0x00000141U -#define _reg_PHY_CSLVL_CS_MAP 0x00000142U -#define _reg_PHY_CSLVL_START 0x00000143U -#define _reg_PHY_CSLVL_QTR 0x00000144U -#define _reg_PHY_CSLVL_COARSE_CHK 0x00000145U -#define _reg_PHY_CSLVL_CAPTURE_CNT 0x00000146U -#define _reg_PHY_CSLVL_COARSE_DLY 0x00000147U -#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT 0x00000148U -#define _reg_PHY_CSLVL_DEBUG_MODE 0x00000149U -#define _reg_SC_PHY_CSLVL_DEBUG_CONT 0x0000014aU -#define _reg_SC_PHY_CSLVL_ERROR_CLR 0x0000014bU -#define _reg_PHY_CSLVL_OBS0 0x0000014cU -#define _reg_PHY_CSLVL_OBS1 0x0000014dU -#define _reg_PHY_CALVL_CS_MAP 0x0000014eU -#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT 0x0000014fU -#define _reg_PHY_GRP_SHIFT_OBS_SELECT 0x00000150U -#define _reg_PHY_GRP_SLV_DLY_ENC_OBS 0x00000151U -#define _reg_PHY_GRP_SHIFT_OBS 0x00000152U -#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE 0x00000153U -#define _reg_PHY_ADRCTL_SNAP_OBS_REGS 0x00000154U -#define _reg_PHY_DFI_PHYUPD_TYPE 0x00000155U -#define _reg_PHY_ADRCTL_LPDDR 0x00000156U -#define _reg_PHY_LP4_ACTIVE 0x00000157U -#define _reg_PHY_LPDDR3_CS 0x00000158U -#define _reg_PHY_CALVL_RESULT_MASK 0x00000159U -#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES 0x0000015aU -#define _reg_PHY_SW_TXIO_CTRL_0 0x0000015bU -#define _reg_PHY_SW_TXIO_CTRL_1 0x0000015cU -#define _reg_PHY_SW_TXIO_CTRL_2 0x0000015dU -#define _reg_PHY_SW_TXIO_CTRL_3 0x0000015eU -#define _reg_PHY_MEMCLK_SW_TXIO_CTRL 0x0000015fU -#define _reg_PHY_CA_SW_TXPWR_CTRL 0x00000160U -#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL 0x00000161U -#define _reg_PHY_USER_DEF_REG_AC_0 0x00000162U -#define _reg_PHY_USER_DEF_REG_AC_1 0x00000163U -#define _reg_PHY_USER_DEF_REG_AC_2 0x00000164U -#define _reg_PHY_USER_DEF_REG_AC_3 0x00000165U -#define _reg_PHY_UPDATE_CLK_CAL_VALUES 0x00000166U -#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE 0x00000167U -#define _reg_PHY_PLL_CTRL 0x00000168U -#define _reg_PHY_PLL_CTRL_TOP 0x00000169U -#define _reg_PHY_PLL_CTRL_CA 0x0000016aU -#define _reg_PHY_PLL_BYPASS 0x0000016bU -#define _reg_PHY_LOW_FREQ_SEL 0x0000016cU -#define _reg_PHY_PAD_VREF_CTRL_DQ_0 0x0000016dU -#define _reg_PHY_PAD_VREF_CTRL_DQ_1 0x0000016eU -#define _reg_PHY_PAD_VREF_CTRL_DQ_2 0x0000016fU -#define _reg_PHY_PAD_VREF_CTRL_DQ_3 0x00000170U -#define _reg_PHY_PAD_VREF_CTRL_AC 0x00000171U -#define _reg_PHY_CSLVL_DLY_STEP 0x00000172U -#define _reg_PHY_SET_DFI_INPUT_0 0x00000173U -#define _reg_PHY_SET_DFI_INPUT_1 0x00000174U -#define _reg_PHY_SET_DFI_INPUT_2 0x00000175U -#define _reg_PHY_SET_DFI_INPUT_3 0x00000176U -#define _reg_PHY_GRP_SLAVE_DELAY_0 0x00000177U -#define _reg_PHY_GRP_SLAVE_DELAY_1 0x00000178U -#define _reg_PHY_GRP_SLAVE_DELAY_2 0x00000179U -#define _reg_PHY_GRP_SLAVE_DELAY_3 0x0000017aU -#define _reg_PHY_CS_ACS_ALLOCATION_0 0x0000017bU -#define _reg_PHY_CS_ACS_ALLOCATION_1 0x0000017cU -#define _reg_PHY_CS_ACS_ALLOCATION_2 0x0000017dU -#define _reg_PHY_CS_ACS_ALLOCATION_3 0x0000017eU -#define _reg_PHY_LP4_BOOT_PLL_CTRL 0x0000017fU -#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA 0x00000180U -#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 0x00000181U -#define _reg_PHY_PLL_CTRL_OVERRIDE 0x00000182U -#define _reg_PHY_PLL_WAIT 0x00000183U -#define _reg_PHY_PLL_WAIT_TOP 0x00000184U -#define _reg_PHY_PLL_OBS_0 0x00000185U -#define _reg_PHY_PLL_OBS_1 0x00000186U -#define _reg_PHY_PLL_OBS_2 0x00000187U -#define _reg_PHY_PLL_OBS_3 0x00000188U -#define _reg_PHY_PLL_OBS_4 0x00000189U -#define _reg_PHY_PLL_TESTOUT_SEL 0x0000018aU -#define _reg_PHY_TCKSRE_WAIT 0x0000018bU -#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL 0x0000018cU -#define _reg_PHY_LP_WAKEUP 0x0000018dU -#define _reg_PHY_LS_IDLE_EN 0x0000018eU -#define _reg_PHY_LP_CTRLUPD_CNTR_CFG 0x0000018fU -#define _reg_PHY_TDFI_PHY_WRDELAY 0x00000190U -#define _reg_PHY_PAD_FDBK_DRIVE 0x00000191U -#define _reg_PHY_PAD_DATA_DRIVE 0x00000192U -#define _reg_PHY_PAD_DQS_DRIVE 0x00000193U -#define _reg_PHY_PAD_ADDR_DRIVE 0x00000194U -#define _reg_PHY_PAD_CLK_DRIVE 0x00000195U -#define _reg_PHY_PAD_FDBK_TERM 0x00000196U -#define _reg_PHY_PAD_DATA_TERM 0x00000197U -#define _reg_PHY_PAD_DQS_TERM 0x00000198U -#define _reg_PHY_PAD_ADDR_TERM 0x00000199U -#define _reg_PHY_PAD_CLK_TERM 0x0000019aU -#define _reg_PHY_PAD_CKE_DRIVE 0x0000019bU -#define _reg_PHY_PAD_CKE_TERM 0x0000019cU -#define _reg_PHY_PAD_RST_DRIVE 0x0000019dU -#define _reg_PHY_PAD_RST_TERM 0x0000019eU -#define _reg_PHY_PAD_CS_DRIVE 0x0000019fU -#define _reg_PHY_PAD_CS_TERM 0x000001a0U -#define _reg_PHY_PAD_ODT_DRIVE 0x000001a1U -#define _reg_PHY_PAD_ODT_TERM 0x000001a2U -#define _reg_PHY_ADRCTL_RX_CAL 0x000001a3U -#define _reg_PHY_ADRCTL_LP3_RX_CAL 0x000001a4U -#define _reg_PHY_TST_CLK_PAD_CTRL 0x000001a5U -#define _reg_PHY_TST_CLK_PAD_CTRL2 0x000001a6U -#define _reg_PHY_CAL_MODE_0 0x000001a7U -#define _reg_PHY_CAL_CLEAR_0 0x000001a8U -#define _reg_PHY_CAL_START_0 0x000001a9U -#define _reg_PHY_CAL_INTERVAL_COUNT_0 0x000001aaU -#define _reg_PHY_CAL_SAMPLE_WAIT_0 0x000001abU -#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0 0x000001acU -#define _reg_PHY_CAL_CLK_SELECT_0 0x000001adU -#define _reg_PHY_CAL_RESULT_OBS_0 0x000001aeU -#define _reg_PHY_CAL_RESULT2_OBS_0 0x000001afU -#define _reg_PHY_CAL_CPTR_CNT_0 0x000001b0U -#define _reg_PHY_CAL_SETTLING_PRD_0 0x000001b1U -#define _reg_PHY_CAL_PU_FINE_ADJ_0 0x000001b2U -#define _reg_PHY_CAL_PD_FINE_ADJ_0 0x000001b3U -#define _reg_PHY_CAL_RCV_FINE_ADJ_0 0x000001b4U -#define _reg_PHY_CAL_DBG_CFG_0 0x000001b5U -#define _reg_SC_PHY_PAD_DBG_CONT_0 0x000001b6U -#define _reg_PHY_CAL_RESULT3_OBS_0 0x000001b7U -#define _reg_PHY_ADRCTL_PVT_MAP_0 0x000001b8U -#define _reg_PHY_CAL_SLOPE_ADJ_0 0x000001b9U -#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0 0x000001baU -#define _reg_PHY_CAL_TWO_PASS_CFG_0 0x000001bbU -#define _reg_PHY_CAL_SW_CAL_CFG_0 0x000001bcU -#define _reg_PHY_CAL_RANGE_MIN_0 0x000001bdU -#define _reg_PHY_CAL_RANGE_MAX_0 0x000001beU -#define _reg_PHY_PAD_ATB_CTRL 0x000001bfU -#define _reg_PHY_ADRCTL_MANUAL_UPDATE 0x000001c0U -#define _reg_PHY_AC_LPBK_ERR_CLEAR 0x000001c1U -#define _reg_PHY_AC_LPBK_OBS_SELECT 0x000001c2U -#define _reg_PHY_AC_LPBK_ENABLE 0x000001c3U -#define _reg_PHY_AC_LPBK_CONTROL 0x000001c4U -#define _reg_PHY_AC_PRBS_PATTERN_START 0x000001c5U -#define _reg_PHY_AC_PRBS_PATTERN_MASK 0x000001c6U -#define _reg_PHY_AC_LPBK_RESULT_OBS 0x000001c7U -#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT 0x000001c8U -#define _reg_PHY_AC_CLK_LPBK_ENABLE 0x000001c9U -#define _reg_PHY_AC_CLK_LPBK_CONTROL 0x000001caU -#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS 0x000001cbU -#define _reg_PHY_AC_PWR_RDC_DISABLE 0x000001ccU -#define _reg_PHY_DATA_BYTE_ORDER_SEL 0x000001cdU -#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH 0x000001ceU -#define _reg_PHY_LPDDR4_CONNECT 0x000001cfU -#define _reg_PHY_CALVL_DEVICE_MAP 0x000001d0U -#define _reg_PHY_ADR_DISABLE 0x000001d1U -#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL 0x000001d2U -#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE 0x000001d3U -#define _reg_PHY_DDL_AC_ENABLE 0x000001d4U -#define _reg_PHY_DDL_AC_MODE 0x000001d5U -#define _reg_PHY_PAD_BACKGROUND_CAL 0x000001d6U -#define _reg_PHY_INIT_UPDATE_CONFIG 0x000001d7U -#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC 0x000001d8U -#define _reg_PHY_DLL_RST_EN 0x000001d9U -#define _reg_PHY_AC_INIT_COMPLETE_OBS 0x000001daU -#define _reg_PHY_DS_INIT_COMPLETE_OBS 0x000001dbU -#define _reg_PHY_UPDATE_MASK 0x000001dcU -#define _reg_PHY_PLL_SWITCH_CNT 0x000001ddU -#define _reg_PI_START 0x000001deU -#define _reg_PI_DRAM_CLASS 0x000001dfU -#define _reg_PI_VERSION 0x000001e0U -#define _reg_PI_NORMAL_LVL_SEQ 0x000001e1U -#define _reg_PI_INIT_LVL_EN 0x000001e2U -#define _reg_PI_NOTCARE_PHYUPD 0x000001e3U -#define _reg_PI_ONBUS_MBIST 0x000001e4U -#define _reg_PI_TCMD_GAP 0x000001e5U -#define _reg_PI_MASTER_ACK_DURATION_MIN 0x000001e6U -#define _reg_PI_DFI_VERSION 0x000001e7U -#define _reg_PI_TDFI_PHYMSTR_TYPE0 0x000001e8U -#define _reg_PI_TDFI_PHYMSTR_TYPE1 0x000001e9U -#define _reg_PI_TDFI_PHYMSTR_TYPE2 0x000001eaU -#define _reg_PI_TDFI_PHYMSTR_TYPE3 0x000001ebU -#define _reg_PI_DFI_PHYMSTR_TYPE 0x000001ecU -#define _reg_PI_DFI_PHYMSTR_CS_STATE_R 0x000001edU -#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R 0x000001eeU -#define _reg_PI_TDFI_PHYMSTR_MAX_F0 0x000001efU -#define _reg_PI_TDFI_PHYMSTR_RESP_F0 0x000001f0U -#define _reg_PI_TDFI_PHYMSTR_MAX_F1 0x000001f1U -#define _reg_PI_TDFI_PHYMSTR_RESP_F1 0x000001f2U -#define _reg_PI_TDFI_PHYMSTR_MAX_F2 0x000001f3U -#define _reg_PI_TDFI_PHYMSTR_RESP_F2 0x000001f4U -#define _reg_PI_TDFI_PHYUPD_RESP_F0 0x000001f5U -#define _reg_PI_TDFI_PHYUPD_TYPE0_F0 0x000001f6U -#define _reg_PI_TDFI_PHYUPD_TYPE1_F0 0x000001f7U -#define _reg_PI_TDFI_PHYUPD_TYPE2_F0 0x000001f8U -#define _reg_PI_TDFI_PHYUPD_TYPE3_F0 0x000001f9U -#define _reg_PI_TDFI_PHYUPD_RESP_F1 0x000001faU -#define _reg_PI_TDFI_PHYUPD_TYPE0_F1 0x000001fbU -#define _reg_PI_TDFI_PHYUPD_TYPE1_F1 0x000001fcU -#define _reg_PI_TDFI_PHYUPD_TYPE2_F1 0x000001fdU -#define _reg_PI_TDFI_PHYUPD_TYPE3_F1 0x000001feU -#define _reg_PI_TDFI_PHYUPD_RESP_F2 0x000001ffU -#define _reg_PI_TDFI_PHYUPD_TYPE0_F2 0x00000200U -#define _reg_PI_TDFI_PHYUPD_TYPE1_F2 0x00000201U -#define _reg_PI_TDFI_PHYUPD_TYPE2_F2 0x00000202U -#define _reg_PI_TDFI_PHYUPD_TYPE3_F2 0x00000203U -#define _reg_PI_CONTROL_ERROR_STATUS 0x00000204U -#define _reg_PI_EXIT_AFTER_INIT_CALVL 0x00000205U -#define _reg_PI_FREQ_MAP 0x00000206U -#define _reg_PI_INIT_WORK_FREQ 0x00000207U -#define _reg_PI_INIT_DFS_CALVL_ONLY 0x00000208U -#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY 0x00000209U -#define _reg_PI_POWER_ON_SEQ_END_ARRAY 0x0000020aU -#define _reg_PI_SEQ1_PAT 0x0000020bU -#define _reg_PI_SEQ1_PAT_MASK 0x0000020cU -#define _reg_PI_SEQ2_PAT 0x0000020dU -#define _reg_PI_SEQ2_PAT_MASK 0x0000020eU -#define _reg_PI_SEQ3_PAT 0x0000020fU -#define _reg_PI_SEQ3_PAT_MASK 0x00000210U -#define _reg_PI_SEQ4_PAT 0x00000211U -#define _reg_PI_SEQ4_PAT_MASK 0x00000212U -#define _reg_PI_SEQ5_PAT 0x00000213U -#define _reg_PI_SEQ5_PAT_MASK 0x00000214U -#define _reg_PI_SEQ6_PAT 0x00000215U -#define _reg_PI_SEQ6_PAT_MASK 0x00000216U -#define _reg_PI_SEQ7_PAT 0x00000217U -#define _reg_PI_SEQ7_PAT_MASK 0x00000218U -#define _reg_PI_SEQ8_PAT 0x00000219U -#define _reg_PI_SEQ8_PAT_MASK 0x0000021aU -#define _reg_PI_WDT_DISABLE 0x0000021bU -#define _reg_PI_SW_RST_N 0x0000021cU -#define _reg_RESERVED_R0 0x0000021dU -#define _reg_PI_CS_MAP 0x0000021eU -#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0 0x0000021fU -#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x00000220U -#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00000221U -#define _reg_PI_TMRR 0x00000222U -#define _reg_PI_WRLAT_F0 0x00000223U -#define _reg_PI_ADDITIVE_LAT_F0 0x00000224U -#define _reg_PI_CASLAT_LIN_F0 0x00000225U -#define _reg_PI_WRLAT_F1 0x00000226U -#define _reg_PI_ADDITIVE_LAT_F1 0x00000227U -#define _reg_PI_CASLAT_LIN_F1 0x00000228U -#define _reg_PI_WRLAT_F2 0x00000229U -#define _reg_PI_ADDITIVE_LAT_F2 0x0000022aU -#define _reg_PI_CASLAT_LIN_F2 0x0000022bU -#define _reg_PI_PREAMBLE_SUPPORT 0x0000022cU -#define _reg_PI_AREFRESH 0x0000022dU -#define _reg_PI_MCAREF_FORWARD_ONLY 0x0000022eU -#define _reg_PI_TRFC_F0 0x0000022fU -#define _reg_PI_TREF_F0 0x00000230U -#define _reg_PI_TRFC_F1 0x00000231U -#define _reg_PI_TREF_F1 0x00000232U -#define _reg_PI_TRFC_F2 0x00000233U -#define _reg_PI_TREF_F2 0x00000234U -#define _reg_RESERVED_H3VER2 0x00000235U -#define _reg_PI_TREF_INTERVAL 0x00000236U -#define _reg_PI_FREQ_CHANGE_REG_COPY 0x00000237U -#define _reg_PI_FREQ_SEL_FROM_REGIF 0x00000238U -#define _reg_PI_SWLVL_LOAD 0x00000239U -#define _reg_PI_SWLVL_OP_DONE 0x0000023aU -#define _reg_PI_SW_WRLVL_RESP_0 0x0000023bU -#define _reg_PI_SW_WRLVL_RESP_1 0x0000023cU -#define _reg_PI_SW_WRLVL_RESP_2 0x0000023dU -#define _reg_PI_SW_WRLVL_RESP_3 0x0000023eU -#define _reg_PI_SW_RDLVL_RESP_0 0x0000023fU -#define _reg_PI_SW_RDLVL_RESP_1 0x00000240U -#define _reg_PI_SW_RDLVL_RESP_2 0x00000241U -#define _reg_PI_SW_RDLVL_RESP_3 0x00000242U -#define _reg_PI_SW_CALVL_RESP_0 0x00000243U -#define _reg_PI_SW_LEVELING_MODE 0x00000244U -#define _reg_PI_SWLVL_START 0x00000245U -#define _reg_PI_SWLVL_EXIT 0x00000246U -#define _reg_PI_SWLVL_WR_SLICE_0 0x00000247U -#define _reg_PI_SWLVL_RD_SLICE_0 0x00000248U -#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0 0x00000249U -#define _reg_PI_SW_WDQLVL_RESP_0 0x0000024aU -#define _reg_PI_SWLVL_WR_SLICE_1 0x0000024bU -#define _reg_PI_SWLVL_RD_SLICE_1 0x0000024cU -#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1 0x0000024dU -#define _reg_PI_SW_WDQLVL_RESP_1 0x0000024eU -#define _reg_PI_SWLVL_WR_SLICE_2 0x0000024fU -#define _reg_PI_SWLVL_RD_SLICE_2 0x00000250U -#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2 0x00000251U -#define _reg_PI_SW_WDQLVL_RESP_2 0x00000252U -#define _reg_PI_SWLVL_WR_SLICE_3 0x00000253U -#define _reg_PI_SWLVL_RD_SLICE_3 0x00000254U -#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3 0x00000255U -#define _reg_PI_SW_WDQLVL_RESP_3 0x00000256U -#define _reg_PI_SW_WDQLVL_VREF 0x00000257U -#define _reg_PI_SWLVL_SM2_START 0x00000258U -#define _reg_PI_SWLVL_SM2_WR 0x00000259U -#define _reg_PI_SWLVL_SM2_RD 0x0000025aU -#define _reg_PI_SEQUENTIAL_LVL_REQ 0x0000025bU -#define _reg_PI_DFS_PERIOD_EN 0x0000025cU -#define _reg_PI_SRE_PERIOD_EN 0x0000025dU -#define _reg_PI_DFI40_POLARITY 0x0000025eU -#define _reg_PI_16BIT_DRAM_CONNECT 0x0000025fU -#define _reg_PI_TDFI_CTRL_DELAY_F0 0x00000260U -#define _reg_PI_TDFI_CTRL_DELAY_F1 0x00000261U -#define _reg_PI_TDFI_CTRL_DELAY_F2 0x00000262U -#define _reg_PI_WRLVL_REQ 0x00000263U -#define _reg_PI_WRLVL_CS 0x00000264U -#define _reg_PI_WLDQSEN 0x00000265U -#define _reg_PI_WLMRD 0x00000266U -#define _reg_PI_WRLVL_EN_F0 0x00000267U -#define _reg_PI_WRLVL_EN_F1 0x00000268U -#define _reg_PI_WRLVL_EN_F2 0x00000269U -#define _reg_PI_WRLVL_EN 0x0000026aU -#define _reg_PI_WRLVL_INTERVAL 0x0000026bU -#define _reg_PI_WRLVL_PERIODIC 0x0000026cU -#define _reg_PI_WRLVL_ON_SREF_EXIT 0x0000026dU -#define _reg_PI_WRLVL_DISABLE_DFS 0x0000026eU -#define _reg_PI_WRLVL_RESP_MASK 0x0000026fU -#define _reg_PI_WRLVL_ROTATE 0x00000270U -#define _reg_PI_WRLVL_CS_MAP 0x00000271U -#define _reg_PI_WRLVL_ERROR_STATUS 0x00000272U -#define _reg_PI_TDFI_WRLVL_EN 0x00000273U -#define _reg_PI_TDFI_WRLVL_WW_F0 0x00000274U -#define _reg_PI_TDFI_WRLVL_WW_F1 0x00000275U -#define _reg_PI_TDFI_WRLVL_WW_F2 0x00000276U -#define _reg_PI_TDFI_WRLVL_WW 0x00000277U -#define _reg_PI_TDFI_WRLVL_RESP 0x00000278U -#define _reg_PI_TDFI_WRLVL_MAX 0x00000279U -#define _reg_PI_WRLVL_STROBE_NUM 0x0000027aU -#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ 0x0000027bU -#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR 0x0000027cU -#define _reg_PI_TODTL_2CMD_F0 0x0000027dU -#define _reg_PI_ODT_EN_F0 0x0000027eU -#define _reg_PI_TODTL_2CMD_F1 0x0000027fU -#define _reg_PI_ODT_EN_F1 0x00000280U -#define _reg_PI_TODTL_2CMD_F2 0x00000281U -#define _reg_PI_ODT_EN_F2 0x00000282U -#define _reg_PI_TODTH_WR 0x00000283U -#define _reg_PI_TODTH_RD 0x00000284U -#define _reg_PI_ODT_RD_MAP_CS0 0x00000285U -#define _reg_PI_ODT_WR_MAP_CS0 0x00000286U -#define _reg_PI_ODT_RD_MAP_CS1 0x00000287U -#define _reg_PI_ODT_WR_MAP_CS1 0x00000288U -#define _reg_PI_ODT_RD_MAP_CS2 0x00000289U -#define _reg_PI_ODT_WR_MAP_CS2 0x0000028aU -#define _reg_PI_ODT_RD_MAP_CS3 0x0000028bU -#define _reg_PI_ODT_WR_MAP_CS3 0x0000028cU -#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD 0x0000028dU -#define _reg_PI_ODTLON_F0 0x0000028eU -#define _reg_PI_TODTON_MIN_F0 0x0000028fU -#define _reg_PI_ODTLON_F1 0x00000290U -#define _reg_PI_TODTON_MIN_F1 0x00000291U -#define _reg_PI_ODTLON_F2 0x00000292U -#define _reg_PI_TODTON_MIN_F2 0x00000293U -#define _reg_PI_WR_TO_ODTH_F0 0x00000294U -#define _reg_PI_WR_TO_ODTH_F1 0x00000295U -#define _reg_PI_WR_TO_ODTH_F2 0x00000296U -#define _reg_PI_RD_TO_ODTH_F0 0x00000297U -#define _reg_PI_RD_TO_ODTH_F1 0x00000298U -#define _reg_PI_RD_TO_ODTH_F2 0x00000299U -#define _reg_PI_ADDRESS_MIRRORING 0x0000029aU -#define _reg_PI_RDLVL_REQ 0x0000029bU -#define _reg_PI_RDLVL_GATE_REQ 0x0000029cU -#define _reg_PI_RDLVL_CS 0x0000029dU -#define _reg_PI_RDLVL_PAT_0 0x0000029eU -#define _reg_PI_RDLVL_PAT_1 0x0000029fU -#define _reg_PI_RDLVL_PAT_2 0x000002a0U -#define _reg_PI_RDLVL_PAT_3 0x000002a1U -#define _reg_PI_RDLVL_PAT_4 0x000002a2U -#define _reg_PI_RDLVL_PAT_5 0x000002a3U -#define _reg_PI_RDLVL_PAT_6 0x000002a4U -#define _reg_PI_RDLVL_PAT_7 0x000002a5U -#define _reg_PI_RDLVL_SEQ_EN 0x000002a6U -#define _reg_PI_RDLVL_GATE_SEQ_EN 0x000002a7U -#define _reg_PI_RDLVL_PERIODIC 0x000002a8U -#define _reg_PI_RDLVL_ON_SREF_EXIT 0x000002a9U -#define _reg_PI_RDLVL_DISABLE_DFS 0x000002aaU -#define _reg_PI_RDLVL_GATE_PERIODIC 0x000002abU -#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT 0x000002acU -#define _reg_PI_RDLVL_GATE_DISABLE_DFS 0x000002adU -#define _reg_RESERVED_R1 0x000002aeU -#define _reg_PI_RDLVL_ROTATE 0x000002afU -#define _reg_PI_RDLVL_GATE_ROTATE 0x000002b0U -#define _reg_PI_RDLVL_CS_MAP 0x000002b1U -#define _reg_PI_RDLVL_GATE_CS_MAP 0x000002b2U -#define _reg_PI_TDFI_RDLVL_RR 0x000002b3U -#define _reg_PI_TDFI_RDLVL_RESP 0x000002b4U -#define _reg_PI_RDLVL_RESP_MASK 0x000002b5U -#define _reg_PI_TDFI_RDLVL_EN 0x000002b6U -#define _reg_PI_RDLVL_EN_F0 0x000002b7U -#define _reg_PI_RDLVL_GATE_EN_F0 0x000002b8U -#define _reg_PI_RDLVL_EN_F1 0x000002b9U -#define _reg_PI_RDLVL_GATE_EN_F1 0x000002baU -#define _reg_PI_RDLVL_EN_F2 0x000002bbU -#define _reg_PI_RDLVL_GATE_EN_F2 0x000002bcU -#define _reg_PI_RDLVL_EN 0x000002bdU -#define _reg_PI_RDLVL_GATE_EN 0x000002beU -#define _reg_PI_TDFI_RDLVL_MAX 0x000002bfU -#define _reg_PI_RDLVL_ERROR_STATUS 0x000002c0U -#define _reg_PI_RDLVL_INTERVAL 0x000002c1U -#define _reg_PI_RDLVL_GATE_INTERVAL 0x000002c2U -#define _reg_PI_RDLVL_PATTERN_START 0x000002c3U -#define _reg_PI_RDLVL_PATTERN_NUM 0x000002c4U -#define _reg_PI_RDLVL_STROBE_NUM 0x000002c5U -#define _reg_PI_RDLVL_GATE_STROBE_NUM 0x000002c6U -#define _reg_PI_LPDDR4_RDLVL_PATTERN_8 0x000002c7U -#define _reg_PI_LPDDR4_RDLVL_PATTERN_9 0x000002c8U -#define _reg_PI_LPDDR4_RDLVL_PATTERN_10 0x000002c9U -#define _reg_PI_LPDDR4_RDLVL_PATTERN_11 0x000002caU -#define _reg_PI_RD_PREAMBLE_TRAINING_EN 0x000002cbU -#define _reg_PI_REG_DIMM_ENABLE 0x000002ccU -#define _reg_PI_RDLAT_ADJ_F0 0x000002cdU -#define _reg_PI_RDLAT_ADJ_F1 0x000002ceU -#define _reg_PI_RDLAT_ADJ_F2 0x000002cfU -#define _reg_PI_TDFI_RDDATA_EN 0x000002d0U -#define _reg_PI_WRLAT_ADJ_F0 0x000002d1U -#define _reg_PI_WRLAT_ADJ_F1 0x000002d2U -#define _reg_PI_WRLAT_ADJ_F2 0x000002d3U -#define _reg_PI_TDFI_PHY_WRLAT 0x000002d4U -#define _reg_PI_TDFI_WRCSLAT_F0 0x000002d5U -#define _reg_PI_TDFI_WRCSLAT_F1 0x000002d6U -#define _reg_PI_TDFI_WRCSLAT_F2 0x000002d7U -#define _reg_PI_TDFI_RDCSLAT_F0 0x000002d8U -#define _reg_PI_TDFI_RDCSLAT_F1 0x000002d9U -#define _reg_PI_TDFI_RDCSLAT_F2 0x000002daU -#define _reg_PI_TDFI_PHY_WRDATA_F0 0x000002dbU -#define _reg_PI_TDFI_PHY_WRDATA_F1 0x000002dcU -#define _reg_PI_TDFI_PHY_WRDATA_F2 0x000002ddU -#define _reg_PI_TDFI_PHY_WRDATA 0x000002deU -#define _reg_PI_CALVL_REQ 0x000002dfU -#define _reg_PI_CALVL_CS 0x000002e0U -#define _reg_RESERVED_R2 0x000002e1U -#define _reg_RESERVED_R3 0x000002e2U -#define _reg_PI_CALVL_SEQ_EN 0x000002e3U -#define _reg_PI_CALVL_PERIODIC 0x000002e4U -#define _reg_PI_CALVL_ON_SREF_EXIT 0x000002e5U -#define _reg_PI_CALVL_DISABLE_DFS 0x000002e6U -#define _reg_PI_CALVL_ROTATE 0x000002e7U -#define _reg_PI_CALVL_CS_MAP 0x000002e8U -#define _reg_PI_TDFI_CALVL_EN 0x000002e9U -#define _reg_PI_TDFI_CALVL_CC_F0 0x000002eaU -#define _reg_PI_TDFI_CALVL_CAPTURE_F0 0x000002ebU -#define _reg_PI_TDFI_CALVL_CC_F1 0x000002ecU -#define _reg_PI_TDFI_CALVL_CAPTURE_F1 0x000002edU -#define _reg_PI_TDFI_CALVL_CC_F2 0x000002eeU -#define _reg_PI_TDFI_CALVL_CAPTURE_F2 0x000002efU -#define _reg_PI_TDFI_CALVL_RESP 0x000002f0U -#define _reg_PI_TDFI_CALVL_MAX 0x000002f1U -#define _reg_PI_CALVL_RESP_MASK 0x000002f2U -#define _reg_PI_CALVL_EN_F0 0x000002f3U -#define _reg_PI_CALVL_EN_F1 0x000002f4U -#define _reg_PI_CALVL_EN_F2 0x000002f5U -#define _reg_PI_CALVL_EN 0x000002f6U -#define _reg_PI_CALVL_ERROR_STATUS 0x000002f7U -#define _reg_PI_CALVL_INTERVAL 0x000002f8U -#define _reg_PI_TCACKEL 0x000002f9U -#define _reg_PI_TCAMRD 0x000002faU -#define _reg_PI_TCACKEH 0x000002fbU -#define _reg_PI_TMRZ_F0 0x000002fcU -#define _reg_PI_TCAENT_F0 0x000002fdU -#define _reg_PI_TMRZ_F1 0x000002feU -#define _reg_PI_TCAENT_F1 0x000002ffU -#define _reg_PI_TMRZ_F2 0x00000300U -#define _reg_PI_TCAENT_F2 0x00000301U -#define _reg_PI_TCAEXT 0x00000302U -#define _reg_PI_CA_TRAIN_VREF_EN 0x00000303U -#define _reg_PI_TDFI_CACSCA_F0 0x00000304U -#define _reg_PI_TDFI_CASEL_F0 0x00000305U -#define _reg_PI_TVREF_SHORT_F0 0x00000306U -#define _reg_PI_TVREF_LONG_F0 0x00000307U -#define _reg_PI_TDFI_CACSCA_F1 0x00000308U -#define _reg_PI_TDFI_CASEL_F1 0x00000309U -#define _reg_PI_TVREF_SHORT_F1 0x0000030aU -#define _reg_PI_TVREF_LONG_F1 0x0000030bU -#define _reg_PI_TDFI_CACSCA_F2 0x0000030cU -#define _reg_PI_TDFI_CASEL_F2 0x0000030dU -#define _reg_PI_TVREF_SHORT_F2 0x0000030eU -#define _reg_PI_TVREF_LONG_F2 0x0000030fU -#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00000310U -#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x00000311U -#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1 0x00000312U -#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00000313U -#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2 0x00000314U -#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x00000315U -#define _reg_PI_CALVL_VREF_INITIAL_START_POINT 0x00000316U -#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT 0x00000317U -#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE 0x00000318U -#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE 0x00000319U -#define _reg_PI_CALVL_VREF_DELTA_F0 0x0000031aU -#define _reg_PI_CALVL_VREF_DELTA_F1 0x0000031bU -#define _reg_PI_CALVL_VREF_DELTA_F2 0x0000031cU -#define _reg_PI_CALVL_VREF_DELTA 0x0000031dU -#define _reg_PI_TDFI_INIT_START_MIN 0x0000031eU -#define _reg_PI_TDFI_INIT_COMPLETE_MIN 0x0000031fU -#define _reg_PI_TDFI_CALVL_STROBE_F0 0x00000320U -#define _reg_PI_TXP_F0 0x00000321U -#define _reg_PI_TMRWCKEL_F0 0x00000322U -#define _reg_PI_TCKELCK_F0 0x00000323U -#define _reg_PI_TDFI_CALVL_STROBE_F1 0x00000324U -#define _reg_PI_TXP_F1 0x00000325U -#define _reg_PI_TMRWCKEL_F1 0x00000326U -#define _reg_PI_TCKELCK_F1 0x00000327U -#define _reg_PI_TDFI_CALVL_STROBE_F2 0x00000328U -#define _reg_PI_TXP_F2 0x00000329U -#define _reg_PI_TMRWCKEL_F2 0x0000032aU -#define _reg_PI_TCKELCK_F2 0x0000032bU -#define _reg_PI_TCKCKEH 0x0000032cU -#define _reg_PI_CALVL_STROBE_NUM 0x0000032dU -#define _reg_PI_SW_CA_TRAIN_VREF 0x0000032eU -#define _reg_PI_TDFI_INIT_START_F0 0x0000032fU -#define _reg_PI_TDFI_INIT_COMPLETE_F0 0x00000330U -#define _reg_PI_TDFI_INIT_START_F1 0x00000331U -#define _reg_PI_TDFI_INIT_COMPLETE_F1 0x00000332U -#define _reg_PI_TDFI_INIT_START_F2 0x00000333U -#define _reg_PI_TDFI_INIT_COMPLETE_F2 0x00000334U -#define _reg_PI_CLKDISABLE_2_INIT_START 0x00000335U -#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE 0x00000336U -#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL 0x00000337U -#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE 0x00000338U -#define _reg_PI_TCKEHDQS_F0 0x00000339U -#define _reg_PI_TCKEHDQS_F1 0x0000033aU -#define _reg_PI_TCKEHDQS_F2 0x0000033bU -#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE 0x0000033cU -#define _reg_PI_WDQLVL_VREF_EN 0x0000033dU -#define _reg_PI_WDQLVL_BST_NUM 0x0000033eU -#define _reg_PI_TDFI_WDQLVL_WR_F0 0x0000033fU -#define _reg_PI_TDFI_WDQLVL_WR_F1 0x00000340U -#define _reg_PI_TDFI_WDQLVL_WR_F2 0x00000341U -#define _reg_PI_TDFI_WDQLVL_WR 0x00000342U -#define _reg_PI_TDFI_WDQLVL_RW 0x00000343U -#define _reg_PI_WDQLVL_RESP_MASK 0x00000344U -#define _reg_PI_WDQLVL_ROTATE 0x00000345U -#define _reg_PI_WDQLVL_CS_MAP 0x00000346U -#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x00000347U -#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x00000348U -#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x00000349U -#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x0000034aU -#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x0000034bU -#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x0000034cU -#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT 0x0000034dU -#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT 0x0000034eU -#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE 0x0000034fU -#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE 0x00000350U -#define _reg_PI_WDQLVL_VREF_DELTA_F0 0x00000351U -#define _reg_PI_WDQLVL_VREF_DELTA_F1 0x00000352U -#define _reg_PI_WDQLVL_VREF_DELTA_F2 0x00000353U -#define _reg_PI_WDQLVL_VREF_DELTA 0x00000354U -#define _reg_PI_WDQLVL_PERIODIC 0x00000355U -#define _reg_PI_WDQLVL_REQ 0x00000356U -#define _reg_PI_WDQLVL_CS 0x00000357U -#define _reg_PI_TDFI_WDQLVL_EN 0x00000358U -#define _reg_PI_TDFI_WDQLVL_RESP 0x00000359U -#define _reg_PI_TDFI_WDQLVL_MAX 0x0000035aU -#define _reg_PI_WDQLVL_INTERVAL 0x0000035bU -#define _reg_PI_WDQLVL_EN_F0 0x0000035cU -#define _reg_PI_WDQLVL_EN_F1 0x0000035dU -#define _reg_PI_WDQLVL_EN_F2 0x0000035eU -#define _reg_PI_WDQLVL_EN 0x0000035fU -#define _reg_PI_WDQLVL_ON_SREF_EXIT 0x00000360U -#define _reg_PI_WDQLVL_DISABLE_DFS 0x00000361U -#define _reg_PI_WDQLVL_ERROR_STATUS 0x00000362U -#define _reg_PI_MR1_DATA_F0_0 0x00000363U -#define _reg_PI_MR2_DATA_F0_0 0x00000364U -#define _reg_PI_MR3_DATA_F0_0 0x00000365U -#define _reg_PI_MR11_DATA_F0_0 0x00000366U -#define _reg_PI_MR12_DATA_F0_0 0x00000367U -#define _reg_PI_MR14_DATA_F0_0 0x00000368U -#define _reg_PI_MR22_DATA_F0_0 0x00000369U -#define _reg_PI_MR1_DATA_F1_0 0x0000036aU -#define _reg_PI_MR2_DATA_F1_0 0x0000036bU -#define _reg_PI_MR3_DATA_F1_0 0x0000036cU -#define _reg_PI_MR11_DATA_F1_0 0x0000036dU -#define _reg_PI_MR12_DATA_F1_0 0x0000036eU -#define _reg_PI_MR14_DATA_F1_0 0x0000036fU -#define _reg_PI_MR22_DATA_F1_0 0x00000370U -#define _reg_PI_MR1_DATA_F2_0 0x00000371U -#define _reg_PI_MR2_DATA_F2_0 0x00000372U -#define _reg_PI_MR3_DATA_F2_0 0x00000373U -#define _reg_PI_MR11_DATA_F2_0 0x00000374U -#define _reg_PI_MR12_DATA_F2_0 0x00000375U -#define _reg_PI_MR14_DATA_F2_0 0x00000376U -#define _reg_PI_MR22_DATA_F2_0 0x00000377U -#define _reg_PI_MR13_DATA_0 0x00000378U -#define _reg_PI_MR1_DATA_F0_1 0x00000379U -#define _reg_PI_MR2_DATA_F0_1 0x0000037aU -#define _reg_PI_MR3_DATA_F0_1 0x0000037bU -#define _reg_PI_MR11_DATA_F0_1 0x0000037cU -#define _reg_PI_MR12_DATA_F0_1 0x0000037dU -#define _reg_PI_MR14_DATA_F0_1 0x0000037eU -#define _reg_PI_MR22_DATA_F0_1 0x0000037fU -#define _reg_PI_MR1_DATA_F1_1 0x00000380U -#define _reg_PI_MR2_DATA_F1_1 0x00000381U -#define _reg_PI_MR3_DATA_F1_1 0x00000382U -#define _reg_PI_MR11_DATA_F1_1 0x00000383U -#define _reg_PI_MR12_DATA_F1_1 0x00000384U -#define _reg_PI_MR14_DATA_F1_1 0x00000385U -#define _reg_PI_MR22_DATA_F1_1 0x00000386U -#define _reg_PI_MR1_DATA_F2_1 0x00000387U -#define _reg_PI_MR2_DATA_F2_1 0x00000388U -#define _reg_PI_MR3_DATA_F2_1 0x00000389U -#define _reg_PI_MR11_DATA_F2_1 0x0000038aU -#define _reg_PI_MR12_DATA_F2_1 0x0000038bU -#define _reg_PI_MR14_DATA_F2_1 0x0000038cU -#define _reg_PI_MR22_DATA_F2_1 0x0000038dU -#define _reg_PI_MR13_DATA_1 0x0000038eU -#define _reg_PI_MR1_DATA_F0_2 0x0000038fU -#define _reg_PI_MR2_DATA_F0_2 0x00000390U -#define _reg_PI_MR3_DATA_F0_2 0x00000391U -#define _reg_PI_MR11_DATA_F0_2 0x00000392U -#define _reg_PI_MR12_DATA_F0_2 0x00000393U -#define _reg_PI_MR14_DATA_F0_2 0x00000394U -#define _reg_PI_MR22_DATA_F0_2 0x00000395U -#define _reg_PI_MR1_DATA_F1_2 0x00000396U -#define _reg_PI_MR2_DATA_F1_2 0x00000397U -#define _reg_PI_MR3_DATA_F1_2 0x00000398U -#define _reg_PI_MR11_DATA_F1_2 0x00000399U -#define _reg_PI_MR12_DATA_F1_2 0x0000039aU -#define _reg_PI_MR14_DATA_F1_2 0x0000039bU -#define _reg_PI_MR22_DATA_F1_2 0x0000039cU -#define _reg_PI_MR1_DATA_F2_2 0x0000039dU -#define _reg_PI_MR2_DATA_F2_2 0x0000039eU -#define _reg_PI_MR3_DATA_F2_2 0x0000039fU -#define _reg_PI_MR11_DATA_F2_2 0x000003a0U -#define _reg_PI_MR12_DATA_F2_2 0x000003a1U -#define _reg_PI_MR14_DATA_F2_2 0x000003a2U -#define _reg_PI_MR22_DATA_F2_2 0x000003a3U -#define _reg_PI_MR13_DATA_2 0x000003a4U -#define _reg_PI_MR1_DATA_F0_3 0x000003a5U -#define _reg_PI_MR2_DATA_F0_3 0x000003a6U -#define _reg_PI_MR3_DATA_F0_3 0x000003a7U -#define _reg_PI_MR11_DATA_F0_3 0x000003a8U -#define _reg_PI_MR12_DATA_F0_3 0x000003a9U -#define _reg_PI_MR14_DATA_F0_3 0x000003aaU -#define _reg_PI_MR22_DATA_F0_3 0x000003abU -#define _reg_PI_MR1_DATA_F1_3 0x000003acU -#define _reg_PI_MR2_DATA_F1_3 0x000003adU -#define _reg_PI_MR3_DATA_F1_3 0x000003aeU -#define _reg_PI_MR11_DATA_F1_3 0x000003afU -#define _reg_PI_MR12_DATA_F1_3 0x000003b0U -#define _reg_PI_MR14_DATA_F1_3 0x000003b1U -#define _reg_PI_MR22_DATA_F1_3 0x000003b2U -#define _reg_PI_MR1_DATA_F2_3 0x000003b3U -#define _reg_PI_MR2_DATA_F2_3 0x000003b4U -#define _reg_PI_MR3_DATA_F2_3 0x000003b5U -#define _reg_PI_MR11_DATA_F2_3 0x000003b6U -#define _reg_PI_MR12_DATA_F2_3 0x000003b7U -#define _reg_PI_MR14_DATA_F2_3 0x000003b8U -#define _reg_PI_MR22_DATA_F2_3 0x000003b9U -#define _reg_PI_MR13_DATA_3 0x000003baU -#define _reg_PI_BANK_DIFF 0x000003bbU -#define _reg_PI_ROW_DIFF 0x000003bcU -#define _reg_PI_TFC_F0 0x000003bdU -#define _reg_PI_TFC_F1 0x000003beU -#define _reg_PI_TFC_F2 0x000003bfU -#define _reg_PI_TCCD 0x000003c0U -#define _reg_PI_TRTP_F0 0x000003c1U -#define _reg_PI_TRP_F0 0x000003c2U -#define _reg_PI_TRCD_F0 0x000003c3U -#define _reg_PI_TWTR_F0 0x000003c4U -#define _reg_PI_TWR_F0 0x000003c5U -#define _reg_PI_TRAS_MAX_F0 0x000003c6U -#define _reg_PI_TRAS_MIN_F0 0x000003c7U -#define _reg_PI_TDQSCK_MAX_F0 0x000003c8U -#define _reg_PI_TCCDMW_F0 0x000003c9U -#define _reg_PI_TSR_F0 0x000003caU -#define _reg_PI_TMRD_F0 0x000003cbU -#define _reg_PI_TMRW_F0 0x000003ccU -#define _reg_PI_TMOD_F0 0x000003cdU -#define _reg_PI_TRTP_F1 0x000003ceU -#define _reg_PI_TRP_F1 0x000003cfU -#define _reg_PI_TRCD_F1 0x000003d0U -#define _reg_PI_TWTR_F1 0x000003d1U -#define _reg_PI_TWR_F1 0x000003d2U -#define _reg_PI_TRAS_MAX_F1 0x000003d3U -#define _reg_PI_TRAS_MIN_F1 0x000003d4U -#define _reg_PI_TDQSCK_MAX_F1 0x000003d5U -#define _reg_PI_TCCDMW_F1 0x000003d6U -#define _reg_PI_TSR_F1 0x000003d7U -#define _reg_PI_TMRD_F1 0x000003d8U -#define _reg_PI_TMRW_F1 0x000003d9U -#define _reg_PI_TMOD_F1 0x000003daU -#define _reg_PI_TRTP_F2 0x000003dbU -#define _reg_PI_TRP_F2 0x000003dcU -#define _reg_PI_TRCD_F2 0x000003ddU -#define _reg_PI_TWTR_F2 0x000003deU -#define _reg_PI_TWR_F2 0x000003dfU -#define _reg_PI_TRAS_MAX_F2 0x000003e0U -#define _reg_PI_TRAS_MIN_F2 0x000003e1U -#define _reg_PI_TDQSCK_MAX_F2 0x000003e2U -#define _reg_PI_TCCDMW_F2 0x000003e3U -#define _reg_PI_TSR_F2 0x000003e4U -#define _reg_PI_TMRD_F2 0x000003e5U -#define _reg_PI_TMRW_F2 0x000003e6U -#define _reg_PI_TMOD_F2 0x000003e7U -#define _reg_RESERVED_R4 0x000003e8U -#define _reg_RESERVED_R5 0x000003e9U -#define _reg_RESERVED_R6 0x000003eaU -#define _reg_RESERVED_R7 0x000003ebU -#define _reg_RESERVED_R8 0x000003ecU -#define _reg_RESERVED_R9 0x000003edU -#define _reg_RESERVED_R10 0x000003eeU -#define _reg_RESERVED_R11 0x000003efU -#define _reg_RESERVED_R12 0x000003f0U -#define _reg_RESERVED_R13 0x000003f1U -#define _reg_RESERVED_R14 0x000003f2U -#define _reg_RESERVED_R15 0x000003f3U -#define _reg_RESERVED_R16 0x000003f4U -#define _reg_RESERVED_R17 0x000003f5U -#define _reg_RESERVED_R18 0x000003f6U -#define _reg_RESERVED_R19 0x000003f7U -#define _reg_RESERVED_R20 0x000003f8U -#define _reg_RESERVED_R21 0x000003f9U -#define _reg_RESERVED_R22 0x000003faU -#define _reg_RESERVED_R23 0x000003fbU -#define _reg_PI_INT_STATUS 0x000003fcU -#define _reg_PI_INT_ACK 0x000003fdU -#define _reg_PI_INT_MASK 0x000003feU -#define _reg_PI_BIST_EXP_DATA_P0 0x000003ffU -#define _reg_PI_BIST_EXP_DATA_P1 0x00000400U -#define _reg_PI_BIST_EXP_DATA_P2 0x00000401U -#define _reg_PI_BIST_EXP_DATA_P3 0x00000402U -#define _reg_PI_BIST_FAIL_DATA_P0 0x00000403U -#define _reg_PI_BIST_FAIL_DATA_P1 0x00000404U -#define _reg_PI_BIST_FAIL_DATA_P2 0x00000405U -#define _reg_PI_BIST_FAIL_DATA_P3 0x00000406U -#define _reg_PI_BIST_FAIL_ADDR_P0 0x00000407U -#define _reg_PI_BIST_FAIL_ADDR_P1 0x00000408U -#define _reg_PI_BSTLEN 0x00000409U -#define _reg_PI_LONG_COUNT_MASK 0x0000040aU -#define _reg_PI_CMD_SWAP_EN 0x0000040bU -#define _reg_PI_CKE_MUX_0 0x0000040cU -#define _reg_PI_CKE_MUX_1 0x0000040dU -#define _reg_PI_CKE_MUX_2 0x0000040eU -#define _reg_PI_CKE_MUX_3 0x0000040fU -#define _reg_PI_CS_MUX_0 0x00000410U -#define _reg_PI_CS_MUX_1 0x00000411U -#define _reg_PI_CS_MUX_2 0x00000412U -#define _reg_PI_CS_MUX_3 0x00000413U -#define _reg_PI_RAS_N_MUX 0x00000414U -#define _reg_PI_CAS_N_MUX 0x00000415U -#define _reg_PI_WE_N_MUX 0x00000416U -#define _reg_PI_BANK_MUX_0 0x00000417U -#define _reg_PI_BANK_MUX_1 0x00000418U -#define _reg_PI_BANK_MUX_2 0x00000419U -#define _reg_PI_ODT_MUX_0 0x0000041aU -#define _reg_PI_ODT_MUX_1 0x0000041bU -#define _reg_PI_ODT_MUX_2 0x0000041cU -#define _reg_PI_ODT_MUX_3 0x0000041dU -#define _reg_PI_RESET_N_MUX_0 0x0000041eU -#define _reg_PI_RESET_N_MUX_1 0x0000041fU -#define _reg_PI_RESET_N_MUX_2 0x00000420U -#define _reg_PI_RESET_N_MUX_3 0x00000421U -#define _reg_PI_DATA_BYTE_SWAP_EN 0x00000422U -#define _reg_PI_DATA_BYTE_SWAP_SLICE0 0x00000423U -#define _reg_PI_DATA_BYTE_SWAP_SLICE1 0x00000424U -#define _reg_PI_DATA_BYTE_SWAP_SLICE2 0x00000425U -#define _reg_PI_DATA_BYTE_SWAP_SLICE3 0x00000426U -#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN 0x00000427U -#define _reg_PI_TDFI_CTRLUPD_MIN 0x00000428U -#define _reg_PI_TDFI_CTRLUPD_MAX_F0 0x00000429U -#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0 0x0000042aU -#define _reg_PI_TDFI_CTRLUPD_MAX_F1 0x0000042bU -#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1 0x0000042cU -#define _reg_PI_TDFI_CTRLUPD_MAX_F2 0x0000042dU -#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2 0x0000042eU -#define _reg_PI_UPDATE_ERROR_STATUS 0x0000042fU -#define _reg_PI_BIST_GO 0x00000430U -#define _reg_PI_BIST_RESULT 0x00000431U -#define _reg_PI_ADDR_SPACE 0x00000432U -#define _reg_PI_BIST_DATA_CHECK 0x00000433U -#define _reg_PI_BIST_ADDR_CHECK 0x00000434U -#define _reg_PI_BIST_START_ADDRESS_P0 0x00000435U -#define _reg_PI_BIST_START_ADDRESS_P1 0x00000436U -#define _reg_PI_BIST_DATA_MASK_P0 0x00000437U -#define _reg_PI_BIST_DATA_MASK_P1 0x00000438U -#define _reg_PI_BIST_ERR_COUNT 0x00000439U -#define _reg_PI_BIST_ERR_STOP 0x0000043aU -#define _reg_PI_BIST_ADDR_MASK_0_P0 0x0000043bU -#define _reg_PI_BIST_ADDR_MASK_0_P1 0x0000043cU -#define _reg_PI_BIST_ADDR_MASK_1_P0 0x0000043dU -#define _reg_PI_BIST_ADDR_MASK_1_P1 0x0000043eU -#define _reg_PI_BIST_ADDR_MASK_2_P0 0x0000043fU -#define _reg_PI_BIST_ADDR_MASK_2_P1 0x00000440U -#define _reg_PI_BIST_ADDR_MASK_3_P0 0x00000441U -#define _reg_PI_BIST_ADDR_MASK_3_P1 0x00000442U -#define _reg_PI_BIST_ADDR_MASK_4_P0 0x00000443U -#define _reg_PI_BIST_ADDR_MASK_4_P1 0x00000444U -#define _reg_PI_BIST_ADDR_MASK_5_P0 0x00000445U -#define _reg_PI_BIST_ADDR_MASK_5_P1 0x00000446U -#define _reg_PI_BIST_ADDR_MASK_6_P0 0x00000447U -#define _reg_PI_BIST_ADDR_MASK_6_P1 0x00000448U -#define _reg_PI_BIST_ADDR_MASK_7_P0 0x00000449U -#define _reg_PI_BIST_ADDR_MASK_7_P1 0x0000044aU -#define _reg_PI_BIST_ADDR_MASK_8_P0 0x0000044bU -#define _reg_PI_BIST_ADDR_MASK_8_P1 0x0000044cU -#define _reg_PI_BIST_ADDR_MASK_9_P0 0x0000044dU -#define _reg_PI_BIST_ADDR_MASK_9_P1 0x0000044eU -#define _reg_PI_BIST_MODE 0x0000044fU -#define _reg_PI_BIST_ADDR_MODE 0x00000450U -#define _reg_PI_BIST_PAT_MODE 0x00000451U -#define _reg_PI_BIST_USER_PAT_P0 0x00000452U -#define _reg_PI_BIST_USER_PAT_P1 0x00000453U -#define _reg_PI_BIST_USER_PAT_P2 0x00000454U -#define _reg_PI_BIST_USER_PAT_P3 0x00000455U -#define _reg_PI_BIST_PAT_NUM 0x00000456U -#define _reg_PI_BIST_STAGE_0 0x00000457U -#define _reg_PI_BIST_STAGE_1 0x00000458U -#define _reg_PI_BIST_STAGE_2 0x00000459U -#define _reg_PI_BIST_STAGE_3 0x0000045aU -#define _reg_PI_BIST_STAGE_4 0x0000045bU -#define _reg_PI_BIST_STAGE_5 0x0000045cU -#define _reg_PI_BIST_STAGE_6 0x0000045dU -#define _reg_PI_BIST_STAGE_7 0x0000045eU -#define _reg_PI_COL_DIFF 0x0000045fU -#define _reg_PI_SELF_REFRESH_EN 0x00000460U -#define _reg_PI_TXSR_F0 0x00000461U -#define _reg_PI_TXSR_F1 0x00000462U -#define _reg_PI_TXSR_F2 0x00000463U -#define _reg_PI_MONITOR_SRC_SEL_0 0x00000464U -#define _reg_PI_MONITOR_CAP_SEL_0 0x00000465U -#define _reg_PI_MONITOR_0 0x00000466U -#define _reg_PI_MONITOR_SRC_SEL_1 0x00000467U -#define _reg_PI_MONITOR_CAP_SEL_1 0x00000468U -#define _reg_PI_MONITOR_1 0x00000469U -#define _reg_PI_MONITOR_SRC_SEL_2 0x0000046aU -#define _reg_PI_MONITOR_CAP_SEL_2 0x0000046bU -#define _reg_PI_MONITOR_2 0x0000046cU -#define _reg_PI_MONITOR_SRC_SEL_3 0x0000046dU -#define _reg_PI_MONITOR_CAP_SEL_3 0x0000046eU -#define _reg_PI_MONITOR_3 0x0000046fU -#define _reg_PI_MONITOR_SRC_SEL_4 0x00000470U -#define _reg_PI_MONITOR_CAP_SEL_4 0x00000471U -#define _reg_PI_MONITOR_4 0x00000472U -#define _reg_PI_MONITOR_SRC_SEL_5 0x00000473U -#define _reg_PI_MONITOR_CAP_SEL_5 0x00000474U -#define _reg_PI_MONITOR_5 0x00000475U -#define _reg_PI_MONITOR_SRC_SEL_6 0x00000476U -#define _reg_PI_MONITOR_CAP_SEL_6 0x00000477U -#define _reg_PI_MONITOR_6 0x00000478U -#define _reg_PI_MONITOR_SRC_SEL_7 0x00000479U -#define _reg_PI_MONITOR_CAP_SEL_7 0x0000047aU -#define _reg_PI_MONITOR_7 0x0000047bU -#define _reg_PI_MONITOR_STROBE 0x0000047cU -#define _reg_PI_DLL_LOCK 0x0000047dU -#define _reg_PI_FREQ_NUMBER_STATUS 0x0000047eU -#define _reg_RESERVED_R24 0x0000047fU -#define _reg_PI_PHYMSTR_TYPE 0x00000480U -#define _reg_PI_POWER_REDUC_EN 0x00000481U -#define _reg_RESERVED_R25 0x00000482U -#define _reg_RESERVED_R26 0x00000483U -#define _reg_RESERVED_R27 0x00000484U -#define _reg_RESERVED_R28 0x00000485U -#define _reg_RESERVED_R29 0x00000486U -#define _reg_RESERVED_R30 0x00000487U -#define _reg_RESERVED_R31 0x00000488U -#define _reg_RESERVED_R32 0x00000489U -#define _reg_RESERVED_R33 0x0000048aU -#define _reg_RESERVED_R34 0x0000048bU -#define _reg_RESERVED_R35 0x0000048cU -#define _reg_RESERVED_R36 0x0000048dU -#define _reg_RESERVED_R37 0x0000048eU -#define _reg_RESERVED_R38 0x0000048fU -#define _reg_RESERVED_R39 0x00000490U -#define _reg_PI_WRLVL_MAX_STROBE_PEND 0x00000491U -#define _reg_PI_TSDO_F0 0x00000492U -#define _reg_PI_TSDO_F1 0x00000493U -#define _reg_PI_TSDO_F2 0x00000494U - -#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff) -#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff) -#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff) - -static const uint32_t DDR_REGDEF_TBL[4][1173] = { - { -/*0000*/ 0xffffffffU, -/*0001*/ 0xffffffffU, -/*0002*/ 0x000b0400U, -/*0003*/ 0xffffffffU, -/*0004*/ 0xffffffffU, -/*0005*/ 0x10010400U, -/*0006*/ 0x18050400U, -/*0007*/ 0x00050401U, -/*0008*/ 0x08050401U, -/*0009*/ 0x10050401U, -/*000a*/ 0x18050401U, -/*000b*/ 0x00050402U, -/*000c*/ 0x08050402U, -/*000d*/ 0x10050402U, -/*000e*/ 0x18050402U, -/*000f*/ 0x00040403U, -/*0010*/ 0x08030403U, -/*0011*/ 0x00180404U, -/*0012*/ 0x18030404U, -/*0013*/ 0x00180405U, -/*0014*/ 0x18020405U, -/*0015*/ 0x00010406U, -/*0016*/ 0x08020406U, -/*0017*/ 0x10010406U, -/*0018*/ 0x18010406U, -/*0019*/ 0x00020407U, -/*001a*/ 0x08040407U, -/*001b*/ 0x10040407U, -/*001c*/ 0x18040407U, -/*001d*/ 0x000a0408U, -/*001e*/ 0x10040408U, -/*001f*/ 0xffffffffU, -/*0020*/ 0xffffffffU, -/*0021*/ 0x18070408U, -/*0022*/ 0xffffffffU, -/*0023*/ 0xffffffffU, -/*0024*/ 0xffffffffU, -/*0025*/ 0xffffffffU, -/*0026*/ 0xffffffffU, -/*0027*/ 0xffffffffU, -/*0028*/ 0x000a0409U, -/*0029*/ 0x10040409U, -/*002a*/ 0x18010409U, -/*002b*/ 0x0001040aU, -/*002c*/ 0x0802040aU, -/*002d*/ 0x1009040aU, -/*002e*/ 0x0009040bU, -/*002f*/ 0x1002040bU, -/*0030*/ 0x0020040cU, -/*0031*/ 0xffffffffU, -/*0032*/ 0x0001040dU, -/*0033*/ 0xffffffffU, -/*0034*/ 0xffffffffU, -/*0035*/ 0xffffffffU, -/*0036*/ 0xffffffffU, -/*0037*/ 0x0020040eU, -/*0038*/ 0x0020040fU, -/*0039*/ 0x00200410U, -/*003a*/ 0x00200411U, -/*003b*/ 0x00030412U, -/*003c*/ 0x08010412U, -/*003d*/ 0x10030412U, -/*003e*/ 0x18030412U, -/*003f*/ 0x00040413U, -/*0040*/ 0x08040413U, -/*0041*/ 0x10040413U, -/*0042*/ 0x18040413U, -/*0043*/ 0x00010414U, -/*0044*/ 0x08010414U, -/*0045*/ 0x10060414U, -/*0046*/ 0x18040414U, -/*0047*/ 0xffffffffU, -/*0048*/ 0x00060415U, -/*0049*/ 0x08040415U, -/*004a*/ 0x10060415U, -/*004b*/ 0x18040415U, -/*004c*/ 0x00020416U, -/*004d*/ 0x08050416U, -/*004e*/ 0x10080416U, -/*004f*/ 0x00200417U, -/*0050*/ 0x00060418U, -/*0051*/ 0x08030418U, -/*0052*/ 0x100b0418U, -/*0053*/ 0x00040419U, -/*0054*/ 0x08040419U, -/*0055*/ 0x10040419U, -/*0056*/ 0xffffffffU, -/*0057*/ 0x18010419U, -/*0058*/ 0x0009041aU, -/*0059*/ 0x0020041bU, -/*005a*/ 0x0020041cU, -/*005b*/ 0x0020041dU, -/*005c*/ 0x0020041eU, -/*005d*/ 0x0010041fU, -/*005e*/ 0x00200420U, -/*005f*/ 0x00010421U, -/*0060*/ 0x08060421U, -/*0061*/ 0x10080421U, -/*0062*/ 0x00200422U, -/*0063*/ 0xffffffffU, -/*0064*/ 0x000a0423U, -/*0065*/ 0x10060423U, -/*0066*/ 0x18070423U, -/*0067*/ 0x00080424U, -/*0068*/ 0x08080424U, -/*0069*/ 0x100a0424U, -/*006a*/ 0x00070425U, -/*006b*/ 0x08080425U, -/*006c*/ 0x10080425U, -/*006d*/ 0x18030425U, -/*006e*/ 0x000a0426U, -/*006f*/ 0x100a0426U, -/*0070*/ 0x00110427U, -/*0071*/ 0x00090428U, -/*0072*/ 0x10090428U, -/*0073*/ 0x00100429U, -/*0074*/ 0x100e0429U, -/*0075*/ 0x000e042aU, -/*0076*/ 0x100c042aU, -/*0077*/ 0x000a042bU, -/*0078*/ 0x100a042bU, -/*0079*/ 0x0002042cU, -/*007a*/ 0x0020042dU, -/*007b*/ 0x000b042eU, -/*007c*/ 0x100b042eU, -/*007d*/ 0x0020042fU, -/*007e*/ 0x00120430U, -/*007f*/ 0x00200431U, -/*0080*/ 0x00200432U, -/*0081*/ 0xffffffffU, -/*0082*/ 0xffffffffU, -/*0083*/ 0x00010433U, -/*0084*/ 0x08010433U, -/*0085*/ 0x10080433U, -/*0086*/ 0x000c0434U, -/*0087*/ 0x100c0434U, -/*0088*/ 0x000c0435U, -/*0089*/ 0x100c0435U, -/*008a*/ 0x000c0436U, -/*008b*/ 0x100c0436U, -/*008c*/ 0x000c0437U, -/*008d*/ 0x100c0437U, -/*008e*/ 0x000c0438U, -/*008f*/ 0x100c0438U, -/*0090*/ 0x000c0439U, -/*0091*/ 0x100b0439U, -/*0092*/ 0xffffffffU, -/*0093*/ 0xffffffffU, -/*0094*/ 0x000b043aU, -/*0095*/ 0x100b043aU, -/*0096*/ 0x000b043bU, -/*0097*/ 0x100b043bU, -/*0098*/ 0x000b043cU, -/*0099*/ 0x100b043cU, -/*009a*/ 0x000b043dU, -/*009b*/ 0x100b043dU, -/*009c*/ 0x000b043eU, -/*009d*/ 0x100a043eU, -/*009e*/ 0xffffffffU, -/*009f*/ 0x000a043fU, -/*00a0*/ 0x100a043fU, -/*00a1*/ 0x000a0440U, -/*00a2*/ 0x100a0440U, -/*00a3*/ 0x000a0441U, -/*00a4*/ 0x100a0441U, -/*00a5*/ 0x000a0442U, -/*00a6*/ 0x100a0442U, -/*00a7*/ 0xffffffffU, -/*00a8*/ 0x000a0443U, -/*00a9*/ 0x100a0443U, -/*00aa*/ 0x000a0444U, -/*00ab*/ 0x100a0444U, -/*00ac*/ 0x000a0445U, -/*00ad*/ 0x100a0445U, -/*00ae*/ 0x000a0446U, -/*00af*/ 0x100a0446U, -/*00b0*/ 0x000a0447U, -/*00b1*/ 0x100a0447U, -/*00b2*/ 0x000a0448U, -/*00b3*/ 0x100a0448U, -/*00b4*/ 0x000a0449U, -/*00b5*/ 0x100a0449U, -/*00b6*/ 0x000a044aU, -/*00b7*/ 0x100a044aU, -/*00b8*/ 0x000a044bU, -/*00b9*/ 0x100a044bU, -/*00ba*/ 0x000a044cU, -/*00bb*/ 0x1004044cU, -/*00bc*/ 0x1803044cU, -/*00bd*/ 0x000a044dU, -/*00be*/ 0x100a044dU, -/*00bf*/ 0x0001044eU, -/*00c0*/ 0x080a044eU, -/*00c1*/ 0x1804044eU, -/*00c2*/ 0x000b044fU, -/*00c3*/ 0x100a044fU, -/*00c4*/ 0xffffffffU, -/*00c5*/ 0x00080450U, -/*00c6*/ 0x08080450U, -/*00c7*/ 0x10080450U, -/*00c8*/ 0x18080450U, -/*00c9*/ 0x00080451U, -/*00ca*/ 0xffffffffU, -/*00cb*/ 0x08080451U, -/*00cc*/ 0x10010451U, -/*00cd*/ 0x18080451U, -/*00ce*/ 0x00080452U, -/*00cf*/ 0x08020452U, -/*00d0*/ 0x10020452U, -/*00d1*/ 0x18040452U, -/*00d2*/ 0x00040453U, -/*00d3*/ 0xffffffffU, -/*00d4*/ 0x08040453U, -/*00d5*/ 0x100a0453U, -/*00d6*/ 0x00060454U, -/*00d7*/ 0x08080454U, -/*00d8*/ 0xffffffffU, -/*00d9*/ 0x10040454U, -/*00da*/ 0x18040454U, -/*00db*/ 0x00050455U, -/*00dc*/ 0x08040455U, -/*00dd*/ 0x10050455U, -/*00de*/ 0x000a0456U, -/*00df*/ 0x100a0456U, -/*00e0*/ 0x00080457U, -/*00e1*/ 0xffffffffU, -/*00e2*/ 0x08040457U, -/*00e3*/ 0xffffffffU, -/*00e4*/ 0xffffffffU, -/*00e5*/ 0x00050600U, -/*00e6*/ 0x08050600U, -/*00e7*/ 0x10050600U, -/*00e8*/ 0x18050600U, -/*00e9*/ 0x00050601U, -/*00ea*/ 0x08050601U, -/*00eb*/ 0x100b0601U, -/*00ec*/ 0x00010602U, -/*00ed*/ 0x08030602U, -/*00ee*/ 0x00200603U, -/*00ef*/ 0xffffffffU, -/*00f0*/ 0x00030604U, -/*00f1*/ 0x080a0604U, -/*00f2*/ 0xffffffffU, -/*00f3*/ 0xffffffffU, -/*00f4*/ 0x18030604U, -/*00f5*/ 0x00030605U, -/*00f6*/ 0x08010605U, -/*00f7*/ 0x10010605U, -/*00f8*/ 0x18060605U, -/*00f9*/ 0xffffffffU, -/*00fa*/ 0xffffffffU, -/*00fb*/ 0xffffffffU, -/*00fc*/ 0x00020606U, -/*00fd*/ 0x08030606U, -/*00fe*/ 0x10010606U, -/*00ff*/ 0x000f0607U, -/*0100*/ 0x00200608U, -/*0101*/ 0x00200609U, -/*0102*/ 0x000b060aU, -/*0103*/ 0x100b060aU, -/*0104*/ 0x000b060bU, -/*0105*/ 0xffffffffU, -/*0106*/ 0xffffffffU, -/*0107*/ 0x0018060cU, -/*0108*/ 0x0018060dU, -/*0109*/ 0x0018060eU, -/*010a*/ 0x0018060fU, -/*010b*/ 0x1804060fU, -/*010c*/ 0x00050610U, -/*010d*/ 0x08020610U, -/*010e*/ 0x10040610U, -/*010f*/ 0x18040610U, -/*0110*/ 0x00010611U, -/*0111*/ 0x08010611U, -/*0112*/ 0x10010611U, -/*0113*/ 0x18030611U, -/*0114*/ 0x00200612U, -/*0115*/ 0x00200613U, -/*0116*/ 0x00010614U, -/*0117*/ 0x08140614U, -/*0118*/ 0x00140615U, -/*0119*/ 0x00140616U, -/*011a*/ 0x00140617U, -/*011b*/ 0x00140618U, -/*011c*/ 0x00140619U, -/*011d*/ 0x0014061aU, -/*011e*/ 0x0014061bU, -/*011f*/ 0x0018061cU, -/*0120*/ 0x000a061dU, -/*0121*/ 0x1006061dU, -/*0122*/ 0x1806061dU, -/*0123*/ 0x0006061eU, -/*0124*/ 0xffffffffU, -/*0125*/ 0xffffffffU, -/*0126*/ 0x0008061fU, -/*0127*/ 0x080b061fU, -/*0128*/ 0x000b0620U, -/*0129*/ 0x100b0620U, -/*012a*/ 0x000b0621U, -/*012b*/ 0x100b0621U, -/*012c*/ 0x000b0622U, -/*012d*/ 0x10040622U, -/*012e*/ 0x000a0623U, -/*012f*/ 0x10060623U, -/*0130*/ 0x18080623U, -/*0131*/ 0xffffffffU, -/*0132*/ 0x00040624U, -/*0133*/ 0xffffffffU, -/*0134*/ 0xffffffffU, -/*0135*/ 0x00010700U, -/*0136*/ 0x08020700U, -/*0137*/ 0x10050700U, -/*0138*/ 0x18050700U, -/*0139*/ 0x00050701U, -/*013a*/ 0x08050701U, -/*013b*/ 0x100b0701U, -/*013c*/ 0x00050702U, -/*013d*/ 0x08010702U, -/*013e*/ 0x10010702U, -/*013f*/ 0xffffffffU, -/*0140*/ 0x18010702U, -/*0141*/ 0x00010703U, -/*0142*/ 0x08040703U, -/*0143*/ 0x100b0703U, -/*0144*/ 0x000b0704U, -/*0145*/ 0xffffffffU, -/*0146*/ 0x10040704U, -/*0147*/ 0x000b0705U, -/*0148*/ 0x10040705U, -/*0149*/ 0x18010705U, -/*014a*/ 0x00010706U, -/*014b*/ 0x08010706U, -/*014c*/ 0x00200707U, -/*014d*/ 0x00200708U, -/*014e*/ 0x00080709U, -/*014f*/ 0x080a0709U, -/*0150*/ 0x18050709U, -/*0151*/ 0x000a070aU, -/*0152*/ 0x1003070aU, -/*0153*/ 0x1803070aU, -/*0154*/ 0x0001070bU, -/*0155*/ 0x0802070bU, -/*0156*/ 0x1001070bU, -/*0157*/ 0x1801070bU, -/*0158*/ 0x0001070cU, -/*0159*/ 0x0802070cU, -/*015a*/ 0xffffffffU, -/*015b*/ 0xffffffffU, -/*015c*/ 0xffffffffU, -/*015d*/ 0xffffffffU, -/*015e*/ 0xffffffffU, -/*015f*/ 0xffffffffU, -/*0160*/ 0xffffffffU, -/*0161*/ 0xffffffffU, -/*0162*/ 0xffffffffU, -/*0163*/ 0xffffffffU, -/*0164*/ 0xffffffffU, -/*0165*/ 0xffffffffU, -/*0166*/ 0x1001070cU, -/*0167*/ 0x1801070cU, -/*0168*/ 0x000d070dU, -/*0169*/ 0xffffffffU, -/*016a*/ 0xffffffffU, -/*016b*/ 0x0005070eU, -/*016c*/ 0x0001070fU, -/*016d*/ 0x080e070fU, -/*016e*/ 0x000e0710U, -/*016f*/ 0x100e0710U, -/*0170*/ 0x000e0711U, -/*0171*/ 0x100e0711U, -/*0172*/ 0x00040712U, -/*0173*/ 0xffffffffU, -/*0174*/ 0xffffffffU, -/*0175*/ 0xffffffffU, -/*0176*/ 0xffffffffU, -/*0177*/ 0x080b0712U, -/*0178*/ 0x000b0713U, -/*0179*/ 0x100b0713U, -/*017a*/ 0x000b0714U, -/*017b*/ 0xffffffffU, -/*017c*/ 0xffffffffU, -/*017d*/ 0xffffffffU, -/*017e*/ 0xffffffffU, -/*017f*/ 0x000d0715U, -/*0180*/ 0xffffffffU, -/*0181*/ 0xffffffffU, -/*0182*/ 0x10100715U, -/*0183*/ 0x00080716U, -/*0184*/ 0xffffffffU, -/*0185*/ 0x08100716U, -/*0186*/ 0x00100717U, -/*0187*/ 0x10100717U, -/*0188*/ 0x00100718U, -/*0189*/ 0x10100718U, -/*018a*/ 0x00030719U, -/*018b*/ 0x08040719U, -/*018c*/ 0x10010719U, -/*018d*/ 0x18040719U, -/*018e*/ 0xffffffffU, -/*018f*/ 0xffffffffU, -/*0190*/ 0x0001071aU, -/*0191*/ 0x0812071aU, -/*0192*/ 0x000a071bU, -/*0193*/ 0x100c071bU, -/*0194*/ 0x0012071cU, -/*0195*/ 0x0014071dU, -/*0196*/ 0x0012071eU, -/*0197*/ 0x0011071fU, -/*0198*/ 0x00110720U, -/*0199*/ 0x00120721U, -/*019a*/ 0x00120722U, -/*019b*/ 0x00120723U, -/*019c*/ 0x00120724U, -/*019d*/ 0x00120725U, -/*019e*/ 0x00120726U, -/*019f*/ 0x00120727U, -/*01a0*/ 0x00120728U, -/*01a1*/ 0xffffffffU, -/*01a2*/ 0xffffffffU, -/*01a3*/ 0x00190729U, -/*01a4*/ 0x0019072aU, -/*01a5*/ 0x0020072bU, -/*01a6*/ 0x0017072cU, -/*01a7*/ 0x1808072cU, -/*01a8*/ 0x0001072dU, -/*01a9*/ 0x0801072dU, -/*01aa*/ 0x0020072eU, -/*01ab*/ 0x0008072fU, -/*01ac*/ 0xffffffffU, -/*01ad*/ 0x0803072fU, -/*01ae*/ 0x00180730U, -/*01af*/ 0x00180731U, -/*01b0*/ 0xffffffffU, -/*01b1*/ 0xffffffffU, -/*01b2*/ 0xffffffffU, -/*01b3*/ 0xffffffffU, -/*01b4*/ 0xffffffffU, -/*01b5*/ 0xffffffffU, -/*01b6*/ 0xffffffffU, -/*01b7*/ 0xffffffffU, -/*01b8*/ 0xffffffffU, -/*01b9*/ 0xffffffffU, -/*01ba*/ 0xffffffffU, -/*01bb*/ 0xffffffffU, -/*01bc*/ 0xffffffffU, -/*01bd*/ 0xffffffffU, -/*01be*/ 0xffffffffU, -/*01bf*/ 0x00100732U, -/*01c0*/ 0x10010732U, -/*01c1*/ 0x18010732U, -/*01c2*/ 0x00050733U, -/*01c3*/ 0x00200734U, -/*01c4*/ 0x00090735U, -/*01c5*/ 0xffffffffU, -/*01c6*/ 0xffffffffU, -/*01c7*/ 0x00200736U, -/*01c8*/ 0x00040737U, -/*01c9*/ 0x08100737U, -/*01ca*/ 0x18060737U, -/*01cb*/ 0x00100738U, -/*01cc*/ 0xffffffffU, -/*01cd*/ 0xffffffffU, -/*01ce*/ 0xffffffffU, -/*01cf*/ 0xffffffffU, -/*01d0*/ 0xffffffffU, -/*01d1*/ 0xffffffffU, -/*01d2*/ 0xffffffffU, -/*01d3*/ 0xffffffffU, -/*01d4*/ 0x00200739U, -/*01d5*/ 0x000b073aU, -/*01d6*/ 0xffffffffU, -/*01d7*/ 0xffffffffU, -/*01d8*/ 0xffffffffU, -/*01d9*/ 0xffffffffU, -/*01da*/ 0xffffffffU, -/*01db*/ 0xffffffffU, -/*01dc*/ 0xffffffffU, -/*01dd*/ 0xffffffffU, -/*01de*/ 0x00010200U, -/*01df*/ 0x08040200U, -/*01e0*/ 0x10100200U, -/*01e1*/ 0x00010201U, -/*01e2*/ 0x08010201U, -/*01e3*/ 0xffffffffU, -/*01e4*/ 0xffffffffU, -/*01e5*/ 0x10100201U, -/*01e6*/ 0xffffffffU, -/*01e7*/ 0xffffffffU, -/*01e8*/ 0xffffffffU, -/*01e9*/ 0xffffffffU, -/*01ea*/ 0xffffffffU, -/*01eb*/ 0xffffffffU, -/*01ec*/ 0xffffffffU, -/*01ed*/ 0xffffffffU, -/*01ee*/ 0xffffffffU, -/*01ef*/ 0x00200202U, -/*01f0*/ 0x00100203U, -/*01f1*/ 0x00200204U, -/*01f2*/ 0x00100205U, -/*01f3*/ 0x00200206U, -/*01f4*/ 0x00100207U, -/*01f5*/ 0x10100207U, -/*01f6*/ 0x00200208U, -/*01f7*/ 0x00200209U, -/*01f8*/ 0x0020020aU, -/*01f9*/ 0x0020020bU, -/*01fa*/ 0x0010020cU, -/*01fb*/ 0x0020020dU, -/*01fc*/ 0x0020020eU, -/*01fd*/ 0x0020020fU, -/*01fe*/ 0x00200210U, -/*01ff*/ 0x00100211U, -/*0200*/ 0x00200212U, -/*0201*/ 0x00200213U, -/*0202*/ 0x00200214U, -/*0203*/ 0x00200215U, -/*0204*/ 0x00090216U, -/*0205*/ 0x10010216U, -/*0206*/ 0x00200217U, -/*0207*/ 0x00050218U, -/*0208*/ 0x08010218U, -/*0209*/ 0x10080218U, -/*020a*/ 0x18080218U, -/*020b*/ 0x001c0219U, -/*020c*/ 0x001c021aU, -/*020d*/ 0x001c021bU, -/*020e*/ 0x001c021cU, -/*020f*/ 0x001c021dU, -/*0210*/ 0x001c021eU, -/*0211*/ 0x001c021fU, -/*0212*/ 0x001c0220U, -/*0213*/ 0x001c0221U, -/*0214*/ 0x001c0222U, -/*0215*/ 0x001c0223U, -/*0216*/ 0x001c0224U, -/*0217*/ 0x001c0225U, -/*0218*/ 0x001c0226U, -/*0219*/ 0x001c0227U, -/*021a*/ 0x001c0228U, -/*021b*/ 0x00010229U, -/*021c*/ 0x08010229U, -/*021d*/ 0x10010229U, -/*021e*/ 0x18040229U, -/*021f*/ 0x0008022aU, -/*0220*/ 0x0808022aU, -/*0221*/ 0x1008022aU, -/*0222*/ 0x1804022aU, -/*0223*/ 0x0006022bU, -/*0224*/ 0xffffffffU, -/*0225*/ 0x0807022bU, -/*0226*/ 0x1006022bU, -/*0227*/ 0xffffffffU, -/*0228*/ 0x1807022bU, -/*0229*/ 0x0006022cU, -/*022a*/ 0xffffffffU, -/*022b*/ 0x0807022cU, -/*022c*/ 0x1002022cU, -/*022d*/ 0x1801022cU, -/*022e*/ 0xffffffffU, -/*022f*/ 0x000a022dU, -/*0230*/ 0x1010022dU, -/*0231*/ 0x000a022eU, -/*0232*/ 0x1010022eU, -/*0233*/ 0x000a022fU, -/*0234*/ 0x1010022fU, -/*0235*/ 0xffffffffU, -/*0236*/ 0x00100230U, -/*0237*/ 0xffffffffU, -/*0238*/ 0xffffffffU, -/*0239*/ 0x10010230U, -/*023a*/ 0x18010230U, -/*023b*/ 0x00010231U, -/*023c*/ 0x08010231U, -/*023d*/ 0x10010231U, -/*023e*/ 0x18010231U, -/*023f*/ 0x00020232U, -/*0240*/ 0x08020232U, -/*0241*/ 0x10020232U, -/*0242*/ 0x18020232U, -/*0243*/ 0x00020233U, -/*0244*/ 0x08030233U, -/*0245*/ 0x10010233U, -/*0246*/ 0x18010233U, -/*0247*/ 0x00010234U, -/*0248*/ 0x08010234U, -/*0249*/ 0xffffffffU, -/*024a*/ 0x10020234U, -/*024b*/ 0x18010234U, -/*024c*/ 0x00010235U, -/*024d*/ 0xffffffffU, -/*024e*/ 0x08020235U, -/*024f*/ 0x10010235U, -/*0250*/ 0x18010235U, -/*0251*/ 0xffffffffU, -/*0252*/ 0x00020236U, -/*0253*/ 0x08010236U, -/*0254*/ 0x10010236U, -/*0255*/ 0xffffffffU, -/*0256*/ 0x18020236U, -/*0257*/ 0x00070237U, -/*0258*/ 0x08010237U, -/*0259*/ 0x10010237U, -/*025a*/ 0x18010237U, -/*025b*/ 0x00010238U, -/*025c*/ 0x08010238U, -/*025d*/ 0x10010238U, -/*025e*/ 0xffffffffU, -/*025f*/ 0x18010238U, -/*0260*/ 0x00040239U, -/*0261*/ 0x08040239U, -/*0262*/ 0x10040239U, -/*0263*/ 0x18010239U, -/*0264*/ 0x0002023aU, -/*0265*/ 0x0806023aU, -/*0266*/ 0x1006023aU, -/*0267*/ 0xffffffffU, -/*0268*/ 0xffffffffU, -/*0269*/ 0xffffffffU, -/*026a*/ 0x1802023aU, -/*026b*/ 0x0010023bU, -/*026c*/ 0x1001023bU, -/*026d*/ 0x1801023bU, -/*026e*/ 0xffffffffU, -/*026f*/ 0x0004023cU, -/*0270*/ 0x0801023cU, -/*0271*/ 0x1004023cU, -/*0272*/ 0x1802023cU, -/*0273*/ 0x0008023dU, -/*0274*/ 0xffffffffU, -/*0275*/ 0xffffffffU, -/*0276*/ 0xffffffffU, -/*0277*/ 0x080a023dU, -/*0278*/ 0x0020023eU, -/*0279*/ 0x0020023fU, -/*027a*/ 0x00050240U, -/*027b*/ 0x08010240U, -/*027c*/ 0x10050240U, -/*027d*/ 0x18080240U, -/*027e*/ 0x00010241U, -/*027f*/ 0x08080241U, -/*0280*/ 0x10010241U, -/*0281*/ 0x18080241U, -/*0282*/ 0x00010242U, -/*0283*/ 0x08040242U, -/*0284*/ 0x10040242U, -/*0285*/ 0x18040242U, -/*0286*/ 0x00040243U, -/*0287*/ 0x08040243U, -/*0288*/ 0x10040243U, -/*0289*/ 0x18040243U, -/*028a*/ 0x00040244U, -/*028b*/ 0x08040244U, -/*028c*/ 0x10040244U, -/*028d*/ 0x18010244U, -/*028e*/ 0x00040245U, -/*028f*/ 0x08040245U, -/*0290*/ 0x10040245U, -/*0291*/ 0x18040245U, -/*0292*/ 0x00040246U, -/*0293*/ 0x08040246U, -/*0294*/ 0x10060246U, -/*0295*/ 0x18060246U, -/*0296*/ 0x00060247U, -/*0297*/ 0x08060247U, -/*0298*/ 0x10060247U, -/*0299*/ 0x18060247U, -/*029a*/ 0xffffffffU, -/*029b*/ 0x00010248U, -/*029c*/ 0x08010248U, -/*029d*/ 0x10020248U, -/*029e*/ 0xffffffffU, -/*029f*/ 0xffffffffU, -/*02a0*/ 0xffffffffU, -/*02a1*/ 0xffffffffU, -/*02a2*/ 0xffffffffU, -/*02a3*/ 0xffffffffU, -/*02a4*/ 0xffffffffU, -/*02a5*/ 0xffffffffU, -/*02a6*/ 0x18040248U, -/*02a7*/ 0x00040249U, -/*02a8*/ 0x08010249U, -/*02a9*/ 0x10010249U, -/*02aa*/ 0xffffffffU, -/*02ab*/ 0x18010249U, -/*02ac*/ 0x0001024aU, -/*02ad*/ 0xffffffffU, -/*02ae*/ 0x0801024aU, -/*02af*/ 0x1001024aU, -/*02b0*/ 0x1801024aU, -/*02b1*/ 0x0004024bU, -/*02b2*/ 0x0804024bU, -/*02b3*/ 0x100a024bU, -/*02b4*/ 0x0020024cU, -/*02b5*/ 0x0004024dU, -/*02b6*/ 0x0808024dU, -/*02b7*/ 0xffffffffU, -/*02b8*/ 0xffffffffU, -/*02b9*/ 0xffffffffU, -/*02ba*/ 0xffffffffU, -/*02bb*/ 0xffffffffU, -/*02bc*/ 0xffffffffU, -/*02bd*/ 0x1002024dU, -/*02be*/ 0x1802024dU, -/*02bf*/ 0x0020024eU, -/*02c0*/ 0x0002024fU, -/*02c1*/ 0x0810024fU, -/*02c2*/ 0x00100250U, -/*02c3*/ 0x10040250U, -/*02c4*/ 0x18040250U, -/*02c5*/ 0x00050251U, -/*02c6*/ 0x08050251U, -/*02c7*/ 0xffffffffU, -/*02c8*/ 0xffffffffU, -/*02c9*/ 0xffffffffU, -/*02ca*/ 0xffffffffU, -/*02cb*/ 0x10010251U, -/*02cc*/ 0x18010251U, -/*02cd*/ 0x00070252U, -/*02ce*/ 0x08070252U, -/*02cf*/ 0x10070252U, -/*02d0*/ 0x18070252U, -/*02d1*/ 0x00070253U, -/*02d2*/ 0x08070253U, -/*02d3*/ 0x10070253U, -/*02d4*/ 0x18070253U, -/*02d5*/ 0x00070254U, -/*02d6*/ 0x08070254U, -/*02d7*/ 0x10070254U, -/*02d8*/ 0xffffffffU, -/*02d9*/ 0xffffffffU, -/*02da*/ 0xffffffffU, -/*02db*/ 0xffffffffU, -/*02dc*/ 0xffffffffU, -/*02dd*/ 0xffffffffU, -/*02de*/ 0x18030254U, -/*02df*/ 0x00010255U, -/*02e0*/ 0x08020255U, -/*02e1*/ 0x10010255U, -/*02e2*/ 0x18040255U, -/*02e3*/ 0x00020256U, -/*02e4*/ 0x08010256U, -/*02e5*/ 0x10010256U, -/*02e6*/ 0xffffffffU, -/*02e7*/ 0x18010256U, -/*02e8*/ 0x00040257U, -/*02e9*/ 0x08080257U, -/*02ea*/ 0x100a0257U, -/*02eb*/ 0x000a0258U, -/*02ec*/ 0x100a0258U, -/*02ed*/ 0x000a0259U, -/*02ee*/ 0x100a0259U, -/*02ef*/ 0x000a025aU, -/*02f0*/ 0x0020025bU, -/*02f1*/ 0x0020025cU, -/*02f2*/ 0x0001025dU, -/*02f3*/ 0xffffffffU, -/*02f4*/ 0xffffffffU, -/*02f5*/ 0xffffffffU, -/*02f6*/ 0x0802025dU, -/*02f7*/ 0x1002025dU, -/*02f8*/ 0x0010025eU, -/*02f9*/ 0x1005025eU, -/*02fa*/ 0x1806025eU, -/*02fb*/ 0x0005025fU, -/*02fc*/ 0x0805025fU, -/*02fd*/ 0x100e025fU, -/*02fe*/ 0x00050260U, -/*02ff*/ 0x080e0260U, -/*0300*/ 0x18050260U, -/*0301*/ 0x000e0261U, -/*0302*/ 0x10050261U, -/*0303*/ 0x18010261U, -/*0304*/ 0x00050262U, -/*0305*/ 0x08050262U, -/*0306*/ 0x100a0262U, -/*0307*/ 0x000a0263U, -/*0308*/ 0x10050263U, -/*0309*/ 0x18050263U, -/*030a*/ 0x000a0264U, -/*030b*/ 0x100a0264U, -/*030c*/ 0x00050265U, -/*030d*/ 0x08050265U, -/*030e*/ 0x100a0265U, -/*030f*/ 0x000a0266U, -/*0310*/ 0xffffffffU, -/*0311*/ 0xffffffffU, -/*0312*/ 0xffffffffU, -/*0313*/ 0xffffffffU, -/*0314*/ 0xffffffffU, -/*0315*/ 0xffffffffU, -/*0316*/ 0x10070266U, -/*0317*/ 0x18070266U, -/*0318*/ 0x00040267U, -/*0319*/ 0x08040267U, -/*031a*/ 0xffffffffU, -/*031b*/ 0xffffffffU, -/*031c*/ 0xffffffffU, -/*031d*/ 0x10040267U, -/*031e*/ 0x18080267U, -/*031f*/ 0x00080268U, -/*0320*/ 0x08040268U, -/*0321*/ 0xffffffffU, -/*0322*/ 0xffffffffU, -/*0323*/ 0xffffffffU, -/*0324*/ 0x10040268U, -/*0325*/ 0xffffffffU, -/*0326*/ 0xffffffffU, -/*0327*/ 0xffffffffU, -/*0328*/ 0x18040268U, -/*0329*/ 0xffffffffU, -/*032a*/ 0xffffffffU, -/*032b*/ 0xffffffffU, -/*032c*/ 0x00040269U, -/*032d*/ 0x08050269U, -/*032e*/ 0x10070269U, -/*032f*/ 0x18080269U, -/*0330*/ 0x0010026aU, -/*0331*/ 0x1008026aU, -/*0332*/ 0x0010026bU, -/*0333*/ 0x1008026bU, -/*0334*/ 0x0010026cU, -/*0335*/ 0x1008026cU, -/*0336*/ 0x1808026cU, -/*0337*/ 0x0001026dU, -/*0338*/ 0x0801026dU, -/*0339*/ 0x1006026dU, -/*033a*/ 0x1806026dU, -/*033b*/ 0x0006026eU, -/*033c*/ 0xffffffffU, -/*033d*/ 0x0801026eU, -/*033e*/ 0x1003026eU, -/*033f*/ 0xffffffffU, -/*0340*/ 0xffffffffU, -/*0341*/ 0xffffffffU, -/*0342*/ 0x000a026fU, -/*0343*/ 0x100a026fU, -/*0344*/ 0x00040270U, -/*0345*/ 0x08010270U, -/*0346*/ 0x10040270U, -/*0347*/ 0xffffffffU, -/*0348*/ 0xffffffffU, -/*0349*/ 0xffffffffU, -/*034a*/ 0xffffffffU, -/*034b*/ 0xffffffffU, -/*034c*/ 0xffffffffU, -/*034d*/ 0x18070270U, -/*034e*/ 0x00070271U, -/*034f*/ 0x08050271U, -/*0350*/ 0x10050271U, -/*0351*/ 0xffffffffU, -/*0352*/ 0xffffffffU, -/*0353*/ 0xffffffffU, -/*0354*/ 0x18040271U, -/*0355*/ 0x00010272U, -/*0356*/ 0x08010272U, -/*0357*/ 0x10020272U, -/*0358*/ 0x18080272U, -/*0359*/ 0x00200273U, -/*035a*/ 0x00200274U, -/*035b*/ 0x00100275U, -/*035c*/ 0xffffffffU, -/*035d*/ 0xffffffffU, -/*035e*/ 0xffffffffU, -/*035f*/ 0x10020275U, -/*0360*/ 0x18010275U, -/*0361*/ 0xffffffffU, -/*0362*/ 0x00020276U, -/*0363*/ 0x08080276U, -/*0364*/ 0x10080276U, -/*0365*/ 0x18080276U, -/*0366*/ 0x00080277U, -/*0367*/ 0x08080277U, -/*0368*/ 0x10080277U, -/*0369*/ 0xffffffffU, -/*036a*/ 0x18080277U, -/*036b*/ 0x00080278U, -/*036c*/ 0x08080278U, -/*036d*/ 0x10080278U, -/*036e*/ 0x18080278U, -/*036f*/ 0x00080279U, -/*0370*/ 0xffffffffU, -/*0371*/ 0x08080279U, -/*0372*/ 0x10080279U, -/*0373*/ 0x18080279U, -/*0374*/ 0x0008027aU, -/*0375*/ 0x0808027aU, -/*0376*/ 0x1008027aU, -/*0377*/ 0xffffffffU, -/*0378*/ 0x1808027aU, -/*0379*/ 0x0008027bU, -/*037a*/ 0x0808027bU, -/*037b*/ 0x1008027bU, -/*037c*/ 0x1808027bU, -/*037d*/ 0x0008027cU, -/*037e*/ 0x0808027cU, -/*037f*/ 0xffffffffU, -/*0380*/ 0x1008027cU, -/*0381*/ 0x1808027cU, -/*0382*/ 0x0008027dU, -/*0383*/ 0x0808027dU, -/*0384*/ 0x1008027dU, -/*0385*/ 0x1808027dU, -/*0386*/ 0xffffffffU, -/*0387*/ 0x0008027eU, -/*0388*/ 0x0808027eU, -/*0389*/ 0x1008027eU, -/*038a*/ 0x1808027eU, -/*038b*/ 0x0008027fU, -/*038c*/ 0x0808027fU, -/*038d*/ 0xffffffffU, -/*038e*/ 0x1008027fU, -/*038f*/ 0x1808027fU, -/*0390*/ 0x00080280U, -/*0391*/ 0x08080280U, -/*0392*/ 0x10080280U, -/*0393*/ 0x18080280U, -/*0394*/ 0x00080281U, -/*0395*/ 0xffffffffU, -/*0396*/ 0x08080281U, -/*0397*/ 0x10080281U, -/*0398*/ 0x18080281U, -/*0399*/ 0x00080282U, -/*039a*/ 0x08080282U, -/*039b*/ 0x10080282U, -/*039c*/ 0xffffffffU, -/*039d*/ 0x18080282U, -/*039e*/ 0x00080283U, -/*039f*/ 0x08080283U, -/*03a0*/ 0x10080283U, -/*03a1*/ 0x18080283U, -/*03a2*/ 0x00080284U, -/*03a3*/ 0xffffffffU, -/*03a4*/ 0x08080284U, -/*03a5*/ 0x10080284U, -/*03a6*/ 0x18080284U, -/*03a7*/ 0x00080285U, -/*03a8*/ 0x08080285U, -/*03a9*/ 0x10080285U, -/*03aa*/ 0x18080285U, -/*03ab*/ 0xffffffffU, -/*03ac*/ 0x00080286U, -/*03ad*/ 0x08080286U, -/*03ae*/ 0x10080286U, -/*03af*/ 0x18080286U, -/*03b0*/ 0x00080287U, -/*03b1*/ 0x08080287U, -/*03b2*/ 0xffffffffU, -/*03b3*/ 0x10080287U, -/*03b4*/ 0x18080287U, -/*03b5*/ 0x00080288U, -/*03b6*/ 0x08080288U, -/*03b7*/ 0x10080288U, -/*03b8*/ 0x18080288U, -/*03b9*/ 0xffffffffU, -/*03ba*/ 0x00080289U, -/*03bb*/ 0x08020289U, -/*03bc*/ 0x10030289U, -/*03bd*/ 0x000a028aU, -/*03be*/ 0x100a028aU, -/*03bf*/ 0x000a028bU, -/*03c0*/ 0x1005028bU, -/*03c1*/ 0x1804028bU, -/*03c2*/ 0x0008028cU, -/*03c3*/ 0x0808028cU, -/*03c4*/ 0x1006028cU, -/*03c5*/ 0x1806028cU, -/*03c6*/ 0x0011028dU, -/*03c7*/ 0x1808028dU, -/*03c8*/ 0x0004028eU, -/*03c9*/ 0x0806028eU, -/*03ca*/ 0xffffffffU, -/*03cb*/ 0x1006028eU, -/*03cc*/ 0x1808028eU, -/*03cd*/ 0xffffffffU, -/*03ce*/ 0x0004028fU, -/*03cf*/ 0x0808028fU, -/*03d0*/ 0x1008028fU, -/*03d1*/ 0x1806028fU, -/*03d2*/ 0x00060290U, -/*03d3*/ 0x08110290U, -/*03d4*/ 0x00080291U, -/*03d5*/ 0x08040291U, -/*03d6*/ 0x10060291U, -/*03d7*/ 0xffffffffU, -/*03d8*/ 0x18060291U, -/*03d9*/ 0x00080292U, -/*03da*/ 0xffffffffU, -/*03db*/ 0x08040292U, -/*03dc*/ 0x10080292U, -/*03dd*/ 0x18080292U, -/*03de*/ 0x00060293U, -/*03df*/ 0x08060293U, -/*03e0*/ 0x00110294U, -/*03e1*/ 0x18080294U, -/*03e2*/ 0x00040295U, -/*03e3*/ 0x08060295U, -/*03e4*/ 0xffffffffU, -/*03e5*/ 0x10060295U, -/*03e6*/ 0x18080295U, -/*03e7*/ 0xffffffffU, -/*03e8*/ 0x00040296U, -/*03e9*/ 0x08040296U, -/*03ea*/ 0x10040296U, -/*03eb*/ 0x18040296U, -/*03ec*/ 0x00040297U, -/*03ed*/ 0x08040297U, -/*03ee*/ 0x10040297U, -/*03ef*/ 0x18040297U, -/*03f0*/ 0x00040298U, -/*03f1*/ 0x08040298U, -/*03f2*/ 0x10040298U, -/*03f3*/ 0x18040298U, -/*03f4*/ 0x00040299U, -/*03f5*/ 0x08040299U, -/*03f6*/ 0x10040299U, -/*03f7*/ 0x18040299U, -/*03f8*/ 0x0004029aU, -/*03f9*/ 0x0804029aU, -/*03fa*/ 0x1004029aU, -/*03fb*/ 0x1804029aU, -/*03fc*/ 0x0011029bU, -/*03fd*/ 0x0010029cU, -/*03fe*/ 0x0011029dU, -/*03ff*/ 0x0020029eU, -/*0400*/ 0x0020029fU, -/*0401*/ 0x002002a0U, -/*0402*/ 0x002002a1U, -/*0403*/ 0x002002a2U, -/*0404*/ 0x002002a3U, -/*0405*/ 0x002002a4U, -/*0406*/ 0x002002a5U, -/*0407*/ 0x002002a6U, -/*0408*/ 0x000202a7U, -/*0409*/ 0x080502a7U, -/*040a*/ 0x100502a7U, -/*040b*/ 0xffffffffU, -/*040c*/ 0xffffffffU, -/*040d*/ 0xffffffffU, -/*040e*/ 0xffffffffU, -/*040f*/ 0xffffffffU, -/*0410*/ 0xffffffffU, -/*0411*/ 0xffffffffU, -/*0412*/ 0xffffffffU, -/*0413*/ 0xffffffffU, -/*0414*/ 0xffffffffU, -/*0415*/ 0xffffffffU, -/*0416*/ 0xffffffffU, -/*0417*/ 0xffffffffU, -/*0418*/ 0xffffffffU, -/*0419*/ 0xffffffffU, -/*041a*/ 0xffffffffU, -/*041b*/ 0xffffffffU, -/*041c*/ 0xffffffffU, -/*041d*/ 0xffffffffU, -/*041e*/ 0xffffffffU, -/*041f*/ 0xffffffffU, -/*0420*/ 0xffffffffU, -/*0421*/ 0xffffffffU, -/*0422*/ 0xffffffffU, -/*0423*/ 0xffffffffU, -/*0424*/ 0xffffffffU, -/*0425*/ 0xffffffffU, -/*0426*/ 0xffffffffU, -/*0427*/ 0x180102a7U, -/*0428*/ 0x000402a8U, -/*0429*/ 0x081002a8U, -/*042a*/ 0x002002a9U, -/*042b*/ 0x001002aaU, -/*042c*/ 0x002002abU, -/*042d*/ 0x001002acU, -/*042e*/ 0x002002adU, -/*042f*/ 0x000702aeU, -/*0430*/ 0x080102aeU, -/*0431*/ 0x100202aeU, -/*0432*/ 0x180602aeU, -/*0433*/ 0x000102afU, -/*0434*/ 0x080102afU, -/*0435*/ 0x002002b0U, -/*0436*/ 0x000202b1U, -/*0437*/ 0x002002b2U, -/*0438*/ 0x002002b3U, -/*0439*/ 0xffffffffU, -/*043a*/ 0xffffffffU, -/*043b*/ 0xffffffffU, -/*043c*/ 0xffffffffU, -/*043d*/ 0xffffffffU, -/*043e*/ 0xffffffffU, -/*043f*/ 0xffffffffU, -/*0440*/ 0xffffffffU, -/*0441*/ 0xffffffffU, -/*0442*/ 0xffffffffU, -/*0443*/ 0xffffffffU, -/*0444*/ 0xffffffffU, -/*0445*/ 0xffffffffU, -/*0446*/ 0xffffffffU, -/*0447*/ 0xffffffffU, -/*0448*/ 0xffffffffU, -/*0449*/ 0xffffffffU, -/*044a*/ 0xffffffffU, -/*044b*/ 0xffffffffU, -/*044c*/ 0xffffffffU, -/*044d*/ 0xffffffffU, -/*044e*/ 0xffffffffU, -/*044f*/ 0xffffffffU, -/*0450*/ 0xffffffffU, -/*0451*/ 0xffffffffU, -/*0452*/ 0xffffffffU, -/*0453*/ 0xffffffffU, -/*0454*/ 0xffffffffU, -/*0455*/ 0xffffffffU, -/*0456*/ 0xffffffffU, -/*0457*/ 0xffffffffU, -/*0458*/ 0xffffffffU, -/*0459*/ 0xffffffffU, -/*045a*/ 0xffffffffU, -/*045b*/ 0xffffffffU, -/*045c*/ 0xffffffffU, -/*045d*/ 0xffffffffU, -/*045e*/ 0xffffffffU, -/*045f*/ 0x000402b4U, -/*0460*/ 0xffffffffU, -/*0461*/ 0xffffffffU, -/*0462*/ 0xffffffffU, -/*0463*/ 0xffffffffU, -/*0464*/ 0xffffffffU, -/*0465*/ 0xffffffffU, -/*0466*/ 0xffffffffU, -/*0467*/ 0xffffffffU, -/*0468*/ 0xffffffffU, -/*0469*/ 0xffffffffU, -/*046a*/ 0xffffffffU, -/*046b*/ 0xffffffffU, -/*046c*/ 0xffffffffU, -/*046d*/ 0xffffffffU, -/*046e*/ 0xffffffffU, -/*046f*/ 0xffffffffU, -/*0470*/ 0xffffffffU, -/*0471*/ 0xffffffffU, -/*0472*/ 0xffffffffU, -/*0473*/ 0xffffffffU, -/*0474*/ 0xffffffffU, -/*0475*/ 0xffffffffU, -/*0476*/ 0xffffffffU, -/*0477*/ 0xffffffffU, -/*0478*/ 0xffffffffU, -/*0479*/ 0xffffffffU, -/*047a*/ 0xffffffffU, -/*047b*/ 0xffffffffU, -/*047c*/ 0xffffffffU, -/*047d*/ 0xffffffffU, -/*047e*/ 0xffffffffU, -/*047f*/ 0xffffffffU, -/*0480*/ 0xffffffffU, -/*0481*/ 0xffffffffU, -/*0482*/ 0xffffffffU, -/*0483*/ 0xffffffffU, -/*0484*/ 0xffffffffU, -/*0485*/ 0xffffffffU, -/*0486*/ 0xffffffffU, -/*0487*/ 0xffffffffU, -/*0488*/ 0xffffffffU, -/*0489*/ 0xffffffffU, -/*048a*/ 0xffffffffU, -/*048b*/ 0xffffffffU, -/*048c*/ 0xffffffffU, -/*048d*/ 0xffffffffU, -/*048e*/ 0xffffffffU, -/*048f*/ 0xffffffffU, -/*0490*/ 0xffffffffU, -/*0491*/ 0xffffffffU, -/*0492*/ 0xffffffffU, -/*0493*/ 0xffffffffU, -/*0494*/ 0xffffffffU, - }, - { -/*0000*/ 0x00200800U, -/*0001*/ 0x00040801U, -/*0002*/ 0x080b0801U, -/*0003*/ 0xffffffffU, -/*0004*/ 0xffffffffU, -/*0005*/ 0x18010801U, -/*0006*/ 0x00050802U, -/*0007*/ 0x08050802U, -/*0008*/ 0x10050802U, -/*0009*/ 0x18050802U, -/*000a*/ 0x00050803U, -/*000b*/ 0x08050803U, -/*000c*/ 0x10050803U, -/*000d*/ 0x18050803U, -/*000e*/ 0x00050804U, -/*000f*/ 0x08040804U, -/*0010*/ 0x10030804U, -/*0011*/ 0x00180805U, -/*0012*/ 0x18030805U, -/*0013*/ 0x00180806U, -/*0014*/ 0x18020806U, -/*0015*/ 0x00010807U, -/*0016*/ 0x08020807U, -/*0017*/ 0x10010807U, -/*0018*/ 0x18010807U, -/*0019*/ 0x00020808U, -/*001a*/ 0x08040808U, -/*001b*/ 0x10040808U, -/*001c*/ 0x18040808U, -/*001d*/ 0x000a0809U, -/*001e*/ 0x10040809U, -/*001f*/ 0xffffffffU, -/*0020*/ 0xffffffffU, -/*0021*/ 0x18070809U, -/*0022*/ 0xffffffffU, -/*0023*/ 0xffffffffU, -/*0024*/ 0xffffffffU, -/*0025*/ 0xffffffffU, -/*0026*/ 0xffffffffU, -/*0027*/ 0xffffffffU, -/*0028*/ 0x000a080aU, -/*0029*/ 0x1005080aU, -/*002a*/ 0x1801080aU, -/*002b*/ 0x0001080bU, -/*002c*/ 0x0802080bU, -/*002d*/ 0x1009080bU, -/*002e*/ 0x0009080cU, -/*002f*/ 0x1002080cU, -/*0030*/ 0x0020080dU, -/*0031*/ 0xffffffffU, -/*0032*/ 0x0001080eU, -/*0033*/ 0xffffffffU, -/*0034*/ 0xffffffffU, -/*0035*/ 0xffffffffU, -/*0036*/ 0xffffffffU, -/*0037*/ 0x0020080fU, -/*0038*/ 0x00200810U, -/*0039*/ 0x00200811U, -/*003a*/ 0x00200812U, -/*003b*/ 0x00030813U, -/*003c*/ 0x08010813U, -/*003d*/ 0x10030813U, -/*003e*/ 0x18030813U, -/*003f*/ 0x00040814U, -/*0040*/ 0x08040814U, -/*0041*/ 0x10040814U, -/*0042*/ 0x18040814U, -/*0043*/ 0x00010815U, -/*0044*/ 0x08010815U, -/*0045*/ 0x10060815U, -/*0046*/ 0x18040815U, -/*0047*/ 0xffffffffU, -/*0048*/ 0x00060816U, -/*0049*/ 0x08040816U, -/*004a*/ 0x10060816U, -/*004b*/ 0x18040816U, -/*004c*/ 0x00020817U, -/*004d*/ 0x08050817U, -/*004e*/ 0x10080817U, -/*004f*/ 0x00200818U, -/*0050*/ 0x00060819U, -/*0051*/ 0x08030819U, -/*0052*/ 0x100b0819U, -/*0053*/ 0x0004081aU, -/*0054*/ 0x0804081aU, -/*0055*/ 0x1004081aU, -/*0056*/ 0xffffffffU, -/*0057*/ 0x1801081aU, -/*0058*/ 0x0009081bU, -/*0059*/ 0x0020081cU, -/*005a*/ 0x0020081dU, -/*005b*/ 0x0020081eU, -/*005c*/ 0x0020081fU, -/*005d*/ 0x00100820U, -/*005e*/ 0xffffffffU, -/*005f*/ 0x10010820U, -/*0060*/ 0x18060820U, -/*0061*/ 0x00080821U, -/*0062*/ 0x00200822U, -/*0063*/ 0xffffffffU, -/*0064*/ 0x000a0823U, -/*0065*/ 0x10060823U, -/*0066*/ 0x18070823U, -/*0067*/ 0x00080824U, -/*0068*/ 0x08080824U, -/*0069*/ 0x100a0824U, -/*006a*/ 0x00070825U, -/*006b*/ 0x08080825U, -/*006c*/ 0x10080825U, -/*006d*/ 0x18030825U, -/*006e*/ 0x000a0826U, -/*006f*/ 0x100a0826U, -/*0070*/ 0x00110827U, -/*0071*/ 0x00090828U, -/*0072*/ 0x10090828U, -/*0073*/ 0x00100829U, -/*0074*/ 0x100e0829U, -/*0075*/ 0x000e082aU, -/*0076*/ 0x100c082aU, -/*0077*/ 0x000a082bU, -/*0078*/ 0x100a082bU, -/*0079*/ 0x0002082cU, -/*007a*/ 0x0020082dU, -/*007b*/ 0x000b082eU, -/*007c*/ 0x100b082eU, -/*007d*/ 0x0020082fU, -/*007e*/ 0x00120830U, -/*007f*/ 0x00200831U, -/*0080*/ 0x00200832U, -/*0081*/ 0xffffffffU, -/*0082*/ 0xffffffffU, -/*0083*/ 0x00010833U, -/*0084*/ 0x08010833U, -/*0085*/ 0x10080833U, -/*0086*/ 0x000c0834U, -/*0087*/ 0x100c0834U, -/*0088*/ 0x000c0835U, -/*0089*/ 0x100c0835U, -/*008a*/ 0x000c0836U, -/*008b*/ 0x100c0836U, -/*008c*/ 0x000c0837U, -/*008d*/ 0x100c0837U, -/*008e*/ 0x000c0838U, -/*008f*/ 0x100c0838U, -/*0090*/ 0x000c0839U, -/*0091*/ 0x100b0839U, -/*0092*/ 0xffffffffU, -/*0093*/ 0xffffffffU, -/*0094*/ 0x000b083aU, -/*0095*/ 0x100b083aU, -/*0096*/ 0x000b083bU, -/*0097*/ 0x100b083bU, -/*0098*/ 0x000b083cU, -/*0099*/ 0x100b083cU, -/*009a*/ 0x000b083dU, -/*009b*/ 0x100b083dU, -/*009c*/ 0x000b083eU, -/*009d*/ 0x100a083eU, -/*009e*/ 0xffffffffU, -/*009f*/ 0x000a083fU, -/*00a0*/ 0x100a083fU, -/*00a1*/ 0x000a0840U, -/*00a2*/ 0x100a0840U, -/*00a3*/ 0x000a0841U, -/*00a4*/ 0x100a0841U, -/*00a5*/ 0x000a0842U, -/*00a6*/ 0x100a0842U, -/*00a7*/ 0x000a0843U, -/*00a8*/ 0x100a0843U, -/*00a9*/ 0x000a0844U, -/*00aa*/ 0x100a0844U, -/*00ab*/ 0x000a0845U, -/*00ac*/ 0x100a0845U, -/*00ad*/ 0x000a0846U, -/*00ae*/ 0x100a0846U, -/*00af*/ 0x000a0847U, -/*00b0*/ 0x100a0847U, -/*00b1*/ 0x000a0848U, -/*00b2*/ 0x100a0848U, -/*00b3*/ 0x000a0849U, -/*00b4*/ 0x100a0849U, -/*00b5*/ 0x000a084aU, -/*00b6*/ 0x100a084aU, -/*00b7*/ 0x000a084bU, -/*00b8*/ 0x100a084bU, -/*00b9*/ 0x000a084cU, -/*00ba*/ 0x100a084cU, -/*00bb*/ 0x0004084dU, -/*00bc*/ 0x0803084dU, -/*00bd*/ 0x100a084dU, -/*00be*/ 0x000a084eU, -/*00bf*/ 0x1001084eU, -/*00c0*/ 0x000a084fU, -/*00c1*/ 0x1004084fU, -/*00c2*/ 0x000b0850U, -/*00c3*/ 0x100a0850U, -/*00c4*/ 0xffffffffU, -/*00c5*/ 0x00080851U, -/*00c6*/ 0x08080851U, -/*00c7*/ 0x10080851U, -/*00c8*/ 0x18080851U, -/*00c9*/ 0x00080852U, -/*00ca*/ 0xffffffffU, -/*00cb*/ 0x08080852U, -/*00cc*/ 0x10010852U, -/*00cd*/ 0x18080852U, -/*00ce*/ 0x00080853U, -/*00cf*/ 0x08020853U, -/*00d0*/ 0x10020853U, -/*00d1*/ 0x18040853U, -/*00d2*/ 0x00040854U, -/*00d3*/ 0xffffffffU, -/*00d4*/ 0x08040854U, -/*00d5*/ 0x100a0854U, -/*00d6*/ 0x00060855U, -/*00d7*/ 0x08080855U, -/*00d8*/ 0xffffffffU, -/*00d9*/ 0x10040855U, -/*00da*/ 0x18040855U, -/*00db*/ 0x00050856U, -/*00dc*/ 0x08040856U, -/*00dd*/ 0x10050856U, -/*00de*/ 0x000a0857U, -/*00df*/ 0x100a0857U, -/*00e0*/ 0x00080858U, -/*00e1*/ 0xffffffffU, -/*00e2*/ 0x08040858U, -/*00e3*/ 0xffffffffU, -/*00e4*/ 0xffffffffU, -/*00e5*/ 0x00050a00U, -/*00e6*/ 0x08050a00U, -/*00e7*/ 0x10050a00U, -/*00e8*/ 0x18050a00U, -/*00e9*/ 0x00050a01U, -/*00ea*/ 0x08050a01U, -/*00eb*/ 0x100b0a01U, -/*00ec*/ 0x00010a02U, -/*00ed*/ 0x08030a02U, -/*00ee*/ 0x00200a03U, -/*00ef*/ 0xffffffffU, -/*00f0*/ 0x00030a04U, -/*00f1*/ 0x080a0a04U, -/*00f2*/ 0xffffffffU, -/*00f3*/ 0xffffffffU, -/*00f4*/ 0x18030a04U, -/*00f5*/ 0x00030a05U, -/*00f6*/ 0x08010a05U, -/*00f7*/ 0x10010a05U, -/*00f8*/ 0x18060a05U, -/*00f9*/ 0xffffffffU, -/*00fa*/ 0xffffffffU, -/*00fb*/ 0xffffffffU, -/*00fc*/ 0x00020a06U, -/*00fd*/ 0x08030a06U, -/*00fe*/ 0x10010a06U, -/*00ff*/ 0x000f0a07U, -/*0100*/ 0x00200a08U, -/*0101*/ 0x00200a09U, -/*0102*/ 0x000b0a0aU, -/*0103*/ 0x100b0a0aU, -/*0104*/ 0x000b0a0bU, -/*0105*/ 0xffffffffU, -/*0106*/ 0xffffffffU, -/*0107*/ 0x00180a0cU, -/*0108*/ 0x00180a0dU, -/*0109*/ 0x00180a0eU, -/*010a*/ 0x00180a0fU, -/*010b*/ 0x18040a0fU, -/*010c*/ 0x00020a10U, -/*010d*/ 0x08020a10U, -/*010e*/ 0x10040a10U, -/*010f*/ 0x18040a10U, -/*0110*/ 0x00010a11U, -/*0111*/ 0x08010a11U, -/*0112*/ 0x10010a11U, -/*0113*/ 0x18030a11U, -/*0114*/ 0x00200a12U, -/*0115*/ 0x00200a13U, -/*0116*/ 0xffffffffU, -/*0117*/ 0x00140a14U, -/*0118*/ 0x00140a15U, -/*0119*/ 0x00140a16U, -/*011a*/ 0x00140a17U, -/*011b*/ 0x00140a18U, -/*011c*/ 0x00140a19U, -/*011d*/ 0x00140a1aU, -/*011e*/ 0x00140a1bU, -/*011f*/ 0x001e0a1cU, -/*0120*/ 0x000a0a1dU, -/*0121*/ 0x10060a1dU, -/*0122*/ 0x18060a1dU, -/*0123*/ 0x00060a1eU, -/*0124*/ 0xffffffffU, -/*0125*/ 0x08060a1eU, -/*0126*/ 0x00080a1fU, -/*0127*/ 0x080b0a1fU, -/*0128*/ 0x000b0a20U, -/*0129*/ 0x100b0a20U, -/*012a*/ 0x000b0a21U, -/*012b*/ 0x100b0a21U, -/*012c*/ 0x000b0a22U, -/*012d*/ 0x10040a22U, -/*012e*/ 0x000a0a23U, -/*012f*/ 0x10060a23U, -/*0130*/ 0x18080a23U, -/*0131*/ 0xffffffffU, -/*0132*/ 0x00040a24U, -/*0133*/ 0xffffffffU, -/*0134*/ 0xffffffffU, -/*0135*/ 0x00010b80U, -/*0136*/ 0x08020b80U, -/*0137*/ 0x10050b80U, -/*0138*/ 0x18050b80U, -/*0139*/ 0x00050b81U, -/*013a*/ 0x08050b81U, -/*013b*/ 0x100b0b81U, -/*013c*/ 0x00050b82U, -/*013d*/ 0x08010b82U, -/*013e*/ 0x10010b82U, -/*013f*/ 0xffffffffU, -/*0140*/ 0x18010b82U, -/*0141*/ 0x00010b83U, -/*0142*/ 0x08040b83U, -/*0143*/ 0x100b0b83U, -/*0144*/ 0x000b0b84U, -/*0145*/ 0xffffffffU, -/*0146*/ 0x10040b84U, -/*0147*/ 0x000b0b85U, -/*0148*/ 0x10040b85U, -/*0149*/ 0x18010b85U, -/*014a*/ 0x00010b86U, -/*014b*/ 0x08010b86U, -/*014c*/ 0x00200b87U, -/*014d*/ 0x00200b88U, -/*014e*/ 0x00080b89U, -/*014f*/ 0x080a0b89U, -/*0150*/ 0x18050b89U, -/*0151*/ 0x000a0b8aU, -/*0152*/ 0x10030b8aU, -/*0153*/ 0x18030b8aU, -/*0154*/ 0x00010b8bU, -/*0155*/ 0x08020b8bU, -/*0156*/ 0x10010b8bU, -/*0157*/ 0x18010b8bU, -/*0158*/ 0x00010b8cU, -/*0159*/ 0x08030b8cU, -/*015a*/ 0xffffffffU, -/*015b*/ 0x10040b8cU, -/*015c*/ 0x18040b8cU, -/*015d*/ 0x00040b8dU, -/*015e*/ 0x08040b8dU, -/*015f*/ 0xffffffffU, -/*0160*/ 0xffffffffU, -/*0161*/ 0xffffffffU, -/*0162*/ 0xffffffffU, -/*0163*/ 0xffffffffU, -/*0164*/ 0xffffffffU, -/*0165*/ 0xffffffffU, -/*0166*/ 0xffffffffU, -/*0167*/ 0xffffffffU, -/*0168*/ 0x000d0b8eU, -/*0169*/ 0x100d0b8eU, -/*016a*/ 0x000d0b8fU, -/*016b*/ 0x00050b90U, -/*016c*/ 0x00010b91U, -/*016d*/ 0x080e0b91U, -/*016e*/ 0x000e0b92U, -/*016f*/ 0x100e0b92U, -/*0170*/ 0x000e0b93U, -/*0171*/ 0x100e0b93U, -/*0172*/ 0x00040b94U, -/*0173*/ 0x08040b94U, -/*0174*/ 0x10040b94U, -/*0175*/ 0x18040b94U, -/*0176*/ 0x00040b95U, -/*0177*/ 0x080b0b95U, -/*0178*/ 0x000b0b96U, -/*0179*/ 0x100b0b96U, -/*017a*/ 0x000b0b97U, -/*017b*/ 0xffffffffU, -/*017c*/ 0xffffffffU, -/*017d*/ 0xffffffffU, -/*017e*/ 0xffffffffU, -/*017f*/ 0x000d0b98U, -/*0180*/ 0x100d0b98U, -/*0181*/ 0x000d0b99U, -/*0182*/ 0x10100b99U, -/*0183*/ 0x10080b8dU, -/*0184*/ 0x18080b8dU, -/*0185*/ 0x00100b9aU, -/*0186*/ 0x10100b9aU, -/*0187*/ 0x00100b9bU, -/*0188*/ 0x10100b9bU, -/*0189*/ 0x00100b9cU, -/*018a*/ 0x10030b9cU, -/*018b*/ 0x18040b9cU, -/*018c*/ 0x00010b9dU, -/*018d*/ 0x08040b9dU, -/*018e*/ 0xffffffffU, -/*018f*/ 0xffffffffU, -/*0190*/ 0x10010b9dU, -/*0191*/ 0x00140b9eU, -/*0192*/ 0x000a0b9fU, -/*0193*/ 0x100c0b9fU, -/*0194*/ 0x00120ba0U, -/*0195*/ 0x00140ba1U, -/*0196*/ 0x00120ba2U, -/*0197*/ 0x00110ba3U, -/*0198*/ 0x00110ba4U, -/*0199*/ 0x00120ba5U, -/*019a*/ 0x00120ba6U, -/*019b*/ 0x00120ba7U, -/*019c*/ 0x00120ba8U, -/*019d*/ 0x00120ba9U, -/*019e*/ 0x00120baaU, -/*019f*/ 0x00120babU, -/*01a0*/ 0x00120bacU, -/*01a1*/ 0xffffffffU, -/*01a2*/ 0xffffffffU, -/*01a3*/ 0x00190badU, -/*01a4*/ 0x00190baeU, -/*01a5*/ 0x00200bafU, -/*01a6*/ 0x00170bb0U, -/*01a7*/ 0x18080bb0U, -/*01a8*/ 0x00010bb1U, -/*01a9*/ 0x08010bb1U, -/*01aa*/ 0x00200bb2U, -/*01ab*/ 0x00080bb3U, -/*01ac*/ 0xffffffffU, -/*01ad*/ 0x08030bb3U, -/*01ae*/ 0x00180bb4U, -/*01af*/ 0x00180bb5U, -/*01b0*/ 0xffffffffU, -/*01b1*/ 0xffffffffU, -/*01b2*/ 0xffffffffU, -/*01b3*/ 0xffffffffU, -/*01b4*/ 0xffffffffU, -/*01b5*/ 0xffffffffU, -/*01b6*/ 0xffffffffU, -/*01b7*/ 0xffffffffU, -/*01b8*/ 0xffffffffU, -/*01b9*/ 0xffffffffU, -/*01ba*/ 0xffffffffU, -/*01bb*/ 0xffffffffU, -/*01bc*/ 0xffffffffU, -/*01bd*/ 0xffffffffU, -/*01be*/ 0xffffffffU, -/*01bf*/ 0x00100bb6U, -/*01c0*/ 0x10010bb6U, -/*01c1*/ 0x18010bb6U, -/*01c2*/ 0x00050bb7U, -/*01c3*/ 0x00200bb8U, -/*01c4*/ 0x00090bb9U, -/*01c5*/ 0xffffffffU, -/*01c6*/ 0xffffffffU, -/*01c7*/ 0x00200bbaU, -/*01c8*/ 0x00040bbbU, -/*01c9*/ 0x08100bbbU, -/*01ca*/ 0x18060bbbU, -/*01cb*/ 0x00100bbcU, -/*01cc*/ 0xffffffffU, -/*01cd*/ 0x10080bbcU, -/*01ce*/ 0xffffffffU, -/*01cf*/ 0xffffffffU, -/*01d0*/ 0xffffffffU, -/*01d1*/ 0x18030bbcU, -/*01d2*/ 0x00020bbdU, -/*01d3*/ 0xffffffffU, -/*01d4*/ 0x00200bbeU, -/*01d5*/ 0x000b0bbfU, -/*01d6*/ 0xffffffffU, -/*01d7*/ 0xffffffffU, -/*01d8*/ 0xffffffffU, -/*01d9*/ 0x10020bbfU, -/*01da*/ 0xffffffffU, -/*01db*/ 0xffffffffU, -/*01dc*/ 0xffffffffU, -/*01dd*/ 0xffffffffU, -/*01de*/ 0x00010200U, -/*01df*/ 0x08040200U, -/*01e0*/ 0x10100200U, -/*01e1*/ 0x00010201U, -/*01e2*/ 0x08010201U, -/*01e3*/ 0xffffffffU, -/*01e4*/ 0xffffffffU, -/*01e5*/ 0x10100201U, -/*01e6*/ 0xffffffffU, -/*01e7*/ 0xffffffffU, -/*01e8*/ 0xffffffffU, -/*01e9*/ 0xffffffffU, -/*01ea*/ 0xffffffffU, -/*01eb*/ 0xffffffffU, -/*01ec*/ 0xffffffffU, -/*01ed*/ 0xffffffffU, -/*01ee*/ 0xffffffffU, -/*01ef*/ 0x00200202U, -/*01f0*/ 0x00100203U, -/*01f1*/ 0x00200204U, -/*01f2*/ 0x00100205U, -/*01f3*/ 0x00200206U, -/*01f4*/ 0x00100207U, -/*01f5*/ 0x10100207U, -/*01f6*/ 0x00200208U, -/*01f7*/ 0x00200209U, -/*01f8*/ 0x0020020aU, -/*01f9*/ 0x0020020bU, -/*01fa*/ 0x0010020cU, -/*01fb*/ 0x0020020dU, -/*01fc*/ 0x0020020eU, -/*01fd*/ 0x0020020fU, -/*01fe*/ 0x00200210U, -/*01ff*/ 0x00100211U, -/*0200*/ 0x00200212U, -/*0201*/ 0x00200213U, -/*0202*/ 0x00200214U, -/*0203*/ 0x00200215U, -/*0204*/ 0x00090216U, -/*0205*/ 0x10010216U, -/*0206*/ 0x00200217U, -/*0207*/ 0x00050218U, -/*0208*/ 0x08010218U, -/*0209*/ 0x10080218U, -/*020a*/ 0x18080218U, -/*020b*/ 0x001e0219U, -/*020c*/ 0x001e021aU, -/*020d*/ 0x001e021bU, -/*020e*/ 0x001e021cU, -/*020f*/ 0x001e021dU, -/*0210*/ 0x001e021eU, -/*0211*/ 0x001e021fU, -/*0212*/ 0x001e0220U, -/*0213*/ 0x001e0221U, -/*0214*/ 0x001e0222U, -/*0215*/ 0x001e0223U, -/*0216*/ 0x001e0224U, -/*0217*/ 0x001e0225U, -/*0218*/ 0x001e0226U, -/*0219*/ 0x001e0227U, -/*021a*/ 0x001e0228U, -/*021b*/ 0x00010229U, -/*021c*/ 0x08010229U, -/*021d*/ 0x10010229U, -/*021e*/ 0x18040229U, -/*021f*/ 0x0008022aU, -/*0220*/ 0x0808022aU, -/*0221*/ 0x1008022aU, -/*0222*/ 0x1804022aU, -/*0223*/ 0x0005022bU, -/*0224*/ 0x0806022bU, -/*0225*/ 0x1007022bU, -/*0226*/ 0x1805022bU, -/*0227*/ 0x0006022cU, -/*0228*/ 0x0807022cU, -/*0229*/ 0x1005022cU, -/*022a*/ 0x1806022cU, -/*022b*/ 0x0007022dU, -/*022c*/ 0x0802022dU, -/*022d*/ 0x1001022dU, -/*022e*/ 0xffffffffU, -/*022f*/ 0x000a022eU, -/*0230*/ 0x1010022eU, -/*0231*/ 0x000a022fU, -/*0232*/ 0x1010022fU, -/*0233*/ 0x000a0230U, -/*0234*/ 0x10100230U, -/*0235*/ 0xffffffffU, -/*0236*/ 0x00100231U, -/*0237*/ 0xffffffffU, -/*0238*/ 0xffffffffU, -/*0239*/ 0x10010231U, -/*023a*/ 0x18010231U, -/*023b*/ 0x00010232U, -/*023c*/ 0x08010232U, -/*023d*/ 0x10010232U, -/*023e*/ 0x18010232U, -/*023f*/ 0x00020233U, -/*0240*/ 0x08020233U, -/*0241*/ 0x10020233U, -/*0242*/ 0x18020233U, -/*0243*/ 0x00020234U, -/*0244*/ 0x08030234U, -/*0245*/ 0x10010234U, -/*0246*/ 0x18010234U, -/*0247*/ 0x00010235U, -/*0248*/ 0x08010235U, -/*0249*/ 0xffffffffU, -/*024a*/ 0x10020235U, -/*024b*/ 0x18010235U, -/*024c*/ 0x00010236U, -/*024d*/ 0xffffffffU, -/*024e*/ 0x08020236U, -/*024f*/ 0x10010236U, -/*0250*/ 0x18010236U, -/*0251*/ 0xffffffffU, -/*0252*/ 0x00020237U, -/*0253*/ 0x08010237U, -/*0254*/ 0x10010237U, -/*0255*/ 0xffffffffU, -/*0256*/ 0x18020237U, -/*0257*/ 0x00070238U, -/*0258*/ 0x08010238U, -/*0259*/ 0x10010238U, -/*025a*/ 0x18010238U, -/*025b*/ 0x00010239U, -/*025c*/ 0x08010239U, -/*025d*/ 0x10010239U, -/*025e*/ 0xffffffffU, -/*025f*/ 0x18010239U, -/*0260*/ 0x0004023aU, -/*0261*/ 0x0804023aU, -/*0262*/ 0x1004023aU, -/*0263*/ 0x1801023aU, -/*0264*/ 0x0002023bU, -/*0265*/ 0x0806023bU, -/*0266*/ 0x1006023bU, -/*0267*/ 0xffffffffU, -/*0268*/ 0xffffffffU, -/*0269*/ 0xffffffffU, -/*026a*/ 0x1802023bU, -/*026b*/ 0x0010023cU, -/*026c*/ 0x1001023cU, -/*026d*/ 0x1801023cU, -/*026e*/ 0xffffffffU, -/*026f*/ 0x0004023dU, -/*0270*/ 0x0801023dU, -/*0271*/ 0x1004023dU, -/*0272*/ 0x1802023dU, -/*0273*/ 0x0008023eU, -/*0274*/ 0xffffffffU, -/*0275*/ 0xffffffffU, -/*0276*/ 0xffffffffU, -/*0277*/ 0x080a023eU, -/*0278*/ 0x0020023fU, -/*0279*/ 0x00200240U, -/*027a*/ 0x00050241U, -/*027b*/ 0x08010241U, -/*027c*/ 0x10050241U, -/*027d*/ 0x18080241U, -/*027e*/ 0x00010242U, -/*027f*/ 0x08080242U, -/*0280*/ 0x10010242U, -/*0281*/ 0x18080242U, -/*0282*/ 0x00010243U, -/*0283*/ 0x08040243U, -/*0284*/ 0x10040243U, -/*0285*/ 0x18040243U, -/*0286*/ 0x00040244U, -/*0287*/ 0x08040244U, -/*0288*/ 0x10040244U, -/*0289*/ 0x18040244U, -/*028a*/ 0x00040245U, -/*028b*/ 0x08040245U, -/*028c*/ 0x10040245U, -/*028d*/ 0x18010245U, -/*028e*/ 0x00040246U, -/*028f*/ 0x08040246U, -/*0290*/ 0x10040246U, -/*0291*/ 0x18040246U, -/*0292*/ 0x00040247U, -/*0293*/ 0x08040247U, -/*0294*/ 0x10060247U, -/*0295*/ 0x18060247U, -/*0296*/ 0x00060248U, -/*0297*/ 0x08060248U, -/*0298*/ 0x10060248U, -/*0299*/ 0x18060248U, -/*029a*/ 0x00040249U, -/*029b*/ 0x08010249U, -/*029c*/ 0x10010249U, -/*029d*/ 0x18020249U, -/*029e*/ 0xffffffffU, -/*029f*/ 0xffffffffU, -/*02a0*/ 0xffffffffU, -/*02a1*/ 0xffffffffU, -/*02a2*/ 0xffffffffU, -/*02a3*/ 0xffffffffU, -/*02a4*/ 0xffffffffU, -/*02a5*/ 0xffffffffU, -/*02a6*/ 0x0004024aU, -/*02a7*/ 0x0804024aU, -/*02a8*/ 0x1001024aU, -/*02a9*/ 0x1801024aU, -/*02aa*/ 0xffffffffU, -/*02ab*/ 0x0001024bU, -/*02ac*/ 0x0801024bU, -/*02ad*/ 0xffffffffU, -/*02ae*/ 0x1001024bU, -/*02af*/ 0x1801024bU, -/*02b0*/ 0x0001024cU, -/*02b1*/ 0x0804024cU, -/*02b2*/ 0x1004024cU, -/*02b3*/ 0x000a024dU, -/*02b4*/ 0x0020024eU, -/*02b5*/ 0x0004024fU, -/*02b6*/ 0x0808024fU, -/*02b7*/ 0xffffffffU, -/*02b8*/ 0xffffffffU, -/*02b9*/ 0xffffffffU, -/*02ba*/ 0xffffffffU, -/*02bb*/ 0xffffffffU, -/*02bc*/ 0xffffffffU, -/*02bd*/ 0x1002024fU, -/*02be*/ 0x1802024fU, -/*02bf*/ 0x00200250U, -/*02c0*/ 0x00020251U, -/*02c1*/ 0x08100251U, -/*02c2*/ 0x00100252U, -/*02c3*/ 0x10040252U, -/*02c4*/ 0x18040252U, -/*02c5*/ 0x00050253U, -/*02c6*/ 0x08050253U, -/*02c7*/ 0xffffffffU, -/*02c8*/ 0xffffffffU, -/*02c9*/ 0xffffffffU, -/*02ca*/ 0xffffffffU, -/*02cb*/ 0x10010253U, -/*02cc*/ 0x18010253U, -/*02cd*/ 0x00080254U, -/*02ce*/ 0x08080254U, -/*02cf*/ 0x10080254U, -/*02d0*/ 0x18080254U, -/*02d1*/ 0x00080255U, -/*02d2*/ 0x08080255U, -/*02d3*/ 0x10080255U, -/*02d4*/ 0x18080255U, -/*02d5*/ 0x00080256U, -/*02d6*/ 0x08080256U, -/*02d7*/ 0x10080256U, -/*02d8*/ 0xffffffffU, -/*02d9*/ 0xffffffffU, -/*02da*/ 0xffffffffU, -/*02db*/ 0xffffffffU, -/*02dc*/ 0xffffffffU, -/*02dd*/ 0xffffffffU, -/*02de*/ 0x18030256U, -/*02df*/ 0x00010257U, -/*02e0*/ 0x08020257U, -/*02e1*/ 0x10010257U, -/*02e2*/ 0x18040257U, -/*02e3*/ 0x00020258U, -/*02e4*/ 0x08010258U, -/*02e5*/ 0x10010258U, -/*02e6*/ 0xffffffffU, -/*02e7*/ 0x18010258U, -/*02e8*/ 0x00040259U, -/*02e9*/ 0x08080259U, -/*02ea*/ 0x100a0259U, -/*02eb*/ 0x000a025aU, -/*02ec*/ 0x100a025aU, -/*02ed*/ 0x000a025bU, -/*02ee*/ 0x100a025bU, -/*02ef*/ 0x000a025cU, -/*02f0*/ 0x0020025dU, -/*02f1*/ 0x0020025eU, -/*02f2*/ 0x0001025fU, -/*02f3*/ 0xffffffffU, -/*02f4*/ 0xffffffffU, -/*02f5*/ 0xffffffffU, -/*02f6*/ 0x0802025fU, -/*02f7*/ 0x1002025fU, -/*02f8*/ 0x00100260U, -/*02f9*/ 0x10050260U, -/*02fa*/ 0x18060260U, -/*02fb*/ 0x00050261U, -/*02fc*/ 0x08050261U, -/*02fd*/ 0x100e0261U, -/*02fe*/ 0x00050262U, -/*02ff*/ 0x080e0262U, -/*0300*/ 0x18050262U, -/*0301*/ 0x000e0263U, -/*0302*/ 0x10050263U, -/*0303*/ 0x18010263U, -/*0304*/ 0x00050264U, -/*0305*/ 0x08050264U, -/*0306*/ 0x100a0264U, -/*0307*/ 0x000a0265U, -/*0308*/ 0x10050265U, -/*0309*/ 0x18050265U, -/*030a*/ 0x000a0266U, -/*030b*/ 0x100a0266U, -/*030c*/ 0x00050267U, -/*030d*/ 0x08050267U, -/*030e*/ 0x100a0267U, -/*030f*/ 0x000a0268U, -/*0310*/ 0xffffffffU, -/*0311*/ 0xffffffffU, -/*0312*/ 0xffffffffU, -/*0313*/ 0xffffffffU, -/*0314*/ 0xffffffffU, -/*0315*/ 0xffffffffU, -/*0316*/ 0x10070268U, -/*0317*/ 0x18070268U, -/*0318*/ 0x00040269U, -/*0319*/ 0x08040269U, -/*031a*/ 0xffffffffU, -/*031b*/ 0xffffffffU, -/*031c*/ 0xffffffffU, -/*031d*/ 0x10040269U, -/*031e*/ 0x18080269U, -/*031f*/ 0x0008026aU, -/*0320*/ 0x0804026aU, -/*0321*/ 0xffffffffU, -/*0322*/ 0xffffffffU, -/*0323*/ 0xffffffffU, -/*0324*/ 0x1004026aU, -/*0325*/ 0xffffffffU, -/*0326*/ 0xffffffffU, -/*0327*/ 0xffffffffU, -/*0328*/ 0x1804026aU, -/*0329*/ 0xffffffffU, -/*032a*/ 0xffffffffU, -/*032b*/ 0xffffffffU, -/*032c*/ 0x0004026bU, -/*032d*/ 0x0805026bU, -/*032e*/ 0x1007026bU, -/*032f*/ 0x1808026bU, -/*0330*/ 0x0010026cU, -/*0331*/ 0x1008026cU, -/*0332*/ 0x0010026dU, -/*0333*/ 0x1008026dU, -/*0334*/ 0x0010026eU, -/*0335*/ 0x1008026eU, -/*0336*/ 0x1808026eU, -/*0337*/ 0x0001026fU, -/*0338*/ 0x0801026fU, -/*0339*/ 0x1006026fU, -/*033a*/ 0x1806026fU, -/*033b*/ 0x00060270U, -/*033c*/ 0xffffffffU, -/*033d*/ 0x08010270U, -/*033e*/ 0x10030270U, -/*033f*/ 0xffffffffU, -/*0340*/ 0xffffffffU, -/*0341*/ 0xffffffffU, -/*0342*/ 0x000a0271U, -/*0343*/ 0x100a0271U, -/*0344*/ 0x00040272U, -/*0345*/ 0x08010272U, -/*0346*/ 0x10040272U, -/*0347*/ 0xffffffffU, -/*0348*/ 0xffffffffU, -/*0349*/ 0xffffffffU, -/*034a*/ 0xffffffffU, -/*034b*/ 0xffffffffU, -/*034c*/ 0xffffffffU, -/*034d*/ 0x18070272U, -/*034e*/ 0x00070273U, -/*034f*/ 0x08050273U, -/*0350*/ 0x10050273U, -/*0351*/ 0xffffffffU, -/*0352*/ 0xffffffffU, -/*0353*/ 0xffffffffU, -/*0354*/ 0x18040273U, -/*0355*/ 0x00010274U, -/*0356*/ 0x08010274U, -/*0357*/ 0x10020274U, -/*0358*/ 0x18080274U, -/*0359*/ 0x00200275U, -/*035a*/ 0x00200276U, -/*035b*/ 0x00100277U, -/*035c*/ 0xffffffffU, -/*035d*/ 0xffffffffU, -/*035e*/ 0xffffffffU, -/*035f*/ 0x10020277U, -/*0360*/ 0x18010277U, -/*0361*/ 0xffffffffU, -/*0362*/ 0x00020278U, -/*0363*/ 0x08100278U, -/*0364*/ 0x00100279U, -/*0365*/ 0x10100279U, -/*0366*/ 0x0008027aU, -/*0367*/ 0x0808027aU, -/*0368*/ 0x1008027aU, -/*0369*/ 0xffffffffU, -/*036a*/ 0x0010027bU, -/*036b*/ 0x1010027bU, -/*036c*/ 0x0010027cU, -/*036d*/ 0x1008027cU, -/*036e*/ 0x1808027cU, -/*036f*/ 0x0008027dU, -/*0370*/ 0xffffffffU, -/*0371*/ 0x0810027dU, -/*0372*/ 0x0010027eU, -/*0373*/ 0x1010027eU, -/*0374*/ 0x0008027fU, -/*0375*/ 0x0808027fU, -/*0376*/ 0x1008027fU, -/*0377*/ 0xffffffffU, -/*0378*/ 0x1808027fU, -/*0379*/ 0x00100280U, -/*037a*/ 0x10100280U, -/*037b*/ 0x00100281U, -/*037c*/ 0x10080281U, -/*037d*/ 0x18080281U, -/*037e*/ 0x00080282U, -/*037f*/ 0xffffffffU, -/*0380*/ 0x08100282U, -/*0381*/ 0x00100283U, -/*0382*/ 0x10100283U, -/*0383*/ 0x00080284U, -/*0384*/ 0x08080284U, -/*0385*/ 0x10080284U, -/*0386*/ 0xffffffffU, -/*0387*/ 0x00100285U, -/*0388*/ 0x10100285U, -/*0389*/ 0x00100286U, -/*038a*/ 0x10080286U, -/*038b*/ 0x18080286U, -/*038c*/ 0x00080287U, -/*038d*/ 0xffffffffU, -/*038e*/ 0x08080287U, -/*038f*/ 0x10100287U, -/*0390*/ 0x00100288U, -/*0391*/ 0x10100288U, -/*0392*/ 0x00080289U, -/*0393*/ 0x08080289U, -/*0394*/ 0x10080289U, -/*0395*/ 0xffffffffU, -/*0396*/ 0x0010028aU, -/*0397*/ 0x1010028aU, -/*0398*/ 0x0010028bU, -/*0399*/ 0x1008028bU, -/*039a*/ 0x1808028bU, -/*039b*/ 0x0008028cU, -/*039c*/ 0xffffffffU, -/*039d*/ 0x0810028cU, -/*039e*/ 0x0010028dU, -/*039f*/ 0x1010028dU, -/*03a0*/ 0x0008028eU, -/*03a1*/ 0x0808028eU, -/*03a2*/ 0x1008028eU, -/*03a3*/ 0xffffffffU, -/*03a4*/ 0x1808028eU, -/*03a5*/ 0x0010028fU, -/*03a6*/ 0x1010028fU, -/*03a7*/ 0x00100290U, -/*03a8*/ 0x10080290U, -/*03a9*/ 0x18080290U, -/*03aa*/ 0x00080291U, -/*03ab*/ 0xffffffffU, -/*03ac*/ 0x08100291U, -/*03ad*/ 0x00100292U, -/*03ae*/ 0x10100292U, -/*03af*/ 0x00080293U, -/*03b0*/ 0x08080293U, -/*03b1*/ 0x10080293U, -/*03b2*/ 0xffffffffU, -/*03b3*/ 0x00100294U, -/*03b4*/ 0x10100294U, -/*03b5*/ 0x00100295U, -/*03b6*/ 0x10080295U, -/*03b7*/ 0x18080295U, -/*03b8*/ 0x00080296U, -/*03b9*/ 0xffffffffU, -/*03ba*/ 0x08080296U, -/*03bb*/ 0x10020296U, -/*03bc*/ 0x18030296U, -/*03bd*/ 0x000a0297U, -/*03be*/ 0x100a0297U, -/*03bf*/ 0x000a0298U, -/*03c0*/ 0x10050298U, -/*03c1*/ 0x18040298U, -/*03c2*/ 0x00080299U, -/*03c3*/ 0x08080299U, -/*03c4*/ 0x10060299U, -/*03c5*/ 0x18060299U, -/*03c6*/ 0x0011029aU, -/*03c7*/ 0x1808029aU, -/*03c8*/ 0x0004029bU, -/*03c9*/ 0x0806029bU, -/*03ca*/ 0xffffffffU, -/*03cb*/ 0x1006029bU, -/*03cc*/ 0x1808029bU, -/*03cd*/ 0x0008029cU, -/*03ce*/ 0x0804029cU, -/*03cf*/ 0x1008029cU, -/*03d0*/ 0x1808029cU, -/*03d1*/ 0x0006029dU, -/*03d2*/ 0x0806029dU, -/*03d3*/ 0x0011029eU, -/*03d4*/ 0x1808029eU, -/*03d5*/ 0x0004029fU, -/*03d6*/ 0x0806029fU, -/*03d7*/ 0xffffffffU, -/*03d8*/ 0x1006029fU, -/*03d9*/ 0x1808029fU, -/*03da*/ 0x000802a0U, -/*03db*/ 0x080402a0U, -/*03dc*/ 0x100802a0U, -/*03dd*/ 0x180802a0U, -/*03de*/ 0x000602a1U, -/*03df*/ 0x080602a1U, -/*03e0*/ 0x001102a2U, -/*03e1*/ 0x180802a2U, -/*03e2*/ 0x000402a3U, -/*03e3*/ 0x080602a3U, -/*03e4*/ 0xffffffffU, -/*03e5*/ 0x100602a3U, -/*03e6*/ 0x180802a3U, -/*03e7*/ 0x000802a4U, -/*03e8*/ 0x080402a4U, -/*03e9*/ 0x100402a4U, -/*03ea*/ 0x180402a4U, -/*03eb*/ 0x000402a5U, -/*03ec*/ 0x080402a5U, -/*03ed*/ 0x100402a5U, -/*03ee*/ 0x180402a5U, -/*03ef*/ 0x000402a6U, -/*03f0*/ 0x080402a6U, -/*03f1*/ 0x100402a6U, -/*03f2*/ 0x180402a6U, -/*03f3*/ 0x000402a7U, -/*03f4*/ 0x080402a7U, -/*03f5*/ 0x100402a7U, -/*03f6*/ 0x180402a7U, -/*03f7*/ 0x000402a8U, -/*03f8*/ 0x080402a8U, -/*03f9*/ 0x100402a8U, -/*03fa*/ 0x180402a8U, -/*03fb*/ 0x000402a9U, -/*03fc*/ 0x081202a9U, -/*03fd*/ 0x001102aaU, -/*03fe*/ 0x001202abU, -/*03ff*/ 0x002002acU, -/*0400*/ 0x002002adU, -/*0401*/ 0x002002aeU, -/*0402*/ 0x002002afU, -/*0403*/ 0x002002b0U, -/*0404*/ 0x002002b1U, -/*0405*/ 0x002002b2U, -/*0406*/ 0x002002b3U, -/*0407*/ 0x002002b4U, -/*0408*/ 0x000302b5U, -/*0409*/ 0x080502b5U, -/*040a*/ 0x100502b5U, -/*040b*/ 0x180102b5U, -/*040c*/ 0x000502b6U, -/*040d*/ 0x080502b6U, -/*040e*/ 0x100502b6U, -/*040f*/ 0x180502b6U, -/*0410*/ 0x000502b7U, -/*0411*/ 0x080502b7U, -/*0412*/ 0x100502b7U, -/*0413*/ 0x180502b7U, -/*0414*/ 0x000502b8U, -/*0415*/ 0x080502b8U, -/*0416*/ 0x100502b8U, -/*0417*/ 0x180502b8U, -/*0418*/ 0x000502b9U, -/*0419*/ 0x080502b9U, -/*041a*/ 0x100502b9U, -/*041b*/ 0x180502b9U, -/*041c*/ 0x000502baU, -/*041d*/ 0x080502baU, -/*041e*/ 0x100502baU, -/*041f*/ 0x180502baU, -/*0420*/ 0x000502bbU, -/*0421*/ 0x080502bbU, -/*0422*/ 0x100102bbU, -/*0423*/ 0x180202bbU, -/*0424*/ 0x000202bcU, -/*0425*/ 0x080202bcU, -/*0426*/ 0x100202bcU, -/*0427*/ 0x180102bcU, -/*0428*/ 0x000402bdU, -/*0429*/ 0x081002bdU, -/*042a*/ 0x002002beU, -/*042b*/ 0x001002bfU, -/*042c*/ 0x002002c0U, -/*042d*/ 0x001002c1U, -/*042e*/ 0x002002c2U, -/*042f*/ 0x000702c3U, -/*0430*/ 0x080102c3U, -/*0431*/ 0x100202c3U, -/*0432*/ 0x180602c3U, -/*0433*/ 0x000102c4U, -/*0434*/ 0x080102c4U, -/*0435*/ 0x002002c5U, -/*0436*/ 0x000302c6U, -/*0437*/ 0x002002c7U, -/*0438*/ 0x002002c8U, -/*0439*/ 0xffffffffU, -/*043a*/ 0xffffffffU, -/*043b*/ 0xffffffffU, -/*043c*/ 0xffffffffU, -/*043d*/ 0xffffffffU, -/*043e*/ 0xffffffffU, -/*043f*/ 0xffffffffU, -/*0440*/ 0xffffffffU, -/*0441*/ 0xffffffffU, -/*0442*/ 0xffffffffU, -/*0443*/ 0xffffffffU, -/*0444*/ 0xffffffffU, -/*0445*/ 0xffffffffU, -/*0446*/ 0xffffffffU, -/*0447*/ 0xffffffffU, -/*0448*/ 0xffffffffU, -/*0449*/ 0xffffffffU, -/*044a*/ 0xffffffffU, -/*044b*/ 0xffffffffU, -/*044c*/ 0xffffffffU, -/*044d*/ 0xffffffffU, -/*044e*/ 0xffffffffU, -/*044f*/ 0xffffffffU, -/*0450*/ 0xffffffffU, -/*0451*/ 0xffffffffU, -/*0452*/ 0xffffffffU, -/*0453*/ 0xffffffffU, -/*0454*/ 0xffffffffU, -/*0455*/ 0xffffffffU, -/*0456*/ 0xffffffffU, -/*0457*/ 0xffffffffU, -/*0458*/ 0xffffffffU, -/*0459*/ 0xffffffffU, -/*045a*/ 0xffffffffU, -/*045b*/ 0xffffffffU, -/*045c*/ 0xffffffffU, -/*045d*/ 0xffffffffU, -/*045e*/ 0xffffffffU, -/*045f*/ 0x000402c9U, -/*0460*/ 0xffffffffU, -/*0461*/ 0xffffffffU, -/*0462*/ 0xffffffffU, -/*0463*/ 0xffffffffU, -/*0464*/ 0xffffffffU, -/*0465*/ 0xffffffffU, -/*0466*/ 0xffffffffU, -/*0467*/ 0xffffffffU, -/*0468*/ 0xffffffffU, -/*0469*/ 0xffffffffU, -/*046a*/ 0xffffffffU, -/*046b*/ 0xffffffffU, -/*046c*/ 0xffffffffU, -/*046d*/ 0xffffffffU, -/*046e*/ 0xffffffffU, -/*046f*/ 0xffffffffU, -/*0470*/ 0xffffffffU, -/*0471*/ 0xffffffffU, -/*0472*/ 0xffffffffU, -/*0473*/ 0xffffffffU, -/*0474*/ 0xffffffffU, -/*0475*/ 0xffffffffU, -/*0476*/ 0xffffffffU, -/*0477*/ 0xffffffffU, -/*0478*/ 0xffffffffU, -/*0479*/ 0xffffffffU, -/*047a*/ 0xffffffffU, -/*047b*/ 0xffffffffU, -/*047c*/ 0xffffffffU, -/*047d*/ 0xffffffffU, -/*047e*/ 0xffffffffU, -/*047f*/ 0xffffffffU, -/*0480*/ 0xffffffffU, -/*0481*/ 0xffffffffU, -/*0482*/ 0xffffffffU, -/*0483*/ 0xffffffffU, -/*0484*/ 0xffffffffU, -/*0485*/ 0xffffffffU, -/*0486*/ 0xffffffffU, -/*0487*/ 0xffffffffU, -/*0488*/ 0xffffffffU, -/*0489*/ 0xffffffffU, -/*048a*/ 0xffffffffU, -/*048b*/ 0xffffffffU, -/*048c*/ 0xffffffffU, -/*048d*/ 0xffffffffU, -/*048e*/ 0xffffffffU, -/*048f*/ 0xffffffffU, -/*0490*/ 0xffffffffU, -/*0491*/ 0xffffffffU, -/*0492*/ 0xffffffffU, -/*0493*/ 0xffffffffU, -/*0494*/ 0xffffffffU, - }, - { -/*0000*/ 0x00200400U, -/*0001*/ 0x00040401U, -/*0002*/ 0x080b0401U, -/*0003*/ 0x000a0402U, -/*0004*/ 0x10020402U, -/*0005*/ 0x18010402U, -/*0006*/ 0x00050403U, -/*0007*/ 0x08050403U, -/*0008*/ 0x10050403U, -/*0009*/ 0x18050403U, -/*000a*/ 0x00050404U, -/*000b*/ 0x08050404U, -/*000c*/ 0x10050404U, -/*000d*/ 0x18050404U, -/*000e*/ 0x00050405U, -/*000f*/ 0x08040405U, -/*0010*/ 0x10030405U, -/*0011*/ 0x00180406U, -/*0012*/ 0x18030406U, -/*0013*/ 0x00180407U, -/*0014*/ 0x18020407U, -/*0015*/ 0x00010408U, -/*0016*/ 0x08020408U, -/*0017*/ 0x10010408U, -/*0018*/ 0x18010408U, -/*0019*/ 0x00020409U, -/*001a*/ 0x08040409U, -/*001b*/ 0x10040409U, -/*001c*/ 0x18040409U, -/*001d*/ 0xffffffffU, -/*001e*/ 0x0004040aU, -/*001f*/ 0xffffffffU, -/*0020*/ 0xffffffffU, -/*0021*/ 0x0809040aU, -/*0022*/ 0x1801040aU, -/*0023*/ 0x0020040bU, -/*0024*/ 0x001c040cU, -/*0025*/ 0x0001040dU, -/*0026*/ 0x0807040dU, -/*0027*/ 0x1009040dU, -/*0028*/ 0x000a040eU, -/*0029*/ 0x1005040eU, -/*002a*/ 0x1801040eU, -/*002b*/ 0x1001040fU, -/*002c*/ 0x1802040fU, -/*002d*/ 0x0009040fU, -/*002e*/ 0x00090410U, -/*002f*/ 0x10020410U, -/*0030*/ 0x00200411U, -/*0031*/ 0x00010412U, -/*0032*/ 0x08020412U, -/*0033*/ 0xffffffffU, -/*0034*/ 0xffffffffU, -/*0035*/ 0xffffffffU, -/*0036*/ 0xffffffffU, -/*0037*/ 0x00200413U, -/*0038*/ 0x00200414U, -/*0039*/ 0x00200415U, -/*003a*/ 0x00200416U, -/*003b*/ 0x00030417U, -/*003c*/ 0x08010417U, -/*003d*/ 0x10040417U, -/*003e*/ 0x18030417U, -/*003f*/ 0x00040418U, -/*0040*/ 0x08040418U, -/*0041*/ 0x10040418U, -/*0042*/ 0x18040418U, -/*0043*/ 0x00010419U, -/*0044*/ 0x08010419U, -/*0045*/ 0x10060419U, -/*0046*/ 0x18040419U, -/*0047*/ 0xffffffffU, -/*0048*/ 0x0006041aU, -/*0049*/ 0x0804041aU, -/*004a*/ 0x1006041aU, -/*004b*/ 0x1804041aU, -/*004c*/ 0x0002041bU, -/*004d*/ 0x0805041bU, -/*004e*/ 0x1008041bU, -/*004f*/ 0xffffffffU, -/*0050*/ 0x1806041bU, -/*0051*/ 0x0003041cU, -/*0052*/ 0x080b041cU, -/*0053*/ 0x1804041cU, -/*0054*/ 0x0004041dU, -/*0055*/ 0x0804041dU, -/*0056*/ 0x1001041dU, -/*0057*/ 0xffffffffU, -/*0058*/ 0x0009041eU, -/*0059*/ 0x0020041fU, -/*005a*/ 0x00200420U, -/*005b*/ 0x00200421U, -/*005c*/ 0x00200422U, -/*005d*/ 0x00100423U, -/*005e*/ 0xffffffffU, -/*005f*/ 0x10010423U, -/*0060*/ 0x18060423U, -/*0061*/ 0x00080424U, -/*0062*/ 0x00200425U, -/*0063*/ 0x00100426U, -/*0064*/ 0x100a0426U, -/*0065*/ 0x00060427U, -/*0066*/ 0x08070427U, -/*0067*/ 0x10080427U, -/*0068*/ 0x18080427U, -/*0069*/ 0x000a0428U, -/*006a*/ 0x10070428U, -/*006b*/ 0x18080428U, -/*006c*/ 0x00080429U, -/*006d*/ 0x08030429U, -/*006e*/ 0x100a0429U, -/*006f*/ 0x000a042aU, -/*0070*/ 0x0011042bU, -/*0071*/ 0x0009042cU, -/*0072*/ 0x1009042cU, -/*0073*/ 0x0010042dU, -/*0074*/ 0x100e042dU, -/*0075*/ 0x000e042eU, -/*0076*/ 0x0012042fU, -/*0077*/ 0x000a0430U, -/*0078*/ 0x100a0430U, -/*0079*/ 0x00020431U, -/*007a*/ 0x00200432U, -/*007b*/ 0x000b0433U, -/*007c*/ 0x100b0433U, -/*007d*/ 0x00200434U, -/*007e*/ 0x00120435U, -/*007f*/ 0x00200436U, -/*0080*/ 0x00200437U, -/*0081*/ 0x00080438U, -/*0082*/ 0x08010438U, -/*0083*/ 0x10010438U, -/*0084*/ 0x18010438U, -/*0085*/ 0x00080439U, -/*0086*/ 0x080c0439U, -/*0087*/ 0x000c043aU, -/*0088*/ 0x100c043aU, -/*0089*/ 0x000c043bU, -/*008a*/ 0x100c043bU, -/*008b*/ 0x000c043cU, -/*008c*/ 0x100c043cU, -/*008d*/ 0x000c043dU, -/*008e*/ 0x100c043dU, -/*008f*/ 0x000c043eU, -/*0090*/ 0x100c043eU, -/*0091*/ 0x000b043fU, -/*0092*/ 0x1009043fU, -/*0093*/ 0x00010440U, -/*0094*/ 0x000b0441U, -/*0095*/ 0x100b0441U, -/*0096*/ 0x000b0442U, -/*0097*/ 0x100b0442U, -/*0098*/ 0x000b0443U, -/*0099*/ 0x100b0443U, -/*009a*/ 0x000b0444U, -/*009b*/ 0x100b0444U, -/*009c*/ 0x000b0445U, -/*009d*/ 0x100a0445U, -/*009e*/ 0x00020446U, -/*009f*/ 0x080a0446U, -/*00a0*/ 0x000a0447U, -/*00a1*/ 0x100a0447U, -/*00a2*/ 0x000a0448U, -/*00a3*/ 0x100a0448U, -/*00a4*/ 0x000a0449U, -/*00a5*/ 0x100a0449U, -/*00a6*/ 0x000a044aU, -/*00a7*/ 0x100a044aU, -/*00a8*/ 0x000a044bU, -/*00a9*/ 0x100a044bU, -/*00aa*/ 0x000a044cU, -/*00ab*/ 0x100a044cU, -/*00ac*/ 0x000a044dU, -/*00ad*/ 0x100a044dU, -/*00ae*/ 0x000a044eU, -/*00af*/ 0x100a044eU, -/*00b0*/ 0x000a044fU, -/*00b1*/ 0x100a044fU, -/*00b2*/ 0x000a0450U, -/*00b3*/ 0x100a0450U, -/*00b4*/ 0x000a0451U, -/*00b5*/ 0x100a0451U, -/*00b6*/ 0x000a0452U, -/*00b7*/ 0x100a0452U, -/*00b8*/ 0x000a0453U, -/*00b9*/ 0x100a0453U, -/*00ba*/ 0x000a0454U, -/*00bb*/ 0x10040454U, -/*00bc*/ 0x18030454U, -/*00bd*/ 0x000a0455U, -/*00be*/ 0x100a0455U, -/*00bf*/ 0x00010456U, -/*00c0*/ 0x080a0456U, -/*00c1*/ 0x18040456U, -/*00c2*/ 0x000b0457U, -/*00c3*/ 0x100a0457U, -/*00c4*/ 0x00030458U, -/*00c5*/ 0x00080459U, -/*00c6*/ 0x08080459U, -/*00c7*/ 0x10080459U, -/*00c8*/ 0x18080459U, -/*00c9*/ 0x0008045aU, -/*00ca*/ 0xffffffffU, -/*00cb*/ 0x0808045aU, -/*00cc*/ 0x1001045aU, -/*00cd*/ 0x1808045aU, -/*00ce*/ 0x0008045bU, -/*00cf*/ 0x0802045bU, -/*00d0*/ 0x1002045bU, -/*00d1*/ 0x1805045bU, -/*00d2*/ 0x0005045cU, -/*00d3*/ 0xffffffffU, -/*00d4*/ 0x0804045cU, -/*00d5*/ 0x100a045cU, -/*00d6*/ 0x0006045dU, -/*00d7*/ 0x0808045dU, -/*00d8*/ 0x1008045dU, -/*00d9*/ 0x1804045dU, -/*00da*/ 0x0004045eU, -/*00db*/ 0x0805045eU, -/*00dc*/ 0x1004045eU, -/*00dd*/ 0x1805045eU, -/*00de*/ 0x000a045fU, -/*00df*/ 0x100a045fU, -/*00e0*/ 0x00080460U, -/*00e1*/ 0xffffffffU, -/*00e2*/ 0x08040460U, -/*00e3*/ 0xffffffffU, -/*00e4*/ 0xffffffffU, -/*00e5*/ 0x00050600U, -/*00e6*/ 0x08050600U, -/*00e7*/ 0x10050600U, -/*00e8*/ 0x18050600U, -/*00e9*/ 0x00050601U, -/*00ea*/ 0x08050601U, -/*00eb*/ 0x100b0601U, -/*00ec*/ 0x00010602U, -/*00ed*/ 0x08030602U, -/*00ee*/ 0x00200603U, -/*00ef*/ 0x00100604U, -/*00f0*/ 0x10040604U, -/*00f1*/ 0x000a0605U, -/*00f2*/ 0x10090605U, -/*00f3*/ 0x00080606U, -/*00f4*/ 0x08030606U, -/*00f5*/ 0x10030606U, -/*00f6*/ 0x18010606U, -/*00f7*/ 0x00010607U, -/*00f8*/ 0x08070607U, -/*00f9*/ 0x10070607U, -/*00fa*/ 0x18050607U, -/*00fb*/ 0x00010608U, -/*00fc*/ 0x08020608U, -/*00fd*/ 0x10030608U, -/*00fe*/ 0x18010608U, -/*00ff*/ 0x000f0609U, -/*0100*/ 0x0020060aU, -/*0101*/ 0x0020060bU, -/*0102*/ 0x000b060cU, -/*0103*/ 0x100b060cU, -/*0104*/ 0x000b060dU, -/*0105*/ 0x0018060eU, -/*0106*/ 0x0018060fU, -/*0107*/ 0xffffffffU, -/*0108*/ 0xffffffffU, -/*0109*/ 0xffffffffU, -/*010a*/ 0xffffffffU, -/*010b*/ 0xffffffffU, -/*010c*/ 0x1802060fU, -/*010d*/ 0x00020610U, -/*010e*/ 0x08040610U, -/*010f*/ 0x10040610U, -/*0110*/ 0x18010610U, -/*0111*/ 0x00010611U, -/*0112*/ 0x08010611U, -/*0113*/ 0x10030611U, -/*0114*/ 0x00200612U, -/*0115*/ 0x00200613U, -/*0116*/ 0xffffffffU, -/*0117*/ 0x00140614U, -/*0118*/ 0x00140615U, -/*0119*/ 0x00140616U, -/*011a*/ 0x00140617U, -/*011b*/ 0x00140618U, -/*011c*/ 0x00140619U, -/*011d*/ 0x0014061aU, -/*011e*/ 0x0014061bU, -/*011f*/ 0x0018061cU, -/*0120*/ 0x000a061dU, -/*0121*/ 0x1006061dU, -/*0122*/ 0x1806061dU, -/*0123*/ 0x0006061eU, -/*0124*/ 0xffffffffU, -/*0125*/ 0x0806061eU, -/*0126*/ 0x0008061fU, -/*0127*/ 0x080b061fU, -/*0128*/ 0x000b0620U, -/*0129*/ 0x100b0620U, -/*012a*/ 0x000b0621U, -/*012b*/ 0x100b0621U, -/*012c*/ 0x000b0622U, -/*012d*/ 0x10040622U, -/*012e*/ 0x000a0623U, -/*012f*/ 0x10060623U, -/*0130*/ 0x18080623U, -/*0131*/ 0x00080624U, -/*0132*/ 0x08040624U, -/*0133*/ 0x00020680U, -/*0134*/ 0x00010681U, -/*0135*/ 0x08010681U, -/*0136*/ 0x10020681U, -/*0137*/ 0x18050681U, -/*0138*/ 0x00050682U, -/*0139*/ 0x08050682U, -/*013a*/ 0x10050682U, -/*013b*/ 0x000b0683U, -/*013c*/ 0x10050683U, -/*013d*/ 0x18010683U, -/*013e*/ 0x00010684U, -/*013f*/ 0xffffffffU, -/*0140*/ 0x08010684U, -/*0141*/ 0x10010684U, -/*0142*/ 0x18040684U, -/*0143*/ 0x000b0685U, -/*0144*/ 0x100b0685U, -/*0145*/ 0x000b0686U, -/*0146*/ 0x10040686U, -/*0147*/ 0x000b0687U, -/*0148*/ 0x10040687U, -/*0149*/ 0x18010687U, -/*014a*/ 0x00010688U, -/*014b*/ 0x08010688U, -/*014c*/ 0x00200689U, -/*014d*/ 0x0020068aU, -/*014e*/ 0x0008068bU, -/*014f*/ 0x080a068bU, -/*0150*/ 0x1805068bU, -/*0151*/ 0x000a068cU, -/*0152*/ 0x1003068cU, -/*0153*/ 0x1803068cU, -/*0154*/ 0x0001068dU, -/*0155*/ 0x0802068dU, -/*0156*/ 0x1001068dU, -/*0157*/ 0x1801068dU, -/*0158*/ 0x0001068eU, -/*0159*/ 0x0802068eU, -/*015a*/ 0x1001068eU, -/*015b*/ 0x0004068fU, -/*015c*/ 0x0804068fU, -/*015d*/ 0x1004068fU, -/*015e*/ 0x1804068fU, -/*015f*/ 0x00010690U, -/*0160*/ 0x08010690U, -/*0161*/ 0x10010690U, -/*0162*/ 0x00200691U, -/*0163*/ 0x00200692U, -/*0164*/ 0x00200693U, -/*0165*/ 0x00200694U, -/*0166*/ 0xffffffffU, -/*0167*/ 0x1801068eU, -/*0168*/ 0x000d0696U, -/*0169*/ 0x100d0696U, -/*016a*/ 0x000d0697U, -/*016b*/ 0x00050698U, -/*016c*/ 0x00010699U, -/*016d*/ 0x080e0699U, -/*016e*/ 0x000e069aU, -/*016f*/ 0x100e069aU, -/*0170*/ 0x000e069bU, -/*0171*/ 0x100e069bU, -/*0172*/ 0x0004069cU, -/*0173*/ 0x0804069cU, -/*0174*/ 0x1004069cU, -/*0175*/ 0x1804069cU, -/*0176*/ 0x0004069dU, -/*0177*/ 0x080b069dU, -/*0178*/ 0x000b069eU, -/*0179*/ 0x100b069eU, -/*017a*/ 0x000b069fU, -/*017b*/ 0xffffffffU, -/*017c*/ 0xffffffffU, -/*017d*/ 0xffffffffU, -/*017e*/ 0xffffffffU, -/*017f*/ 0x000d06a0U, -/*0180*/ 0x100d06a0U, -/*0181*/ 0x000d06a1U, -/*0182*/ 0x101006a1U, -/*0183*/ 0x00080695U, -/*0184*/ 0x08080695U, -/*0185*/ 0x001006a2U, -/*0186*/ 0x101006a2U, -/*0187*/ 0x001006a3U, -/*0188*/ 0x101006a3U, -/*0189*/ 0x001006a4U, -/*018a*/ 0x100306a4U, -/*018b*/ 0x180406a4U, -/*018c*/ 0x000106a5U, -/*018d*/ 0x080806a5U, -/*018e*/ 0x100106a5U, -/*018f*/ 0x180506a5U, -/*0190*/ 0x000106a6U, -/*0191*/ 0x081406a6U, -/*0192*/ 0x000a06a7U, -/*0193*/ 0x100c06a7U, -/*0194*/ 0x001206a8U, -/*0195*/ 0x001406a9U, -/*0196*/ 0x001206aaU, -/*0197*/ 0x001106abU, -/*0198*/ 0x001106acU, -/*0199*/ 0x001206adU, -/*019a*/ 0x001206aeU, -/*019b*/ 0x001206afU, -/*019c*/ 0x001206b0U, -/*019d*/ 0x001206b1U, -/*019e*/ 0x001206b2U, -/*019f*/ 0x001206b3U, -/*01a0*/ 0x001206b4U, -/*01a1*/ 0x001206b5U, -/*01a2*/ 0x001206b6U, -/*01a3*/ 0x000e06b7U, -/*01a4*/ 0x100d06b7U, -/*01a5*/ 0x002006b8U, -/*01a6*/ 0x001706b9U, -/*01a7*/ 0x000906baU, -/*01a8*/ 0x100106baU, -/*01a9*/ 0x180106baU, -/*01aa*/ 0x002006bbU, -/*01ab*/ 0x000806bcU, -/*01ac*/ 0x080306bcU, -/*01ad*/ 0x100306bcU, -/*01ae*/ 0x001806bdU, -/*01af*/ 0x001806beU, -/*01b0*/ 0x180706beU, -/*01b1*/ 0x000506bfU, -/*01b2*/ 0x080806bfU, -/*01b3*/ 0x100806bfU, -/*01b4*/ 0x180806bfU, -/*01b5*/ 0x000106c0U, -/*01b6*/ 0x080106c0U, -/*01b7*/ 0x002006c1U, -/*01b8*/ 0xffffffffU, -/*01b9*/ 0xffffffffU, -/*01ba*/ 0xffffffffU, -/*01bb*/ 0xffffffffU, -/*01bc*/ 0xffffffffU, -/*01bd*/ 0xffffffffU, -/*01be*/ 0xffffffffU, -/*01bf*/ 0x001006c2U, -/*01c0*/ 0x100106c2U, -/*01c1*/ 0x180106c2U, -/*01c2*/ 0x000206c3U, -/*01c3*/ 0x080406c3U, -/*01c4*/ 0x100906c3U, -/*01c5*/ 0x000706c4U, -/*01c6*/ 0x080406c4U, -/*01c7*/ 0x002006c5U, -/*01c8*/ 0x000106c6U, -/*01c9*/ 0x080206c6U, -/*01ca*/ 0x100606c6U, -/*01cb*/ 0x001006c7U, -/*01cc*/ 0x100106c7U, -/*01cd*/ 0x002006c8U, -/*01ce*/ 0x000806c9U, -/*01cf*/ 0x080106c9U, -/*01d0*/ 0x100506c9U, -/*01d1*/ 0xffffffffU, -/*01d2*/ 0x180206c9U, -/*01d3*/ 0x000106caU, -/*01d4*/ 0x002006cbU, -/*01d5*/ 0x000b06ccU, -/*01d6*/ 0x100106ccU, -/*01d7*/ 0x180306ccU, -/*01d8*/ 0x000806cdU, -/*01d9*/ 0x080206cdU, -/*01da*/ 0x100c06cdU, -/*01db*/ 0x000406ceU, -/*01dc*/ 0x080106ceU, -/*01dd*/ 0xffffffffU, -/*01de*/ 0x00010200U, -/*01df*/ 0x08040200U, -/*01e0*/ 0x10100200U, -/*01e1*/ 0x00010201U, -/*01e2*/ 0x08010201U, -/*01e3*/ 0x10010201U, -/*01e4*/ 0xffffffffU, -/*01e5*/ 0x00100202U, -/*01e6*/ 0x10080202U, -/*01e7*/ 0xffffffffU, -/*01e8*/ 0xffffffffU, -/*01e9*/ 0xffffffffU, -/*01ea*/ 0xffffffffU, -/*01eb*/ 0xffffffffU, -/*01ec*/ 0xffffffffU, -/*01ed*/ 0xffffffffU, -/*01ee*/ 0xffffffffU, -/*01ef*/ 0x00200203U, -/*01f0*/ 0x00100204U, -/*01f1*/ 0x00200205U, -/*01f2*/ 0x00100206U, -/*01f3*/ 0x00200207U, -/*01f4*/ 0x00100208U, -/*01f5*/ 0x00140209U, -/*01f6*/ 0x0020020aU, -/*01f7*/ 0x0020020bU, -/*01f8*/ 0x0020020cU, -/*01f9*/ 0x0020020dU, -/*01fa*/ 0x0014020eU, -/*01fb*/ 0x0020020fU, -/*01fc*/ 0x00200210U, -/*01fd*/ 0x00200211U, -/*01fe*/ 0x00200212U, -/*01ff*/ 0x00140213U, -/*0200*/ 0x00200214U, -/*0201*/ 0x00200215U, -/*0202*/ 0x00200216U, -/*0203*/ 0x00200217U, -/*0204*/ 0x00090218U, -/*0205*/ 0x10010218U, -/*0206*/ 0x00200219U, -/*0207*/ 0x0005021aU, -/*0208*/ 0x0801021aU, -/*0209*/ 0x1008021aU, -/*020a*/ 0x1808021aU, -/*020b*/ 0x001c021bU, -/*020c*/ 0x001c021cU, -/*020d*/ 0x001c021dU, -/*020e*/ 0x001c021eU, -/*020f*/ 0x001c021fU, -/*0210*/ 0x001c0220U, -/*0211*/ 0x001c0221U, -/*0212*/ 0x001c0222U, -/*0213*/ 0x001c0223U, -/*0214*/ 0x001c0224U, -/*0215*/ 0x001c0225U, -/*0216*/ 0x001c0226U, -/*0217*/ 0x001c0227U, -/*0218*/ 0x001c0228U, -/*0219*/ 0x001c0229U, -/*021a*/ 0x001c022aU, -/*021b*/ 0x0001022bU, -/*021c*/ 0x0801022bU, -/*021d*/ 0x1001022bU, -/*021e*/ 0x1804022bU, -/*021f*/ 0x0008022cU, -/*0220*/ 0x0808022cU, -/*0221*/ 0x1008022cU, -/*0222*/ 0x1804022cU, -/*0223*/ 0x0007022dU, -/*0224*/ 0xffffffffU, -/*0225*/ 0x0807022dU, -/*0226*/ 0x1007022dU, -/*0227*/ 0xffffffffU, -/*0228*/ 0x1807022dU, -/*0229*/ 0x0007022eU, -/*022a*/ 0xffffffffU, -/*022b*/ 0x0807022eU, -/*022c*/ 0x1002022eU, -/*022d*/ 0x1801022eU, -/*022e*/ 0x0001022fU, -/*022f*/ 0x080a022fU, -/*0230*/ 0x00140230U, -/*0231*/ 0x000a0231U, -/*0232*/ 0x00140232U, -/*0233*/ 0x000a0233U, -/*0234*/ 0x00140234U, -/*0235*/ 0x18010234U, -/*0236*/ 0x00100235U, -/*0237*/ 0x10050235U, -/*0238*/ 0x18010235U, -/*0239*/ 0x00010236U, -/*023a*/ 0x08010236U, -/*023b*/ 0x10010236U, -/*023c*/ 0x18010236U, -/*023d*/ 0x00010237U, -/*023e*/ 0x08010237U, -/*023f*/ 0x10020237U, -/*0240*/ 0x18020237U, -/*0241*/ 0x00020238U, -/*0242*/ 0x08020238U, -/*0243*/ 0x10020238U, -/*0244*/ 0x18030238U, -/*0245*/ 0x00010239U, -/*0246*/ 0x08010239U, -/*0247*/ 0x10010239U, -/*0248*/ 0x18010239U, -/*0249*/ 0xffffffffU, -/*024a*/ 0x0002023aU, -/*024b*/ 0x0801023aU, -/*024c*/ 0x1001023aU, -/*024d*/ 0xffffffffU, -/*024e*/ 0x1802023aU, -/*024f*/ 0x0001023bU, -/*0250*/ 0x0801023bU, -/*0251*/ 0xffffffffU, -/*0252*/ 0x1002023bU, -/*0253*/ 0x1801023bU, -/*0254*/ 0x0001023cU, -/*0255*/ 0xffffffffU, -/*0256*/ 0x0802023cU, -/*0257*/ 0x1007023cU, -/*0258*/ 0x1801023cU, -/*0259*/ 0x0001023dU, -/*025a*/ 0x0801023dU, -/*025b*/ 0x1001023dU, -/*025c*/ 0x1801023dU, -/*025d*/ 0x0001023eU, -/*025e*/ 0x0801023eU, -/*025f*/ 0x1001023eU, -/*0260*/ 0x1804023eU, -/*0261*/ 0x0004023fU, -/*0262*/ 0x0804023fU, -/*0263*/ 0x1001023fU, -/*0264*/ 0x1802023fU, -/*0265*/ 0x00060240U, -/*0266*/ 0x08060240U, -/*0267*/ 0x10020240U, -/*0268*/ 0x18020240U, -/*0269*/ 0x00020241U, -/*026a*/ 0xffffffffU, -/*026b*/ 0x08100241U, -/*026c*/ 0x18010241U, -/*026d*/ 0x00010242U, -/*026e*/ 0x08010242U, -/*026f*/ 0x10040242U, -/*0270*/ 0x18010242U, -/*0271*/ 0x00040243U, -/*0272*/ 0x08020243U, -/*0273*/ 0x10080243U, -/*0274*/ 0xffffffffU, -/*0275*/ 0xffffffffU, -/*0276*/ 0xffffffffU, -/*0277*/ 0x000a0244U, -/*0278*/ 0x00200245U, -/*0279*/ 0x00200246U, -/*027a*/ 0x00050247U, -/*027b*/ 0x08010247U, -/*027c*/ 0x10050247U, -/*027d*/ 0x18080247U, -/*027e*/ 0x00010248U, -/*027f*/ 0x08080248U, -/*0280*/ 0x10010248U, -/*0281*/ 0x18080248U, -/*0282*/ 0x00010249U, -/*0283*/ 0x08040249U, -/*0284*/ 0x10040249U, -/*0285*/ 0x18040249U, -/*0286*/ 0x0004024aU, -/*0287*/ 0x0804024aU, -/*0288*/ 0x1004024aU, -/*0289*/ 0x1804024aU, -/*028a*/ 0x0004024bU, -/*028b*/ 0x0804024bU, -/*028c*/ 0x1004024bU, -/*028d*/ 0x1801024bU, -/*028e*/ 0x0004024cU, -/*028f*/ 0x0804024cU, -/*0290*/ 0x1004024cU, -/*0291*/ 0x1804024cU, -/*0292*/ 0x0004024dU, -/*0293*/ 0x0804024dU, -/*0294*/ 0x1006024dU, -/*0295*/ 0x1806024dU, -/*0296*/ 0x0006024eU, -/*0297*/ 0x0806024eU, -/*0298*/ 0x1006024eU, -/*0299*/ 0x1806024eU, -/*029a*/ 0xffffffffU, -/*029b*/ 0x0001024fU, -/*029c*/ 0x0801024fU, -/*029d*/ 0x1002024fU, -/*029e*/ 0xffffffffU, -/*029f*/ 0xffffffffU, -/*02a0*/ 0xffffffffU, -/*02a1*/ 0xffffffffU, -/*02a2*/ 0xffffffffU, -/*02a3*/ 0xffffffffU, -/*02a4*/ 0xffffffffU, -/*02a5*/ 0xffffffffU, -/*02a6*/ 0x1804024fU, -/*02a7*/ 0x00040250U, -/*02a8*/ 0x08010250U, -/*02a9*/ 0x10010250U, -/*02aa*/ 0x18010250U, -/*02ab*/ 0x00010251U, -/*02ac*/ 0x08010251U, -/*02ad*/ 0x10010251U, -/*02ae*/ 0x18010251U, -/*02af*/ 0x00010252U, -/*02b0*/ 0x08010252U, -/*02b1*/ 0x10040252U, -/*02b2*/ 0x18040252U, -/*02b3*/ 0x000a0253U, -/*02b4*/ 0x00200254U, -/*02b5*/ 0x00040255U, -/*02b6*/ 0x08080255U, -/*02b7*/ 0x10020255U, -/*02b8*/ 0x18020255U, -/*02b9*/ 0x00020256U, -/*02ba*/ 0x08020256U, -/*02bb*/ 0x10020256U, -/*02bc*/ 0x18020256U, -/*02bd*/ 0xffffffffU, -/*02be*/ 0xffffffffU, -/*02bf*/ 0x00200257U, -/*02c0*/ 0x00020258U, -/*02c1*/ 0x08100258U, -/*02c2*/ 0x00100259U, -/*02c3*/ 0x10040259U, -/*02c4*/ 0x18040259U, -/*02c5*/ 0x0005025aU, -/*02c6*/ 0x0805025aU, -/*02c7*/ 0x0020025bU, -/*02c8*/ 0x0020025cU, -/*02c9*/ 0x0020025dU, -/*02ca*/ 0x0020025eU, -/*02cb*/ 0x0001025fU, -/*02cc*/ 0x0801025fU, -/*02cd*/ 0x1007025fU, -/*02ce*/ 0x1807025fU, -/*02cf*/ 0x00070260U, -/*02d0*/ 0x08070260U, -/*02d1*/ 0x10070260U, -/*02d2*/ 0x18070260U, -/*02d3*/ 0x00070261U, -/*02d4*/ 0x08070261U, -/*02d5*/ 0x10070261U, -/*02d6*/ 0x18070261U, -/*02d7*/ 0x00070262U, -/*02d8*/ 0x08070262U, -/*02d9*/ 0x10070262U, -/*02da*/ 0x18070262U, -/*02db*/ 0x00030263U, -/*02dc*/ 0x08030263U, -/*02dd*/ 0x10030263U, -/*02de*/ 0xffffffffU, -/*02df*/ 0x18010263U, -/*02e0*/ 0x00020264U, -/*02e1*/ 0x08010264U, -/*02e2*/ 0x10040264U, -/*02e3*/ 0x18020264U, -/*02e4*/ 0x00010265U, -/*02e5*/ 0x08010265U, -/*02e6*/ 0x10010265U, -/*02e7*/ 0x18010265U, -/*02e8*/ 0x00040266U, -/*02e9*/ 0x08080266U, -/*02ea*/ 0x100a0266U, -/*02eb*/ 0x000a0267U, -/*02ec*/ 0x100a0267U, -/*02ed*/ 0x000a0268U, -/*02ee*/ 0x100a0268U, -/*02ef*/ 0x000a0269U, -/*02f0*/ 0x0020026aU, -/*02f1*/ 0x0020026bU, -/*02f2*/ 0x0001026cU, -/*02f3*/ 0x0802026cU, -/*02f4*/ 0x1002026cU, -/*02f5*/ 0x1802026cU, -/*02f6*/ 0xffffffffU, -/*02f7*/ 0x0002026dU, -/*02f8*/ 0x0810026dU, -/*02f9*/ 0x1805026dU, -/*02fa*/ 0x0006026eU, -/*02fb*/ 0x0805026eU, -/*02fc*/ 0x1005026eU, -/*02fd*/ 0x000e026fU, -/*02fe*/ 0x1005026fU, -/*02ff*/ 0x000e0270U, -/*0300*/ 0x10050270U, -/*0301*/ 0x000e0271U, -/*0302*/ 0x10050271U, -/*0303*/ 0x18010271U, -/*0304*/ 0x00050272U, -/*0305*/ 0x08050272U, -/*0306*/ 0x100a0272U, -/*0307*/ 0x000a0273U, -/*0308*/ 0x10050273U, -/*0309*/ 0x18050273U, -/*030a*/ 0x000a0274U, -/*030b*/ 0x100a0274U, -/*030c*/ 0x00050275U, -/*030d*/ 0x08050275U, -/*030e*/ 0x100a0275U, -/*030f*/ 0x000a0276U, -/*0310*/ 0xffffffffU, -/*0311*/ 0xffffffffU, -/*0312*/ 0xffffffffU, -/*0313*/ 0xffffffffU, -/*0314*/ 0xffffffffU, -/*0315*/ 0xffffffffU, -/*0316*/ 0x10070276U, -/*0317*/ 0x18070276U, -/*0318*/ 0x00040277U, -/*0319*/ 0x08040277U, -/*031a*/ 0xffffffffU, -/*031b*/ 0xffffffffU, -/*031c*/ 0xffffffffU, -/*031d*/ 0x10040277U, -/*031e*/ 0x18080277U, -/*031f*/ 0x00080278U, -/*0320*/ 0x08040278U, -/*0321*/ 0xffffffffU, -/*0322*/ 0xffffffffU, -/*0323*/ 0xffffffffU, -/*0324*/ 0x10040278U, -/*0325*/ 0xffffffffU, -/*0326*/ 0xffffffffU, -/*0327*/ 0xffffffffU, -/*0328*/ 0x18040278U, -/*0329*/ 0xffffffffU, -/*032a*/ 0xffffffffU, -/*032b*/ 0xffffffffU, -/*032c*/ 0x00040279U, -/*032d*/ 0x08050279U, -/*032e*/ 0x10070279U, -/*032f*/ 0x18080279U, -/*0330*/ 0x0010027aU, -/*0331*/ 0x1008027aU, -/*0332*/ 0x0010027bU, -/*0333*/ 0x1008027bU, -/*0334*/ 0x0010027cU, -/*0335*/ 0x1008027cU, -/*0336*/ 0x1808027cU, -/*0337*/ 0x0001027dU, -/*0338*/ 0x0801027dU, -/*0339*/ 0x1006027dU, -/*033a*/ 0x1806027dU, -/*033b*/ 0x0006027eU, -/*033c*/ 0x0801027eU, -/*033d*/ 0x1001027eU, -/*033e*/ 0x1803027eU, -/*033f*/ 0x000a027fU, -/*0340*/ 0x100a027fU, -/*0341*/ 0x000a0280U, -/*0342*/ 0xffffffffU, -/*0343*/ 0x100a0280U, -/*0344*/ 0x00040281U, -/*0345*/ 0x08010281U, -/*0346*/ 0x10040281U, -/*0347*/ 0xffffffffU, -/*0348*/ 0xffffffffU, -/*0349*/ 0xffffffffU, -/*034a*/ 0xffffffffU, -/*034b*/ 0xffffffffU, -/*034c*/ 0xffffffffU, -/*034d*/ 0x18070281U, -/*034e*/ 0x00070282U, -/*034f*/ 0x08050282U, -/*0350*/ 0x10050282U, -/*0351*/ 0xffffffffU, -/*0352*/ 0xffffffffU, -/*0353*/ 0xffffffffU, -/*0354*/ 0x18040282U, -/*0355*/ 0x00010283U, -/*0356*/ 0x08010283U, -/*0357*/ 0x10020283U, -/*0358*/ 0x18080283U, -/*0359*/ 0x00200284U, -/*035a*/ 0x00200285U, -/*035b*/ 0x00100286U, -/*035c*/ 0x10020286U, -/*035d*/ 0x18020286U, -/*035e*/ 0x00020287U, -/*035f*/ 0xffffffffU, -/*0360*/ 0x08010287U, -/*0361*/ 0x10010287U, -/*0362*/ 0x18020287U, -/*0363*/ 0x00080288U, -/*0364*/ 0x08080288U, -/*0365*/ 0x10080288U, -/*0366*/ 0x18080288U, -/*0367*/ 0x00080289U, -/*0368*/ 0x08080289U, -/*0369*/ 0xffffffffU, -/*036a*/ 0x10080289U, -/*036b*/ 0x18080289U, -/*036c*/ 0x0008028aU, -/*036d*/ 0x0808028aU, -/*036e*/ 0x1008028aU, -/*036f*/ 0x1808028aU, -/*0370*/ 0xffffffffU, -/*0371*/ 0x0008028bU, -/*0372*/ 0x0808028bU, -/*0373*/ 0x1008028bU, -/*0374*/ 0x1808028bU, -/*0375*/ 0x0008028cU, -/*0376*/ 0x0808028cU, -/*0377*/ 0xffffffffU, -/*0378*/ 0x1008028cU, -/*0379*/ 0x1808028cU, -/*037a*/ 0x0008028dU, -/*037b*/ 0x0808028dU, -/*037c*/ 0x1008028dU, -/*037d*/ 0x1808028dU, -/*037e*/ 0x0008028eU, -/*037f*/ 0xffffffffU, -/*0380*/ 0x0808028eU, -/*0381*/ 0x1008028eU, -/*0382*/ 0x1808028eU, -/*0383*/ 0x0008028fU, -/*0384*/ 0x0808028fU, -/*0385*/ 0x1008028fU, -/*0386*/ 0xffffffffU, -/*0387*/ 0x1808028fU, -/*0388*/ 0x00080290U, -/*0389*/ 0x08080290U, -/*038a*/ 0x10080290U, -/*038b*/ 0x18080290U, -/*038c*/ 0x00080291U, -/*038d*/ 0xffffffffU, -/*038e*/ 0x08080291U, -/*038f*/ 0x10080291U, -/*0390*/ 0x18080291U, -/*0391*/ 0x00080292U, -/*0392*/ 0x08080292U, -/*0393*/ 0x10080292U, -/*0394*/ 0x18080292U, -/*0395*/ 0xffffffffU, -/*0396*/ 0x00080293U, -/*0397*/ 0x08080293U, -/*0398*/ 0x10080293U, -/*0399*/ 0x18080293U, -/*039a*/ 0x00080294U, -/*039b*/ 0x08080294U, -/*039c*/ 0xffffffffU, -/*039d*/ 0x10080294U, -/*039e*/ 0x18080294U, -/*039f*/ 0x00080295U, -/*03a0*/ 0x08080295U, -/*03a1*/ 0x10080295U, -/*03a2*/ 0x18080295U, -/*03a3*/ 0xffffffffU, -/*03a4*/ 0x00080296U, -/*03a5*/ 0x08080296U, -/*03a6*/ 0x10080296U, -/*03a7*/ 0x18080296U, -/*03a8*/ 0x00080297U, -/*03a9*/ 0x08080297U, -/*03aa*/ 0x10080297U, -/*03ab*/ 0xffffffffU, -/*03ac*/ 0x18080297U, -/*03ad*/ 0x00080298U, -/*03ae*/ 0x08080298U, -/*03af*/ 0x10080298U, -/*03b0*/ 0x18080298U, -/*03b1*/ 0x00080299U, -/*03b2*/ 0xffffffffU, -/*03b3*/ 0x08080299U, -/*03b4*/ 0x10080299U, -/*03b5*/ 0x18080299U, -/*03b6*/ 0x0008029aU, -/*03b7*/ 0x0808029aU, -/*03b8*/ 0x1008029aU, -/*03b9*/ 0xffffffffU, -/*03ba*/ 0x1808029aU, -/*03bb*/ 0x0002029bU, -/*03bc*/ 0x0803029bU, -/*03bd*/ 0x100a029bU, -/*03be*/ 0x000a029cU, -/*03bf*/ 0x100a029cU, -/*03c0*/ 0x0005029dU, -/*03c1*/ 0x0808029dU, -/*03c2*/ 0x1008029dU, -/*03c3*/ 0x1808029dU, -/*03c4*/ 0x0006029eU, -/*03c5*/ 0x0806029eU, -/*03c6*/ 0x0011029fU, -/*03c7*/ 0x1808029fU, -/*03c8*/ 0x000402a0U, -/*03c9*/ 0x080602a0U, -/*03ca*/ 0xffffffffU, -/*03cb*/ 0x100602a0U, -/*03cc*/ 0x180802a0U, -/*03cd*/ 0xffffffffU, -/*03ce*/ 0x000802a1U, -/*03cf*/ 0x080802a1U, -/*03d0*/ 0x100802a1U, -/*03d1*/ 0x180602a1U, -/*03d2*/ 0x000602a2U, -/*03d3*/ 0x081102a2U, -/*03d4*/ 0x000802a3U, -/*03d5*/ 0x080402a3U, -/*03d6*/ 0x100602a3U, -/*03d7*/ 0xffffffffU, -/*03d8*/ 0x180602a3U, -/*03d9*/ 0x000802a4U, -/*03da*/ 0xffffffffU, -/*03db*/ 0x080802a4U, -/*03dc*/ 0x100802a4U, -/*03dd*/ 0x180802a4U, -/*03de*/ 0x000602a5U, -/*03df*/ 0x080602a5U, -/*03e0*/ 0x001102a6U, -/*03e1*/ 0x180802a6U, -/*03e2*/ 0x000402a7U, -/*03e3*/ 0x080602a7U, -/*03e4*/ 0xffffffffU, -/*03e5*/ 0x100602a7U, -/*03e6*/ 0x180802a7U, -/*03e7*/ 0xffffffffU, -/*03e8*/ 0x000402a8U, -/*03e9*/ 0x080402a8U, -/*03ea*/ 0x100402a8U, -/*03eb*/ 0x180402a8U, -/*03ec*/ 0x000402a9U, -/*03ed*/ 0x080402a9U, -/*03ee*/ 0x100402a9U, -/*03ef*/ 0x180402a9U, -/*03f0*/ 0x000402aaU, -/*03f1*/ 0x080402aaU, -/*03f2*/ 0x100402aaU, -/*03f3*/ 0x180402aaU, -/*03f4*/ 0x000402abU, -/*03f5*/ 0x080402abU, -/*03f6*/ 0x100402abU, -/*03f7*/ 0x180402abU, -/*03f8*/ 0x000402acU, -/*03f9*/ 0x080402acU, -/*03fa*/ 0x100402acU, -/*03fb*/ 0x180402acU, -/*03fc*/ 0x001202adU, -/*03fd*/ 0x001102aeU, -/*03fe*/ 0x001202afU, -/*03ff*/ 0x002002b0U, -/*0400*/ 0x002002b1U, -/*0401*/ 0x002002b2U, -/*0402*/ 0x002002b3U, -/*0403*/ 0x002002b4U, -/*0404*/ 0x002002b5U, -/*0405*/ 0x002002b6U, -/*0406*/ 0x002002b7U, -/*0407*/ 0x002002b8U, -/*0408*/ 0x000202b9U, -/*0409*/ 0x080502b9U, -/*040a*/ 0x100502b9U, -/*040b*/ 0x180102b9U, -/*040c*/ 0x000402baU, -/*040d*/ 0x080402baU, -/*040e*/ 0x100402baU, -/*040f*/ 0x180402baU, -/*0410*/ 0x000402bbU, -/*0411*/ 0x080402bbU, -/*0412*/ 0x100402bbU, -/*0413*/ 0x180402bbU, -/*0414*/ 0xffffffffU, -/*0415*/ 0xffffffffU, -/*0416*/ 0xffffffffU, -/*0417*/ 0xffffffffU, -/*0418*/ 0xffffffffU, -/*0419*/ 0xffffffffU, -/*041a*/ 0x000402bcU, -/*041b*/ 0x080402bcU, -/*041c*/ 0x100402bcU, -/*041d*/ 0x180402bcU, -/*041e*/ 0x000402bdU, -/*041f*/ 0x080402bdU, -/*0420*/ 0x100402bdU, -/*0421*/ 0x180402bdU, -/*0422*/ 0x000102beU, -/*0423*/ 0x080202beU, -/*0424*/ 0x100202beU, -/*0425*/ 0x180202beU, -/*0426*/ 0x000202bfU, -/*0427*/ 0x080102bfU, -/*0428*/ 0x100402bfU, -/*0429*/ 0x001002c0U, -/*042a*/ 0x002002c1U, -/*042b*/ 0x001002c2U, -/*042c*/ 0x002002c3U, -/*042d*/ 0x001002c4U, -/*042e*/ 0x002002c5U, -/*042f*/ 0x000702c6U, -/*0430*/ 0x080102c6U, -/*0431*/ 0x100202c6U, -/*0432*/ 0x180602c6U, -/*0433*/ 0x000102c7U, -/*0434*/ 0x080102c7U, -/*0435*/ 0x002002c8U, -/*0436*/ 0x000202c9U, -/*0437*/ 0x002002caU, -/*0438*/ 0x002002cbU, -/*0439*/ 0x000c02ccU, -/*043a*/ 0x100c02ccU, -/*043b*/ 0x002002cdU, -/*043c*/ 0x000302ceU, -/*043d*/ 0x002002cfU, -/*043e*/ 0x000302d0U, -/*043f*/ 0x002002d1U, -/*0440*/ 0x000302d2U, -/*0441*/ 0x002002d3U, -/*0442*/ 0x000302d4U, -/*0443*/ 0x002002d5U, -/*0444*/ 0x000302d6U, -/*0445*/ 0x002002d7U, -/*0446*/ 0x000302d8U, -/*0447*/ 0x002002d9U, -/*0448*/ 0x000302daU, -/*0449*/ 0x002002dbU, -/*044a*/ 0x000302dcU, -/*044b*/ 0x002002ddU, -/*044c*/ 0x000302deU, -/*044d*/ 0x002002dfU, -/*044e*/ 0x000302e0U, -/*044f*/ 0x080302e0U, -/*0450*/ 0x100202e0U, -/*0451*/ 0x180202e0U, -/*0452*/ 0x002002e1U, -/*0453*/ 0x002002e2U, -/*0454*/ 0x002002e3U, -/*0455*/ 0x002002e4U, -/*0456*/ 0x000402e5U, -/*0457*/ 0x001e02e6U, -/*0458*/ 0x001e02e7U, -/*0459*/ 0x001e02e8U, -/*045a*/ 0x001e02e9U, -/*045b*/ 0x001e02eaU, -/*045c*/ 0x001e02ebU, -/*045d*/ 0x001e02ecU, -/*045e*/ 0x001e02edU, -/*045f*/ 0x000402eeU, -/*0460*/ 0xffffffffU, -/*0461*/ 0xffffffffU, -/*0462*/ 0xffffffffU, -/*0463*/ 0xffffffffU, -/*0464*/ 0x080402eeU, -/*0465*/ 0x100102eeU, -/*0466*/ 0x180802eeU, -/*0467*/ 0x000402efU, -/*0468*/ 0x080102efU, -/*0469*/ 0x100802efU, -/*046a*/ 0x180402efU, -/*046b*/ 0x000102f0U, -/*046c*/ 0x080802f0U, -/*046d*/ 0x100402f0U, -/*046e*/ 0x180102f0U, -/*046f*/ 0x000802f1U, -/*0470*/ 0x080402f1U, -/*0471*/ 0x100102f1U, -/*0472*/ 0x180802f1U, -/*0473*/ 0x000402f2U, -/*0474*/ 0x080102f2U, -/*0475*/ 0x100802f2U, -/*0476*/ 0x180402f2U, -/*0477*/ 0x000102f3U, -/*0478*/ 0x080802f3U, -/*0479*/ 0x100402f3U, -/*047a*/ 0x180102f3U, -/*047b*/ 0x000802f4U, -/*047c*/ 0x080802f4U, -/*047d*/ 0x100102f4U, -/*047e*/ 0x180502f4U, -/*047f*/ 0xffffffffU, -/*0480*/ 0xffffffffU, -/*0481*/ 0xffffffffU, -/*0482*/ 0xffffffffU, -/*0483*/ 0xffffffffU, -/*0484*/ 0xffffffffU, -/*0485*/ 0xffffffffU, -/*0486*/ 0xffffffffU, -/*0487*/ 0xffffffffU, -/*0488*/ 0xffffffffU, -/*0489*/ 0xffffffffU, -/*048a*/ 0xffffffffU, -/*048b*/ 0xffffffffU, -/*048c*/ 0xffffffffU, -/*048d*/ 0xffffffffU, -/*048e*/ 0xffffffffU, -/*048f*/ 0xffffffffU, -/*0490*/ 0xffffffffU, -/*0491*/ 0xffffffffU, -/*0492*/ 0xffffffffU, -/*0493*/ 0xffffffffU, -/*0494*/ 0xffffffffU, - }, - { -/*0000*/ 0x00200800U, -/*0001*/ 0x00040801U, -/*0002*/ 0x080b0801U, -/*0003*/ 0x000a0802U, -/*0004*/ 0x10020802U, -/*0005*/ 0x18010802U, -/*0006*/ 0x00060803U, -/*0007*/ 0x08060803U, -/*0008*/ 0x10060803U, -/*0009*/ 0x18060803U, -/*000a*/ 0x00060804U, -/*000b*/ 0x08060804U, -/*000c*/ 0x10050804U, -/*000d*/ 0x18060804U, -/*000e*/ 0x00060805U, -/*000f*/ 0x08040805U, -/*0010*/ 0x10030805U, -/*0011*/ 0x00180806U, -/*0012*/ 0x18030806U, -/*0013*/ 0x00180807U, -/*0014*/ 0x18020807U, -/*0015*/ 0x0801085eU, -/*0016*/ 0x00020808U, -/*0017*/ 0x08010808U, -/*0018*/ 0x10010808U, -/*0019*/ 0x18020808U, -/*001a*/ 0x00050809U, -/*001b*/ 0x08050809U, -/*001c*/ 0x10040809U, -/*001d*/ 0xffffffffU, -/*001e*/ 0x18040809U, -/*001f*/ 0x0002080aU, -/*0020*/ 0x0805080aU, -/*0021*/ 0x1009080aU, -/*0022*/ 0x0001080bU, -/*0023*/ 0x0020080cU, -/*0024*/ 0x001c080dU, -/*0025*/ 0x0001080eU, -/*0026*/ 0x0807080eU, -/*0027*/ 0x1009080eU, -/*0028*/ 0x000a080fU, -/*0029*/ 0x1005080fU, -/*002a*/ 0x1801080fU, -/*002b*/ 0x10010810U, -/*002c*/ 0x18020810U, -/*002d*/ 0x00090810U, -/*002e*/ 0x00090811U, -/*002f*/ 0x10020811U, -/*0030*/ 0x00200812U, -/*0031*/ 0x00010813U, -/*0032*/ 0x08020813U, -/*0033*/ 0x00200814U, -/*0034*/ 0x00200815U, -/*0035*/ 0x00200816U, -/*0036*/ 0x00200817U, -/*0037*/ 0xffffffffU, -/*0038*/ 0xffffffffU, -/*0039*/ 0xffffffffU, -/*003a*/ 0xffffffffU, -/*003b*/ 0x00030818U, -/*003c*/ 0x08010818U, -/*003d*/ 0x10040818U, -/*003e*/ 0x18030818U, -/*003f*/ 0x00040819U, -/*0040*/ 0x08040819U, -/*0041*/ 0x10040819U, -/*0042*/ 0x18040819U, -/*0043*/ 0x0001081aU, -/*0044*/ 0x0801081aU, -/*0045*/ 0x1006081aU, -/*0046*/ 0x1804081aU, -/*0047*/ 0x0008081bU, -/*0048*/ 0x0806081bU, -/*0049*/ 0x1004081bU, -/*004a*/ 0x1806081bU, -/*004b*/ 0x0004081cU, -/*004c*/ 0x0802081cU, -/*004d*/ 0x1005081cU, -/*004e*/ 0x1808081cU, -/*004f*/ 0xffffffffU, -/*0050*/ 0x0006081dU, -/*0051*/ 0x0803081dU, -/*0052*/ 0x100b081dU, -/*0053*/ 0x0004081eU, -/*0054*/ 0x0804081eU, -/*0055*/ 0x1004081eU, -/*0056*/ 0x1801081eU, -/*0057*/ 0xffffffffU, -/*0058*/ 0x0009081fU, -/*0059*/ 0x00200820U, -/*005a*/ 0x00200821U, -/*005b*/ 0x00200822U, -/*005c*/ 0x00200823U, -/*005d*/ 0x00100824U, -/*005e*/ 0xffffffffU, -/*005f*/ 0x10010824U, -/*0060*/ 0x18060824U, -/*0061*/ 0x00080825U, -/*0062*/ 0x00200826U, -/*0063*/ 0x00100827U, -/*0064*/ 0x100b0827U, -/*0065*/ 0x00070828U, -/*0066*/ 0x08070828U, -/*0067*/ 0x10090828U, -/*0068*/ 0x00090829U, -/*0069*/ 0x100b0829U, -/*006a*/ 0x0007082aU, -/*006b*/ 0x0808082aU, -/*006c*/ 0x1009082aU, -/*006d*/ 0x0003082bU, -/*006e*/ 0x080a082bU, -/*006f*/ 0x000a082cU, -/*0070*/ 0x0011082dU, -/*0071*/ 0x000a082eU, -/*0072*/ 0x100a082eU, -/*0073*/ 0x0010082fU, -/*0074*/ 0x100e082fU, -/*0075*/ 0x000e0830U, -/*0076*/ 0x00120831U, -/*0077*/ 0x000a0832U, -/*0078*/ 0x100a0832U, -/*0079*/ 0x00020833U, -/*007a*/ 0x00200834U, -/*007b*/ 0x000b0835U, -/*007c*/ 0x100b0835U, -/*007d*/ 0x00200836U, -/*007e*/ 0x00130837U, -/*007f*/ 0x00200838U, -/*0080*/ 0x00200839U, -/*0081*/ 0x0008083aU, -/*0082*/ 0x0801083aU, -/*0083*/ 0x1001083aU, -/*0084*/ 0x1801083aU, -/*0085*/ 0x0008083bU, -/*0086*/ 0x080c083bU, -/*0087*/ 0x000c083cU, -/*0088*/ 0x100c083cU, -/*0089*/ 0x000c083dU, -/*008a*/ 0x100c083dU, -/*008b*/ 0x000c083eU, -/*008c*/ 0x100c083eU, -/*008d*/ 0x000c083fU, -/*008e*/ 0x100c083fU, -/*008f*/ 0x000c0840U, -/*0090*/ 0x100c0840U, -/*0091*/ 0x000b0841U, -/*0092*/ 0x10090841U, -/*0093*/ 0x00010842U, -/*0094*/ 0x000b0843U, -/*0095*/ 0x100b0843U, -/*0096*/ 0x000b0844U, -/*0097*/ 0x100b0844U, -/*0098*/ 0x000b0845U, -/*0099*/ 0x100b0845U, -/*009a*/ 0x000b0846U, -/*009b*/ 0x100b0846U, -/*009c*/ 0x000b0847U, -/*009d*/ 0x100a0847U, -/*009e*/ 0x00020848U, -/*009f*/ 0x080a0848U, -/*00a0*/ 0x000a0849U, -/*00a1*/ 0x100a0849U, -/*00a2*/ 0x000a084aU, -/*00a3*/ 0x100a084aU, -/*00a4*/ 0x000a084bU, -/*00a5*/ 0x100a084bU, -/*00a6*/ 0x000a084cU, -/*00a7*/ 0x100a084cU, -/*00a8*/ 0x000a084dU, -/*00a9*/ 0x100a084dU, -/*00aa*/ 0x000a084eU, -/*00ab*/ 0x100a084eU, -/*00ac*/ 0x000a084fU, -/*00ad*/ 0x100a084fU, -/*00ae*/ 0x000a0850U, -/*00af*/ 0x100a0850U, -/*00b0*/ 0x000a0851U, -/*00b1*/ 0x100a0851U, -/*00b2*/ 0x000a0852U, -/*00b3*/ 0x100a0852U, -/*00b4*/ 0x000a0853U, -/*00b5*/ 0x100a0853U, -/*00b6*/ 0x000a0854U, -/*00b7*/ 0x100a0854U, -/*00b8*/ 0x000a0855U, -/*00b9*/ 0x100a0855U, -/*00ba*/ 0x000a0856U, -/*00bb*/ 0x10040856U, -/*00bc*/ 0x18030856U, -/*00bd*/ 0x000a0857U, -/*00be*/ 0x100a0857U, -/*00bf*/ 0x00010858U, -/*00c0*/ 0x080a0858U, -/*00c1*/ 0x18040858U, -/*00c2*/ 0x000b0859U, -/*00c3*/ 0x100a0859U, -/*00c4*/ 0x0003085aU, -/*00c5*/ 0x0008085bU, -/*00c6*/ 0x0808085bU, -/*00c7*/ 0x1008085bU, -/*00c8*/ 0x1808085bU, -/*00c9*/ 0x0008085cU, -/*00ca*/ 0x0808085cU, -/*00cb*/ 0x1008085cU, -/*00cc*/ 0x1801085cU, -/*00cd*/ 0x0008085dU, -/*00ce*/ 0x0808085dU, -/*00cf*/ 0x1002085dU, -/*00d0*/ 0x1802085dU, -/*00d1*/ 0x0005085eU, -/*00d2*/ 0x1005085eU, -/*00d3*/ 0x1805085eU, -/*00d4*/ 0x0004085fU, -/*00d5*/ 0x080b085fU, -/*00d6*/ 0x1806085fU, -/*00d7*/ 0x00080860U, -/*00d8*/ 0x08080860U, -/*00d9*/ 0x10040860U, -/*00da*/ 0x18040860U, -/*00db*/ 0x00060861U, -/*00dc*/ 0x08040861U, -/*00dd*/ 0x10050861U, -/*00de*/ 0x000a0862U, -/*00df*/ 0x100a0862U, -/*00e0*/ 0x00080863U, -/*00e1*/ 0x08010863U, -/*00e2*/ 0x10040863U, -/*00e3*/ 0x00020864U, -/*00e4*/ 0x08030864U, -/*00e5*/ 0x00050a00U, -/*00e6*/ 0x08050a00U, -/*00e7*/ 0x10050a00U, -/*00e8*/ 0x18050a00U, -/*00e9*/ 0x00050a01U, -/*00ea*/ 0x08050a01U, -/*00eb*/ 0x100b0a01U, -/*00ec*/ 0x00010a02U, -/*00ed*/ 0x08030a02U, -/*00ee*/ 0x00200a03U, -/*00ef*/ 0x00100a04U, -/*00f0*/ 0x10040a04U, -/*00f1*/ 0x000b0a05U, -/*00f2*/ 0x10070a05U, -/*00f3*/ 0x00090a06U, -/*00f4*/ 0x10030a06U, -/*00f5*/ 0x18030a06U, -/*00f6*/ 0x00010a07U, -/*00f7*/ 0x08010a07U, -/*00f8*/ 0x10070a07U, -/*00f9*/ 0x18070a07U, -/*00fa*/ 0x00050a08U, -/*00fb*/ 0x08010a08U, -/*00fc*/ 0x10020a08U, -/*00fd*/ 0x18030a08U, -/*00fe*/ 0x00010a09U, -/*00ff*/ 0x080f0a09U, -/*0100*/ 0x00200a0aU, -/*0101*/ 0x00200a0bU, -/*0102*/ 0x000b0a0cU, -/*0103*/ 0x100b0a0cU, -/*0104*/ 0x000b0a0dU, -/*0105*/ 0x00180a0eU, -/*0106*/ 0x00180a0fU, -/*0107*/ 0xffffffffU, -/*0108*/ 0xffffffffU, -/*0109*/ 0xffffffffU, -/*010a*/ 0xffffffffU, -/*010b*/ 0xffffffffU, -/*010c*/ 0x18020a0fU, -/*010d*/ 0x00020a10U, -/*010e*/ 0x08040a10U, -/*010f*/ 0x10040a10U, -/*0110*/ 0x18010a10U, -/*0111*/ 0x00010a11U, -/*0112*/ 0x08010a11U, -/*0113*/ 0x10030a11U, -/*0114*/ 0x00200a12U, -/*0115*/ 0x00200a13U, -/*0116*/ 0xffffffffU, -/*0117*/ 0x00140a14U, -/*0118*/ 0x00140a15U, -/*0119*/ 0x00140a16U, -/*011a*/ 0x00140a17U, -/*011b*/ 0x00140a18U, -/*011c*/ 0x00140a19U, -/*011d*/ 0x00140a1aU, -/*011e*/ 0x00140a1bU, -/*011f*/ 0x001e0a1cU, -/*0120*/ 0x000a0a1dU, -/*0121*/ 0x10060a1dU, -/*0122*/ 0x18060a1dU, -/*0123*/ 0x00060a1eU, -/*0124*/ 0x08060a1eU, -/*0125*/ 0x10060a1eU, -/*0126*/ 0x00080a1fU, -/*0127*/ 0x080b0a1fU, -/*0128*/ 0x000b0a20U, -/*0129*/ 0x100b0a20U, -/*012a*/ 0x000b0a21U, -/*012b*/ 0x100b0a21U, -/*012c*/ 0x000b0a22U, -/*012d*/ 0x10040a22U, -/*012e*/ 0x000b0a23U, -/*012f*/ 0x10060a23U, -/*0130*/ 0x18080a23U, -/*0131*/ 0x00080a24U, -/*0132*/ 0x08040a24U, -/*0133*/ 0x00020b80U, -/*0134*/ 0x00010b81U, -/*0135*/ 0x08010b81U, -/*0136*/ 0x10020b81U, -/*0137*/ 0x18050b81U, -/*0138*/ 0x00050b82U, -/*0139*/ 0x08050b82U, -/*013a*/ 0x10050b82U, -/*013b*/ 0x000b0b83U, -/*013c*/ 0x10050b83U, -/*013d*/ 0x18010b83U, -/*013e*/ 0x00010b84U, -/*013f*/ 0x08010b84U, -/*0140*/ 0x10010b84U, -/*0141*/ 0x18010b84U, -/*0142*/ 0x00040b85U, -/*0143*/ 0x080b0b85U, -/*0144*/ 0x000b0b86U, -/*0145*/ 0x100b0b86U, -/*0146*/ 0x00040b87U, -/*0147*/ 0x080b0b87U, -/*0148*/ 0x18040b87U, -/*0149*/ 0x00010b88U, -/*014a*/ 0x08010b88U, -/*014b*/ 0x10010b88U, -/*014c*/ 0x00200b89U, -/*014d*/ 0x00200b8aU, -/*014e*/ 0x00080b8bU, -/*014f*/ 0x080a0b8bU, -/*0150*/ 0x18050b8bU, -/*0151*/ 0x000b0b8cU, -/*0152*/ 0x10030b8cU, -/*0153*/ 0x18030b8cU, -/*0154*/ 0x00010b8dU, -/*0155*/ 0x08020b8dU, -/*0156*/ 0x10010b8dU, -/*0157*/ 0x18010b8dU, -/*0158*/ 0x00010b8eU, -/*0159*/ 0xffffffffU, -/*015a*/ 0x08010b8eU, -/*015b*/ 0x18040b8eU, -/*015c*/ 0x00040b8fU, -/*015d*/ 0x08040b8fU, -/*015e*/ 0x10040b8fU, -/*015f*/ 0x18010b8fU, -/*0160*/ 0x00010b90U, -/*0161*/ 0x08010b90U, -/*0162*/ 0x00200b91U, -/*0163*/ 0x00200b92U, -/*0164*/ 0x00200b93U, -/*0165*/ 0x00200b94U, -/*0166*/ 0xffffffffU, -/*0167*/ 0x10010b8eU, -/*0168*/ 0x000d0b96U, -/*0169*/ 0x100d0b96U, -/*016a*/ 0x000d0b97U, -/*016b*/ 0x00050b98U, -/*016c*/ 0x00010b99U, -/*016d*/ 0x080e0b99U, -/*016e*/ 0x000e0b9aU, -/*016f*/ 0x100e0b9aU, -/*0170*/ 0x000e0b9bU, -/*0171*/ 0x100e0b9bU, -/*0172*/ 0x00040b9cU, -/*0173*/ 0x08040b9cU, -/*0174*/ 0x10040b9cU, -/*0175*/ 0x18040b9cU, -/*0176*/ 0x00040b9dU, -/*0177*/ 0x080b0b9dU, -/*0178*/ 0x000b0b9eU, -/*0179*/ 0x100b0b9eU, -/*017a*/ 0x000b0b9fU, -/*017b*/ 0x00040ba0U, -/*017c*/ 0x08040ba0U, -/*017d*/ 0x10040ba0U, -/*017e*/ 0x18040ba0U, -/*017f*/ 0x000d0ba1U, -/*0180*/ 0x100d0ba1U, -/*0181*/ 0x000d0ba2U, -/*0182*/ 0x10100ba2U, -/*0183*/ 0x00080b95U, -/*0184*/ 0x08080b95U, -/*0185*/ 0x00100ba3U, -/*0186*/ 0x10100ba3U, -/*0187*/ 0x00100ba4U, -/*0188*/ 0x10100ba4U, -/*0189*/ 0x00100ba5U, -/*018a*/ 0x10030ba5U, -/*018b*/ 0x18040ba5U, -/*018c*/ 0x00010ba6U, -/*018d*/ 0x08080ba6U, -/*018e*/ 0x10010ba6U, -/*018f*/ 0x000a0ba7U, -/*0190*/ 0x10010ba7U, -/*0191*/ 0x00140ba8U, -/*0192*/ 0x000b0ba9U, -/*0193*/ 0x100c0ba9U, -/*0194*/ 0x00120baaU, -/*0195*/ 0x00140babU, -/*0196*/ 0x00120bacU, -/*0197*/ 0x00110badU, -/*0198*/ 0x00110baeU, -/*0199*/ 0x00120bafU, -/*019a*/ 0x00120bb0U, -/*019b*/ 0x00120bb1U, -/*019c*/ 0x00120bb2U, -/*019d*/ 0x00120bb3U, -/*019e*/ 0x00120bb4U, -/*019f*/ 0x00120bb5U, -/*01a0*/ 0x00120bb6U, -/*01a1*/ 0x00120bb7U, -/*01a2*/ 0x00120bb8U, -/*01a3*/ 0x000e0bb9U, -/*01a4*/ 0x100d0bb9U, -/*01a5*/ 0x00200bbaU, -/*01a6*/ 0x00170bbbU, -/*01a7*/ 0x000d0bbcU, -/*01a8*/ 0x10010bbcU, -/*01a9*/ 0x18010bbcU, -/*01aa*/ 0x00200bbdU, -/*01ab*/ 0x00080bbeU, -/*01ac*/ 0x08030bbeU, -/*01ad*/ 0x10030bbeU, -/*01ae*/ 0x00180bbfU, -/*01af*/ 0x00180bc0U, -/*01b0*/ 0x18070bc0U, -/*01b1*/ 0x00070bc1U, -/*01b2*/ 0x08080bc1U, -/*01b3*/ 0x10080bc1U, -/*01b4*/ 0x18080bc1U, -/*01b5*/ 0x00010bc2U, -/*01b6*/ 0x08010bc2U, -/*01b7*/ 0x00200bc3U, -/*01b8*/ 0x00070bc4U, -/*01b9*/ 0x08140bc4U, -/*01ba*/ 0x00140bc5U, -/*01bb*/ 0x00190bc6U, -/*01bc*/ 0x00170bc7U, -/*01bd*/ 0x00110bc8U, -/*01be*/ 0x00110bc9U, -/*01bf*/ 0x00100bcaU, -/*01c0*/ 0x10010bcaU, -/*01c1*/ 0x18010bcaU, -/*01c2*/ 0x00020bcbU, -/*01c3*/ 0x08040bcbU, -/*01c4*/ 0x10090bcbU, -/*01c5*/ 0x00070bccU, -/*01c6*/ 0x08040bccU, -/*01c7*/ 0x00200bcdU, -/*01c8*/ 0x00010bceU, -/*01c9*/ 0x08020bceU, -/*01ca*/ 0x10060bceU, -/*01cb*/ 0x00100bcfU, -/*01cc*/ 0x10010bcfU, -/*01cd*/ 0x00200bd0U, -/*01ce*/ 0x00080bd1U, -/*01cf*/ 0x08010bd1U, -/*01d0*/ 0x10050bd1U, -/*01d1*/ 0x18030bd1U, -/*01d2*/ 0x00020bd2U, -/*01d3*/ 0xffffffffU, -/*01d4*/ 0x00200bd3U, -/*01d5*/ 0x000b0bd4U, -/*01d6*/ 0xffffffffU, -/*01d7*/ 0x10030bd4U, -/*01d8*/ 0x18080bd4U, -/*01d9*/ 0x00020bd5U, -/*01da*/ 0x080c0bd5U, -/*01db*/ 0x18040bd5U, -/*01dc*/ 0x00010bd6U, -/*01dd*/ 0x08050bd6U, -/*01de*/ 0x00010200U, -/*01df*/ 0x08040200U, -/*01e0*/ 0x10100200U, -/*01e1*/ 0x00010201U, -/*01e2*/ 0x08010201U, -/*01e3*/ 0x10010201U, -/*01e4*/ 0x18010201U, -/*01e5*/ 0x00100202U, -/*01e6*/ 0x10080202U, -/*01e7*/ 0x18010202U, -/*01e8*/ 0x00200203U, -/*01e9*/ 0x00200204U, -/*01ea*/ 0x00200205U, -/*01eb*/ 0x00200206U, -/*01ec*/ 0x00020207U, -/*01ed*/ 0x08010207U, -/*01ee*/ 0x10010207U, -/*01ef*/ 0x00200208U, -/*01f0*/ 0x00140209U, -/*01f1*/ 0x0020020aU, -/*01f2*/ 0x0014020bU, -/*01f3*/ 0x0020020cU, -/*01f4*/ 0x0014020dU, -/*01f5*/ 0x0014020eU, -/*01f6*/ 0x0020020fU, -/*01f7*/ 0x00200210U, -/*01f8*/ 0x00200211U, -/*01f9*/ 0x00200212U, -/*01fa*/ 0x00140213U, -/*01fb*/ 0x00200214U, -/*01fc*/ 0x00200215U, -/*01fd*/ 0x00200216U, -/*01fe*/ 0x00200217U, -/*01ff*/ 0x00140218U, -/*0200*/ 0x00200219U, -/*0201*/ 0x0020021aU, -/*0202*/ 0x0020021bU, -/*0203*/ 0x0020021cU, -/*0204*/ 0x0009021dU, -/*0205*/ 0x1001021dU, -/*0206*/ 0x0020021eU, -/*0207*/ 0x0005021fU, -/*0208*/ 0x0801021fU, -/*0209*/ 0x1008021fU, -/*020a*/ 0x1808021fU, -/*020b*/ 0x001e0220U, -/*020c*/ 0x001e0221U, -/*020d*/ 0x001e0222U, -/*020e*/ 0x001e0223U, -/*020f*/ 0x001e0224U, -/*0210*/ 0x001e0225U, -/*0211*/ 0x001e0226U, -/*0212*/ 0x001e0227U, -/*0213*/ 0x001e0228U, -/*0214*/ 0x001e0229U, -/*0215*/ 0x001e022aU, -/*0216*/ 0x001e022bU, -/*0217*/ 0x001e022cU, -/*0218*/ 0x001e022dU, -/*0219*/ 0x001e022eU, -/*021a*/ 0x001e022fU, -/*021b*/ 0x00010230U, -/*021c*/ 0x08010230U, -/*021d*/ 0x10010230U, -/*021e*/ 0x18040230U, -/*021f*/ 0x00080231U, -/*0220*/ 0x08080231U, -/*0221*/ 0x10080231U, -/*0222*/ 0x18040231U, -/*0223*/ 0x00070232U, -/*0224*/ 0x08060232U, -/*0225*/ 0x10070232U, -/*0226*/ 0x18070232U, -/*0227*/ 0x00060233U, -/*0228*/ 0x08070233U, -/*0229*/ 0x10070233U, -/*022a*/ 0x18060233U, -/*022b*/ 0x00070234U, -/*022c*/ 0x08020234U, -/*022d*/ 0x10010234U, -/*022e*/ 0x18010234U, -/*022f*/ 0x000a0235U, -/*0230*/ 0x00140236U, -/*0231*/ 0x000a0237U, -/*0232*/ 0x00140238U, -/*0233*/ 0x000a0239U, -/*0234*/ 0x0014023aU, -/*0235*/ 0xffffffffU, -/*0236*/ 0xffffffffU, -/*0237*/ 0x0005023bU, -/*0238*/ 0x0001023cU, -/*0239*/ 0x1001023cU, -/*023a*/ 0x1801023cU, -/*023b*/ 0x0001023dU, -/*023c*/ 0x0801023dU, -/*023d*/ 0x1001023dU, -/*023e*/ 0x1801023dU, -/*023f*/ 0x0002023eU, -/*0240*/ 0x0802023eU, -/*0241*/ 0x1002023eU, -/*0242*/ 0x1802023eU, -/*0243*/ 0x0002023fU, -/*0244*/ 0x0803023fU, -/*0245*/ 0x1001023fU, -/*0246*/ 0x1801023fU, -/*0247*/ 0x00010240U, -/*0248*/ 0x08010240U, -/*0249*/ 0x10010240U, -/*024a*/ 0x18020240U, -/*024b*/ 0x00010241U, -/*024c*/ 0x08010241U, -/*024d*/ 0x10010241U, -/*024e*/ 0x18020241U, -/*024f*/ 0x00010242U, -/*0250*/ 0x08010242U, -/*0251*/ 0x10010242U, -/*0252*/ 0x18020242U, -/*0253*/ 0x00010243U, -/*0254*/ 0x08010243U, -/*0255*/ 0x10010243U, -/*0256*/ 0x18020243U, -/*0257*/ 0xffffffffU, -/*0258*/ 0x00010244U, -/*0259*/ 0x08010244U, -/*025a*/ 0x10010244U, -/*025b*/ 0x18010244U, -/*025c*/ 0x00010245U, -/*025d*/ 0x08010245U, -/*025e*/ 0x10010245U, -/*025f*/ 0x18010245U, -/*0260*/ 0x00040246U, -/*0261*/ 0x08040246U, -/*0262*/ 0x10040246U, -/*0263*/ 0x18010246U, -/*0264*/ 0x00020247U, -/*0265*/ 0x08060247U, -/*0266*/ 0x10060247U, -/*0267*/ 0x18020247U, -/*0268*/ 0x00020248U, -/*0269*/ 0x08020248U, -/*026a*/ 0xffffffffU, -/*026b*/ 0x10100248U, -/*026c*/ 0x00010249U, -/*026d*/ 0x08010249U, -/*026e*/ 0x10010249U, -/*026f*/ 0x18040249U, -/*0270*/ 0x0001024aU, -/*0271*/ 0x0804024aU, -/*0272*/ 0x1003024aU, -/*0273*/ 0x1808024aU, -/*0274*/ 0x000a024bU, -/*0275*/ 0x100a024bU, -/*0276*/ 0x000a024cU, -/*0277*/ 0xffffffffU, -/*0278*/ 0x0020024dU, -/*0279*/ 0x0020024eU, -/*027a*/ 0x0005024fU, -/*027b*/ 0x1801023aU, -/*027c*/ 0x0805023cU, -/*027d*/ 0x0808024fU, -/*027e*/ 0x1001024fU, -/*027f*/ 0x1808024fU, -/*0280*/ 0x00010250U, -/*0281*/ 0x08080250U, -/*0282*/ 0x10010250U, -/*0283*/ 0x18040250U, -/*0284*/ 0x00040251U, -/*0285*/ 0x08040251U, -/*0286*/ 0x10040251U, -/*0287*/ 0x18040251U, -/*0288*/ 0x00040252U, -/*0289*/ 0x08040252U, -/*028a*/ 0x10040252U, -/*028b*/ 0x18040252U, -/*028c*/ 0x00040253U, -/*028d*/ 0x08010253U, -/*028e*/ 0x10040253U, -/*028f*/ 0x18040253U, -/*0290*/ 0x00040254U, -/*0291*/ 0x08040254U, -/*0292*/ 0x10040254U, -/*0293*/ 0x18040254U, -/*0294*/ 0x00060255U, -/*0295*/ 0x08060255U, -/*0296*/ 0x10060255U, -/*0297*/ 0x18060255U, -/*0298*/ 0x00060256U, -/*0299*/ 0x08060256U, -/*029a*/ 0x10040256U, -/*029b*/ 0x18010256U, -/*029c*/ 0x00010257U, -/*029d*/ 0x08020257U, -/*029e*/ 0x00200258U, -/*029f*/ 0x00200259U, -/*02a0*/ 0x0020025aU, -/*02a1*/ 0x0020025bU, -/*02a2*/ 0x0020025cU, -/*02a3*/ 0x0020025dU, -/*02a4*/ 0x0020025eU, -/*02a5*/ 0x0020025fU, -/*02a6*/ 0x00040260U, -/*02a7*/ 0x08040260U, -/*02a8*/ 0x10010260U, -/*02a9*/ 0x18010260U, -/*02aa*/ 0x00010261U, -/*02ab*/ 0x08010261U, -/*02ac*/ 0x10010261U, -/*02ad*/ 0x18010261U, -/*02ae*/ 0x00010262U, -/*02af*/ 0x08010262U, -/*02b0*/ 0x10010262U, -/*02b1*/ 0x18040262U, -/*02b2*/ 0x00040263U, -/*02b3*/ 0x080a0263U, -/*02b4*/ 0x00200264U, -/*02b5*/ 0x00040265U, -/*02b6*/ 0x08080265U, -/*02b7*/ 0x10020265U, -/*02b8*/ 0x18020265U, -/*02b9*/ 0x00020266U, -/*02ba*/ 0x08020266U, -/*02bb*/ 0x10020266U, -/*02bc*/ 0x18020266U, -/*02bd*/ 0xffffffffU, -/*02be*/ 0xffffffffU, -/*02bf*/ 0x00200267U, -/*02c0*/ 0x00030268U, -/*02c1*/ 0x08100268U, -/*02c2*/ 0x00100269U, -/*02c3*/ 0x10040269U, -/*02c4*/ 0x18040269U, -/*02c5*/ 0x0005026aU, -/*02c6*/ 0x0805026aU, -/*02c7*/ 0xffffffffU, -/*02c8*/ 0xffffffffU, -/*02c9*/ 0xffffffffU, -/*02ca*/ 0xffffffffU, -/*02cb*/ 0x1001026aU, -/*02cc*/ 0x1801026aU, -/*02cd*/ 0x0008026bU, -/*02ce*/ 0x0808026bU, -/*02cf*/ 0x1008026bU, -/*02d0*/ 0x1808026bU, -/*02d1*/ 0x0008026cU, -/*02d2*/ 0x0808026cU, -/*02d3*/ 0x1008026cU, -/*02d4*/ 0x1808026cU, -/*02d5*/ 0x0008026dU, -/*02d6*/ 0x0808026dU, -/*02d7*/ 0x1008026dU, -/*02d8*/ 0x1808026dU, -/*02d9*/ 0x0008026eU, -/*02da*/ 0x0808026eU, -/*02db*/ 0x1003026eU, -/*02dc*/ 0x1803026eU, -/*02dd*/ 0x0003026fU, -/*02de*/ 0xffffffffU, -/*02df*/ 0x0801026fU, -/*02e0*/ 0x1002026fU, -/*02e1*/ 0x1801026fU, -/*02e2*/ 0x00040270U, -/*02e3*/ 0x08020270U, -/*02e4*/ 0x10010270U, -/*02e5*/ 0x18010270U, -/*02e6*/ 0x00010271U, -/*02e7*/ 0x08010271U, -/*02e8*/ 0x10040271U, -/*02e9*/ 0x18080271U, -/*02ea*/ 0x000a0272U, -/*02eb*/ 0x100a0272U, -/*02ec*/ 0x000a0273U, -/*02ed*/ 0x100a0273U, -/*02ee*/ 0x000a0274U, -/*02ef*/ 0x100a0274U, -/*02f0*/ 0x00200275U, -/*02f1*/ 0x00200276U, -/*02f2*/ 0x00010277U, -/*02f3*/ 0x08020277U, -/*02f4*/ 0x10020277U, -/*02f5*/ 0x18020277U, -/*02f6*/ 0xffffffffU, -/*02f7*/ 0x00020278U, -/*02f8*/ 0x08100278U, -/*02f9*/ 0x18050278U, -/*02fa*/ 0x00060279U, -/*02fb*/ 0x08050279U, -/*02fc*/ 0x10050279U, -/*02fd*/ 0x000e027aU, -/*02fe*/ 0x1005027aU, -/*02ff*/ 0x000e027bU, -/*0300*/ 0x1005027bU, -/*0301*/ 0x000e027cU, -/*0302*/ 0x1005027cU, -/*0303*/ 0x1801027cU, -/*0304*/ 0x0005027dU, -/*0305*/ 0x0805027dU, -/*0306*/ 0x100a027dU, -/*0307*/ 0x000a027eU, -/*0308*/ 0x1005027eU, -/*0309*/ 0x1805027eU, -/*030a*/ 0x000a027fU, -/*030b*/ 0x100a027fU, -/*030c*/ 0x00050280U, -/*030d*/ 0x08050280U, -/*030e*/ 0x100a0280U, -/*030f*/ 0x000a0281U, -/*0310*/ 0x10070281U, -/*0311*/ 0x18070281U, -/*0312*/ 0x00070282U, -/*0313*/ 0x08070282U, -/*0314*/ 0x10070282U, -/*0315*/ 0x18070282U, -/*0316*/ 0xffffffffU, -/*0317*/ 0xffffffffU, -/*0318*/ 0x00040283U, -/*0319*/ 0x08040283U, -/*031a*/ 0x10040283U, -/*031b*/ 0x18040283U, -/*031c*/ 0x00040284U, -/*031d*/ 0xffffffffU, -/*031e*/ 0x08080284U, -/*031f*/ 0x10080284U, -/*0320*/ 0x18040284U, -/*0321*/ 0x00050285U, -/*0322*/ 0x08080285U, -/*0323*/ 0x10050285U, -/*0324*/ 0x18040285U, -/*0325*/ 0x00050286U, -/*0326*/ 0x08080286U, -/*0327*/ 0x10050286U, -/*0328*/ 0x18040286U, -/*0329*/ 0x00050287U, -/*032a*/ 0x08080287U, -/*032b*/ 0x10050287U, -/*032c*/ 0x18040287U, -/*032d*/ 0x00050288U, -/*032e*/ 0x08070288U, -/*032f*/ 0x10080288U, -/*0330*/ 0x00100289U, -/*0331*/ 0x10080289U, -/*0332*/ 0x0010028aU, -/*0333*/ 0x1008028aU, -/*0334*/ 0x0010028bU, -/*0335*/ 0x1008028bU, -/*0336*/ 0x1808028bU, -/*0337*/ 0x0001028cU, -/*0338*/ 0x0801028cU, -/*0339*/ 0x1006028cU, -/*033a*/ 0x1806028cU, -/*033b*/ 0x0006028dU, -/*033c*/ 0x0801028dU, -/*033d*/ 0x1001028dU, -/*033e*/ 0x1803028dU, -/*033f*/ 0x000a028eU, -/*0340*/ 0x100a028eU, -/*0341*/ 0x000a028fU, -/*0342*/ 0xffffffffU, -/*0343*/ 0x100a028fU, -/*0344*/ 0x00040290U, -/*0345*/ 0x08010290U, -/*0346*/ 0x10040290U, -/*0347*/ 0x18070290U, -/*0348*/ 0x00070291U, -/*0349*/ 0x08070291U, -/*034a*/ 0x10070291U, -/*034b*/ 0x18070291U, -/*034c*/ 0x00070292U, -/*034d*/ 0xffffffffU, -/*034e*/ 0xffffffffU, -/*034f*/ 0x08050292U, -/*0350*/ 0x10050292U, -/*0351*/ 0x18040292U, -/*0352*/ 0x00040293U, -/*0353*/ 0x08040293U, -/*0354*/ 0xffffffffU, -/*0355*/ 0x10010293U, -/*0356*/ 0x18010293U, -/*0357*/ 0x00020294U, -/*0358*/ 0x08080294U, -/*0359*/ 0x00200295U, -/*035a*/ 0x00200296U, -/*035b*/ 0x00100297U, -/*035c*/ 0x10020297U, -/*035d*/ 0x18020297U, -/*035e*/ 0x00020298U, -/*035f*/ 0xffffffffU, -/*0360*/ 0x08010298U, -/*0361*/ 0x10010298U, -/*0362*/ 0x18020298U, -/*0363*/ 0x00100299U, -/*0364*/ 0x10100299U, -/*0365*/ 0x0010029aU, -/*0366*/ 0x1008029aU, -/*0367*/ 0x1808029aU, -/*0368*/ 0x0008029bU, -/*0369*/ 0x0808029bU, -/*036a*/ 0x1010029bU, -/*036b*/ 0x0010029cU, -/*036c*/ 0x1010029cU, -/*036d*/ 0x0008029dU, -/*036e*/ 0x0808029dU, -/*036f*/ 0x1008029dU, -/*0370*/ 0x1808029dU, -/*0371*/ 0x0010029eU, -/*0372*/ 0x1010029eU, -/*0373*/ 0x0010029fU, -/*0374*/ 0x1008029fU, -/*0375*/ 0x1808029fU, -/*0376*/ 0x000802a0U, -/*0377*/ 0x080802a0U, -/*0378*/ 0x100802a0U, -/*0379*/ 0x001002a1U, -/*037a*/ 0x101002a1U, -/*037b*/ 0x001002a2U, -/*037c*/ 0x100802a2U, -/*037d*/ 0x180802a2U, -/*037e*/ 0x000802a3U, -/*037f*/ 0x080802a3U, -/*0380*/ 0x101002a3U, -/*0381*/ 0x001002a4U, -/*0382*/ 0x101002a4U, -/*0383*/ 0x000802a5U, -/*0384*/ 0x080802a5U, -/*0385*/ 0x100802a5U, -/*0386*/ 0x180802a5U, -/*0387*/ 0x001002a6U, -/*0388*/ 0x101002a6U, -/*0389*/ 0x001002a7U, -/*038a*/ 0x100802a7U, -/*038b*/ 0x180802a7U, -/*038c*/ 0x000802a8U, -/*038d*/ 0x080802a8U, -/*038e*/ 0x100802a8U, -/*038f*/ 0x001002a9U, -/*0390*/ 0x101002a9U, -/*0391*/ 0x001002aaU, -/*0392*/ 0x100802aaU, -/*0393*/ 0x180802aaU, -/*0394*/ 0x000802abU, -/*0395*/ 0x080802abU, -/*0396*/ 0x101002abU, -/*0397*/ 0x001002acU, -/*0398*/ 0x101002acU, -/*0399*/ 0x000802adU, -/*039a*/ 0x080802adU, -/*039b*/ 0x100802adU, -/*039c*/ 0x180802adU, -/*039d*/ 0x001002aeU, -/*039e*/ 0x101002aeU, -/*039f*/ 0x001002afU, -/*03a0*/ 0x100802afU, -/*03a1*/ 0x180802afU, -/*03a2*/ 0x000802b0U, -/*03a3*/ 0x080802b0U, -/*03a4*/ 0x100802b0U, -/*03a5*/ 0x001002b1U, -/*03a6*/ 0x101002b1U, -/*03a7*/ 0x001002b2U, -/*03a8*/ 0x100802b2U, -/*03a9*/ 0x180802b2U, -/*03aa*/ 0x000802b3U, -/*03ab*/ 0x080802b3U, -/*03ac*/ 0x101002b3U, -/*03ad*/ 0x001002b4U, -/*03ae*/ 0x101002b4U, -/*03af*/ 0x000802b5U, -/*03b0*/ 0x080802b5U, -/*03b1*/ 0x100802b5U, -/*03b2*/ 0x180802b5U, -/*03b3*/ 0x001002b6U, -/*03b4*/ 0x101002b6U, -/*03b5*/ 0x001002b7U, -/*03b6*/ 0x100802b7U, -/*03b7*/ 0x180802b7U, -/*03b8*/ 0x000802b8U, -/*03b9*/ 0x080802b8U, -/*03ba*/ 0x100802b8U, -/*03bb*/ 0x180202b8U, -/*03bc*/ 0x000302b9U, -/*03bd*/ 0x080a02b9U, -/*03be*/ 0x000a02baU, -/*03bf*/ 0x100a02baU, -/*03c0*/ 0x000502bbU, -/*03c1*/ 0x080802bbU, -/*03c2*/ 0x100802bbU, -/*03c3*/ 0x180802bbU, -/*03c4*/ 0x000602bcU, -/*03c5*/ 0x080602bcU, -/*03c6*/ 0x001102bdU, -/*03c7*/ 0x180802bdU, -/*03c8*/ 0x000402beU, -/*03c9*/ 0x080602beU, -/*03ca*/ 0x100802beU, -/*03cb*/ 0x180802beU, -/*03cc*/ 0x000802bfU, -/*03cd*/ 0x080802bfU, -/*03ce*/ 0x100802bfU, -/*03cf*/ 0x180802bfU, -/*03d0*/ 0x000802c0U, -/*03d1*/ 0x080602c0U, -/*03d2*/ 0x100602c0U, -/*03d3*/ 0x001102c1U, -/*03d4*/ 0x180802c1U, -/*03d5*/ 0x000402c2U, -/*03d6*/ 0x080602c2U, -/*03d7*/ 0x100802c2U, -/*03d8*/ 0x180802c2U, -/*03d9*/ 0x000802c3U, -/*03da*/ 0x080802c3U, -/*03db*/ 0x100802c3U, -/*03dc*/ 0x180802c3U, -/*03dd*/ 0x000802c4U, -/*03de*/ 0x080602c4U, -/*03df*/ 0x100602c4U, -/*03e0*/ 0x001102c5U, -/*03e1*/ 0x180802c5U, -/*03e2*/ 0x000402c6U, -/*03e3*/ 0x080602c6U, -/*03e4*/ 0x100802c6U, -/*03e5*/ 0x180802c6U, -/*03e6*/ 0x000802c7U, -/*03e7*/ 0x080802c7U, -/*03e8*/ 0x100402c7U, -/*03e9*/ 0x180402c7U, -/*03ea*/ 0x000402c8U, -/*03eb*/ 0x080402c8U, -/*03ec*/ 0x100402c8U, -/*03ed*/ 0x180402c8U, -/*03ee*/ 0x000402c9U, -/*03ef*/ 0x080402c9U, -/*03f0*/ 0x100402c9U, -/*03f1*/ 0x180402c9U, -/*03f2*/ 0x000402caU, -/*03f3*/ 0x080402caU, -/*03f4*/ 0x100402caU, -/*03f5*/ 0x180402caU, -/*03f6*/ 0x000402cbU, -/*03f7*/ 0x080402cbU, -/*03f8*/ 0x100402cbU, -/*03f9*/ 0x180402cbU, -/*03fa*/ 0x000402ccU, -/*03fb*/ 0x080402ccU, -/*03fc*/ 0x001702cdU, -/*03fd*/ 0x001602ceU, -/*03fe*/ 0x001702cfU, -/*03ff*/ 0x002002d0U, -/*0400*/ 0x002002d1U, -/*0401*/ 0x002002d2U, -/*0402*/ 0x002002d3U, -/*0403*/ 0x002002d4U, -/*0404*/ 0x002002d5U, -/*0405*/ 0x002002d6U, -/*0406*/ 0x002002d7U, -/*0407*/ 0x002002d8U, -/*0408*/ 0x000202d9U, -/*0409*/ 0x080502d9U, -/*040a*/ 0x100502d9U, -/*040b*/ 0x180102d9U, -/*040c*/ 0x000502daU, -/*040d*/ 0x080502daU, -/*040e*/ 0x100502daU, -/*040f*/ 0x180502daU, -/*0410*/ 0x000502dbU, -/*0411*/ 0x080502dbU, -/*0412*/ 0x100502dbU, -/*0413*/ 0x180502dbU, -/*0414*/ 0x000502dcU, -/*0415*/ 0x080502dcU, -/*0416*/ 0x100502dcU, -/*0417*/ 0x180502dcU, -/*0418*/ 0x000502ddU, -/*0419*/ 0x080502ddU, -/*041a*/ 0x100502ddU, -/*041b*/ 0x180502ddU, -/*041c*/ 0x000502deU, -/*041d*/ 0x080502deU, -/*041e*/ 0x100502deU, -/*041f*/ 0x180502deU, -/*0420*/ 0x000502dfU, -/*0421*/ 0x080502dfU, -/*0422*/ 0x100102dfU, -/*0423*/ 0x180202dfU, -/*0424*/ 0x000202e0U, -/*0425*/ 0x080202e0U, -/*0426*/ 0x100202e0U, -/*0427*/ 0x180102e0U, -/*0428*/ 0x000802e1U, -/*0429*/ 0x081502e1U, -/*042a*/ 0x002002e2U, -/*042b*/ 0x001502e3U, -/*042c*/ 0x002002e4U, -/*042d*/ 0x001502e5U, -/*042e*/ 0x002002e6U, -/*042f*/ 0x000702e7U, -/*0430*/ 0x080102e7U, -/*0431*/ 0x100202e7U, -/*0432*/ 0x180602e7U, -/*0433*/ 0x000102e8U, -/*0434*/ 0x080102e8U, -/*0435*/ 0x002002e9U, -/*0436*/ 0x000202eaU, -/*0437*/ 0x002002ebU, -/*0438*/ 0x002002ecU, -/*0439*/ 0x000c02edU, -/*043a*/ 0x100c02edU, -/*043b*/ 0x002002eeU, -/*043c*/ 0x000302efU, -/*043d*/ 0x002002f0U, -/*043e*/ 0x000302f1U, -/*043f*/ 0x002002f2U, -/*0440*/ 0x000302f3U, -/*0441*/ 0x002002f4U, -/*0442*/ 0x000302f5U, -/*0443*/ 0x002002f6U, -/*0444*/ 0x000302f7U, -/*0445*/ 0x002002f8U, -/*0446*/ 0x000302f9U, -/*0447*/ 0x002002faU, -/*0448*/ 0x000302fbU, -/*0449*/ 0x002002fcU, -/*044a*/ 0x000302fdU, -/*044b*/ 0x002002feU, -/*044c*/ 0x000302ffU, -/*044d*/ 0x00200300U, -/*044e*/ 0x00030301U, -/*044f*/ 0x08030301U, -/*0450*/ 0x10020301U, -/*0451*/ 0x18020301U, -/*0452*/ 0x00200302U, -/*0453*/ 0x00200303U, -/*0454*/ 0x00200304U, -/*0455*/ 0x00200305U, -/*0456*/ 0x00040306U, -/*0457*/ 0x001e0307U, -/*0458*/ 0x001e0308U, -/*0459*/ 0x001e0309U, -/*045a*/ 0x001e030aU, -/*045b*/ 0x001e030bU, -/*045c*/ 0x001e030cU, -/*045d*/ 0x001e030dU, -/*045e*/ 0x001e030eU, -/*045f*/ 0x0004030fU, -/*0460*/ 0x0801030fU, -/*0461*/ 0x1010030fU, -/*0462*/ 0x00100310U, -/*0463*/ 0x10100310U, -/*0464*/ 0x00040311U, -/*0465*/ 0x08010311U, -/*0466*/ 0x10080311U, -/*0467*/ 0x18040311U, -/*0468*/ 0x00010312U, -/*0469*/ 0x08080312U, -/*046a*/ 0x10040312U, -/*046b*/ 0x18010312U, -/*046c*/ 0x00080313U, -/*046d*/ 0x08040313U, -/*046e*/ 0x10010313U, -/*046f*/ 0x18080313U, -/*0470*/ 0x00040314U, -/*0471*/ 0x08010314U, -/*0472*/ 0x10080314U, -/*0473*/ 0x18040314U, -/*0474*/ 0x00010315U, -/*0475*/ 0x08080315U, -/*0476*/ 0x10040315U, -/*0477*/ 0x18010315U, -/*0478*/ 0x00080316U, -/*0479*/ 0x08040316U, -/*047a*/ 0x10010316U, -/*047b*/ 0x18080316U, -/*047c*/ 0x00080317U, -/*047d*/ 0x00010318U, -/*047e*/ 0x08050318U, -/*047f*/ 0x10010318U, -/*0480*/ 0x18020318U, -/*0481*/ 0x00010319U, -/*0482*/ 0x08010319U, -/*0483*/ 0x10010319U, -/*0484*/ 0x18010319U, -/*0485*/ 0x0001031aU, -/*0486*/ 0x0801031aU, -/*0487*/ 0x1001031aU, -/*0488*/ 0x1801031aU, -/*0489*/ 0x0001031bU, -/*048a*/ 0x0801031bU, -/*048b*/ 0x1001031bU, -/*048c*/ 0x1801031bU, -/*048d*/ 0x0001031cU, -/*048e*/ 0x0801031cU, -/*048f*/ 0x1001031cU, -/*0490*/ 0x1801031cU, -/*0491*/ 0x0008031dU, -/*0492*/ 0x0808031dU, -/*0493*/ 0x1008031dU, -/*0494*/ 0x1808031dU, - } -}; diff --git a/ddr/lpddr4/init_dram_tbl_g2h.h b/ddr/lpddr4/init_dram_tbl_g2h.h deleted file mode 100644 index 965d9fe..0000000 --- a/ddr/lpddr4/init_dram_tbl_g2h.h +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define DDR_PHY_SLICE_REGSET_OFS_G2H 0x0400 -#define DDR_PHY_ADR_V_REGSET_OFS_G2H 0x0600 -#define DDR_PHY_ADR_I_REGSET_OFS_G2H 0x0640 -#define DDR_PHY_ADR_G_REGSET_OFS_G2H 0x0680 -#define DDR_PI_REGSET_OFS_G2H 0x0200 - -#define DDR_PHY_SLICE_REGSET_SIZE_G2H 0x80 -#define DDR_PHY_ADR_V_REGSET_SIZE_G2H 0x40 -#define DDR_PHY_ADR_I_REGSET_SIZE_G2H 0x40 -#define DDR_PHY_ADR_G_REGSET_SIZE_G2H 0x80 -#define DDR_PI_REGSET_SIZE_G2H 0x100 - -#define DDR_PHY_SLICE_REGSET_NUM_G2H 97 -#define DDR_PHY_ADR_V_REGSET_NUM_G2H 37 -#define DDR_PHY_ADR_I_REGSET_NUM_G2H 37 -#define DDR_PHY_ADR_G_REGSET_NUM_G2H 79 -#define DDR_PI_REGSET_NUM_G2H 245 - -static const uint32_t DDR_PHY_SLICE_REGSET_G2H[DDR_PHY_SLICE_REGSET_NUM_G2H] = { -/*0400*/ 0x76543210, -/*0401*/ 0x0004f008, -/*0402*/ 0x00020133, -/*0403*/ 0x00000000, -/*0404*/ 0x00000000, -/*0405*/ 0x00010000, -/*0406*/ 0x016e6e0e, -/*0407*/ 0x026e6e0e, -/*0408*/ 0x00010300, -/*0409*/ 0x04000100, -/*040a*/ 0x01000000, -/*040b*/ 0x00000000, -/*040c*/ 0x00000000, -/*040d*/ 0x00000100, -/*040e*/ 0x001700c0, -/*040f*/ 0x020100b0, -/*0410*/ 0x00030020, -/*0411*/ 0x00000000, -/*0412*/ 0x00000000, -/*0413*/ 0x00000000, -/*0414*/ 0x00000000, -/*0415*/ 0x00000000, -/*0416*/ 0x00000000, -/*0417*/ 0x00000000, -/*0418*/ 0x09000000, -/*0419*/ 0x04080000, -/*041a*/ 0x04080400, -/*041b*/ 0x08000000, -/*041c*/ 0x0c008007, -/*041d*/ 0x00000f00, -/*041e*/ 0x00000100, -/*041f*/ 0x55aa55aa, -/*0420*/ 0x33cc33cc, -/*0421*/ 0x0ff00ff0, -/*0422*/ 0x0f0ff0f0, -/*0423*/ 0x00018e38, -/*0424*/ 0x00000000, -/*0425*/ 0x00000000, -/*0426*/ 0x00000000, -/*0427*/ 0x00000000, -/*0428*/ 0x00000000, -/*0429*/ 0x00000000, -/*042a*/ 0x00000000, -/*042b*/ 0x00000000, -/*042c*/ 0x00000000, -/*042d*/ 0x00000000, -/*042e*/ 0x00000000, -/*042f*/ 0x00000000, -/*0430*/ 0x00000000, -/*0431*/ 0x00000000, -/*0432*/ 0x00000000, -/*0433*/ 0x00000000, -/*0434*/ 0x00000000, -/*0435*/ 0x00000000, -/*0436*/ 0x00000000, -/*0437*/ 0x00000000, -/*0438*/ 0x00000104, -/*0439*/ 0x00082020, -/*043a*/ 0x08200820, -/*043b*/ 0x08200820, -/*043c*/ 0x08200820, -/*043d*/ 0x08200820, -/*043e*/ 0x08200820, -/*043f*/ 0x00000000, -/*0440*/ 0x00000000, -/*0441*/ 0x03000300, -/*0442*/ 0x03000300, -/*0443*/ 0x03000300, -/*0444*/ 0x03000300, -/*0445*/ 0x00000300, -/*0446*/ 0x00000000, -/*0447*/ 0x00000000, -/*0448*/ 0x00000000, -/*0449*/ 0x00000000, -/*044a*/ 0x00000000, -/*044b*/ 0x00a000a0, -/*044c*/ 0x00a000a0, -/*044d*/ 0x00a000a0, -/*044e*/ 0x00a000a0, -/*044f*/ 0x00a000a0, -/*0450*/ 0x00a000a0, -/*0451*/ 0x00a000a0, -/*0452*/ 0x00a000a0, -/*0453*/ 0x00a000a0, -/*0454*/ 0x01040109, -/*0455*/ 0x00000200, -/*0456*/ 0x01000000, -/*0457*/ 0x00000200, -/*0458*/ 0x00000004, -/*0459*/ 0x4041a151, -/*045a*/ 0xc00141a0, -/*045b*/ 0x0e0000c0, -/*045c*/ 0x0010000c, -/*045d*/ 0x063e4208, -/*045e*/ 0x0f0c180c, -/*045f*/ 0x00e00140, -/*0460*/ 0x00000c20 -}; - -static const uint32_t DDR_PHY_ADR_V_REGSET_G2H[DDR_PHY_ADR_V_REGSET_NUM_G2H] = { -/*0600*/ 0x00000000, -/*0601*/ 0x00000000, -/*0602*/ 0x00000000, -/*0603*/ 0x00000000, -/*0604*/ 0x00000000, -/*0605*/ 0x00000000, -/*0606*/ 0x00000000, -/*0607*/ 0x00010000, -/*0608*/ 0x00000200, -/*0609*/ 0x00000000, -/*060a*/ 0x00000000, -/*060b*/ 0x00000000, -/*060c*/ 0x00400320, -/*060d*/ 0x00000040, -/*060e*/ 0x00dcba98, -/*060f*/ 0x03000000, -/*0610*/ 0x00000200, -/*0611*/ 0x00000000, -/*0612*/ 0x00000000, -/*0613*/ 0x00000000, -/*0614*/ 0x0000002a, -/*0615*/ 0x00000015, -/*0616*/ 0x00000015, -/*0617*/ 0x0000002a, -/*0618*/ 0x00000033, -/*0619*/ 0x0000000c, -/*061a*/ 0x0000000c, -/*061b*/ 0x00000033, -/*061c*/ 0x00418820, -/*061d*/ 0x003f0000, -/*061e*/ 0x0000003f, -/*061f*/ 0x0002c06e, -/*0620*/ 0x02c002c0, -/*0621*/ 0x02c002c0, -/*0622*/ 0x000002c0, -/*0623*/ 0x42080010, -/*0624*/ 0x0000033e -}; - -static const uint32_t DDR_PHY_ADR_I_REGSET_G2H[DDR_PHY_ADR_I_REGSET_NUM_G2H] = { -/*0640*/ 0x00000000, -/*0641*/ 0x00000000, -/*0642*/ 0x00000000, -/*0643*/ 0x00000000, -/*0644*/ 0x00000000, -/*0645*/ 0x00000000, -/*0646*/ 0x00000000, -/*0647*/ 0x00000000, -/*0648*/ 0x00000000, -/*0649*/ 0x00000000, -/*064a*/ 0x00000000, -/*064b*/ 0x00000000, -/*064c*/ 0x00000000, -/*064d*/ 0x00000000, -/*064e*/ 0x00000000, -/*064f*/ 0x00000000, -/*0650*/ 0x00000000, -/*0651*/ 0x00000000, -/*0652*/ 0x00000000, -/*0653*/ 0x00000000, -/*0654*/ 0x00000000, -/*0655*/ 0x00000000, -/*0656*/ 0x00000000, -/*0657*/ 0x00000000, -/*0658*/ 0x00000000, -/*0659*/ 0x00000000, -/*065a*/ 0x00000000, -/*065b*/ 0x00000000, -/*065c*/ 0x00000000, -/*065d*/ 0x00000000, -/*065e*/ 0x00000000, -/*065f*/ 0x00000000, -/*0660*/ 0x00000000, -/*0661*/ 0x00000000, -/*0662*/ 0x00000000, -/*0663*/ 0x00000000, -/*0664*/ 0x00000000 -}; - -static const uint32_t DDR_PHY_ADR_G_REGSET_G2H[DDR_PHY_ADR_G_REGSET_NUM_G2H] = { -/*0680*/ 0x00000000, -/*0681*/ 0x00000100, -/*0682*/ 0x00000000, -/*0683*/ 0x00050000, -/*0684*/ 0x0f000000, -/*0685*/ 0x00800400, -/*0686*/ 0x00020032, -/*0687*/ 0x00020055, -/*0688*/ 0x00000000, -/*0689*/ 0x00000000, -/*068a*/ 0x00000000, -/*068b*/ 0x00000050, -/*068c*/ 0x00000000, -/*068d*/ 0x01010100, -/*068e*/ 0x01000200, -/*068f*/ 0x00000000, -/*0690*/ 0x00010100, -/*0691*/ 0x00000000, -/*0692*/ 0x00000000, -/*0693*/ 0x00000000, -/*0694*/ 0x00000000, -/*0695*/ 0x00005064, -/*0696*/ 0x01421142, -/*0697*/ 0x00000142, -/*0698*/ 0x00000000, -/*0699*/ 0x000f1100, -/*069a*/ 0x0f110f11, -/*069b*/ 0x09000f11, -/*069c*/ 0x00000003, -/*069d*/ 0x0002c000, -/*069e*/ 0x02c002c0, -/*069f*/ 0x000002c0, -/*06a0*/ 0x03421342, -/*06a1*/ 0x00000342, -/*06a2*/ 0x00000000, -/*06a3*/ 0x00000000, -/*06a4*/ 0x05020000, -/*06a5*/ 0x14000000, -/*06a6*/ 0x027f6e00, -/*06a7*/ 0x047f027f, -/*06a8*/ 0x00027f6e, -/*06a9*/ 0x00047f6e, -/*06aa*/ 0x0003554f, -/*06ab*/ 0x0001554f, -/*06ac*/ 0x0001554f, -/*06ad*/ 0x0001554f, -/*06ae*/ 0x0001554f, -/*06af*/ 0x00003fee, -/*06b0*/ 0x0001554f, -/*06b1*/ 0x00003fee, -/*06b2*/ 0x0001554f, -/*06b3*/ 0x00027f6e, -/*06b4*/ 0x0001554f, -/*06b5*/ 0x00004011, -/*06b6*/ 0x00004410, -/*06b7*/ 0x00000000, -/*06b8*/ 0x00000000, -/*06b9*/ 0x00000000, -/*06ba*/ 0x00000065, -/*06bb*/ 0x00000000, -/*06bc*/ 0x00020201, -/*06bd*/ 0x00000000, -/*06be*/ 0x03000000, -/*06bf*/ 0x00000008, -/*06c0*/ 0x00000000, -/*06c1*/ 0x00000000, -/*06c2*/ 0x00000000, -/*06c3*/ 0x00000000, -/*06c4*/ 0x00000001, -/*06c5*/ 0x00000000, -/*06c6*/ 0x00000000, -/*06c7*/ 0x00000000, -/*06c8*/ 0x000000e4, -/*06c9*/ 0x00010198, -/*06ca*/ 0x00000000, -/*06cb*/ 0x00000000, -/*06cc*/ 0x07010000, -/*06cd*/ 0x00000104, -/*06ce*/ 0x00000000 -}; - -static const uint32_t DDR_PI_REGSET_G2H[DDR_PI_REGSET_NUM_G2H] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000100, -/*0202*/ 0x00640000, -/*0203*/ 0x00000000, -/*0204*/ 0x0000ffff, -/*0205*/ 0x00000000, -/*0206*/ 0x0000ffff, -/*0207*/ 0x00000000, -/*0208*/ 0x0000ffff, -/*0209*/ 0x0000304c, -/*020a*/ 0x00000200, -/*020b*/ 0x00000200, -/*020c*/ 0x00000200, -/*020d*/ 0x00000200, -/*020e*/ 0x0000304c, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x00000200, -/*0212*/ 0x00000200, -/*0213*/ 0x0000304c, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00000200, -/*0217*/ 0x00000200, -/*0218*/ 0x00010000, -/*0219*/ 0x00000003, -/*021a*/ 0x01000001, -/*021b*/ 0x00000000, -/*021c*/ 0x00000000, -/*021d*/ 0x00000000, -/*021e*/ 0x00000000, -/*021f*/ 0x00000000, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x00000000, -/*022a*/ 0x00000000, -/*022b*/ 0x0f000101, -/*022c*/ 0x08492d25, -/*022d*/ 0x500e0c04, -/*022e*/ 0x0002500e, -/*022f*/ 0x00000301, -/*0230*/ 0x00000046, -/*0231*/ 0x000000cf, -/*0232*/ 0x00001826, -/*0233*/ 0x000000cf, -/*0234*/ 0x00001826, -/*0235*/ 0x00000005, -/*0236*/ 0x00000000, -/*0237*/ 0x00000000, -/*0238*/ 0x00000000, -/*0239*/ 0x00000000, -/*023a*/ 0x00000000, -/*023b*/ 0x00000000, -/*023c*/ 0x00000000, -/*023d*/ 0x00000000, -/*023e*/ 0x04010000, -/*023f*/ 0x00000404, -/*0240*/ 0x0101280a, -/*0241*/ 0x00000000, -/*0242*/ 0x00000000, -/*0243*/ 0x0003000f, -/*0244*/ 0x00000018, -/*0245*/ 0x00000000, -/*0246*/ 0x00000000, -/*0247*/ 0x00060002, -/*0248*/ 0x00010001, -/*0249*/ 0x01000101, -/*024a*/ 0x04020201, -/*024b*/ 0x00080804, -/*024c*/ 0x00000000, -/*024d*/ 0x08030000, -/*024e*/ 0x15150408, -/*024f*/ 0x00000000, -/*0250*/ 0x00000000, -/*0251*/ 0x00000000, -/*0252*/ 0x0f0f0000, -/*0253*/ 0x0000001e, -/*0254*/ 0x00000000, -/*0255*/ 0x01000300, -/*0256*/ 0x00000100, -/*0257*/ 0x00000000, -/*0258*/ 0x00000000, -/*0259*/ 0x01000000, -/*025a*/ 0x00000101, -/*025b*/ 0x55555a5a, -/*025c*/ 0x55555a5a, -/*025d*/ 0x55555a5a, -/*025e*/ 0x55555a5a, -/*025f*/ 0x0e0e0001, -/*0260*/ 0x0c0c000e, -/*0261*/ 0x0601000c, -/*0262*/ 0x17170106, -/*0263*/ 0x00020202, -/*0264*/ 0x03000000, -/*0265*/ 0x00000000, -/*0266*/ 0x00181703, -/*0267*/ 0x00280006, -/*0268*/ 0x00280016, -/*0269*/ 0x00000016, -/*026a*/ 0x00000000, -/*026b*/ 0x00000000, -/*026c*/ 0x00000000, -/*026d*/ 0x0a000000, -/*026e*/ 0x00010a14, -/*026f*/ 0x00030005, -/*0270*/ 0x0003018d, -/*0271*/ 0x000a018d, -/*0272*/ 0x00060100, -/*0273*/ 0x01000006, -/*0274*/ 0x018e018e, -/*0275*/ 0x018e0100, -/*0276*/ 0x1111018e, -/*0277*/ 0x10010204, -/*0278*/ 0x09090650, -/*0279*/ 0xff110202, -/*027a*/ 0x00ff1000, -/*027b*/ 0x00ff1000, -/*027c*/ 0x04041000, -/*027d*/ 0x18020100, -/*027e*/ 0x01010018, -/*027f*/ 0x004a004a, -/*0280*/ 0x004b004a, -/*0281*/ 0x050f0000, -/*0282*/ 0x0c01021e, -/*0283*/ 0x34000000, -/*0284*/ 0x00000000, -/*0285*/ 0x00000000, -/*0286*/ 0x00000000, -/*0287*/ 0x00000000, -/*0288*/ 0x36312ed4, -/*0289*/ 0x2ed41111, -/*028a*/ 0x11113631, -/*028b*/ 0x36312ed4, -/*028c*/ 0xd4001111, -/*028d*/ 0x1136312e, -/*028e*/ 0x312ed411, -/*028f*/ 0xd4111136, -/*0290*/ 0x1136312e, -/*0291*/ 0x2ed40011, -/*0292*/ 0x11113631, -/*0293*/ 0x36312ed4, -/*0294*/ 0x2ed41111, -/*0295*/ 0x11113631, -/*0296*/ 0x312ed400, -/*0297*/ 0xd4111136, -/*0298*/ 0x1136312e, -/*0299*/ 0x312ed411, -/*029a*/ 0x00111136, -/*029b*/ 0x018d0200, -/*029c*/ 0x018d018d, -/*029d*/ 0x1d220c08, -/*029e*/ 0x00001f12, -/*029f*/ 0x4301b344, -/*02a0*/ 0x10172006, -/*02a1*/ 0x121d220c, -/*02a2*/ 0x01b3441f, -/*02a3*/ 0x17200643, -/*02a4*/ 0x1d220c10, -/*02a5*/ 0x00001f12, -/*02a6*/ 0x4301b344, -/*02a7*/ 0x10172006, -/*02a8*/ 0x00020002, -/*02a9*/ 0x00020002, -/*02aa*/ 0x00020002, -/*02ab*/ 0x00020002, -/*02ac*/ 0x00020002, -/*02ad*/ 0x00000000, -/*02ae*/ 0x00000000, -/*02af*/ 0x00000000, -/*02b0*/ 0x00000000, -/*02b1*/ 0x00000000, -/*02b2*/ 0x00000000, -/*02b3*/ 0x00000000, -/*02b4*/ 0x00000000, -/*02b5*/ 0x00000000, -/*02b6*/ 0x00000000, -/*02b7*/ 0x00000000, -/*02b8*/ 0x00000000, -/*02b9*/ 0x00000400, -/*02ba*/ 0x05040302, -/*02bb*/ 0x01000f0e, -/*02bc*/ 0x07060504, -/*02bd*/ 0x03020100, -/*02be*/ 0x02010000, -/*02bf*/ 0x00000103, -/*02c0*/ 0x0000304c, -/*02c1*/ 0x0001e2f8, -/*02c2*/ 0x0000304c, -/*02c3*/ 0x0001e2f8, -/*02c4*/ 0x0000304c, -/*02c5*/ 0x0001e2f8, -/*02c6*/ 0x08000000, -/*02c7*/ 0x00000100, -/*02c8*/ 0x00000000, -/*02c9*/ 0x00000000, -/*02ca*/ 0x00000000, -/*02cb*/ 0x00000000, -/*02cc*/ 0x00010000, -/*02cd*/ 0x00000000, -/*02ce*/ 0x00000000, -/*02cf*/ 0x00000000, -/*02d0*/ 0x00000000, -/*02d1*/ 0x00000000, -/*02d2*/ 0x00000000, -/*02d3*/ 0x00000000, -/*02d4*/ 0x00000000, -/*02d5*/ 0x00000000, -/*02d6*/ 0x00000000, -/*02d7*/ 0x00000000, -/*02d8*/ 0x00000000, -/*02d9*/ 0x00000000, -/*02da*/ 0x00000000, -/*02db*/ 0x00000000, -/*02dc*/ 0x00000000, -/*02dd*/ 0x00000000, -/*02de*/ 0x00000000, -/*02df*/ 0x00000000, -/*02e0*/ 0x00000000, -/*02e1*/ 0x00000000, -/*02e2*/ 0x00000000, -/*02e3*/ 0x00000000, -/*02e4*/ 0x00000000, -/*02e5*/ 0x00000000, -/*02e6*/ 0x00000000, -/*02e7*/ 0x00000000, -/*02e8*/ 0x00000000, -/*02e9*/ 0x00000000, -/*02ea*/ 0x00000000, -/*02eb*/ 0x00000000, -/*02ec*/ 0x00000000, -/*02ed*/ 0x00000000, -/*02ee*/ 0x00000002, -/*02ef*/ 0x00000000, -/*02f0*/ 0x00000000, -/*02f1*/ 0x00000000, -/*02f2*/ 0x00000000, -/*02f3*/ 0x00000000, -/*02f4*/ 0x00000000 -}; diff --git a/ddr/lpddr4/init_dram_tbl_g2m.h b/ddr/lpddr4/init_dram_tbl_g2m.h deleted file mode 100755 index faaeb3c..0000000 --- a/ddr/lpddr4/init_dram_tbl_g2m.h +++ /dev/null @@ -1,467 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define DDR_PHY_SLICE_REGSET_OFS_G2M 0x0800 -#define DDR_PHY_ADR_V_REGSET_OFS_G2M 0x0a00 -#define DDR_PHY_ADR_I_REGSET_OFS_G2M 0x0a80 -#define DDR_PHY_ADR_G_REGSET_OFS_G2M 0x0b80 -#define DDR_PI_REGSET_OFS_G2M 0x0200 - -#define DDR_PHY_SLICE_REGSET_SIZE_G2M 0x80 -#define DDR_PHY_ADR_V_REGSET_SIZE_G2M 0x80 -#define DDR_PHY_ADR_I_REGSET_SIZE_G2M 0x80 -#define DDR_PHY_ADR_G_REGSET_SIZE_G2M 0x80 -#define DDR_PI_REGSET_SIZE_G2M 0x100 - -#define DDR_PHY_SLICE_REGSET_NUM_G2M 89 -#define DDR_PHY_ADR_V_REGSET_NUM_G2M 37 -#define DDR_PHY_ADR_I_REGSET_NUM_G2M 37 -#define DDR_PHY_ADR_G_REGSET_NUM_G2M 64 -#define DDR_PI_REGSET_NUM_G2M 202 - -static const uint32_t DDR_PHY_SLICE_REGSET_G2M[DDR_PHY_SLICE_REGSET_NUM_G2M] = { -/*0800*/ 0x76543210, -/*0801*/ 0x0004f008, -/*0802*/ 0x00000000, -/*0803*/ 0x00000000, -/*0804*/ 0x00010000, -/*0805*/ 0x036e6e0e, -/*0806*/ 0x026e6e0e, -/*0807*/ 0x00010300, -/*0808*/ 0x04000100, -/*0809*/ 0x00000300, -/*080a*/ 0x001700c0, -/*080b*/ 0x00b00201, -/*080c*/ 0x00030020, -/*080d*/ 0x00000000, -/*080e*/ 0x00000000, -/*080f*/ 0x00000000, -/*0810*/ 0x00000000, -/*0811*/ 0x00000000, -/*0812*/ 0x00000000, -/*0813*/ 0x00000000, -/*0814*/ 0x09000000, -/*0815*/ 0x04080000, -/*0816*/ 0x04080400, -/*0817*/ 0x00000000, -/*0818*/ 0x32103210, -/*0819*/ 0x00800708, -/*081a*/ 0x000f000c, -/*081b*/ 0x00000100, -/*081c*/ 0x55aa55aa, -/*081d*/ 0x33cc33cc, -/*081e*/ 0x0ff00ff0, -/*081f*/ 0x0f0ff0f0, -/*0820*/ 0x00018e38, -/*0821*/ 0x00000000, -/*0822*/ 0x00000000, -/*0823*/ 0x00000000, -/*0824*/ 0x00000000, -/*0825*/ 0x00000000, -/*0826*/ 0x00000000, -/*0827*/ 0x00000000, -/*0828*/ 0x00000000, -/*0829*/ 0x00000000, -/*082a*/ 0x00000000, -/*082b*/ 0x00000000, -/*082c*/ 0x00000000, -/*082d*/ 0x00000000, -/*082e*/ 0x00000000, -/*082f*/ 0x00000000, -/*0830*/ 0x00000000, -/*0831*/ 0x00000000, -/*0832*/ 0x00000000, -/*0833*/ 0x00200000, -/*0834*/ 0x08200820, -/*0835*/ 0x08200820, -/*0836*/ 0x08200820, -/*0837*/ 0x08200820, -/*0838*/ 0x08200820, -/*0839*/ 0x00000820, -/*083a*/ 0x03000300, -/*083b*/ 0x03000300, -/*083c*/ 0x03000300, -/*083d*/ 0x03000300, -/*083e*/ 0x00000300, -/*083f*/ 0x00000000, -/*0840*/ 0x00000000, -/*0841*/ 0x00000000, -/*0842*/ 0x00000000, -/*0843*/ 0x00a00000, -/*0844*/ 0x00a000a0, -/*0845*/ 0x00a000a0, -/*0846*/ 0x00a000a0, -/*0847*/ 0x00a000a0, -/*0848*/ 0x00a000a0, -/*0849*/ 0x00a000a0, -/*084a*/ 0x00a000a0, -/*084b*/ 0x00a000a0, -/*084c*/ 0x010900a0, -/*084d*/ 0x02000104, -/*084e*/ 0x00000000, -/*084f*/ 0x00010000, -/*0850*/ 0x00000200, -/*0851*/ 0x4041a151, -/*0852*/ 0xc00141a0, -/*0853*/ 0x0e0100c0, -/*0854*/ 0x0010000c, -/*0855*/ 0x0c064208, -/*0856*/ 0x000f0c18, -/*0857*/ 0x00e00140, -/*0858*/ 0x00000c20 -}; - -static const uint32_t DDR_PHY_ADR_V_REGSET_G2M[DDR_PHY_ADR_V_REGSET_NUM_G2M] = { -/*0a00*/ 0x00000000, -/*0a01*/ 0x00000000, -/*0a02*/ 0x00000000, -/*0a03*/ 0x00000000, -/*0a04*/ 0x00000000, -/*0a05*/ 0x00000000, -/*0a06*/ 0x00000002, -/*0a07*/ 0x00000000, -/*0a08*/ 0x00000000, -/*0a09*/ 0x00000000, -/*0a0a*/ 0x00400320, -/*0a0b*/ 0x00000040, -/*0a0c*/ 0x00dcba98, -/*0a0d*/ 0x00000000, -/*0a0e*/ 0x00dcba98, -/*0a0f*/ 0x01000000, -/*0a10*/ 0x00020003, -/*0a11*/ 0x00000000, -/*0a12*/ 0x00000000, -/*0a13*/ 0x00000000, -/*0a14*/ 0x0000002a, -/*0a15*/ 0x00000015, -/*0a16*/ 0x00000015, -/*0a17*/ 0x0000002a, -/*0a18*/ 0x00000033, -/*0a19*/ 0x0000000c, -/*0a1a*/ 0x0000000c, -/*0a1b*/ 0x00000033, -/*0a1c*/ 0x0a418820, -/*0a1d*/ 0x003f0000, -/*0a1e*/ 0x0000003f, -/*0a1f*/ 0x0002c06e, -/*0a20*/ 0x02c002c0, -/*0a21*/ 0x02c002c0, -/*0a22*/ 0x000002c0, -/*0a23*/ 0x42080010, -/*0a24*/ 0x00000003 -}; - -static const uint32_t DDR_PHY_ADR_I_REGSET_G2M[DDR_PHY_ADR_I_REGSET_NUM_G2M] = { -/*0a80*/ 0x04040404, -/*0a81*/ 0x00000404, -/*0a82*/ 0x00000000, -/*0a83*/ 0x00000000, -/*0a84*/ 0x00000000, -/*0a85*/ 0x00000000, -/*0a86*/ 0x00000002, -/*0a87*/ 0x00000000, -/*0a88*/ 0x00000000, -/*0a89*/ 0x00000000, -/*0a8a*/ 0x00400320, -/*0a8b*/ 0x00000040, -/*0a8c*/ 0x00000000, -/*0a8d*/ 0x00000000, -/*0a8e*/ 0x00000000, -/*0a8f*/ 0x01000000, -/*0a90*/ 0x00020003, -/*0a91*/ 0x00000000, -/*0a92*/ 0x00000000, -/*0a93*/ 0x00000000, -/*0a94*/ 0x0000002a, -/*0a95*/ 0x00000015, -/*0a96*/ 0x00000015, -/*0a97*/ 0x0000002a, -/*0a98*/ 0x00000033, -/*0a99*/ 0x0000000c, -/*0a9a*/ 0x0000000c, -/*0a9b*/ 0x00000033, -/*0a9c*/ 0x00000000, -/*0a9d*/ 0x00000000, -/*0a9e*/ 0x00000000, -/*0a9f*/ 0x0002c06e, -/*0aa0*/ 0x02c002c0, -/*0aa1*/ 0x02c002c0, -/*0aa2*/ 0x000002c0, -/*0aa3*/ 0x42080010, -/*0aa4*/ 0x00000003 -}; - -static const uint32_t DDR_PHY_ADR_G_REGSET_G2M[DDR_PHY_ADR_G_REGSET_NUM_G2M] = { -/*0b80*/ 0x00000001, -/*0b81*/ 0x00000000, -/*0b82*/ 0x00000005, -/*0b83*/ 0x04000f00, -/*0b84*/ 0x00020080, -/*0b85*/ 0x00020055, -/*0b86*/ 0x00000000, -/*0b87*/ 0x00000000, -/*0b88*/ 0x00000000, -/*0b89*/ 0x00000050, -/*0b8a*/ 0x00000000, -/*0b8b*/ 0x01010100, -/*0b8c*/ 0x00000600, -/*0b8d*/ 0x50640000, -/*0b8e*/ 0x01421142, -/*0b8f*/ 0x00000142, -/*0b90*/ 0x00000000, -/*0b91*/ 0x000f1600, -/*0b92*/ 0x0f160f16, -/*0b93*/ 0x0f160f16, -/*0b94*/ 0x00000003, -/*0b95*/ 0x0002c000, -/*0b96*/ 0x02c002c0, -/*0b97*/ 0x000002c0, -/*0b98*/ 0x03421342, -/*0b99*/ 0x00000342, -/*0b9a*/ 0x00000000, -/*0b9b*/ 0x00000000, -/*0b9c*/ 0x05020000, -/*0b9d*/ 0x00000000, -/*0b9e*/ 0x00027f6e, -/*0b9f*/ 0x047f027f, -/*0ba0*/ 0x00027f6e, -/*0ba1*/ 0x00047f6e, -/*0ba2*/ 0x0003554f, -/*0ba3*/ 0x0001554f, -/*0ba4*/ 0x0001554f, -/*0ba5*/ 0x0001554f, -/*0ba6*/ 0x0001554f, -/*0ba7*/ 0x00003fee, -/*0ba8*/ 0x0001554f, -/*0ba9*/ 0x00003fee, -/*0baa*/ 0x0001554f, -/*0bab*/ 0x00027f6e, -/*0bac*/ 0x0001554f, -/*0bad*/ 0x00000000, -/*0bae*/ 0x00000000, -/*0baf*/ 0x00000000, -/*0bb0*/ 0x65000000, -/*0bb1*/ 0x00000000, -/*0bb2*/ 0x00000000, -/*0bb3*/ 0x00000201, -/*0bb4*/ 0x00000000, -/*0bb5*/ 0x00000000, -/*0bb6*/ 0x00000000, -/*0bb7*/ 0x00000000, -/*0bb8*/ 0x00000000, -/*0bb9*/ 0x00000000, -/*0bba*/ 0x00000000, -/*0bbb*/ 0x00000000, -/*0bbc*/ 0x06e40000, -/*0bbd*/ 0x00000000, -/*0bbe*/ 0x00000000, -/*0bbf*/ 0x00010000 -}; - -static const uint32_t DDR_PI_REGSET_G2M[DDR_PI_REGSET_NUM_G2M] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000100, -/*0202*/ 0x00000000, -/*0203*/ 0x0000ffff, -/*0204*/ 0x00000000, -/*0205*/ 0x0000ffff, -/*0206*/ 0x00000000, -/*0207*/ 0x304cffff, -/*0208*/ 0x00000200, -/*0209*/ 0x00000200, -/*020a*/ 0x00000200, -/*020b*/ 0x00000200, -/*020c*/ 0x0000304c, -/*020d*/ 0x00000200, -/*020e*/ 0x00000200, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x0000304c, -/*0212*/ 0x00000200, -/*0213*/ 0x00000200, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00010000, -/*0217*/ 0x00000003, -/*0218*/ 0x01000001, -/*0219*/ 0x00000000, -/*021a*/ 0x00000000, -/*021b*/ 0x00000000, -/*021c*/ 0x00000000, -/*021d*/ 0x00000000, -/*021e*/ 0x00000000, -/*021f*/ 0x00000000, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x0f000101, -/*022a*/ 0x08492d25, -/*022b*/ 0x0e0c0004, -/*022c*/ 0x000e5000, -/*022d*/ 0x00000250, -/*022e*/ 0x00460003, -/*022f*/ 0x182600cf, -/*0230*/ 0x182600cf, -/*0231*/ 0x00000005, -/*0232*/ 0x00000000, -/*0233*/ 0x00000000, -/*0234*/ 0x00000000, -/*0235*/ 0x00000000, -/*0236*/ 0x00000000, -/*0237*/ 0x00000000, -/*0238*/ 0x00000000, -/*0239*/ 0x01000000, -/*023a*/ 0x00040404, -/*023b*/ 0x01280a00, -/*023c*/ 0x00000000, -/*023d*/ 0x000f0000, -/*023e*/ 0x00001803, -/*023f*/ 0x00000000, -/*0240*/ 0x00000000, -/*0241*/ 0x00060002, -/*0242*/ 0x00010001, -/*0243*/ 0x01000101, -/*0244*/ 0x04020201, -/*0245*/ 0x00080804, -/*0246*/ 0x00000000, -/*0247*/ 0x08030000, -/*0248*/ 0x15150408, -/*0249*/ 0x00000000, -/*024a*/ 0x00000000, -/*024b*/ 0x00000000, -/*024c*/ 0x000f0f00, -/*024d*/ 0x0000001e, -/*024e*/ 0x00000000, -/*024f*/ 0x01000300, -/*0250*/ 0x00000000, -/*0251*/ 0x00000000, -/*0252*/ 0x01000000, -/*0253*/ 0x00010101, -/*0254*/ 0x000e0e0e, -/*0255*/ 0x000c0c0c, -/*0256*/ 0x02060601, -/*0257*/ 0x00000000, -/*0258*/ 0x00000003, -/*0259*/ 0x00181703, -/*025a*/ 0x00280006, -/*025b*/ 0x00280016, -/*025c*/ 0x00000016, -/*025d*/ 0x00000000, -/*025e*/ 0x00000000, -/*025f*/ 0x00000000, -/*0260*/ 0x140a0000, -/*0261*/ 0x0005010a, -/*0262*/ 0x03018d03, -/*0263*/ 0x000a018d, -/*0264*/ 0x00060100, -/*0265*/ 0x01000006, -/*0266*/ 0x018e018e, -/*0267*/ 0x018e0100, -/*0268*/ 0x1111018e, -/*0269*/ 0x10010204, -/*026a*/ 0x09090650, -/*026b*/ 0x20110202, -/*026c*/ 0x00201000, -/*026d*/ 0x00201000, -/*026e*/ 0x04041000, -/*026f*/ 0x18020100, -/*0270*/ 0x00010118, -/*0271*/ 0x004b004a, -/*0272*/ 0x050f0000, -/*0273*/ 0x0c01021e, -/*0274*/ 0x34000000, -/*0275*/ 0x00000000, -/*0276*/ 0x00000000, -/*0277*/ 0x00000000, -/*0278*/ 0x0000d400, -/*0279*/ 0x0031002e, -/*027a*/ 0x00111136, -/*027b*/ 0x002e00d4, -/*027c*/ 0x11360031, -/*027d*/ 0x0000d411, -/*027e*/ 0x0031002e, -/*027f*/ 0x00111136, -/*0280*/ 0x002e00d4, -/*0281*/ 0x11360031, -/*0282*/ 0x0000d411, -/*0283*/ 0x0031002e, -/*0284*/ 0x00111136, -/*0285*/ 0x002e00d4, -/*0286*/ 0x11360031, -/*0287*/ 0x00d40011, -/*0288*/ 0x0031002e, -/*0289*/ 0x00111136, -/*028a*/ 0x002e00d4, -/*028b*/ 0x11360031, -/*028c*/ 0x0000d411, -/*028d*/ 0x0031002e, -/*028e*/ 0x00111136, -/*028f*/ 0x002e00d4, -/*0290*/ 0x11360031, -/*0291*/ 0x0000d411, -/*0292*/ 0x0031002e, -/*0293*/ 0x00111136, -/*0294*/ 0x002e00d4, -/*0295*/ 0x11360031, -/*0296*/ 0x02000011, -/*0297*/ 0x018d018d, -/*0298*/ 0x0c08018d, -/*0299*/ 0x1f121d22, -/*029a*/ 0x4301b344, -/*029b*/ 0x10172006, -/*029c*/ 0x1d220c10, -/*029d*/ 0x00001f12, -/*029e*/ 0x4301b344, -/*029f*/ 0x10172006, -/*02a0*/ 0x1d220c10, -/*02a1*/ 0x00001f12, -/*02a2*/ 0x4301b344, -/*02a3*/ 0x10172006, -/*02a4*/ 0x02000210, -/*02a5*/ 0x02000200, -/*02a6*/ 0x02000200, -/*02a7*/ 0x02000200, -/*02a8*/ 0x02000200, -/*02a9*/ 0x00000000, -/*02aa*/ 0x00000000, -/*02ab*/ 0x00000000, -/*02ac*/ 0x00000000, -/*02ad*/ 0x00000000, -/*02ae*/ 0x00000000, -/*02af*/ 0x00000000, -/*02b0*/ 0x00000000, -/*02b1*/ 0x00000000, -/*02b2*/ 0x00000000, -/*02b3*/ 0x00000000, -/*02b4*/ 0x00000000, -/*02b5*/ 0x00000400, -/*02b6*/ 0x15141312, -/*02b7*/ 0x11100f0e, -/*02b8*/ 0x080b0c0d, -/*02b9*/ 0x05040a09, -/*02ba*/ 0x01000706, -/*02bb*/ 0x00000302, -/*02bc*/ 0x01030201, -/*02bd*/ 0x00304c00, -/*02be*/ 0x0001e2f8, -/*02bf*/ 0x0000304c, -/*02c0*/ 0x0001e2f8, -/*02c1*/ 0x0000304c, -/*02c2*/ 0x0001e2f8, -/*02c3*/ 0x08000000, -/*02c4*/ 0x00000100, -/*02c5*/ 0x00000000, -/*02c6*/ 0x00000000, -/*02c7*/ 0x00000000, -/*02c8*/ 0x00000000, -/*02c9*/ 0x00000002 -}; diff --git a/ddr/lpddr4/init_dram_tbl_g2n.h b/ddr/lpddr4/init_dram_tbl_g2n.h deleted file mode 100644 index 2fde1bf..0000000 --- a/ddr/lpddr4/init_dram_tbl_g2n.h +++ /dev/null @@ -1,586 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define DDR_PHY_SLICE_REGSET_OFS_G2N 0x0800 -#define DDR_PHY_ADR_V_REGSET_OFS_G2N 0x0a00 -#define DDR_PHY_ADR_I_REGSET_OFS_G2N 0x0a80 -#define DDR_PHY_ADR_G_REGSET_OFS_G2N 0x0b80 -#define DDR_PI_REGSET_OFS_G2N 0x0200 - -#define DDR_PHY_SLICE_REGSET_SIZE_G2N 0x80 -#define DDR_PHY_ADR_V_REGSET_SIZE_G2N 0x80 -#define DDR_PHY_ADR_I_REGSET_SIZE_G2N 0x80 -#define DDR_PHY_ADR_G_REGSET_SIZE_G2N 0x80 -#define DDR_PI_REGSET_SIZE_G2N 0x100 - -#define DDR_PHY_SLICE_REGSET_NUM_G2N 101 -#define DDR_PHY_ADR_V_REGSET_NUM_G2N 37 -#define DDR_PHY_ADR_I_REGSET_NUM_G2N 37 -#define DDR_PHY_ADR_G_REGSET_NUM_G2N 87 -#define DDR_PI_REGSET_NUM_G2N 286 - -static const uint32_t DDR_PHY_SLICE_REGSET_G2N[DDR_PHY_SLICE_REGSET_NUM_G2N] = { -/*0800*/ 0x76543210, -/*0801*/ 0x0004f008, -/*0802*/ 0x00020200, -/*0803*/ 0x00000000, -/*0804*/ 0x00000000, -/*0805*/ 0x00010000, -/*0806*/ 0x036e6e0e, -/*0807*/ 0x026e6e0e, -/*0808*/ 0x00000103, -/*0809*/ 0x00040001, -/*080a*/ 0x00000103, -/*080b*/ 0x00000001, -/*080c*/ 0x00000000, -/*080d*/ 0x00000000, -/*080e*/ 0x00000100, -/*080f*/ 0x001800c0, -/*0810*/ 0x020100b0, -/*0811*/ 0x00030020, -/*0812*/ 0x00000000, -/*0813*/ 0x00000000, -/*0814*/ 0x0000aaaa, -/*0815*/ 0x00005555, -/*0816*/ 0x0000b5b5, -/*0817*/ 0x00004a4a, -/*0818*/ 0x00000000, -/*0819*/ 0x09000000, -/*081a*/ 0x04080000, -/*081b*/ 0x08040000, -/*081c*/ 0x00000004, -/*081d*/ 0x00800710, -/*081e*/ 0x000f000c, -/*081f*/ 0x00000100, -/*0820*/ 0x55aa55aa, -/*0821*/ 0x33cc33cc, -/*0822*/ 0x0ff00ff0, -/*0823*/ 0x0f0ff0f0, -/*0824*/ 0x00018e38, -/*0825*/ 0x00000000, -/*0826*/ 0x00000000, -/*0827*/ 0x00000000, -/*0828*/ 0x00000000, -/*0829*/ 0x00000000, -/*082a*/ 0x00000000, -/*082b*/ 0x00000000, -/*082c*/ 0x00000000, -/*082d*/ 0x00000000, -/*082e*/ 0x00000000, -/*082f*/ 0x00000000, -/*0830*/ 0x00000000, -/*0831*/ 0x00000000, -/*0832*/ 0x00000000, -/*0833*/ 0x00000000, -/*0834*/ 0x00000000, -/*0835*/ 0x00000000, -/*0836*/ 0x00000000, -/*0837*/ 0x00000000, -/*0838*/ 0x00000000, -/*0839*/ 0x00000000, -/*083a*/ 0x00000104, -/*083b*/ 0x00082020, -/*083c*/ 0x08200820, -/*083d*/ 0x08200820, -/*083e*/ 0x08200820, -/*083f*/ 0x08200820, -/*0840*/ 0x08200820, -/*0841*/ 0x00000000, -/*0842*/ 0x00000000, -/*0843*/ 0x03000300, -/*0844*/ 0x03000300, -/*0845*/ 0x03000300, -/*0846*/ 0x03000300, -/*0847*/ 0x00000300, -/*0848*/ 0x00000000, -/*0849*/ 0x00000000, -/*084a*/ 0x00000000, -/*084b*/ 0x00000000, -/*084c*/ 0x00000000, -/*084d*/ 0x00a000a0, -/*084e*/ 0x00a000a0, -/*084f*/ 0x00a000a0, -/*0850*/ 0x00a000a0, -/*0851*/ 0x00a000a0, -/*0852*/ 0x00a000a0, -/*0853*/ 0x00a000a0, -/*0854*/ 0x00a000a0, -/*0855*/ 0x00a000a0, -/*0856*/ 0x01040119, -/*0857*/ 0x00000200, -/*0858*/ 0x01000000, -/*0859*/ 0x00000200, -/*085a*/ 0x00000004, -/*085b*/ 0x4041a151, -/*085c*/ 0x0141a0a0, -/*085d*/ 0x0000c0c0, -/*085e*/ 0x0e0c000e, -/*085f*/ 0x10001000, -/*0860*/ 0x0c073e42, -/*0861*/ 0x000f0c28, -/*0862*/ 0x00e00140, -/*0863*/ 0x000c0020, -/*0864*/ 0x00000203 -}; - -static const uint32_t DDR_PHY_ADR_V_REGSET_G2N[DDR_PHY_ADR_V_REGSET_NUM_G2N] = { -/*0a00*/ 0x00000000, -/*0a01*/ 0x00000000, -/*0a02*/ 0x00000000, -/*0a03*/ 0x00000000, -/*0a04*/ 0x00000000, -/*0a05*/ 0x00000000, -/*0a06*/ 0x00000000, -/*0a07*/ 0x01000000, -/*0a08*/ 0x00020000, -/*0a09*/ 0x00000000, -/*0a0a*/ 0x00000000, -/*0a0b*/ 0x00000000, -/*0a0c*/ 0x00400000, -/*0a0d*/ 0x00000080, -/*0a0e*/ 0x00dcba98, -/*0a0f*/ 0x03000000, -/*0a10*/ 0x00000200, -/*0a11*/ 0x00000000, -/*0a12*/ 0x00000000, -/*0a13*/ 0x00000000, -/*0a14*/ 0x0000002a, -/*0a15*/ 0x00000015, -/*0a16*/ 0x00000015, -/*0a17*/ 0x0000002a, -/*0a18*/ 0x00000033, -/*0a19*/ 0x0000000c, -/*0a1a*/ 0x0000000c, -/*0a1b*/ 0x00000033, -/*0a1c*/ 0x0a418820, -/*0a1d*/ 0x003f0000, -/*0a1e*/ 0x0000013f, -/*0a1f*/ 0x0002c06e, -/*0a20*/ 0x02c002c0, -/*0a21*/ 0x02c002c0, -/*0a22*/ 0x000002c0, -/*0a23*/ 0x42080010, -/*0a24*/ 0x0000033e -}; - -static const uint32_t DDR_PHY_ADR_I_REGSET_G2N[DDR_PHY_ADR_I_REGSET_NUM_G2N] = { -/*0a80*/ 0x00000000, -/*0a81*/ 0x00000000, -/*0a82*/ 0x00000000, -/*0a83*/ 0x00000000, -/*0a84*/ 0x00000000, -/*0a85*/ 0x00000000, -/*0a86*/ 0x00000000, -/*0a87*/ 0x01000000, -/*0a88*/ 0x00020000, -/*0a89*/ 0x00000000, -/*0a8a*/ 0x00000000, -/*0a8b*/ 0x00000000, -/*0a8c*/ 0x00400000, -/*0a8d*/ 0x00000080, -/*0a8e*/ 0x00000000, -/*0a8f*/ 0x03000000, -/*0a90*/ 0x00000200, -/*0a91*/ 0x00000000, -/*0a92*/ 0x00000000, -/*0a93*/ 0x00000000, -/*0a94*/ 0x0000002a, -/*0a95*/ 0x00000015, -/*0a96*/ 0x00000015, -/*0a97*/ 0x0000002a, -/*0a98*/ 0x00000033, -/*0a99*/ 0x0000000c, -/*0a9a*/ 0x0000000c, -/*0a9b*/ 0x00000033, -/*0a9c*/ 0x00000000, -/*0a9d*/ 0x00000000, -/*0a9e*/ 0x00000000, -/*0a9f*/ 0x0002c06e, -/*0aa0*/ 0x02c002c0, -/*0aa1*/ 0x02c002c0, -/*0aa2*/ 0x000002c0, -/*0aa3*/ 0x42080010, -/*0aa4*/ 0x0000033e -}; - -static const uint32_t DDR_PHY_ADR_G_REGSET_G2N[DDR_PHY_ADR_G_REGSET_NUM_G2N] = { -/*0b80*/ 0x00000000, -/*0b81*/ 0x00000100, -/*0b82*/ 0x00000000, -/*0b83*/ 0x00050000, -/*0b84*/ 0x00000000, -/*0b85*/ 0x0004000f, -/*0b86*/ 0x00280080, -/*0b87*/ 0x02005502, -/*0b88*/ 0x00000000, -/*0b89*/ 0x00000000, -/*0b8a*/ 0x00000000, -/*0b8b*/ 0x00000050, -/*0b8c*/ 0x00000000, -/*0b8d*/ 0x01010100, -/*0b8e*/ 0x00010000, -/*0b8f*/ 0x00000000, -/*0b90*/ 0x00000101, -/*0b91*/ 0x00000000, -/*0b92*/ 0x00000000, -/*0b93*/ 0x00000000, -/*0b94*/ 0x00000000, -/*0b95*/ 0x00005064, -/*0b96*/ 0x01421142, -/*0b97*/ 0x00000142, -/*0b98*/ 0x00000000, -/*0b99*/ 0x000f1600, -/*0b9a*/ 0x0f160f16, -/*0b9b*/ 0x0f160f16, -/*0b9c*/ 0x00000003, -/*0b9d*/ 0x0002c000, -/*0b9e*/ 0x02c002c0, -/*0b9f*/ 0x000002c0, -/*0ba0*/ 0x08040201, -/*0ba1*/ 0x03421342, -/*0ba2*/ 0x00000342, -/*0ba3*/ 0x00000000, -/*0ba4*/ 0x00000000, -/*0ba5*/ 0x05030000, -/*0ba6*/ 0x00010700, -/*0ba7*/ 0x00000014, -/*0ba8*/ 0x00027f6e, -/*0ba9*/ 0x047f027f, -/*0baa*/ 0x00027f6e, -/*0bab*/ 0x00047f6e, -/*0bac*/ 0x0003554f, -/*0bad*/ 0x0001554f, -/*0bae*/ 0x0001554f, -/*0baf*/ 0x0001554f, -/*0bb0*/ 0x0001554f, -/*0bb1*/ 0x00003fee, -/*0bb2*/ 0x0001554f, -/*0bb3*/ 0x00003fee, -/*0bb4*/ 0x0001554f, -/*0bb5*/ 0x00027f6e, -/*0bb6*/ 0x0001554f, -/*0bb7*/ 0x00004011, -/*0bb8*/ 0x00004410, -/*0bb9*/ 0x00000000, -/*0bba*/ 0x00000000, -/*0bbb*/ 0x00000000, -/*0bbc*/ 0x00000265, -/*0bbd*/ 0x00000000, -/*0bbe*/ 0x00040401, -/*0bbf*/ 0x00000000, -/*0bc0*/ 0x03000000, -/*0bc1*/ 0x00000020, -/*0bc2*/ 0x00000000, -/*0bc3*/ 0x00000000, -/*0bc4*/ 0x04102006, -/*0bc5*/ 0x00041020, -/*0bc6*/ 0x01c98c98, -/*0bc7*/ 0x00400000, -/*0bc8*/ 0x00000000, -/*0bc9*/ 0x0001ffff, -/*0bca*/ 0x00000000, -/*0bcb*/ 0x00000000, -/*0bcc*/ 0x00000001, -/*0bcd*/ 0x00000000, -/*0bce*/ 0x00000000, -/*0bcf*/ 0x00000000, -/*0bd0*/ 0x76543210, -/*0bd1*/ 0x06010198, -/*0bd2*/ 0x00000000, -/*0bd3*/ 0x00000000, -/*0bd4*/ 0x04070000, -/*0bd5*/ 0x00000001, -/*0bd6*/ 0x00000f00 -}; - -static const uint32_t DDR_PI_REGSET_G2N[DDR_PI_REGSET_NUM_G2N] = { -/*0200*/ 0x00000b00, -/*0201*/ 0x00000101, -/*0202*/ 0x01640000, -/*0203*/ 0x00000014, -/*0204*/ 0x00000014, -/*0205*/ 0x00000014, -/*0206*/ 0x00000014, -/*0207*/ 0x00000000, -/*0208*/ 0x00000000, -/*0209*/ 0x0000ffff, -/*020a*/ 0x00000000, -/*020b*/ 0x0000ffff, -/*020c*/ 0x00000000, -/*020d*/ 0x0000ffff, -/*020e*/ 0x0000304c, -/*020f*/ 0x00000200, -/*0210*/ 0x00000200, -/*0211*/ 0x00000200, -/*0212*/ 0x00000200, -/*0213*/ 0x0000304c, -/*0214*/ 0x00000200, -/*0215*/ 0x00000200, -/*0216*/ 0x00000200, -/*0217*/ 0x00000200, -/*0218*/ 0x0000304c, -/*0219*/ 0x00000200, -/*021a*/ 0x00000200, -/*021b*/ 0x00000200, -/*021c*/ 0x00000200, -/*021d*/ 0x00010000, -/*021e*/ 0x00000003, -/*021f*/ 0x01000001, -/*0220*/ 0x00000000, -/*0221*/ 0x00000000, -/*0222*/ 0x00000000, -/*0223*/ 0x00000000, -/*0224*/ 0x00000000, -/*0225*/ 0x00000000, -/*0226*/ 0x00000000, -/*0227*/ 0x00000000, -/*0228*/ 0x00000000, -/*0229*/ 0x00000000, -/*022a*/ 0x00000000, -/*022b*/ 0x00000000, -/*022c*/ 0x00000000, -/*022d*/ 0x00000000, -/*022e*/ 0x00000000, -/*022f*/ 0x00000000, -/*0230*/ 0x0f000101, -/*0231*/ 0x084d3129, -/*0232*/ 0x0e0c0004, -/*0233*/ 0x000e5000, -/*0234*/ 0x01000250, -/*0235*/ 0x00000003, -/*0236*/ 0x00000046, -/*0237*/ 0x000000cf, -/*0238*/ 0x00001826, -/*0239*/ 0x000000cf, -/*023a*/ 0x00001826, -/*023b*/ 0x00000000, -/*023c*/ 0x00000000, -/*023d*/ 0x00000000, -/*023e*/ 0x00000000, -/*023f*/ 0x00000000, -/*0240*/ 0x00000000, -/*0241*/ 0x00000000, -/*0242*/ 0x00000000, -/*0243*/ 0x00000000, -/*0244*/ 0x00000000, -/*0245*/ 0x01000000, -/*0246*/ 0x00040404, -/*0247*/ 0x01280a00, -/*0248*/ 0x00000001, -/*0249*/ 0x00000000, -/*024a*/ 0x03000f00, -/*024b*/ 0x00200020, -/*024c*/ 0x00000020, -/*024d*/ 0x00000000, -/*024e*/ 0x00000000, -/*024f*/ 0x00010002, -/*0250*/ 0x01010001, -/*0251*/ 0x02010100, -/*0252*/ 0x08040402, -/*0253*/ 0x00000008, -/*0254*/ 0x00000000, -/*0255*/ 0x04080803, -/*0256*/ 0x00001515, -/*0257*/ 0x00000000, -/*0258*/ 0x000000aa, -/*0259*/ 0x00000055, -/*025a*/ 0x000000b5, -/*025b*/ 0x0000004a, -/*025c*/ 0x00000056, -/*025d*/ 0x000000a9, -/*025e*/ 0x000000a9, -/*025f*/ 0x000000b5, -/*0260*/ 0x00000000, -/*0261*/ 0x00000000, -/*0262*/ 0x0f000000, -/*0263*/ 0x00001e0f, -/*0264*/ 0x000007d0, -/*0265*/ 0x01000300, -/*0266*/ 0x00000100, -/*0267*/ 0x00000000, -/*0268*/ 0x00000000, -/*0269*/ 0x01000000, -/*026a*/ 0x00010101, -/*026b*/ 0x000e0e0e, -/*026c*/ 0x000c0c0c, -/*026d*/ 0x01060601, -/*026e*/ 0x04041717, -/*026f*/ 0x00000004, -/*0270*/ 0x00000300, -/*0271*/ 0x17030000, -/*0272*/ 0x00060018, -/*0273*/ 0x00160028, -/*0274*/ 0x00160028, -/*0275*/ 0x00000000, -/*0276*/ 0x00000000, -/*0277*/ 0x00000000, -/*0278*/ 0x0a000000, -/*0279*/ 0x00010a14, -/*027a*/ 0x00030005, -/*027b*/ 0x0003018d, -/*027c*/ 0x000a018d, -/*027d*/ 0x00060100, -/*027e*/ 0x01000006, -/*027f*/ 0x018e018e, -/*0280*/ 0x018e0100, -/*0281*/ 0x1e1a018e, -/*0282*/ 0x1e1a1e1a, -/*0283*/ 0x01010204, -/*0284*/ 0x06501001, -/*0285*/ 0x090d0a07, -/*0286*/ 0x090d0a07, -/*0287*/ 0x0811180f, -/*0288*/ 0x00ff1102, -/*0289*/ 0x00ff1000, -/*028a*/ 0x00ff1000, -/*028b*/ 0x04041000, -/*028c*/ 0x18020100, -/*028d*/ 0x01010018, -/*028e*/ 0x005f005f, -/*028f*/ 0x005f005f, -/*0290*/ 0x050f0000, -/*0291*/ 0x051e051e, -/*0292*/ 0x0c01021e, -/*0293*/ 0x00000c0c, -/*0294*/ 0x00003400, -/*0295*/ 0x00000000, -/*0296*/ 0x00000000, -/*0297*/ 0x00000000, -/*0298*/ 0x00000000, -/*0299*/ 0x002e00d4, -/*029a*/ 0x11360031, -/*029b*/ 0x00d41611, -/*029c*/ 0x0031002e, -/*029d*/ 0x16111136, -/*029e*/ 0x002e00d4, -/*029f*/ 0x11360031, -/*02a0*/ 0x00001611, -/*02a1*/ 0x002e00d4, -/*02a2*/ 0x11360031, -/*02a3*/ 0x00d41611, -/*02a4*/ 0x0031002e, -/*02a5*/ 0x16111136, -/*02a6*/ 0x002e00d4, -/*02a7*/ 0x11360031, -/*02a8*/ 0x00001611, -/*02a9*/ 0x002e00d4, -/*02aa*/ 0x11360031, -/*02ab*/ 0x00d41611, -/*02ac*/ 0x0031002e, -/*02ad*/ 0x16111136, -/*02ae*/ 0x002e00d4, -/*02af*/ 0x11360031, -/*02b0*/ 0x00001611, -/*02b1*/ 0x002e00d4, -/*02b2*/ 0x11360031, -/*02b3*/ 0x00d41611, -/*02b4*/ 0x0031002e, -/*02b5*/ 0x16111136, -/*02b6*/ 0x002e00d4, -/*02b7*/ 0x11360031, -/*02b8*/ 0x00001611, -/*02b9*/ 0x00018d00, -/*02ba*/ 0x018d018d, -/*02bb*/ 0x1d220c08, -/*02bc*/ 0x00001f12, -/*02bd*/ 0x4301b344, -/*02be*/ 0x17032006, -/*02bf*/ 0x220c1010, -/*02c0*/ 0x001f121d, -/*02c1*/ 0x4301b344, -/*02c2*/ 0x17062006, -/*02c3*/ 0x220c1010, -/*02c4*/ 0x001f121d, -/*02c5*/ 0x4301b344, -/*02c6*/ 0x17182006, -/*02c7*/ 0x00021010, -/*02c8*/ 0x00020002, -/*02c9*/ 0x00020002, -/*02ca*/ 0x00020002, -/*02cb*/ 0x00020002, -/*02cc*/ 0x00000002, -/*02cd*/ 0x00000000, -/*02ce*/ 0x00000000, -/*02cf*/ 0x00000000, -/*02d0*/ 0x00000000, -/*02d1*/ 0x00000000, -/*02d2*/ 0x00000000, -/*02d3*/ 0x00000000, -/*02d4*/ 0x00000000, -/*02d5*/ 0x00000000, -/*02d6*/ 0x00000000, -/*02d7*/ 0x00000000, -/*02d8*/ 0x00000000, -/*02d9*/ 0x00000400, -/*02da*/ 0x15141312, -/*02db*/ 0x11100f0e, -/*02dc*/ 0x080b0c0d, -/*02dd*/ 0x05040a09, -/*02de*/ 0x01000706, -/*02df*/ 0x00000302, -/*02e0*/ 0x01030201, -/*02e1*/ 0x00304c08, -/*02e2*/ 0x0001e2f8, -/*02e3*/ 0x0000304c, -/*02e4*/ 0x0001e2f8, -/*02e5*/ 0x0000304c, -/*02e6*/ 0x0001e2f8, -/*02e7*/ 0x08000000, -/*02e8*/ 0x00000100, -/*02e9*/ 0x00000000, -/*02ea*/ 0x00000000, -/*02eb*/ 0x00000000, -/*02ec*/ 0x00000000, -/*02ed*/ 0x00010000, -/*02ee*/ 0x00000000, -/*02ef*/ 0x00000000, -/*02f0*/ 0x00000000, -/*02f1*/ 0x00000000, -/*02f2*/ 0x00000000, -/*02f3*/ 0x00000000, -/*02f4*/ 0x00000000, -/*02f5*/ 0x00000000, -/*02f6*/ 0x00000000, -/*02f7*/ 0x00000000, -/*02f8*/ 0x00000000, -/*02f9*/ 0x00000000, -/*02fa*/ 0x00000000, -/*02fb*/ 0x00000000, -/*02fc*/ 0x00000000, -/*02fd*/ 0x00000000, -/*02fe*/ 0x00000000, -/*02ff*/ 0x00000000, -/*0300*/ 0x00000000, -/*0301*/ 0x00000000, -/*0302*/ 0x00000000, -/*0303*/ 0x00000000, -/*0304*/ 0x00000000, -/*0305*/ 0x00000000, -/*0306*/ 0x00000000, -/*0307*/ 0x00000000, -/*0308*/ 0x00000000, -/*0309*/ 0x00000000, -/*030a*/ 0x00000000, -/*030b*/ 0x00000000, -/*030c*/ 0x00000000, -/*030d*/ 0x00000000, -/*030e*/ 0x00000000, -/*030f*/ 0x00050002, -/*0310*/ 0x015c0057, -/*0311*/ 0x01000100, -/*0312*/ 0x01020001, -/*0313*/ 0x00010300, -/*0314*/ 0x05000104, -/*0315*/ 0x01060001, -/*0316*/ 0x00010700, -/*0317*/ 0x00000000, -/*0318*/ 0x00000000, -/*0319*/ 0x00000001, -/*031a*/ 0x00000000, -/*031b*/ 0x00000000, -/*031c*/ 0x00000000, -/*031d*/ 0x20080101 -}; diff --git a/ddrcheck.c b/ddrcheck.c deleted file mode 100644 index dea4ae7..0000000 --- a/ddrcheck.c +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "dgtable.h" -#include "reg_rzg2.h" -#include "ramckmdl.h" -#include "dmaspi.h" -#include "devdrv.h" -#include "ddrcheck.h" - -uintptr_t gErrDdrAdd; -uint32_t gErrDdrData,gTrueDdrData; -uintptr_t gSubErrAdd; -uintptr_t gSubErrData; -uintptr_t gSubTrueData; - -extern char gKeyBuf[64]; - -static uint32_t PutDdrErrInfo(void) -{ - char str[64]; - - PutStr(" error address : H'",0); Data2HexAscii_64(gErrDdrAdd,str,CPU_BYTE_SIZE); PutStr(str,1); - PutStr(" error data : H'",0); Data2HexAscii(gErrDdrData,str,4); PutStr(str,1); - PutStr(" true data : H'",0); Data2HexAscii(gTrueDdrData,str,4); PutStr(str,1); -} - -static uint32_t CkExtendDdrRamCheck(void* ramAddr) -{ - volatile uint32_t *read_adr; - uint32_t data; - uint32_t loop, i; - char str[64]; - - read_adr = (uint32_t *)ramAddr; - - PutStr("Data=0x5A5A5A5A",0); - - /* Write */ - data = 0x5A5A5A5A; - for (loop = 0; loop < 0x100000; loop++) - { - read_adr[loop] = data; - } - /* Verify */ - data = 0x5A5A5A5A; - for (loop = 0; loop < 0x100000; loop++) - { - if (read_adr[loop] != data) - { - gErrDdrAdd = (uintptr_t)&read_adr[loop]; - gErrDdrData = read_adr[loop]; - gTrueDdrData = data; - return(ERROR_END); - } - } - DelStr(15); - PutStr("Data=0xA5A5A5A5",0); - - /* Write */ - data = 0xA5A5A5A5; - for (loop = 0; loop < 0x100000; loop++) - { - read_adr[loop] = data; - } - /* Verify */ - data = 0xA5A5A5A5; - for (loop = 0; loop < 0x100000; loop++) - { - if (read_adr[loop] != data) - { - gErrDdrAdd = (uintptr_t)&read_adr[loop]; - gErrDdrData = read_adr[loop]; - gTrueDdrData = data; - return(ERROR_END); - } - } - DelStr(15); - PutStr("Data=0x12345678",0); - - /* Write */ - data = 0x12345678; - for (loop = 0; loop < 0x100000; loop++) - { - read_adr[loop] = data; - data += 0x11111111; - } - /* Verify */ - data = 0x12345678; - for (loop = 0; loop < 0x100000; loop++) - { - if (read_adr[loop] != data) - { - gErrDdrAdd = (uintptr_t)&read_adr[loop]; - gErrDdrData = read_adr[loop]; - gTrueDdrData = data; - return(ERROR_END); - } - data += 0x11111111; - } - DelStr(15); - return(NORMAL_END); -} - -static int32_t CheckAndFillData8Bit( uint8_t *startAddr, uint8_t *endAddr, uint8_t writeData, uint8_t checkData ) -{ - volatile uint8_t *pData; - pData = (uint8_t *)startAddr; - while(1) - { - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (*pData!=checkData) break; *(pData++) = writeData; - if (pData >= endAddr) return NORMAL_END; - } - gSubErrAdd = (uint64_t)pData; - gSubErrData = (uint64_t)*pData; - gSubTrueData = (uint64_t)checkData; - return ERROR_END; -} - -static int32_t FillData8Bit(uint8_t *startAddr, uint8_t *endAddr, uint8_t writeData) -{ - volatile uint8_t *pData; - pData = (uint8_t *)startAddr; - while(1){ - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - *(pData++) = writeData; - if( pData >= endAddr ) return NORMAL_END; - } - return NORMAL_END; -} - -static int32_t CheckData8Bit( uint8_t *startAddr, uint8_t *endAddr, uint8_t checkData ) -{ - volatile uint8_t *pData; - pData = (uint8_t *)startAddr; - while(1) - { - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if(*(pData++)!=checkData) break; - if (pData >= endAddr) return NORMAL_END; - } - pData--; - gSubErrAdd = (uint64_t)pData; - gSubErrData = (uint64_t)*pData; - gSubTrueData = (uint64_t)checkData; - return ERROR_END; -} - -static int32_t WriteIncData8Bit( uint8_t *startAddr, uint8_t *endAddr, uint8_t startData ) -{ - volatile uint8_t *pData; - pData = (uint8_t *)startAddr; - while(1) - { - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - *(pData++) = (startData++); - if (pData >= endAddr) return NORMAL_END; - } - return NORMAL_END; -} - -static int32_t CheckIncData8Bit( uint8_t *startAddr, uint8_t *endAddr, uint8_t startData ) -{ - volatile uint8_t *pData; - pData = (uint8_t *)startAddr; - while(1) - { - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if(*(pData++)!=(startData++)) break; - if( pData >= endAddr ) return NORMAL_END; - } - pData--; - startData--; - gSubErrAdd = (uint64_t)pData; - gSubErrData = (uint64_t)*pData; - gSubTrueData = (uint64_t)startData; - return ERROR_END; -} - -static char DecodeForm5(uintptr_t *para1st, uintptr_t *para2nd, uint32_t *setPara) -{ - char tmp[64],tmp2[64],chPtr,chPtr2,endCh,getCnt,value; - uintptr_t tmpData; - - *setPara = 0; - chPtr = getCnt = 0; - do - { - endCh = GetStrBlk(gKeyBuf,tmp,&chPtr,0); - switch(getCnt) - { - /*********** "RAMCK" Block parameter *************/ - case 0: - if (endCh == 0) - { - /* non set start Add */ - return(2); - } - break; - /*********** Ana 1st parameter *******************/ - case 1: - value = HexAscii2Data_64((unsigned char*)tmp,para1st); - if (value == 0) - { - *setPara |= 0x01; - } - else - { - return(1); - } - break; - /*********** Ana 2nd parameter *******************/ - case 2: - value = HexAscii2Data_64((unsigned char*)tmp,&tmpData); - if (value == 0) - { - *setPara |= 0x02; - if (*para1st > tmpData) - { - return(2); - } - else - { - *setPara |= 0x02; - *para2nd = (tmpData - *para1st) + 0x01 ; - } - } - else if (value == 3) - { - /* find @ */ - chPtr2 = 1; - GetStrBlk(tmp,tmp2,&chPtr2,0); - if (HexAscii2Data_64((unsigned char*)tmp2,para2nd)) - { - return(1); - } - *setPara |= 0x02; - } - else - { - return(1); - } - break; - } - if (endCh == ';') - { - if (GetStrBlk(gKeyBuf,tmp,&chPtr,0)) - { - return(1); - } - endCh=0; - *setPara |= 0x08; - } - getCnt++; - } while(endCh); - return(0); -} - -static int32_t TPRAMCK( uint8_t *startAddr, uint8_t *endAddr ) -{ - FillData8Bit(startAddr, endAddr, 0x00 ); - if (CheckAndFillData8Bit(startAddr, endAddr, 0x55, 0x00)) - { - return ERROR_END; - } - if (CheckAndFillData8Bit(startAddr, endAddr, 0xAA, 0x55)) - { - return ERROR_END; - } - if (CheckAndFillData8Bit(startAddr, endAddr, 0xFF, 0xAA)) - { - return ERROR_END; - } - if (CheckData8Bit(startAddr, endAddr, 0xFF)) - { - return ERROR_END; - } - WriteIncData8Bit(startAddr, endAddr, 0x00); - if (CheckIncData8Bit(startAddr, endAddr, 0x00)) - { - return ERROR_END; - } - return NORMAL_END; -} - -void dgDdrTest(void) -{ - uint32_t readData; - - uint32_t product; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - - PutStr("=== DDR R/W CHECK ====",1); - switch (product) - { - case PRR_PRODUCT_G2E: - case PRR_PRODUCT_G2N: - if (product == PRR_PRODUCT_G2E) - { - PutStr("=== RZ/G2E (Memory controller is only channel 1) ===",1); - } - else - { - PutStr("=== RZ/G2N (Memory controller is only channel 1) ===",1); - } - readData = *((volatile uint32_t*)0x0000000410000000); //Access Check - PutStr("Check:0x04_10000000 ... ",0); - if (CkExtendDdrRamCheck((void*)0x0000000410000000)) - { - PutStr(" Fail!",1); - PutDdrErrInfo(); - return; - } - else - { - PutStr(" Pass!",1); - } - PutStr("Check:0x04_40000000 ... ",0); - if (CkExtendDdrRamCheck((void*)0x0000000440000000)) - { - PutStr(" Fail!",1); - PutDdrErrInfo(); - return; - } - else - { - PutStr(" Pass!",1); - } - break; - case PRR_PRODUCT_G2H: - case PRR_PRODUCT_G2M: - if (product == PRR_PRODUCT_G2H) - { - PutStr("=== Memory map RZ/G2H ====",1); - - } - else - { - PutStr("=== Memory map RZ/G2M ====",1); - } - //CH0 Check - readData = *((volatile uint32_t*)0x0000000410000000); //Access Check - PutStr("Check:0x04_10000000 ... ",0); - if (CkExtendDdrRamCheck((void*)0x0000000410000000)) - { - PutStr(" Fail!",1); - PutDdrErrInfo(); - PutStr("Next channel Test OK?(y/n)",0); - if (WaitKeyIn_YorN()) - { - // Return1=N - DelStr(26); - return; - } - DelStr(26); - } - else - { - PutStr(" Pass!",1); - } - //CH2 Check - PutStr("Check:0x06_00000100 ... ",0); - if (CkExtendDdrRamCheck((void*)0x0000000600000100)) - { - PutStr(" Fail!",1); - PutDdrErrInfo(); - return; - } - else - { - PutStr(" Pass!",1); - } - break; - default: - break; - } -} - -void dgRamTest(void) -{ - uint64_t ramck1st,ramck2nd; - uint32_t setPara; - - char decRtn; - char str[10]; - - ramck1st=ramck2nd=0x0; - decRtn = DecodeForm5(&ramck1st,&ramck2nd,&setPara); - if (!(setPara&0x3)) - { - PutStr("Syntax Error",1); return; - } - else if (decRtn==1) - { - PutStr("Syntax Error",1); return; - } - else if (decRtn==2) - { - PutStr("Address Size Error",1); return; - } - else - { - PutStr("== RAM CHECK (Byte Access) ===",1); - PutStr("- Marching Data Check --------",1); - PutStr(" [ Write H'00 ]",1); - PutStr(" [ Check H'00 -> Write H'55 ]",1); - PutStr(" [ Check H'55 -> Write H'AA ]",1); - PutStr(" [ Check H'AA -> Write H'FF ]",1); - PutStr(" [ Check H'FF ]",1); - PutStr("- Decoder Pattern Check ------",1); - PutStr(" [ Write H'00,H'01,H'02 ... ]",1); - PutStr(" [ Check H'00,H'01,H'02 ... ]",1); - PutStr("CHECK RESULT",0); - } - if (TPRAMCK( ((uint8_t *)ramck1st),((uint8_t *)(ramck1st+ramck2nd)) ) ) - { - PutStr("---->NG",1); - Data2HexAscii_64(gSubErrAdd,str,CPU_BYTE_SIZE); - PutStr("ERROR ADDRESS:",0); PutStr(str,1); - Data2HexAscii_64(gSubErrData,str,CPU_BYTE_SIZE); - PutStr("ERROR DATA :",0); PutStr(str,1); - Data2HexAscii_64(gSubTrueData,str,CPU_BYTE_SIZE); - PutStr("TRUE DATA :",0); PutStr(str,1); - return; - } - else - { - PutStr("---->OK",1); - } -} diff --git a/devdrv.c b/devdrv.c index 442bf58..ddc484e 100644 --- a/devdrv.c +++ b/devdrv.c @@ -1,41 +1,31 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + #include "common.h" #include "devdrv.h" #include "scifdrv.h" -#if USB_ENABLE == 1 -uint32_t gTerminal = SCIF2_TERMINAL; -#endif /* USB_ENABLE == 1 */ /************************ PutChar * @@ -43,18 +33,7 @@ uint32_t gTerminal = SCIF2_TERMINAL; int32_t PutChar(char outChar) { -#if USB_ENABLE == 1 - if (gTerminal == USB_TERMINAL) - { - PutCharUSB(outChar); - } - else - { - PutCharSCIF2(outChar); - } -#else /* USB_ENABLE == 1 */ PutCharSCIF2(outChar); -#endif /* USB_ENABLE == 1 */ return(0); } @@ -64,22 +43,12 @@ int32_t PutChar(char outChar) int32_t GetChar(char *inChar) { -#if USB_ENABLE == 1 - if (gTerminal == USB_TERMINAL) - { - GetCharUSB(inChar); - } - else - { - GetCharSCIF2(inChar); - } -#else /* USB_ENABLE == 1 */ GetCharSCIF2(inChar); -#endif /* USB_ENABLE == 1 */ return(0); } -int32_t WaitPutCharSendEnd(void) +int32_t GetCharTimeOut(char *inChar, uint64_t us) { - WaitPutScif2SendEnd(); + return GetCharTimeOutSCIF2(inChar, us); } + diff --git a/dg_emmc_access.c b/dg_emmc_access.c index 364493e..bf77cb2 100644 --- a/dg_emmc_access.c +++ b/dg_emmc_access.c @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #include "emmc_config.h" #include "emmc_hal.h" @@ -39,14 +31,8 @@ #include "common.h" #include "types.h" -#include "reg_rzg2.h" #include "ramckmdl.h" -#include "dgmodul1.h" #include "devdrv.h" -#include "boardid.h" -#if USB_ENABLE == 1 -#include "usb_lib.h" -#endif /* USB_ENABLE == 1 */ #define SIZE2SECTOR(x) ( (x) >> 9 ) /* 512Byte */ @@ -54,13 +40,11 @@ #define EMMC_MAX_SECTOR ((SIZE2SECTOR( EMMC_MAX_SIZE * 1024 )) * 1024 * 1024 ) /* MAX SECTOR (8Gbyte) */ #define MULTI_PARTITION_SIZE (128 * 1024) /* 128 Kbyte */ -#define EMMC_WORK_DRAM_SADD 0x50000000U -#define EMMC_WORK_DRAM_EADD_2M 0x501FFFFFU -#define EMMC_WORK_DRAM_EADD_4M 0x503FFFFFU -#define EMMC_WORK_DRAM_EADD_16M 0x50FFFFFFU -#define EMMC_WORK_DRAM_EADD_64M 0x53FFFFFFU -#define EMMC_WORK_DRAM_EADD_512M 0x6FFFFFFFU -#define EMMC_WORK_DRAM_SECTOR_MAX ((EMMC_WORK_DRAM_EADD_512M - EMMC_WORK_DRAM_SADD + 1)>>9) +#define BASEADDR_RAMB0 0xB6000000 +#define EMMC_WORK_RAMB_SADD BASEADDR_RAMB0 +#define EMMC_WORK_RAMB_MAX_SIZ 0x100000 //1Mbyte +#define EMMC_WORK_RAMB_EADD 0xB60FFFFF +#define EMMC_WORK_RAMB_SECTOR_MAX (EMMC_WORK_RAMB_MAX_SIZ >>9) #define EMMC_SECURERAM_SADD 0xE6300000U #define EMMC_SECURERAM_EADD 0xE635FFFFU @@ -68,6 +52,8 @@ #define DMA_TRANSFER_SIZE (0x20) /* DMA Transfer size = 32 Bytes*/ #define DMA_ROUNDUP_VALUE (0xFFFFFFE0) +#define DATA_RECV_TIMEOUT 3000*1000 /*3000ms*/ + typedef enum { EMMC_PARTITION_USER_AREA = 0, @@ -97,20 +83,17 @@ typedef struct typedef enum { - EMMC_WRITE_MOT = 0, EMMC_WRITE_BINARY, } EMMC_WRITE_COMMAND; -static void dg_emmc_write_bin_serial(uint32_t* workStartAdd, uint32_t fileSize); +static int32_t dg_emmc_write_bin_serial(uint32_t* workStartAdd, uint32_t fileSize); static EMMC_ERROR_CODE dg_emmc_init(void); static uint32_t InputEmmcSector( EMMC_PARTITION partitionArea, uint32_t maxSectorCnt, uint32_t *startSector, uint32_t *sizeSector, EMMC_INPUT_TYPE type ); static uint32_t InputEmmcSectorArea( EMMC_PARTITION *partitionArea ); -static uint32_t InputEmmcPrgStartAdd( uint32_t *prgStartAdd ); static uint32_t InputFileSize( uint32_t *fileSize ); static int32_t ChkSectorSize( uint32_t maxSectorCnt, uint32_t startSector, uint32_t sizeSector ); static void SetSectorData(EMMC_SECTOR *sectorData); static void DispAreaData(EMMC_SECTOR sectorData); -static int8_t dg_emmc_mot_load(uint32_t *maxADD ,uint32_t *minADD, uint32_t gUserPrgStartAdd ); static uint32_t emmcInit; /* eMMC drv init */ @@ -209,7 +192,7 @@ void dg_emmc_write(EMMC_WRITE_COMMAND wc) uint32_t *Load_workStartAdd; uint32_t *Load_workEndAdd; - uint32_t flags = 0x00000001; + uint32_t flags = 0x00000000; uint32_t sectorStartAddress; uint32_t sectorSize; uint32_t prgStartAdd; @@ -233,11 +216,9 @@ void dg_emmc_write(EMMC_WRITE_COMMAND wc) int8_t motLoad = 1; int8_t oldPartitionConfig; - static const int8_t startMessage[][32] = {"EM_W Start --------------", - "EM_WB Start --------------"}; + static const int8_t startMessage[][32] = {"EM_WB Start --------------"}; - static const int8_t endMessage[][32] = {"EM_W Complete!", - "EM_WB Complete!"}; + static const int8_t endMessage[][32] = {"EM_WB Complete!"}; result = dg_emmc_check_init(); if (EMMC_SUCCESS != result) @@ -259,22 +240,20 @@ void dg_emmc_write(EMMC_WRITE_COMMAND wc) return; } - Load_workStartAdd = (uint32_t*)EMMC_WORK_DRAM_SADD; + Load_workStartAdd = (uint32_t*)EMMC_WORK_RAMB_SADD; switch(partitionArea) { case EMMC_PARTITION_USER_AREA: //User Partition Area Program - Load_workEndAdd = (uint32_t*)EMMC_WORK_DRAM_EADD_512M; PutStr("-- User Partition Area Program --------------------------",1); break; case EMMC_PARTITION_BOOT_1: //Boot Partition 1 Program - Load_workEndAdd = (uint32_t*)EMMC_WORK_DRAM_EADD_16M; PutStr("-- Boot Partition 1 Program -----------------------------",1); break; case EMMC_PARTITION_BOOT_2: //Boot Partition 2 Program - Load_workEndAdd = (uint32_t*)EMMC_WORK_DRAM_EADD_16M; PutStr("-- Boot Partition 2 Program -----------------------------",1); break; } + Load_workEndAdd = (uint32_t*)EMMC_WORK_RAMB_EADD; //Input address(mmc sector) chkInput = InputEmmcSector( partitionArea, sectorData.maxSectorCount[partitionArea], @@ -287,34 +266,11 @@ void dg_emmc_write(EMMC_WRITE_COMMAND wc) mmcPrgStartAdd = sectorStartAddress<<9; //Input address( program start address) - if (wc == EMMC_WRITE_MOT) - { - chkInput = InputEmmcPrgStartAdd( &prgStartAdd ); - if (1 != chkInput) - { - return; - } - } // WorkMemory CLEAR (Write H'00000000) - switch( partitionArea) - { - case EMMC_PARTITION_USER_AREA: //User Partition Area Program - PutStr("Work RAM(H'50000000-H'6FFFFFFF) Clear....",1); - FillData32Bit((uint32_t *)Load_workStartAdd,(uint32_t *)Load_workEndAdd,0x00000000); - break; - default: - PutStr("Work RAM(H'50000000-H'50FFFFFF) Clear....",1); - FillData32Bit((uint32_t *)Load_workStartAdd,(uint32_t *)Load_workEndAdd,0x00000000); - break; - } + PutStr("Work RAM(H'B6000000-H'B60FFFFF) Clear....",1); + FillData32Bit((uint32_t *)Load_workStartAdd,(uint32_t *)Load_workEndAdd,0x00000000); -// MOT file load - if (wc == EMMC_WRITE_MOT) - { - motLoad = dg_emmc_mot_load(&workAdd_Max ,&workAdd_Min, prgStartAdd); - } - else { chkInput = InputFileSize( &fileSize ); if (1 != chkInput) @@ -323,20 +279,13 @@ void dg_emmc_write(EMMC_WRITE_COMMAND wc) } PutStr("please send binary file!",1); -#if USB_ENABLE == 1 - if (gTerminal == USB_TERMINAL) - { - totalDownloadSize = ((fileSize + (DMA_TRANSFER_SIZE - 1)) & DMA_ROUNDUP_VALUE); - USB_ReadDataWithDMA((unsigned long)Load_workStartAdd, totalDownloadSize); - } - else - { - dg_emmc_write_bin_serial(Load_workStartAdd, fileSize); - } -#else /* USB_ENABLE == 1 */ - dg_emmc_write_bin_serial(Load_workStartAdd, fileSize); -#endif /* USB_ENABLE == 1 */ - + //If send a file smaller than the specified file size, + //Flash writer will output the message and command exit force. + if (dg_emmc_write_bin_serial(Load_workStartAdd, fileSize) != 0) + { + PutStr("Time out! Unable to receive data for the specified size!",1); + return; + } workAdd_Min = (uintptr_t)Load_workStartAdd; workAdd_Max = workAdd_Min + fileSize - 1; } @@ -350,15 +299,6 @@ void dg_emmc_write(EMMC_WRITE_COMMAND wc) PutStr(buf,1); #endif /* EMMC_DEBUG */ - if (wc == EMMC_WRITE_MOT) - { - if (1 == motLoad ) - { - PutStr("EM_W mot file read ERR",1); - return; - } - } - //transfer data calc mmcPrgStartAdd = mmcPrgStartAdd + (workAdd_Min - (uintptr_t)Load_workStartAdd); mmcPrgEndAdd = mmcPrgStartAdd + (workAdd_Max - workAdd_Min); @@ -421,36 +361,34 @@ void dg_emmc_write_bin(void) dg_emmc_write(EMMC_WRITE_BINARY); } -/**************************************************************** - MODULE : dg_emmc_write_mot * - FUNCTION : Write Memory to eMMC * - COMMAND : EMMC_W * - INPUT PARAMETER : EMMC_W * -*****************************************************************/ -void dg_emmc_write_mot(void) -{ - dg_emmc_write(EMMC_WRITE_MOT); -} - /************************************************************************ MODULE : dg_emmc_write_bin_serial * FUNCTION : Write Memory to eMMC (Binary(Serial)) * COMMAND : EMMC_WB * INPUT PARAMETER : EMMC_WB * *************************************************************************/ -static void dg_emmc_write_bin_serial(uint32_t* workStartAdd, uint32_t fileSize) +static int32_t dg_emmc_write_bin_serial(uint32_t* workStartAdd, uint32_t fileSize) { uint32_t i; int8_t byteData = 0; uintptr_t ptr; - + int32_t isTimeout; + ptr = (uintptr_t)workStartAdd; for (i = 0; i < fileSize; i++) { - GetChar(&byteData); + if( i != 0 ) { + isTimeout = GetCharTimeOut(&byteData,DATA_RECV_TIMEOUT); + if (isTimeout == -1) //if time out is occured. + return -1; + } + else { + GetChar(&byteData); + } *((uint8_t *)ptr) = byteData; ptr++; } + return 0; } /**************************************************************** @@ -525,208 +463,6 @@ void dg_emmc_erase(void) PutStr("EM_E Complete!",1); } - -/**************************************************************** - MODULE : dg_emmc_mot_load * - FUNCTION : load emmc mot file * - COMMAND : * - INPUT PARAMETER : * -*****************************************************************/ -static int8_t dg_emmc_mot_load(uint32_t *maxADD ,uint32_t *minADD, uint32_t gUserPrgStartAdd ) -{ -//MIN,MAX address calc - int8_t str[12]; //max getByteCount=4 -> 4 * 2 +1 (NULL) = 9 - uint32_t data,getByteCount,byteCount; - uint32_t loadGetCount,adByteCount,loadGetData,loadGetSum,loadGetCR; - uintptr_t loadGetAddress; - uint32_t loop,loop_S0,s0flag,errFlg,endFlg; -//**** Add dgLS_Load2 ******************************************************************** - uint32_t workAdd_Min,workAdd_Max; -//**************************************************************************************** -//LAGER Add------------------------------------------------------------------------ - uint32_t WorkStartAdd,Calculation; - uint32_t loadOffset; - - workAdd_Min = 0xFFFFFFFFU; - workAdd_Max = 0x00000000U; - - WorkStartAdd = LS_WORK_DRAM_SADD; //H'50000000 - - if ((0x40000000U <= gUserPrgStartAdd) && (gUserPrgStartAdd < WorkStartAdd)) - { - //H'40000000 =< gUserPrgStartAdd < H'50000000 - loadOffset = WorkStartAdd - gUserPrgStartAdd ; - Calculation = ADDITION; - } - else if ((WorkStartAdd <= gUserPrgStartAdd) && (gUserPrgStartAdd < 0xC0000000U)) - { - //H'50000000 =< gUserPrgStartAdd < H'C0000000 - loadOffset = gUserPrgStartAdd - WorkStartAdd ; - Calculation = SUBTRACTION; - } - else if ((EMMC_SECURERAM_SADD <= gUserPrgStartAdd) && (gUserPrgStartAdd <= EMMC_SECURERAM_EADD)) - { - //H'E6300000 =< gUserPrgStartAdd < H'E631FFFF 1st cut - loadOffset = gUserPrgStartAdd - WorkStartAdd ; - Calculation = SUBTRACTION; - } - else - { - PutStr("ERROR Load file. ",1); - return(1); - } - - loop = 1; - loop_S0 = 1; - errFlg = 0; - endFlg = 0; - - PutStr("please send ! ('.' & CR stop load)",1); - while(loop) - { - loop_S0 = 1; - s0flag = 0; - while(1) - { - GetChar(str); - if (*str == '.' || *str == 's' || *str =='S') - { - break; - } - } - if (*str == '.') - { - while(1) - { - GetChar(str); - if (*str == CR_CODE) - { - return(1); - } - } - } - else if (*str == 's' || *str == 'S') - { - GetChar(str); - switch(*str) - { - case '0': // S0:Title - s0flag = 1; - while(loop_S0) - { - // loop CRorLR code - GetChar(str); - if ((*str == CR_CODE) || (*str == LF_CODE)) - { - loop_S0 = 0; - } - } - break; - case '1': // S1:2Byte Address - adByteCount = 2; - break; - case '2': // S2:3Byte Address - adByteCount = 3; - break; - case '3': // S3:4Byte Address - adByteCount = 4; - break; - case '7': // S7,S8,S9:end code - case '8': - case '9': - endFlg = 1; - break; - default: - errFlg = 1; - break; - } - } - if (endFlg == 1 || errFlg == 1) - { - // end code etc. - while(1) - { - // loop CRorLR code ,CRorLR Return - GetChar(str); - if ((*str == CR_CODE) || (*str == LF_CODE)) - { - -//**** Add dgLS_Load2 ******************************************************************** - *maxADD = workAdd_Max; - *minADD = workAdd_Min; -//**************************************************************************************** - return(0); - } - } - } - if (s0flag == 0) - { - //Get Byte count (addressByteCount + dataByteCount + sumCheckByteCount(=1) ) - getByteCount =1; - GetStr_ByteCount(str,getByteCount); - HexAscii2Data((uint8_t*)str,&data); - loadGetCount = data; - //Get Address - getByteCount =adByteCount; - GetStr_ByteCount(str,getByteCount); - HexAscii2Data((uint8_t*)str,&data); - loadGetAddress = data; - -//LAGER Add------------------------------------------------------------------------ - if (Calculation == SUBTRACTION) - { - loadGetAddress = loadGetAddress - loadOffset; - } - else - { - loadGetAddress = loadGetAddress + loadOffset; - } -//--------------------------------------------------------------------------------- - - loadGetCount = loadGetCount - getByteCount; // Get Address byte count - - - -//**** Add dgLS_Load2 ******************************************************************** - //Min Address Check - if (loadGetAddress < workAdd_Min) - { - workAdd_Min = loadGetAddress; - } -//**************************************************************************************** - - //Get Data & Data write - getByteCount = 1; - for(byteCount = loadGetCount; loadGetCount > 1; loadGetCount = loadGetCount - 1) - { - GetStr_ByteCount(str,getByteCount); - HexAscii2Data((uint8_t*)str,&data); - loadGetData = data; - *((uint8_t *)loadGetAddress) = loadGetData; - loadGetAddress = loadGetAddress +1; - } -//**** Add dgLS_Load2 ******************************************************************** - //Max Address Check - if ((loadGetAddress - 1) > workAdd_Max) - { - workAdd_Max = (loadGetAddress-1); - } -//**************************************************************************************** - //Get sum - getByteCount =1; - GetStr_ByteCount(str,getByteCount); - HexAscii2Data((uint8_t*)str,&data); - loadGetSum = data; - //Get CR code - GetChar(str); // char input - loadGetCR = *str; - if ((loadGetCR == CR_CODE) || (loadGetCR == LF_CODE)) - { - loop=1; - } - } - } -} - /************************************************************************ MODULE : InputEmmcSector * FUNCTION : Input eMMC address and size in sector * @@ -887,62 +623,6 @@ static uint32_t InputEmmcSectorArea( EMMC_PARTITION *partitionArea ) return(1); } -/**************************************************************** - MODULE : InputEmmcPrgStartAdd * - FUNCTION : Input Program Start Add * - COMMAND : * - INPUT PARAMETER : * -*****************************************************************/ -static uint32_t InputEmmcPrgStartAdd( uint32_t *prgStartAdd ) -{ - uint32_t loop; - uint32_t wrData; - int8_t key[16]; - int8_t buf[16]; - int8_t chCnt = 0; - int8_t chPtr; - - loop = 1; - while(loop) - { - PutStr("Please Input Program Start Address : ",0); - GetStr(key,&chCnt); - chPtr = 0; - if (!GetStrBlk(key,buf,&chPtr,0)) - { - if (chPtr==1) - { /* Case Return */ - return(0); - } - else if (chPtr > (int8_t)((SIZE_32BIT<<1)+1)) - { /* Case Data Size Over */ - PutStr("Syntax Error",1); - } - else - { - if (HexAscii2Data((uint8_t*)buf,&wrData)) - { - PutStr("Syntax Error",1); - } - else - { - if (wrData & 0x000001FFU) - { - PutStr("Memory Boundary Error",1); - } - else - { - *prgStartAdd = wrData; - loop = 0; - } - } - } - } - } - - return(1); -} - /**************************************************************** MODULE : InputFileSize * FUNCTION : Input Binary File Size * @@ -978,8 +658,14 @@ static uint32_t InputFileSize( uint32_t *fileSize ) } else { - *fileSize = wrData; - loop = 0; + if ( wrData > EMMC_WORK_RAMB_MAX_SIZ ) + { + PutStr("Size Parameter Error",1); + } + else{ + *fileSize = wrData; + loop = 0; + } } } } @@ -999,7 +685,7 @@ static int32_t ChkSectorSize( uint32_t maxSectorCnt, uint32_t startSector, uint3 { uint32_t sumSector; - if (EMMC_WORK_DRAM_SECTOR_MAX < sizeSector) + if (EMMC_WORK_RAMB_SECTOR_MAX < sizeSector) { return(-1); /* Size Over */ } diff --git a/dg_emmc_config.c b/dg_emmc_config.c index a1c43dc..dcb32f4 100644 --- a/dg_emmc_config.c +++ b/dg_emmc_config.c @@ -1,33 +1,26 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + #define __EMMC_GLOBAL_DEFINE__ #include "emmc_config.h" diff --git a/dgmodul1.c b/dgmodul1.c deleted file mode 100644 index e7a64d8..0000000 --- a/dgmodul1.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "dgtable.h" -#include "dgmodul1.h" -#include "devdrv.h" -#include "devdrv.h" -#include "bit.h" -#include "cpudrv.h" -#include "scifdrv.h" - -#include "reg_rzg2.h" -#include "boot_init_lbsc.h" - - -extern const char *const AllHelpMess[ALL_HELP_MESS_LINE]; -extern const com_menu MonCom[COMMAND_UNIT]; -extern int32_t gComNo; -extern char gKeyBuf[64]; - -uint32_t gFLASH_CS1_ID; - -/**************************************************************** - MODULE : dgHelp * - FUNCTION : HELP MESSAGE * - COMMAND : H * - INPUT PARAMETER : H * -*****************************************************************/ -void dgHelp(void) -{ - char tmp[64],chPtr,helpNo; - - chPtr = 0; - if (!GetStrBlk(gKeyBuf,tmp,&chPtr,0)) - { - PutMess(AllHelpMess); - } -} - - - -int32_t GetStr_ByteCount(char *str,uint32_t getByteCount) -{ - uint32_t byteCount; - int32_t i; - - for(byteCount = 1; byteCount <= getByteCount;byteCount = byteCount + 1) - { - i = 1; - while(i == 1) - { - i = GetChar(str); - } - str++; - i = 1; - while(i == 1) - { - i = GetChar(str); - } - str++; - } - *str = 0; -} - -void dgScifSpeedUp(void) -{ - dgScifSpeedUp_921600(); -} - -/**************************************************************** - MODULE : dgScifSpeedUp * - FUNCTION : Scif speed UP Change 921.6kbps * - COMMAND : SUP * - INPUT PARAMETER : SUP * -*****************************************************************/ -void dgScifSpeedUp_921600(void) -{ - uint16_t setData; -#ifdef RZG2_HIHOPE - uint32_t product; -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - uint32_t sscg; - uint32_t md; - - md = *((volatile uint32_t*)RST_MODEMR); - sscg = (md & 0x00001000) >> 12; -#endif /* RZG2_EK874 */ - - PutStr("Scif speed UP",1); - PutStr("Please change to 921.6Kbps baud rate setting of the terminal.",1); - WaitPutCharSendEnd(); - -#ifdef RZG2_HIHOPE - product = *((volatile uint32_t*)PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); - setData =0x12; /* 266.66MHz / (921600*16) = 18.08 @S3D1 */ -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - if (sscg == 0x0) - { /* MD12=0 (SSCG off) F S3D1C=266.6MHz */ - setData =0x12; /* 266.66MHz / (921600*16) = 18.08 @S3D1 */ - } - else - { /* MD12=1 (SSCG on) F S3D1C=240MHz */ - setData =0x10; /* 240MHz / (921600*16) = 16.28 @S3D1C */ - } -#endif /* RZG2_EK874 */ - SetScif2_DL(setData); -} diff --git a/dgmodul4.c b/dgmodul4.c deleted file mode 100644 index ddef91c..0000000 --- a/dgmodul4.c +++ /dev/null @@ -1,1418 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "dgtable.h" -#include "dgmodul4.h" -#include "rpcqspidrv.h" -#include "spiflash1drv.h" -#include "reg_rzg2.h" -#include "ramckmdl.h" -#include "dmaspi.h" -#include "devdrv.h" -#include "dgmodul1.h" -#include "boardid.h" -#if USB_ENABLE == 1 -#include "usb_lib.h" -#endif /* USB_ENABLE == 1 */ - -uint32_t gSpiFlashSvArea; -uint32_t gUserPrgStartAdd; -uint32_t gUserPrgSize; - -uint32_t gManufacturerId; -uint32_t gDeviceId; -uint32_t gQspi_sa_size; -uint32_t gQspi_end_addess; - -extern uintptr_t gErrDdrAdd; -extern uint32_t gErrDdrData,gTrueDdrData; -extern uintptr_t gSubErrAdd; -extern uintptr_t gSubErrData; -extern uintptr_t gSubTrueData; - -extern char gKeyBuf[64]; - -/**************************************************************** - MODULE : dgG2LoadSpi * - FUNCTION : load Program to Spi memory * - COMMAND : XLS * - INPUT PARAMETER : XLS * -*****************************************************************/ -void dgG2LoadSpiflash0(void) -{ - char str[64]; - uint32_t OnBoardSpiSysSize; - - char buf[16],key[16],chCnt,chPtr; - uint32_t readManuId,readDevId; - uint32_t loop; - uint32_t wrData; - - uintptr_t Load_workStartAdd,Load_workEndAdd; - uint32_t workAdd_Min,workAdd_Max; - - uint32_t Read_workStartAdd; - uint32_t ClrSpiStartSecTopAdd,ClrSpiSecEndAdd; - uint32_t clearSize; - - uint32_t MaskSectorSize; - uint32_t WriteDataStatAdd; - uint32_t PrgSpiStatAdd,PrgSpiEndAdd; - uint32_t saveSize; - - uint32_t InfoPrgStatAdd; - uint32_t rdBufstatAdd; - uintptr_t prgStAdd,prgSize; - - uint32_t WrittenSize; - uint32_t RemainingSize; - - PutStr("===== Qspi writing of RZ/G2 Board Command ========",1); - PutStr("Load Program to Spiflash",1); - InitRPC_Mode(); - if (CheckQspiFlashId()) - { - return; //Error abortt - } - PutStr("------------------------------------------------------------",1); - PutStr("Please select,Qspi Save Area. ",1); - PutStr(" ",1); - PutStr("== Loader Program : Program to execute on SystemRAM ========",1); - PutStr(" 1 : A-Side SPI_Address = H' 004_0000-H' 007_FFFF ",1); - PutStr(" 2 : B-Side SPI_Address = H' 008_0000-H' 00B_FFFF ",1); - PutStr(" ",1); - PutStr("== User Program : Program to execute on DRAM or SystemRAM ==",1); - PutStr(" 3 : SPI_Address = H' 010_0000-H' 3FF_FFFF ",1); - PutStr("------------------------------------------------------------",1); - - loop = 1; - while(loop) - { - PutStr(" Select area(1-3)>",0); - GetStr(str,&chCnt); - switch(str[0]) - { - case '1': //LoaderProgram - gSpiFlashSvArea = 1; - Load_workStartAdd = LS_WORK_DRAM_SADD; - Load_workEndAdd = LS_WORK_DRAM_EADD_192K; - PrgSpiStatAdd = QSPI_SA01_STARTAD; - loop = 0; - break; - case '2': //LoaderProgram - gSpiFlashSvArea = 2; - Load_workStartAdd = LS_WORK_DRAM_SADD; - Load_workEndAdd = LS_WORK_DRAM_EADD_192K; - PrgSpiStatAdd = QSPI_SA02_STARTAD; - loop = 0; - break; - case '3': //UserProgram - gSpiFlashSvArea = 3; - Load_workStartAdd = LS_WORK_DRAM_SADD; - Load_workEndAdd = LS_WORK_DRAM_EADD_64M; - PrgSpiStatAdd = QSPI_SA04_STARTAD; - loop = 0; - break; - } - } - if (gSpiFlashSvArea == 1 || gSpiFlashSvArea ==2 ) - { - gUserPrgStartAdd = SYSTEMRAM_IPL_SADD; - PutStr("-- Loader Program --------------------------",1); - } - else if (gSpiFlashSvArea == 3) - { - PutStr("-- User Program ----------------------------",1); - loop = 1; - while(loop) - { - PutStr("Please Input User Program Start Address : ",0); - GetStr(key,&chCnt); - chPtr = 0; - if (!GetStrBlk(key,buf,&chPtr,0)) - { - if (chPtr == 1) - { - /* Case Return */ - } - else if ((buf[0] == '.')) - { - /* Case End */ - gUserPrgStartAdd = 0x40000000; - loop = 0; - } - else if (chPtr > (char)((SIZE_32BIT<<1)+1)) - { - /* Case Data Size Over */ - PutStr("Syntax Error",1); - } - else - { - if (HexAscii2Data((unsigned char*)buf,&wrData)) - { - PutStr("Syntax Error",1); - } - else - { - if (wrData & 0x00000003) - { - PutStr("Memory Boundary Error",1); - } - else - { - gUserPrgStartAdd = wrData; - loop = 0; - } - } - } - } - else - { - PutStr("Syntax Error",1); - } - } - } - //===================================================================================== - // InfoPrgStatAdd = QSPI_SA03_STARTAD; - // InfoPrgSizeAdd = QSPI_SA03_STARTAD + 0x04; - //===================================================================================== - // WorkMemory CLEAR (Write H'FF) - if (gSpiFlashSvArea == 1 || gSpiFlashSvArea == 2) - { - //Loader Area - PutStr("Work RAM(H'50000000-H'5002FFFF) Clear....",1); - } - else if (gSpiFlashSvArea == 3) - { - PutStr("Work RAM(H'50000000-H'53FFFFFF) Clear....",1); - } - FillData32Bit((uint32_t *)Load_workStartAdd,(uint32_t *)Load_workEndAdd,0xFFFFFFFF); - - if (dgLS_Load_Offset2(&workAdd_Max ,&workAdd_Min)) - { - return; - } - PrgSpiStatAdd = PrgSpiStatAdd + (workAdd_Min - Load_workStartAdd); - PrgSpiEndAdd = PrgSpiStatAdd + (workAdd_Max - workAdd_Min); - saveSize = (PrgSpiEndAdd-PrgSpiStatAdd)+1; - MaskSectorSize = (~gQspi_sa_size) + 1; - - WriteDataStatAdd = workAdd_Min; - ClrSpiStartSecTopAdd = PrgSpiStatAdd & MaskSectorSize; - ClrSpiSecEndAdd = PrgSpiEndAdd | ~(MaskSectorSize); - - clearSize = (ClrSpiSecEndAdd-ClrSpiStartSecTopAdd)+1; - - Read_workStartAdd = WORK_SPI_LOAD_AREA; - - if (CkQspiFlash1ClearSectorSize(Read_workStartAdd,ClrSpiStartSecTopAdd,clearSize,1)) - { - return; - } - - // SAVE QSPI-FLASH - PutStr("SAVE SPI-FLASH.......",0); - SaveDataWithBuffeQspiFlash(WriteDataStatAdd, PrgSpiStatAdd, saveSize); //Manual Mode Single WriteBuffe - PutStr("-- Save (Program Start Address & Size ) -----",1); - if (gSpiFlashSvArea == 1) - { - //A-Side IPL - InfoPrgStatAdd = QSPI_SA00_STARTAD; - prgStAdd = Read_workStartAdd + SPIBOOT_A_IPL_ADD; - prgSize = Read_workStartAdd + SPIBOOT_A_IPL_SIZE; - } - else if (gSpiFlashSvArea == 2) - { - //B-Side IPL - InfoPrgStatAdd = QSPI_SA00_STARTAD; - prgStAdd = Read_workStartAdd + SPIBOOT_B_IPL_ADD; - prgSize = Read_workStartAdd + SPIBOOT_B_IPL_SIZE; - } - else if (gSpiFlashSvArea == 3) - { - //User Program Area - InfoPrgStatAdd = QSPI_SA03_STARTAD; - prgStAdd = Read_workStartAdd + SPIBOOT_UPRG_ST_AD; - prgSize = Read_workStartAdd + SPIBOOT_UPRG_SIZE; - } - rdBufstatAdd = Read_workStartAdd + InfoPrgStatAdd; - OnBoardSpiSysSize = 0x2000; - - if ((gSpiFlashSvArea == 1) || (gSpiFlashSvArea == 2)) - { - if (gQspi_end_addess <= TOTAL_SIZE_16MB) - { - FastRdQspiFlash(InfoPrgStatAdd, rdBufstatAdd, OnBoardSpiSysSize); - } - else - { - Fast4RdQspiFlash(InfoPrgStatAdd, rdBufstatAdd, OnBoardSpiSysSize); - } - PutStr("SPI Data Clear(H'FF):H'000000-03FFFF Erasing.", 0); - ParameterSectorEraseQspiFlash(InfoPrgStatAdd, ((OnBoardSpiSysSize) - 1)); - } - else - { - SectorRdQspiFlash(InfoPrgStatAdd, rdBufstatAdd); - PutStr("SPI Data Clear(H'FF):H'0C0000-0FFFFF Erasing.", 0); - SectorEraseQspi_Flash(InfoPrgStatAdd, ((InfoPrgStatAdd + 0x8) -1)); - } - - *((uint32_t*)prgStAdd) = gUserPrgStartAdd; - saveSize = (saveSize|0x3)>>2; - *((uint32_t*)prgSize) = saveSize; - - PutStr("SAVE SPI-FLASH.......",0); - if ((gSpiFlashSvArea == 1) || (gSpiFlashSvArea == 2)) - { - SaveDataWithBuffeQspiFlash(rdBufstatAdd, InfoPrgStatAdd, OnBoardSpiSysSize); //Manual Mode Single WriteBuffe - } - else - { - SaveDataWithBuffeQspiFlash(rdBufstatAdd, InfoPrgStatAdd, gQspi_sa_size); //Manual Mode Single WriteBuffe - } - PutStr(" complete!",1); - - PutStr("",1); - PutStr("========== Qspi Save Information =================",1); - PutStr(" Program Start Address : H'",0); - Data2HexAscii(gUserPrgStartAdd,str,4); - PutStr(str,1); - Data2HexAscii(saveSize,str,4); - PutStr(" Program Size (Byte/4) : H'",0); - PutStr(str,1); - PutStr("===============================================================",1); - PutStr("",1); -} - -void InitRPC_Mode(void) -{ - InitRPC_QspiFlash(RPC_CLK_40M); -// InitRPC_QspiFlash(RPC_CLK_80M); -} - -uint32_t CheckQspiFlashId(void) -{ - char str[64]; - uint32_t readDevId, ret = 0; - uint8_t manuId; - uint16_t deviceId; - - ReadQspiFlashID(&readDevId); - - manuId = readDevId & 0x000000ff; - deviceId = (readDevId & 0x0000ff00) | ((readDevId >> 16) & 0xff); - - gManufacturerId = manuId; - gDeviceId = deviceId; - switch(manuId) - { - case CYPRESS_MANUFACTURER_ID: - PutStr(" Cypress : ", 0); - switch(deviceId) - { - case DEVICE_ID_S25FS512S: - PutStr("S25FS512S", 1); - gQspi_sa_size = SA_256KB; - gQspi_end_addess = TOTAL_SIZE_64MB - 0x8000 - 1; - break; - case DEVICE_ID_S25FS128S: - PutStr("S25FS128S", 1); - gQspi_sa_size = SA_256KB; - gQspi_end_addess = TOTAL_SIZE_16MB - 0x8000 - 1; - break; - default: - ret = 1; - break; - } - break; - case WINBOND_MANUFACTURER_ID: - PutStr(" Winbond : ", 0); - switch(deviceId) - { - case DEVICE_ID_W25Q64JV: - PutStr("W25Q64JV", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_8MB - 0x8000 - 1; - break; - case DEVICE_ID_W25Q64JW: - PutStr("W25Q64JW", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_8MB - 0x8000 - 1; - break; - case DEVICE_ID_W25Q128JV: - PutStr("W25Q128JV", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_16MB - 0x8000 - 1; - break; - - case DEVICE_ID_W25Q128JW: - PutStr("W25Q128JW", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_16MB - 0x8000 - 1; - break; - case DEVICE_ID_W25Q256: - PutStr("W25Q256", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_32MB - 0x8000 - 1; - break; - case DEVICE_ID_W25M512JV: - PutStr("W25M512JV", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_32MB - 0x8000 - 1; - break; - case DEVICE_ID_W25M512JW: - PutStr("W25M512JW", 1); - gQspi_sa_size = SA_64KB; - - gQspi_end_addess = TOTAL_SIZE_32MB - 0x8000 - 1; - break; - case DEVICE_ID_W25Q512JV: - PutStr("W25Q512JV", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_64MB - 0x8000 - 1; - break; - case DEVICE_ID_W25Q512JV_DTR: - PutStr("W25Q512JV-DTR", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_64MB - 0x8000 - 1; - break; - default: - ret = -1; - break; - } - break; - case MACRONIX_MANUFACTURER_ID: - PutStr(" Macronix : ", 0); - switch(deviceId) - { - case DEVICE_ID_MX25L12805: - PutStr("MX25L12805", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_16MB - 0x8000 - 1; - break; - case DEVICE_ID_MX25L25635F: - PutStr("MX25L25635F", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_32MB - 0x8000 - 1; - break; - case DEVICE_ID_MX25L51245G: - PutStr("MX25L51245G", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_64MB - 0x8000 - 1; - break; - case DEVICE_ID_MX66U25635F: - PutStr("MX66U25635F", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_32MB - 0x8000 - 1; - break; - case DEVICE_ID_MX66U51235F: - PutStr("MX66U51235F", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_64MB - 0x8000 - 1; - break; - default: - ret = -1; - break; - } - break; - case MICRON_MANUFACTURER_ID: - PutStr(" Micron : ", 0); - switch(deviceId) - { - case DEVICE_ID_MT25QL128: - PutStr("MT25QL128", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_16MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QU128: - PutStr("MT25QU128", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_16MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QL256: - PutStr("MT25QL256", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_32MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QU256: - PutStr("MT25QU256", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_32MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QL512: - PutStr("MT25QL512", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_64MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QU512: - PutStr("MT25QU512", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_64MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QL01G: - PutStr("MT25QL01G", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_128MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QU01G: - PutStr("MT25QU01G", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_128MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QL02G: - PutStr("MT25QL02G", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_256MB - 0x8000 - 1; - break; - case DEVICE_ID_MT25QU02G: - PutStr("MT25QU02G", 1); - gQspi_sa_size = SA_64KB; - gQspi_end_addess = TOTAL_SIZE_256MB - 0x8000 - 1; - break; - default: - ret = -1; - break; - } - break; - default: - ret = 1; - break; - } - if (ret) - { - Data2HexAscii(readDevId, str, 4); - PutStr(" FlashID = 0x", 0); - PutStr(str, 1); - } - return ret; -} - -int32_t CkQspiFlash1ClearSectorSize(uint32_t rdBufAdd,uint32_t spiFlashStatAdd,uint32_t checkSize,uint32_t accessSize) -{ - uint32_t flashStatus,flashEraseFlg; - char str1Buf[10],str2Buf[10]; - char str[64]; - - PutStr("SPI Data Clear(H'FF) Check :",0); - if (gQspi_end_addess <= TOTAL_SIZE_16MB) - { - FastRdQspiFlash(spiFlashStatAdd, rdBufAdd,checkSize); - } - else - { - Fast4RdQspiFlash(spiFlashStatAdd, rdBufAdd,checkSize); - } - - flashEraseFlg = 0; - - if (CkSpiFlashAllF(rdBufAdd,checkSize)) - { - PutStr("H'",0); - Data2HexAscii(spiFlashStatAdd,str1Buf,4); - PutStr(&str1Buf[0],0); - PutStr("-",0); - Data2HexAscii(((spiFlashStatAdd+checkSize)-1),str2Buf,4); - PutStr(&str2Buf[0],0); - PutStr(",Clear OK?(y/n)",0); - - if (WaitKeyIn_YorN()) - { - DelStr(34); - PutStr(" Exit ",1); - return(1); - } - DelStr(34); - flashEraseFlg = 1; - } - else - { - PutStr(" OK ",1); - } - if (flashEraseFlg) - { - // FLASH: erase - if (spiFlashStatAdd < 0x40000) - { - //Parameter Data Area Erase (H'0-H'7FFF) - PutStr("H'00000000-H'00007FFF",0); - PutStr(" Erasing.",1); - ParameterSectorEraseQspiFlash(0x0, 0x7FFF); - } - PutStr("H'",0); - PutStr(&str1Buf[0],0); - PutStr("-",0); - PutStr(&str2Buf[0],0); - PutStr(" Erasing.",0); - SectorEraseQspi_Flash(spiFlashStatAdd, ((spiFlashStatAdd + checkSize) - 1)); //SPI-FLASH-Address H'0000-H'FFFF - } - return(0); -} - -void mem_copy(uint32_t prgStartAd, uint32_t sector_Ad, uint32_t accessSize) -{ - uintptr_t readAdd, wrAdd; - uint32_t paddingOffset = 0; - uint32_t accessCount = 0; - - paddingOffset = (accessSize + 0xFF ) & ~0xFF; - - //accessCount = accessSize/64; - accessCount = paddingOffset >> 6; - //DMA Setting - InitDma01_Data(prgStartAd, sector_Ad, accessCount); - StartDma01(); - WaitDma01(); - DisableDma01(); - ClearDmaCh01(); -} - -/**************************************************************** - MODULE : dgG2LoadSpiflash0_3 * - FUNCTION : load Program to Spiflash memory * - COMMAND : XLS3 * - INPUT PARAMETER : XLS3 * -*****************************************************************/ -void dgG2LoadSpiflash0_3(void) -{ - XLoadSpiflash0_2(1U); -} - -/************************************************************************ - MODULE : dgG2LoadSpiflash0_2 * - FUNCTION : load Program to Spiflash memory * - COMMAND : XLS2 * - INPUT PARAMETER : XLS2 * -*************************************************************************/ -void dgG2LoadSpiflash0_2(void) -{ - XLoadSpiflash0_2(0U); -} - -void XLoadSpiflash0_2(uint32_t mode) -{ - char str[64]; - uint32_t readManuId,readDevId; - - uintptr_t Load_workStartAdd,Load_workEndAdd; - uint32_t workAdd_Min,workAdd_Max; - - uint32_t Read_workStartAdd; - uint32_t ClrSpiStartSecTopAdd,ClrSpiSecEndAdd; - uint32_t clearSize; - - uint32_t MaskSectorSize; - uint32_t WriteDataStatAdd; - uint32_t PrgSpiStatAdd,PrgSpiEndAdd; - uint32_t saveSize; - - uint32_t WrittenSize; - uint32_t RemainingSize; - - PutStr("===== Qspi writing of RZ/G2 Board Command =============",1); - PutStr("Load Program to Spiflash",1); - PutStr("Writes to any of SPI address.",1); - InitRPC_Mode(); - - if(CheckQspiFlashId()) - { - return; //Error abortt - } - gUserPrgStartAdd = 0x0; - PutStr((mode == 0U ? "Program Top Address & Qspi Save Address " : "Program size & Qspi Save Address "),1); - - gSpiFlashSvArea = 3; - Load_workStartAdd = LS_WORK_DRAM_SADD; - Load_workEndAdd = LS_WORK_DRAM_EADD_64M; - - PrgSpiStatAdd = 0x0; - gUserPrgStartAdd = 0x0; - - if (0U == mode) - { - PutStr("===== Please Input Program Top Address ============",1); - SetAddInputKey(&gUserPrgStartAdd); - } - else - { - PutStr("===== Please Input Program size ============",1); - SetSizeInputKey(&gUserPrgSize); - } - - PutStr(" ",1); - PutStr("===== Please Input Qspi Save Address ===",1); - SetAddInputKey(&PrgSpiStatAdd); - - if (gQspi_end_addess < PrgSpiStatAdd) - { - PutStr("Address Input Error", 1); - PutStr("Range of H'000_0000 ~ H'0FF_7FFF", 1); - return; - } - // WorkMemory CLEAR (Write H'FF) - PutStr("Work RAM(H'50000000-H'53FFFFFF) Clear....",1); - FillData32Bit((uint32_t *)Load_workStartAdd,(uint32_t *)Load_workEndAdd,0xFFFFFFFF); - - if (0U == mode) - { - if (dgLS_Load_Offset2(&workAdd_Max, &workAdd_Min)) - { - return; - } - } - else - { - char bin_data; - uint32_t image_offset = 0U; - PutStr("please send ! (binary)",1); - -#if USB_ENABLE == 1 - if (gTerminal == USB_TERMINAL) - { - image_offset = ((gUserPrgSize + (DMA_TRANSFER_SIZE-1)) & ~(DMA_TRANSFER_SIZE-1)); - USB_ReadDataWithDMA((unsigned long)Load_workStartAdd, image_offset); - } - else - { - while (image_offset < gUserPrgSize) - { - GetChar(&bin_data); - *(uint8_t *)(Load_workStartAdd + image_offset) = bin_data; - image_offset++; - } - } -#else /* USB_ENABLE == 1 */ - while (image_offset < gUserPrgSize) - { - GetChar(&bin_data); - *(uint8_t *)(Load_workStartAdd + image_offset) = bin_data; - image_offset++; - } -#endif /* USB_ENABLE == 1 */ - - workAdd_Min = Load_workStartAdd; - workAdd_Max = Load_workStartAdd + gUserPrgSize - 1; - } - PrgSpiStatAdd = PrgSpiStatAdd + (workAdd_Min - Load_workStartAdd); - PrgSpiEndAdd = PrgSpiStatAdd + (workAdd_Max - workAdd_Min); - saveSize = (PrgSpiEndAdd-PrgSpiStatAdd) + 1; - if (PrgSpiEndAdd > gQspi_end_addess) - { - PutStr("Program over size Error", 1); - PutStr(" SpiFlashMemory Stat Address : H'", 0); - Data2HexAscii(PrgSpiStatAdd, str, 4); - PutStr(str ,1); - PutStr(" SpiFlashMemory End Address : H'", 0); - Data2HexAscii(PrgSpiEndAdd,str, 4); - PutStr(str, 1); - return; - } - MaskSectorSize = (~gQspi_sa_size) + 1; - - WriteDataStatAdd = workAdd_Min; - ClrSpiStartSecTopAdd = PrgSpiStatAdd & MaskSectorSize; - ClrSpiSecEndAdd = PrgSpiEndAdd | ~(MaskSectorSize); - - clearSize = (ClrSpiSecEndAdd-ClrSpiStartSecTopAdd)+1; - - Read_workStartAdd = WORK_SPI_LOAD_AREA; - - if (CkQspiFlash1ClearSectorSize(Read_workStartAdd, ClrSpiStartSecTopAdd, clearSize,1)) - { - return; - } - // SAVE QSPI-FLASH - PutStr("SAVE SPI-FLASH.......",0); - SaveDataWithBuffeQspiFlash(WriteDataStatAdd, PrgSpiStatAdd, saveSize); //Manual Mode Single WriteBuffe - PutStr("",1); - PutStr("======= Qspi Save Information =================",1); - PutStr(" SpiFlashMemory Stat Address : H'",0); - Data2HexAscii(PrgSpiStatAdd,str,4); - PutStr(str,1); - PutStr(" SpiFlashMemory End Address : H'",0); - Data2HexAscii(PrgSpiEndAdd,str,4); - PutStr(str,1); - PutStr("===========================================================",1); - PutStr("",1); -} - -void SetData(uint32_t *setAdd) -{ - char buf[16],key[16],chCnt,chPtr; - uint32_t loop; - uint32_t wrData; - - loop = 1; - - while(loop) - { - PutStr(" Set Data : ",0); - GetStr(key,&chCnt); - chPtr = 0; - if (!GetStrBlk(key,buf,&chPtr,0)) - { - if (chPtr == 1) - { - /* Case Return */ - } - else if (chPtr > (char)((SIZE_32BIT<<1)+1)) - { - /* Case Data Size Over */ - PutStr("Syntax Error",1); - } - else - { - if (HexAscii2Data((unsigned char*)buf,&wrData)) - { - PutStr("Syntax Error",1); - } - else - { - *setAdd = wrData; - loop = 0; - } - } - } - else - { - PutStr("Syntax Error",1); - } - } -} - -int32_t CkSpiFlashAllF(int32_t sAdd,int32_t cap) -{ - uintptr_t ckAdd; - unsigned char rdData; - - for (ckAdd = sAdd; ckAdd < (sAdd+cap); ckAdd++) - { - rdData = *((volatile unsigned char*)ckAdd); - if (rdData != 0xFF) - { - return(1); - } - } - return(0); -} - -void SetAddInputKey(uint32_t *Address) -{ - char str[64]; - char buf[16],key[16],chCnt,chPtr; - uint32_t loop; - uint32_t wrData; - - loop = 1; - while(loop) - { - PutStr(" Please Input : H'",0); - GetStr(key,&chCnt); - chPtr = 0; - if (!GetStrBlk(key,buf,&chPtr,0)) - { - if (chPtr == 1) - { - /* Case Return */ - } - else if((buf[0]=='.')) - { - /* Case End */ - gUserPrgStartAdd = 0x40000000; - loop = 0; - } - else if (chPtr > (char)((SIZE_32BIT<<1)+1)) - { - /* Case Data Size Over */ - PutStr("Syntax Error",1); - } - else - { - if (HexAscii2Data((unsigned char*)buf,&wrData)) - { - PutStr("Syntax Error",1); - } - else - { - if (wrData & 0x00000003) - { - PutStr("Memory Boundary Error",1); - } - else - { - *Address = wrData; - loop = 0; - } - } - } - } - else - { - PutStr("Syntax Error",1); - } - } -} - -void SetSizeInputKey(uint32_t *size) -{ - char str[64]; - char buf[16],key[16],chCnt,chPtr; - uint32_t loop; - uint32_t wrData; - - loop = 1; - while(loop) - { - PutStr(" Please Input : H'",0); - GetStr(key,&chCnt); - chPtr = 0; - if (!GetStrBlk(key,buf,&chPtr,0)) - { - if (chPtr == 1) - { - /* Case Return */ - } else if ((buf[0]=='.')) - { - /* Case End */ - loop = 0; - } - else if (chPtr > (char)((SIZE_32BIT<<1)+1)) - { - /* Case Data Size Over */ - PutStr("Syntax Error",1); - } - else - { - if (HexAscii2Data((unsigned char*)buf,&wrData)) - { - PutStr("Syntax Error",1); - } - else - { - *size = wrData; - loop = 0; - } - } - } - else - { - PutStr("Syntax Error",1); - } - } -} - - -/**************************************************************** - MODULE : dgG2InfoSpiflash0_SA0 * - FUNCTION : read SA0 spi Spiflash memory * - COMMAND : XINFO_SA0 * - INPUT PARAMETER : XINFO_SA0 * -*****************************************************************/ -void dgG2InfoSpiflash0_SA0(void) -{ - char str[64]; - uint32_t bootRomPara; - uint32_t prgStAdd,prgSize; - uint32_t prgStAdd_B,prgSize_B; - uint32_t readManuId,readDevId; - uint32_t spiFlashStatAdd,workTopAdd,rdBufstatAdd; - uintptr_t readAdd; - - PutStr("=== SPI SA0 System Area Information ===",1); - InitRPC_Mode(); - if (CheckQspiFlashId()) - { - return; //Error abortt - } - //Setting SPI_Add, workRAM_Add - spiFlashStatAdd = QSPI_SA00_STARTAD; - workTopAdd = WORK_SPI_LOAD_AREA; - rdBufstatAdd = workTopAdd + spiFlashStatAdd; - - SectorRdQspiFlash(spiFlashStatAdd, rdBufstatAdd); - - readAdd = workTopAdd + SPIBOOT_BTROM_PARA; bootRomPara = *(uint32_t *)readAdd; //Read Boot ROM Parameters Address - readAdd = workTopAdd + SPIBOOT_A_IPL_ADD; prgStAdd = *(uint32_t *)readAdd; //Read Program Start Address - readAdd = workTopAdd + SPIBOOT_A_IPL_SIZE; prgSize = *(uint32_t *)readAdd; //Read Program Size - readAdd = workTopAdd + SPIBOOT_B_IPL_ADD; prgStAdd_B = *(uint32_t *)readAdd; //Read Program Start Address - readAdd = workTopAdd + SPIBOOT_B_IPL_SIZE; prgSize_B = *(uint32_t *)readAdd; //Read Program Size - - Data2HexAscii(bootRomPara,str,4); PutStr(" Boot ROM Parameters : H'", 0); PutStr(str, 1); - Data2HexAscii(prgStAdd,str,4); PutStr(" A-side IPL Address (Loader Address) : H'", 0); PutStr(str, 1); - Data2HexAscii(prgSize,str,4); PutStr(" A-side IPL data size (Loader size) : H'", 0); PutStr(str, 1); - Data2HexAscii(prgStAdd_B,str,4); PutStr(" B-side IPL Address (Loader Address) : H'", 0); PutStr(str, 1); - Data2HexAscii(prgSize_B,str,4); PutStr(" B-side IPL data size (Loader size) : H'", 0); PutStr(str, 1); - PutStr("=========================================================", 1); -} - -int32_t CheckDataChange(uintptr_t checkAdd) -{ - uint32_t data; - uint32_t change; - char str[64]; - char keyBuf[32],chCnt; - - change = CHANGE_OFF; - - data = *(uint32_t *)checkAdd; - - Data2HexAscii(data,str,4); PutStr(str,1); - while(1) - { - PutStr(" Change ?(Y/N)",0); - GetStr(keyBuf,&chCnt); - if (chCnt ==1) - { - if ((keyBuf[0] == 'Y') || (keyBuf[0] == 'y')) - { - PutStr(" Please Input New Data ",1); - SetData(&data); - *((uint32_t*)checkAdd) = data; - change = CHANGE_ON; - break; - } - if ((keyBuf[0] == 'N') || (keyBuf[0] == 'n')) - { - break; - } - } - } - return(change); -} - -/**************************************************************** - MODULE : dgG2InfoSpiflash0_SA0 * - FUNCTION : set SA0 spi Spiflash memory * - COMMAND : XINFO_SA0_S * - INPUT PARAMETER : XINFO_SA0_S * -*****************************************************************/ -void dgG2InfoSetSpiflash0_SA0(void) -{ - char str[64]; - uint32_t change; - uint32_t spiFlashStatAdd,workTopAdd,rdBufstatAdd; - uintptr_t readAdd; - uint32_t readManuId,readDevId; - uint32_t OnBoardSpiSysSize; - - change = CHANGE_OFF; - - PutStr("=== SPI SA0 System Area Information ===",1); - InitRPC_Mode(); - if(CheckQspiFlashId()) - { - return; //Error abortt - } - //Setting SPI_Add, workRAM_Add - spiFlashStatAdd = QSPI_SA00_STARTAD; - workTopAdd = WORK_SPI_LOAD_AREA; - rdBufstatAdd = workTopAdd + spiFlashStatAdd; - - OnBoardSpiSysSize = 0x2000; - - if (gQspi_end_addess <= TOTAL_SIZE_16MB) - { - FastRdQspiFlash(spiFlashStatAdd, rdBufstatAdd, OnBoardSpiSysSize); - } - else - { - Fast4RdQspiFlash(spiFlashStatAdd, rdBufstatAdd, OnBoardSpiSysSize); - } - //Boot ROM Parameter - readAdd = workTopAdd + SPIBOOT_BTROM_PARA; - PutStr(" Boot ROM Parameters : H'", 0); - if (CHANGE_ON == CheckDataChange(readAdd)) - { - change = CHANGE_ON; - } - //A-side IPL Address - readAdd = workTopAdd + SPIBOOT_A_IPL_ADD; - PutStr(" A-side IPL Address (Loader Address) : H'", 0); - if (CHANGE_ON == CheckDataChange(readAdd)) - { - change = CHANGE_ON; - } - //A-side IPL data size - readAdd = workTopAdd + SPIBOOT_A_IPL_SIZE; - PutStr(" A-side IPL data size (Loader size) : H'", 0); - if (CHANGE_ON == CheckDataChange(readAdd)) - { - change = CHANGE_ON; - } - //B-side IPL Address - readAdd = workTopAdd + SPIBOOT_B_IPL_ADD; - PutStr(" B-side IPL Address (Loader Address) : H'", 0); - if (CHANGE_ON == CheckDataChange(readAdd)) - { - change = CHANGE_ON; - } - //B-side IPL data size - readAdd = workTopAdd + SPIBOOT_B_IPL_SIZE; - PutStr(" B-side IPL data size (Loader size) : H'", 0); - if (CHANGE_ON == CheckDataChange(readAdd)) - { - change = CHANGE_ON; - } - if (change == CHANGE_ON) - { - PutStr("SPI Data Clear(H'FF):H'000000-007FFF Erasing.",0); - ParameterSectorEraseQspiFlash(spiFlashStatAdd, ((OnBoardSpiSysSize) - 1)); - PutStr("SAVE SPI-FLASH.......", 0); - SaveDataWithBuffeQspiFlash(rdBufstatAdd, spiFlashStatAdd, OnBoardSpiSysSize); //Manual Mode Single WriteBuffe - PutStr(" complete!", 1); - } -} - -/**************************************************************** - MODULE : dgG2InfoSpiflash0 * - FUNCTION : read SA3 spi Spiflash memory * - COMMAND : XINFO * - INPUT PARAMETER : XINFO * -*****************************************************************/ -void dgG2InfoSpiflash0(void) -{ - char str[64]; - uint32_t prgStAdd,prgSize; - uint32_t readManuId,readDevId; - uint32_t spiFlashStatAdd,workTopAdd,rdBufstatAdd; - uintptr_t readAdd; - - PutStr("=== SPI SA3 System Area Information ===",1); - InitRPC_Mode(); - if(CheckQspiFlashId()) - { - return; //Error abortt - } - //Setting SPI_Add, workRAM_Add - spiFlashStatAdd = QSPI_SA03_STARTAD; - workTopAdd = WORK_SPI_LOAD_AREA; - rdBufstatAdd = workTopAdd + spiFlashStatAdd; - - SectorRdQspiFlash(spiFlashStatAdd, rdBufstatAdd); - //Read Program Start Address - readAdd = workTopAdd + SPIBOOT_UPRG_ST_AD; - prgStAdd = *(uint32_t *)readAdd; - //Read Program Size - readAdd = workTopAdd + SPIBOOT_UPRG_SIZE; - prgSize = *(uint32_t *)readAdd; - - Data2HexAscii(prgStAdd,str,4); - PutStr(" Program Start Address : H'",0); - PutStr(str,1); - Data2HexAscii(prgSize,str,4); - PutStr(" Program Size (Byte/4) : H'",0); - PutStr(str,1); - PutStr("==================================================",1); -} - - - -/**************************************************************** - MODULE : dgG2InfoSetSpiflash0 * - FUNCTION : set SA3 spi Spiflash memory * - COMMAND : XINFO_S * - INPUT PARAMETER : XINFO_S * -*****************************************************************/ -void dgG2InfoSetSpiflash0(void) -{ - char str[64]; - uint32_t change; - uint32_t spiFlashStatAdd,workTopAdd,rdBufstatAdd,readAdd; - uint32_t readManuId,readDevId; - - change = CHANGE_OFF; - - PutStr("=== SPI SA3 System Area Information ===",1); - InitRPC_Mode(); - if(CheckQspiFlashId()) - { - return; //Error abortt - } - //Setting SPI_Add, workRAM_Add - spiFlashStatAdd = QSPI_SA03_STARTAD; - workTopAdd = WORK_SPI_LOAD_AREA; - rdBufstatAdd = workTopAdd + spiFlashStatAdd; - - SectorRdQspiFlash(spiFlashStatAdd, rdBufstatAdd); - //Address - readAdd = workTopAdd + SPIBOOT_UPRG_ST_AD; - PutStr(" Program Start Address : H'",0); - if (CHANGE_ON == CheckDataChange(readAdd)) - { - change = CHANGE_ON; - } - //Size - readAdd = workTopAdd + SPIBOOT_UPRG_SIZE; - PutStr(" Program Size (Byte/4) : H'",0); - if (CHANGE_ON == CheckDataChange(readAdd)) - { - change=CHANGE_ON; - } - if (change == CHANGE_ON) - { - PutStr("SPI Data Clear(H'FF):H'0C0000-0FFFFF Erasing.",0); - SectorEraseQspi_Flash(spiFlashStatAdd, ((spiFlashStatAdd + 0x4) - 1)); - - PutStr("SAVE SPI-FLASH.......",0); - SaveDataWithBuffeQspiFlash(rdBufstatAdd, spiFlashStatAdd, gQspi_sa_size); //Manual Mode Single WriteBuffe - PutStr(" complete!",1); - } -} - -/******************************************************** - MODULE : dgClearSpiflash0 * - FUNCTION : Clear Spiflash memory * - COMMAND : CS * - INPUT PARAMETER : CS * -*********************************************************/ -void dgClearSpiflash0(void) -{ - char str[64]; - uint32_t readManuId,readDevId; - int32_t Rtn; - - Rtn = NORMAL_END; - - PutStr("ALL ERASE SpiFlash memory ",1); - PutStr("Clear OK?(y/n)",0); - if (WaitKeyIn_YorN()) - { - // Return1=N - DelStr(14); - return; - } - DelStr(14); - InitRPC_Mode(); - - if (CheckQspiFlashId()) - { - return; //Error abortt - } - PutStr(" ERASE QSPI-FLASH (60sec[typ])....",0); - Rtn = BulkEraseQspiFlash(); - if (Rtn == NORMAL_END) - { - PutStr(" complete!",1); - } - else - { - PutStr(" Fail!",1); - } -} - -char dgLS_Load_Offset2(uint32_t *maxADD ,uint32_t *minADD) -{ - char str[12]; - uint32_t data; - uint32_t getByteCount,byteCount; - uint32_t loadGetCount,adByteCount,loadGetData,loadGetSum,loadGetCR; - uintptr_t loadGetAddress; - uint32_t loop,loop_S0,s0flag,errFlg,checkData,endFlg; - uint32_t workAdd_Min,workAdd_Max; - uint32_t WorkStartAdd,Calculation; - uint32_t loadOffset; - - workAdd_Min = 0xFFFFFFFF; - workAdd_Max = 0x00000000; - - WorkStartAdd = LS_WORK_DRAM_SADD; - - if (gSpiFlashSvArea == 1 || gSpiFlashSvArea == 2) - { - loadOffset = gUserPrgStartAdd - WorkStartAdd; - Calculation = SUBTRACTION; - } - if (gSpiFlashSvArea == 3) - { - if ((0x40000000 <= gUserPrgStartAdd) && (gUserPrgStartAdd < WorkStartAdd)) - { - //H'40000000 =< gUserPrgStartAdd < H'50000000 - loadOffset = WorkStartAdd - gUserPrgStartAdd ; - Calculation = ADDITION; - } - else if((WorkStartAdd <= gUserPrgStartAdd) && (gUserPrgStartAdd < 0xC0000000)) - { - //H'50000000 =< gUserPrgStartAdd < H'C0000000 - loadOffset = gUserPrgStartAdd - WorkStartAdd ; - Calculation = SUBTRACTION; - } - else if(( SYSTEMRAM_SADD<= gUserPrgStartAdd) && (gUserPrgStartAdd <= PUBLICRAM_EADD)) - { - //H'E6300000 =< gUserPrgStartAdd < H'E635FFFF - loadOffset = gUserPrgStartAdd - WorkStartAdd; - Calculation = SUBTRACTION; - } - else - { - PutStr("ERROR Load file. ",1); - return(1); - } - } - - loop = 1; - loop_S0 = 1; - errFlg = 0; - endFlg = 0; - checkData = 0xFF; - - PutStr("please send ! ('.' & CR stop load)",1); - while(loop) - { - loop_S0 = 1; - s0flag = 0; - while(1) - { - GetChar(str); - if (*str == '.' || *str == 's' || *str == 'S') - { - break; - } - } - if (*str == '.') - { - while(1) - { - GetChar(str); - if (*str == CR_CODE) - { - return(1); - } - } - } - else if (*str == 's' || *str == 'S') - { - GetChar(str); - switch(*str) - { - case '0': - s0flag = 1; - while(loop_S0) - { - GetChar(str); - if ((*str == CR_CODE) || (*str == LF_CODE)) - { - loop_S0 = 0; - } - } - break; - case '1': - // S1:2Byte Address - adByteCount = 2; - break; - case '2': - // S2:3Byte Address - adByteCount = 3; - break; - case '3': - // S3:4Byte Address - adByteCount = 4; - break; - case '7': - case '8': - case '9': - endFlg = 1; - break; - default: - errFlg = 1; - break; - } - } - if (endFlg == 1 || errFlg == 1) - { - while(1) - { - GetChar(str); - if ((*str == CR_CODE) || (*str == LF_CODE)) - { - *maxADD = workAdd_Max; - *minADD = workAdd_Min; - return(0); - } - } - } - if (s0flag == 0) - { - //Get Byte count (addressByteCount + dataByteCount + sumCheckByteCount(=1) ) - getByteCount = 1; - GetStr_ByteCount(str,getByteCount); - HexAscii2Data((unsigned char*)str,&data); - loadGetCount = data; - //Get Address - getByteCount = adByteCount; - GetStr_ByteCount(str,getByteCount); - HexAscii2Data((unsigned char*)str,&data); - loadGetAddress = data; - - if(Calculation == SUBTRACTION) - { - loadGetAddress = loadGetAddress - loadOffset; - } - else - { - loadGetAddress = loadGetAddress + loadOffset; - } - loadGetCount = loadGetCount - getByteCount; // Get Address byte count - - //Min Address Check - if (loadGetAddress < workAdd_Min) - { - workAdd_Min = loadGetAddress; - } - //Get Data & Data write - getByteCount = 1; - for (byteCount = loadGetCount; loadGetCount > 1; loadGetCount=loadGetCount-1) - { - GetStr_ByteCount(str,getByteCount); - HexAscii2Data((unsigned char*)str,&data); - loadGetData = data; - *((unsigned char *)loadGetAddress) = loadGetData; - loadGetAddress = loadGetAddress +1; - } - //Max Address Check - if ((loadGetAddress-1) > workAdd_Max) - { - workAdd_Max = (loadGetAddress-1); - } - //Get sum - getByteCount = 1; - GetStr_ByteCount(str,getByteCount); - HexAscii2Data((unsigned char*)str,&data); - loadGetSum = data; - //Get CR code - GetChar(str); - loadGetCR = *str; - if ((loadGetCR == CR_CODE) || (loadGetCR == LF_CODE)) - { - loop=1; - } - } - } -} diff --git a/dgtable.c b/dgtable.c index 55dea72..2508ce0 100644 --- a/dgtable.c +++ b/dgtable.c @@ -1,41 +1,29 @@ -/* - * Copyright (c) 2015-2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + #include "common.h" #include "dgtable.h" -#include "dgmodul1.h" -#include "ddrcheck.h" -#if SERIAL_FLASH == 1 -#include "dgmodul4.h" -#endif /* SERIAL_FLASH == 1 */ #if EMMC == 1 #include "dgemmc.h" #endif /* EMMC == 1 */ @@ -45,28 +33,13 @@ /********************************************************/ const com_menu MonCom[COMMAND_UNIT] = { /*--------------------- Basic command ------------------------------*/ - "H" , dgHelp , 0 , -#if SERIAL_FLASH == 1 - "XCS" , dgClearSpiflash0 , 0 , - "XLS" , dgG2LoadSpiflash0 , 0 , - "XLS2" , dgG2LoadSpiflash0_2 , 0 , - "XLS3" , dgG2LoadSpiflash0_3 , 0 , - "XINFO_SA0" , dgG2InfoSpiflash0_SA0 , 0 , - "XINFO_SA0_S" , dgG2InfoSetSpiflash0_SA0 , 0 , - "XINFO" , dgG2InfoSpiflash0 , 0 , - "XINFO_S" , dgG2InfoSetSpiflash0 , 0 , -#endif /* SERIAL_FLASH == 1 */ #if EMMC == 1 "EM_DCID" , &dg_emmc_disp_cid , 0 , "EM_DCSD" , &dg_emmc_disp_csd , 0 , "EM_DECSD" , &dg_emmc_disp_ext_csd , 0 , "EM_SECSD" , &dg_emmc_set_ext_csd , 0 , - "EM_W" , &dg_emmc_write_mot , 0 , "EM_WB" , &dg_emmc_write_bin , 0 , "EM_E" , &dg_emmc_erase , 0 , #endif /* EMMC == 1 */ - "SUP" , dgScifSpeedUp , 0 , - "DDRCK" , dgDdrTest , 0 , - "RAMCK" , dgRamTest , 0 , TBL_END , 0 , 0 }; diff --git a/dmaspi.c b/dmaspi.c deleted file mode 100644 index aea6e53..0000000 --- a/dmaspi.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "dmaspi.h" -#include "bit.h" -#include "spiflash1drv.h" -#include "reg_rzg2.h" - -void InitDma01_Data(uint32_t prgStartAd, uint32_t sector_Ad, uint32_t accessCount) -{ - //DMA Setting - *((volatile uint32_t*)SYSDMAC_DMASAR_0) = sector_Ad; // RPC area - *((volatile uint32_t*)SYSDMAC_DMADAR_0) = prgStartAd; // - *((volatile uint32_t*)SYSDMAC_DMATCR_0) = accessCount; // - *((volatile uint32_t*)SYSDMAC_DMACHCR_0) = 0x00105409; //64Byte/AutoRequest mode -} - -void DisableDma01(void) -{ - *((volatile uint32_t*)SYSDMAC_DMACHCR_0) &= 0x00105410; //64Byte/AutoRequest mode -} - -void ClearDmaCh01(void) -{ - *((volatile uint32_t*)SYSDMAC_DMACHCLR_0) |= BIT0; -} - -void StartDma01(void) -{ - *((volatile uint16_t*)SYSDMAC_DMAOR_0) = 0x0001; //Start DMA ( Priority Mode:Fixed ) -} - -uint32_t WaitDma01(void) -{ - uint32_t dataL=0; - - //////////////////////////////// - // DMA transfer complite check - //////////////////////////////// - while(1) - { - dataL = *((volatile uint32_t*)SYSDMAC_DMACHCR_0); - if (dataL & BIT1) - { - *((volatile uint32_t*)SYSDMAC_DMACHCR_0) &= ~BIT1; // TE Clear - break; - } - if(dataL & BIT31) - { - *((volatile uint32_t*)SYSDMAC_DMACHCR_0) &= ~BIT31; // CAE Clear - return(1); - } - } - *((volatile uint16_t*)SYSDMAC_DMAOR_0) = 0x0000; //0: Disables DMA transfers on all channels - return(0); -} diff --git a/emmc_cmd.c b/emmc_cmd.c index 11ea610..bd2c12a 100644 --- a/emmc_cmd.c +++ b/emmc_cmd.c @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ /** * @file emmc_cmd.c diff --git a/emmc_erase.c b/emmc_erase.c index 5aeaf01..cca79c7 100644 --- a/emmc_erase.c +++ b/emmc_erase.c @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ /** * @file emmc_erase.c @@ -88,7 +80,6 @@ EMMC_ERROR_CODE emmc_erase_sector( return EMMC_ERR_STATE; } /* EXT_CSD[175] ERASE_GROUP_DEF check */ - //if( ) /* CMD35 */ diff --git a/emmc_init.c b/emmc_init.c index 4c0234d..957604e 100644 --- a/emmc_init.c +++ b/emmc_init.c @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ /** * @file emmc_init.c @@ -41,7 +33,6 @@ #include "emmc_std.h" #include "emmc_registers.h" #include "emmc_def.h" -#include "reg_rzg2.h" #include "common.h" #include "bit.h" @@ -253,41 +244,6 @@ static EMMC_ERROR_CODE emmc_dev_init(void) uint32_t dataL; uint32_t tmp_val; volatile uint32_t* adr_cpg_sdxckcr; - - switch(mmc_ch) { - case 0x0 : - tmp_val = BIT12; - adr_cpg_sdxckcr = (volatile uint32_t*)CPG_SD2CKCR; - break; - case 0x1 : - tmp_val = BIT11; - adr_cpg_sdxckcr = (volatile uint32_t*)CPG_SD3CKCR; - break; - } - - /* Power on eMMC */ - dataL = *((volatile uint32_t*)CPG_SMSTPCR3); - if ((dataL) & (tmp_val)) { - dataL &= ~(tmp_val); - *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; - *((volatile uint32_t*)CPG_SMSTPCR3) = dataL; - } - - dataL = *((volatile uint32_t*)CPG_MSTPSR3); - while ( (dataL & (tmp_val)) != 0x0 ) {// wait tmp_val=0 - dataL = *((volatile uint32_t*)CPG_MSTPSR3); - } - - /* Set SD clock */ - *((volatile uint32_t*)CPG_CPGWPR) = ~(BIT9|BIT0); //SD phy 200MHz - /* Stop SDnH clock & SDn=200MHz */ - *adr_cpg_sdxckcr = (BIT9|BIT0); - -#ifdef EMMC_VOLTAGE_1_8 - InitMmcPinFunction(); - SetMmcVoltage(1); /* I/O Voltage=1.8V */ - StartTMU2(10); /* wait 100ms */ -#endif /* EMMC_VOLTAGE_1_8 */ /* MMCIF initialize */ SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ @@ -331,31 +287,12 @@ static EMMC_ERROR_CODE emmc_dev_finalize(void) } /* host controller reset */ -// SETR_32(SOFT_RST, ( GETR(SOFT_RST) & (~SOFT_RST_SDRST) ) ); /* Soft reset */ -// SETR_32(SOFT_RST, ( GETR(SOFT_RST) | SOFT_RST_SDRST ) ); /* Soft reset released */ SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ SETR_32(SD_INFO2, SD_INFO2_CLEAR ); /* all interrupt clear */ SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR ); /* all interrupt disable */ SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */ - switch (mmc_ch) { - case 0x0 : - tmp_val = BIT12; - break; - case 0x1 : - tmp_val = BIT11; - break; - } - - - dataL = *((volatile uint32_t*)CPG_SMSTPCR3); - if ((dataL & tmp_val) == 0U) { - dataL |= (tmp_val); - *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; - *((volatile uint32_t*)CPG_SMSTPCR3) = dataL; - } - return result; } diff --git a/emmc_interrupt.c b/emmc_interrupt.c index 48f40b7..18c2508 100644 --- a/emmc_interrupt.c +++ b/emmc_interrupt.c @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ /** * @file emmc_interrupt.c @@ -129,7 +121,7 @@ uint32_t emmc_interrupt(void) #endif /* EMMC_DEBUG */ result = emmc_trans_sector((uint32_t *)mmc_drv_obj.buff_address_virtual); /* sector R/W */ - mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH; + mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH/sizeof(uint32_t); mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH; #ifdef EMMC_DEBUG @@ -155,12 +147,11 @@ uint32_t emmc_interrupt(void) } else { -#ifdef EMMC_DEBUG - PutStr("Transfer End", 0); -#endif /* EMMC_DEBUG */ - mmc_drv_obj.during_transfer = FALSE; + if(mmc_drv_obj.remain_size < EMMC_BLOCK_LENGTH){ + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + } } - mmc_drv_obj.state_machine_blocking = FALSE; } /* DMA_TRANSFER */ @@ -260,10 +251,10 @@ static EMMC_ERROR_CODE emmc_trans_sector ( { uint32_t length,i; uint64_t *bufPtrLL; -#ifdef EMMC_DEBUG +//#ifdef EMMC_DEBUG char str[16]; int32_t chCnt; -#endif /* EMMC_DEBUG */ +//#endif /* EMMC_DEBUG */ if (buff_address_virtual == NULL) { @@ -282,11 +273,14 @@ static EMMC_ERROR_CODE emmc_trans_sector ( } bufPtrLL = (uint64_t*)buff_address_virtual; - length = mmc_drv_obj.remain_size; + length = EMMC_BLOCK_LENGTH; #ifdef EMMC_DEBUG PutStr("remain_size = 0x",0); Hex2Ascii(mmc_drv_obj.remain_size, str, &chCnt); + PutStr(str, 1); + PutStr("buff_address_virtual = 0x",0); + Hex2Ascii(buff_address_virtual, str, &chCnt); PutStr(str, 1); PutStr("length = 0x",0); Hex2Ascii(length, str, &chCnt); diff --git a/emmc_mount.c b/emmc_mount.c index b9ab63f..b55b913 100644 --- a/emmc_mount.c +++ b/emmc_mount.c @@ -1,33 +1,26 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + /** * @file emmc_mount.c @@ -57,7 +50,6 @@ static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode); static EMMC_ERROR_CODE emmc_card_init (void); static EMMC_ERROR_CODE emmc_high_speed(void); static EMMC_ERROR_CODE emmc_bus_width(uint32_t width); -//static EMMC_ERROR_CODE emmc_check_pattern(uint8_t *pat, uint32_t size); static uint32_t emmc_set_timeout_register_value(uint32_t freq); static void set_sd_clk(uint32_t clkDiv); static uint32_t emmc_calc_tran_speed(uint32_t* freq); @@ -148,7 +140,7 @@ EMMC_ERROR_CODE emmc_mount(void) static EMMC_ERROR_CODE emmc_card_init (void) { int32_t retry; - uint32_t freq = MMC_400KHZ; /* 390KHz */ + uint32_t freq = MMC_400KHZ; /*390KHz */ EMMC_ERROR_CODE result; uint32_t resultCalc; diff --git a/emmc_utility.c b/emmc_utility.c index e15db80..2955fd9 100644 --- a/emmc_utility.c +++ b/emmc_utility.c @@ -1,33 +1,26 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + /** * @file emmc_utility.c diff --git a/emmc_write.c b/emmc_write.c index c2c753f..3d7ba04 100644 --- a/emmc_write.c +++ b/emmc_write.c @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ /** * @file emmc_write.c diff --git a/gen_128Kbin/sumzero.py b/gen_128Kbin/sumzero.py new file mode 100644 index 0000000..3eeb5a0 --- /dev/null +++ b/gen_128Kbin/sumzero.py @@ -0,0 +1,57 @@ +# -*- coding: utf-8 -*- +import argparse +import struct + +#define +MEM_S = 128 +MAX_MEM_SIZE = MEM_S*1024 + +# main +if __name__ == "__main__": + + parser = argparse.ArgumentParser(description='hashApp') + parser.add_argument('input', help='Input file path') + parser.add_argument('output', help='Output file path') + + args = parser.parse_args() + filePath = args.input + filePath2 = args.output + + cnt = 0 + a_data = 0 + b_data = 0 + + with open(filePath, 'rb') as f: + chunk = f.read(MAX_MEM_SIZE) + #print(chunk) + + with open(filePath2, 'ab') as f: + f.write(chunk) + size = len(chunk) + + with open(filePath2, 'rb') as f: + while True: + chunk = f.read(2) + a_data += int.from_bytes(chunk, byteorder='little') + if len(chunk) == 0: + break + + a_data = a_data & 0x000000FFFF + b_data = a_data.to_bytes(2, 'little') + + print("{0} : {1}".format(filePath, hex(a_data))) + + f=open(filePath2, mode ='ab') + + for i in range(MAX_MEM_SIZE): + # chunk size skip + if(cnt<=size): + cnt+=1 + elif(cnt==MAX_MEM_SIZE-1): + f.write(b_data) + cnt+=2 + + else: + f.write(struct.pack("b", 0)) + cnt+=1 + f.close diff --git a/include/HardwareSetup.h b/include/HardwareSetup.h new file mode 100644 index 0000000..5dab384 --- /dev/null +++ b/include/HardwareSetup.h @@ -0,0 +1,33 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : HardwareSetup.h + * Description : + ******************************************************************************/ + + +void InitPFC(void); +void InitCPG(void); +void SYC_enable(void); +void PowerOnRAMB(void); + diff --git a/include/bit.h b/include/bit.h index 4fa0b25..0855253 100644 --- a/include/bit.h +++ b/include/bit.h @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #define BIT0 0x00000001 #define BIT1 0x00000002 diff --git a/include/boardid.h b/include/boardid.h deleted file mode 100644 index b23650f..0000000 --- a/include/boardid.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -extern uint32_t gBoardFlag; - -//BOARD_CODE (gBoardFlag) -#define BD_EK874 0x00000000 /* RZ/G2E */ -#define BD_HIHOPE 0x00000001 /* RZ/G2M, RZ/G2N */ - -void CheckBoard(void); diff --git a/include/boot_init_gpio.h b/include/boot_init_gpio.h deleted file mode 100644 index e3396ad..0000000 --- a/include/boot_init_gpio.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2015-2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -void InitGPIO(void); diff --git a/include/boot_init_lbsc.h b/include/boot_init_lbsc.h deleted file mode 100644 index 1e5904d..0000000 --- a/include/boot_init_lbsc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -void InitLBSC(void); -void InitCSCTRL(void); -void InitCSWCR(void); -void InitCSPWCR(void); -void InitEXWTSYNC(void); diff --git a/include/boot_init_port.h b/include/boot_init_port.h deleted file mode 100644 index ef515b4..0000000 --- a/include/boot_init_port.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2015-2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -void InitPORT(void); diff --git a/include/common.h b/include/common.h index 4ac22b0..6a82ace 100644 --- a/include/common.h +++ b/include/common.h @@ -1,49 +1,33 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #ifndef COMMON_H #define COMMON_H #include -#ifdef AArch64 typedef uint64_t uintptr_t; #define CPU_BYTE_SIZE SIZE_64BIT -#endif - -#ifdef AArch32 -//typedef uint32_t uintptr_t; -#define CPU_BYTE_SIZE SIZE_32BIT -#endif - #define DIS_RTN 0 /* Disable Return */ #define ENB_RTN 1 /* Enable Return */ @@ -66,25 +50,11 @@ typedef uint64_t uintptr_t; #define COMMAND_BUFFER_SIZE 1024 -#if USB_ENABLE == 1 -#define SCIF2_TERMINAL 0 -#define USB_TERMINAL 1 -#define DMA_TRANSFER_SIZE (0x20) /* DMA Transfer size = 32 Bytes */ - -extern uint32_t gTerminal; -#endif /* USB_ENABLE == 1 */ /******************************** Module Proto Type * *********************************/ -int32_t PutMess(const char *const mess[]); int32_t PutStr(const char *str,char rtn); -#if USB_ENABLE == 1 -int32_t PutMessUSB(const char *const mess[]); -int32_t PutStrUSB(const char *str,char rtn); -int32_t PutCharUSB(char outChar); -int32_t GetCharUSB(char *inChar); -#endif /* USB_ENABLE == 1 */ int32_t GetStr(char *str,char *chCnt); uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt); uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt); diff --git a/include/cpudrv.h b/include/cpudrv.h index 02f11ef..282d3f2 100644 --- a/include/cpudrv.h +++ b/include/cpudrv.h @@ -1,36 +1,29 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +#include "rdk_common.h" + +#define StartTMU0(t) CMN_DelayInMS(t) +#define StartTMU0usec(t) CMN_DelayInUS(t) -void StartTMU0(uint32_t tenmSec); -void StartTMU0usec(uint32_t tenuSec); -void PowerOnTmu0(void); -uint32_t GetGpioInputLevel( uint32_t gp, uint32_t bit ); diff --git a/include/ddrcheck.h b/include/ddrcheck.h deleted file mode 100644 index accee70..0000000 --- a/include/ddrcheck.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -void dgDdrTest(void); -void dgRamTest(void); diff --git a/include/debug.h b/include/debug.h deleted file mode 100644 index 50fd4b3..0000000 --- a/include/debug.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - - -#define tf_printf(...) -#define NOTICE(...) - -#endif /* __DEBUG_H__ */ diff --git a/include/devdrv.h b/include/devdrv.h index dfaea4a..2aae941 100644 --- a/include/devdrv.h +++ b/include/devdrv.h @@ -1,34 +1,26 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ int32_t PutChar(char outChar); int32_t GetChar(char *inChar); -int32_t WaitPutCharSendEnd(void); +int32_t GetCharTimeOut(char *inChar, uint64_t us); diff --git a/include/dgemmc.h b/include/dgemmc.h index 57e8b10..1287993 100644 --- a/include/dgemmc.h +++ b/include/dgemmc.h @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #ifndef __DG_EMMC_H__ #define __DG_EMMC_H__ @@ -39,7 +31,6 @@ extern void dg_emmc_set_ext_csd(void); extern void dg_init_emmc(void); extern unsigned long dg_emmc_check_init(void); -extern void dg_emmc_write_mot(void); extern void dg_emmc_write_bin(void); extern void dg_emmc_erase(void); extern void InitMmcDrv(void); diff --git a/include/dgmodul1.h b/include/dgmodul1.h deleted file mode 100644 index e517ebf..0000000 --- a/include/dgmodul1.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#define VERIFY_OFF 0 -#define VERIFY_ON 1 - -// LF Work Memory -#define DramArea3_SADD 0x50000000 -#define DramArea3_EADD 0x53FFFFFF -#define FlashArea1_SADD 0x04000000 - -#define ADDITION 0x00000000 -#define SUBTRACTION 0x00000001 - -#define LS_WORK_DRAM_SADD 0x50000000 - -void dgHelp(void); -int32_t GetStr_ByteCount(char *str,uint32_t getByteCount); -void dgScifSpeedUp(void); -void dgScifSpeedUp_921600(void); - diff --git a/include/dgmodul4.h b/include/dgmodul4.h deleted file mode 100644 index aea773d..0000000 --- a/include/dgmodul4.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#define CHANGE_OFF 0 -#define CHANGE_ON 1 - -#define ADDITION 0x00000000 -#define SUBTRACTION 0x00000001 - -#define SYSTEMRAM_SADD 0xE6300000 -#define SYSTEMRAM_IPL_SADD 0xE6302000 -#define PUBLICRAM_EADD 0xE635FFFF - -#define LS_WORK_DRAM_SADD 0x50000000 -#define LS_WORK_DRAM_EADD_192K 0x5002FFFF -#define LS_WORK_DRAM_EADD_16K 0x50003FFF -#define LS_WORK_DRAM_EADD_64M 0x53FFFFFF - -#define WORK_SPI_LOAD_AREA 0x58000000 - -#define LS_WORK_SRAMBD_SADD 0x04000000 -#define LS_WORK_SRAMBD_EADD_192K 0x0402FFFF -#define LS_WORK_SRAMBD_EADD_16M 0x04FFFFFF - -//Serial Flash ROM -#define QSPI_SA_SIZE 0x0040000 - -#define QSPI_SA00_STARTAD 0x0000000 -#define QSPI_SA01_STARTAD 0x0040000 -#define QSPI_SA02_STARTAD 0x0080000 -#define QSPI_SA03_STARTAD 0x00C0000 //User Add,Size -#define QSPI_SA04_STARTAD 0x0100000 //User Image -#define QSPI_END_ADDRESS 0x3FF7FFF - -#define SPIBOOT_UPRG_ST_AD 0x00C0000 -#define SPIBOOT_UPRG_SIZE 0x00C0004 - -#define SPIBOOT_BTROM_PARA 0x0000000 //Boot ROM Parameters (4Byte) -#define SPIBOOT_A_IPL_ADD 0x0000D54 //A-side IPL address (4Byte) -#define SPIBOOT_A_IPL_SIZE 0x0000E64 //A-side IPL data size(4Byte) -#define SPIBOOT_B_IPL_ADD 0x0001154 //B-side IPL address (4Byte) -#define SPIBOOT_B_IPL_SIZE 0x0001264 //B-side IPL data size(4Byte) - -#define SA_256KB 0x40000 -#define SA_64KB 0x10000 - -#define TOTAL_SIZE_256MB 0x10000000 -#define TOTAL_SIZE_128MB 0x08000000 -#define TOTAL_SIZE_64MB 0x04000000 -#define TOTAL_SIZE_32MB 0x02000000 -#define TOTAL_SIZE_16MB 0x01000000 -#define TOTAL_SIZE_8MB 0x00800000 - -#define CYPRESS_MANUFACTURER_ID 0x01 /* Cypress */ -#define WINBOND_MANUFACTURER_ID 0xEF /* Winbond */ -#define MACRONIX_MANUFACTURER_ID 0xC2 /* Macronix */ -#define MICRON_MANUFACTURER_ID 0x20 /* Micron */ - -#define DEVICE_ID_S25FS128S 0x2018 -#define DEVICE_ID_S25FS512S 0x0220 - -#define DEVICE_ID_W25Q64JV 0x4017 -#define DEVICE_ID_W25Q64JW 0x6017 -#define DEVICE_ID_W25Q128JV 0x4018 -#define DEVICE_ID_W25Q128JW 0x6018 -#define DEVICE_ID_W25Q256 0x4019 -#define DEVICE_ID_W25M512JV 0x7119 -#define DEVICE_ID_W25M512JW 0x6119 -#define DEVICE_ID_W25Q512JV 0x4020 -#define DEVICE_ID_W25Q512JV_DTR 0x7020 - -#define DEVICE_ID_MX25L12805 0x2018 -#define DEVICE_ID_MX25L25635F 0x2019 -#define DEVICE_ID_MX25L51245G 0x201A -#define DEVICE_ID_MX66U25635F 0x2539 -#define DEVICE_ID_MX66U51235F 0x253A - -#define DEVICE_ID_MT25QL128 0xBA18 -#define DEVICE_ID_MT25QU128 0xBB18 -#define DEVICE_ID_MT25QL256 0xBA19 -#define DEVICE_ID_MT25QU256 0xBB19 -#define DEVICE_ID_MT25QL512 0xBA20 -#define DEVICE_ID_MT25QU512 0xBB20 -#define DEVICE_ID_MT25QL01G 0xBA21 -#define DEVICE_ID_MT25QU01G 0xBB21 -#define DEVICE_ID_MT25QL02G 0xBA22 -#define DEVICE_ID_MT25QU02G 0xBB22 - -void dgG2LoadSpiflash0(void); -void InitRPC_Mode(void); -uint32_t CheckQspiFlashId(void); -int32_t CkQspiFlash1ClearSectorSize(uint32_t rdBufAdd,uint32_t spiFlashStatAdd,uint32_t checkSize,uint32_t accessSize); -void mem_copy(uint32_t prgStartAd, uint32_t sector_Ad, uint32_t accessSize); -void dgG2LoadSpiflash0_2(void); -void dgG2LoadSpiflash0_3(void); -void XLoadSpiflash0_2(uint32_t mode); - -void SetData(uint32_t *setAdd); -int32_t CkSpiFlashAllF(int32_t sAdd,int32_t cap); -void SetAddInputKey(uint32_t *Address); -void SetSizeInputKey(uint32_t *size); -void dgG2InfoSpiflash0_SA0(void); -int32_t CheckDataChange(uintptr_t checkAdd); -void dgG2InfoSetSpiflash0_SA0(void); -void dgG2InfoSpiflash0(void); -void dgG2InfoSetSpiflash0(void); -void dgClearSpiflash0(void); -char dgLS_Load_Offset2(uint32_t *maxADD ,uint32_t *minADD); diff --git a/include/dgtable.h b/include/dgtable.h index 2d8f277..cb6d5b1 100644 --- a/include/dgtable.h +++ b/include/dgtable.h @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ /********************** * COMMAND_UNITE * @@ -50,29 +42,6 @@ #define DISABLE 0x00 #define ENABLE 0x01 -#ifdef AArch32 -#define ARM_CPSR 0 -#define ARM_R0 1 -#define ARM_R1 2 -#define ARM_R2 3 -#define ARM_R3 4 -#define ARM_R4 5 -#define ARM_R5 6 -#define ARM_R6 7 -#define ARM_R7 8 -#define ARM_R8 9 -#define ARM_R9 10 -#define ARM_R10 11 -#define ARM_R11 12 -#define ARM_R12 13 -//#define ARM_R13(SP) 13 -//#define ARM_R14(LR) 14 -//#define ARM_R15(PC) 15 -#define ARM_R14(LR) 14 -#define ARM_R15(PC) 15 -#define ARM_R13(SP) 16 -#endif - /****************************************************************/ /* */ /* Command Table Struct */ diff --git a/include/dmaspi.h b/include/dmaspi.h deleted file mode 100644 index 27700b2..0000000 --- a/include/dmaspi.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -void InitDma01_Data(uint32_t prgStartAd, uint32_t sector_Ad, uint32_t accessCount); -void DisableDma01(void); -void StartDma01(void); -uint32_t WaitDma01(void); -void ClearDmaCh01(void); diff --git a/include/emmc_config.h b/include/emmc_config.h index 24f4223..c65409c 100644 --- a/include/emmc_config.h +++ b/include/emmc_config.h @@ -1,84 +1,61 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file emmc_config.h - * @brief Configuration file - * - */ - -#ifndef __EMMC_CONFIG_H__ -#define __EMMC_CONFIG_H__ - -/* ************************ HEADER (INCLUDE) SECTION *********************** */ - -/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ - -/** @brief eMMC address map - */ -#define SYS_RAM_BASE_ADD 0xE6300000UL /* SYSTEM RAM BASE ADD */ -#define EMMC_MULTI_BOOT_SADD 0x00004000UL /* Multi Boot start add (512byte order) */ -#define EMMC_MULTI_BOOT_SIZE 0x0000A000UL /* Multi Boot size (512byte order) */ -#define EMMC_MULTI_BOOT_DEST_ADD (SYS_RAM_BASE_ADD + EMMC_MULTI_BOOT_SADD) /* Multi Boot dest add */ -#define EMMC_UBOOT_TRANS_DATA_SADD 0x0001EFF0UL /* UBOOT trans data add */ -#define EMMC_UBOOT_TRANS_DATA_DEST_ADD (SYS_RAM_BASE_ADD + EMMC_UBOOT_TRANS_DATA_SADD) /* UBOOT trans data dest add (512byte order) */ - -#define EMMC_UBOOT_TRANS_DEST_ADD_INDEX ((EMMC_UBOOT_TRANS_DATA_SADD & 0x1FF)>>2) /* UBOOT trans dest add index */ -#define EMMC_UBOOT_TRANS_SIZE_INDEX (EMMC_UBOOT_TRANS_DEST_ADD_INDEX+1) /* UBOOT trans size index */ - -/** @brief MMC driver config - */ -#define EMMC_RCA 1UL /* RCA */ -#define EMMC_RW_DATA_TIMEOUT 0x40UL /* 345ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ -#define EMMC_RETRY_COUNT 0 /* how many times to try after fail. Don't change. */ -#define EMMC_CMD_MAX 60UL /* Don't change. */ - -/** @brief etc - */ -#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL - - -/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ -//#define EMMC_VOLTAGE_1_8 /* Voltage=1.8V driver spec 1/2 */ - /* invalid: Voltage=3.3V driver spec 3/4 */ -//#define EMMC_DEBUG /* eMMC drv debug log output */ - /* 1st Cut: No conditions */ - /* 2nd Cut: After the multi-boot was successful */ -//#define EMMC_TOOL_DUMP /* eMMC Tool dump log output */ -/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ - -/* ************************** FUNCTION PROTOTYPES ************************** */ - -/* ********************************* CODE ********************************** */ - -#endif /* #ifndef __EMMC_CONFIG_H__ */ -/* ******************************** END ************************************ */ - +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +#ifndef __EMMC_CONFIG_H__ +#define __EMMC_CONFIG_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define SYS_RAM_BASE_ADD 0xE6300000UL /* SYSTEM RAM BASE ADD */ +#define EMMC_MULTI_BOOT_SADD 0x00004000UL /* Multi Boot start add (512byte order) */ +#define EMMC_MULTI_BOOT_SIZE 0x0000A000UL /* Multi Boot size (512byte order) */ +#define EMMC_MULTI_BOOT_DEST_ADD (SYS_RAM_BASE_ADD + EMMC_MULTI_BOOT_SADD) /* Multi Boot dest add */ +#define EMMC_UBOOT_TRANS_DATA_SADD 0x0001EFF0UL /* UBOOT trans data add */ +#define EMMC_UBOOT_TRANS_DATA_DEST_ADD (SYS_RAM_BASE_ADD + EMMC_UBOOT_TRANS_DATA_SADD) /* UBOOT trans data dest add (512byte order) */ + +#define EMMC_UBOOT_TRANS_DEST_ADD_INDEX ((EMMC_UBOOT_TRANS_DATA_SADD & 0x1FF)>>2) /* UBOOT trans dest add index */ +#define EMMC_UBOOT_TRANS_SIZE_INDEX (EMMC_UBOOT_TRANS_DEST_ADD_INDEX+1) /* UBOOT trans size index */ + +#define EMMC_RCA 1UL /* RCA */ +#define EMMC_RW_DATA_TIMEOUT 0x40UL /* 345ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ +#define EMMC_RETRY_COUNT 0 /* how many times to try after fail. Don't change. */ +#define EMMC_CMD_MAX 60UL /* Don't change. */ + +#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ +//#define EMMC_VOLTAGE_1_8 /* Voltage=1.8V driver spec 1/2 */ + /* invalid: Voltage=3.3V driver spec 3/4 */ +//#define EMMC_DEBUG /* eMMC drv debug log output */ +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* #ifndef __EMMC_CONFIG_H__ */ +/* ******************************** END ************************************ */ + diff --git a/include/emmc_def.h b/include/emmc_def.h index ea7e503..cb6a63d 100644 --- a/include/emmc_def.h +++ b/include/emmc_def.h @@ -1,39 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file emmc_def.h - * @brief eMMC boot is expecting this header file - * - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #ifndef __EMMC_DEF_H__ #define __EMMC_DEF_H__ @@ -61,12 +47,8 @@ EXTERN st_mmc_base mmc_drv_obj; #endif /* REWRITE_TOOL */ /* ************************** FUNCTION PROTOTYPES ************************** */ -/** @brief for assembler program - */ EXTERN uint32_t _rom_emmc_finalize (void); -/** @brief eMMC driver API - */ EXTERN EMMC_ERROR_CODE emmc_init(uint8_t low_clock_mode_enable); EXTERN EMMC_ERROR_CODE emmc_terminate(void); EXTERN EMMC_ERROR_CODE emmc_memcard_power(uint8_t mode); @@ -80,24 +62,14 @@ EXTERN EMMC_ERROR_CODE emmc_erase_sector(uint32_t start_address,uint32_t end_add EXTERN uint32_t emmc_bit_field (uint8_t *data, uint32_t top, uint32_t bottom); -/** @brief interrupt service - */ EXTERN uint32_t emmc_interrupt(void); -/** @brief DMA - */ - - -/** @brief send command API - */ EXTERN EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response); EXTERN void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg); EXTERN void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); EXTERN EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg); -/** @brief for error information - */ EXTERN void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code); EXTERN void emmc_write_error_info_func_no (uint16_t func_no); diff --git a/include/emmc_hal.h b/include/emmc_hal.h index 068fec4..8a35f92 100644 --- a/include/emmc_hal.h +++ b/include/emmc_hal.h @@ -1,39 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file emmc_hal.h - * @brief emmc boot driver is expecting this header file - * - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #ifndef __EMMC_HAL_H__ #define __EMMC_HAL_H__ @@ -41,8 +27,6 @@ #include "types.h" /* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ -/** @brief memory card error/status types - */ #define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L #define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L #define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L @@ -69,14 +53,10 @@ #define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L #define HAL_MEMCARD_NO_ERRORS 0x00000000L -/** @brief Memory card response types - */ #define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f /* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ -/** @brief Type of the return value. - */ typedef enum { HAL_MEMCARD_FAIL = 0U, @@ -90,16 +70,12 @@ typedef enum HAL_MEMCARD_DATA_CRC_ERROR = 8U /**< Data CRC error occurred */ } HAL_MEMCARD_RETURN; -/** @brief memory access operation - */ typedef enum { HAL_MEMCARD_READ = 0U, /**< read */ HAL_MEMCARD_WRITE = 1U /**< write */ } HAL_MEMCARD_OPERATION; -/** @brief Type of data width on memorycard bus - */ typedef enum { HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U, @@ -107,25 +83,18 @@ typedef enum HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U } HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */ -/** @brief Presence of the memory card - */ typedef enum { HAL_MEMCARD_CARD_IS_IN = 0U, HAL_MEMCARD_CARD_IS_OUT = 1U } HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card*/ -/** @brief mode of data transfer - */ typedef enum { HAL_MEMCARD_DMA = 0U, HAL_MEMCARD_NOT_DMA = 1U } HAL_MEMCARD_DATA_TRANSFER_MODE; - -/** @brief Memory card response types. - */ typedef enum hal_memcard_response_type { HAL_MEMCARD_RESPONSE_NONE = 0x00000U, @@ -141,8 +110,6 @@ typedef enum hal_memcard_response_type } HAL_MEMCARD_RESPONSE_TYPE; -/** @brief Memory card command types. - */ typedef enum hal_memcard_command_type { HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U, @@ -153,8 +120,6 @@ typedef enum hal_memcard_command_type HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U } HAL_MEMCARD_COMMAND_TYPE; -/** @brief Type of memory card - */ typedef enum hal_memcard_command_card_type { HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U, @@ -163,8 +128,6 @@ typedef enum hal_memcard_command_card_type HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U } HAL_MEMCARD_COMMAND_CARD_TYPE; -/** @brief Memory card application command. - */ typedef enum hal_memcard_command_app_norm { HAL_MEMCARD_COMMAND_NORMAL = 0x00000U, @@ -173,8 +136,6 @@ typedef enum hal_memcard_command_app_norm } HAL_MEMCARD_COMMAND_APP_NORM; -/** @brief Memory card command codes. - */ typedef enum { /* class 0 and class 1 */ @@ -275,54 +236,6 @@ typedef enum } HAL_MEMCARD_COMMAND; -/** @brief Configuration structure from HAL layer. - * - * If some field is not available it should be filled with 0xFF. - * The API version is 32-bit unsigned integer telling the version of the API. The integer is divided to four sections which each can be treated as a 8-bit unsigned number: - * Bits 31-24 make the most significant part of the version number. This number starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This number changes only, if the API itself changes so much that it is not compatible anymore with older releases. - * Bits 23-16 API minor version number. For example API version 2.1 would be 0x0201xxxx. - * Bits 15-8 are the number of the year when release is done. The 0 is year 2000, 1 is year 2001 and so on - * Bits 7- are the week number when release is done. First full week of the year is 1 - * - * @note Example: let's assume that release 2.1 is done on week 10 year 2008 the version will get the value 0x0201080A - */ -typedef struct -{ - /** - * Version of the chipset API implementation - * - * bits [31:24] API specification major version number.
- * bits [23:16] API specification minor version number.
- * bits [15:8] API implemention year. (2000 = 0, 2001 = 1, ...)
- * bits [7:0] API implemention week.
- * Example: API specification version 4.0, implementation w46 2008 => 0x0400082E - */ - uint32_t api_version; - - /** maximum block count which can be transferred at once */ - uint32_t max_block_count; - - /** maximum clock frequence in Hz supported by HW */ - uint32_t max_clock_freq; - - /** maximum data bus width supported by HW */ - uint16_t max_data_width; - - /** Is high-speed mode supported by HW (yes=1, no=0) */ - uint8_t hs_mode_supported; - - /** Is memory card removable (yes=1, no=0) */ - uint8_t card_removable; - -} HAL_MEMCARD_HW_CONF; - -/** @brief Configuration structure to HAL layer. - */ -typedef struct -{ - /** how many times to try after fail, for instance sending command */ - uint32_t retries_after_fail; -} HAL_MEMCARD_INIT_CONF; /* ********************** DECLARATION OF EXTERNAL DATA ********************* */ diff --git a/include/emmc_registers.h b/include/emmc_registers.h index 1add419..af83b64 100644 --- a/include/emmc_registers.h +++ b/include/emmc_registers.h @@ -1,39 +1,25 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file emmc_registers.h - * @brief emmc boot driver is expecting this header file. HS-MMC module header file. - * - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #ifndef __EMMC_REGISTERS_H__ #define __EMMC_REGISTERS_H__ @@ -45,12 +31,10 @@ #define MMC_CH0 (0U) /* SDHI2/MMC0 */ #define MMC_CH1 (1U) /* SDHI3/MMC1 */ -#define USE_MMC_CH (MMC_CH1) /* RZ/G2E, RZ/G2M, RZ/G2N */ +#define USE_MMC_CH (MMC_CH1) -/** @brief eMMC registers - */ -#define MMC0_SD_BASE (0xEE140000U) -#define MMC1_SD_BASE (0xEE160000U) +#define MMC0_SD_BASE (0x85020000U) +#define MMC1_SD_BASE (0x85020000U) #if USE_MMC_CH == MMC_CH0 #define MMC_SD_BASE (MMC0_SD_BASE) @@ -100,8 +84,6 @@ -/** @brief SD_INFO1 Registers - */ #define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */ #define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */ #define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */ @@ -113,8 +95,6 @@ #define SD_INFO1_INFO2 0x00000004UL /* Access end */ #define SD_INFO1_INFO0 0x00000001UL /* Response end */ -/** @brief SD_INFO2 Registers - */ #define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */ #define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */ #define SD_INFO2_SCLKDIVEN 0x00002000UL @@ -131,12 +111,8 @@ #define SD_INFO2_ALL_ERR 0x0000807FUL #define SD_INFO2_CLEAR 0x00000800UL /* BIT11 The write value should always be 1. HWM_0003 */ -/** @brief SOFT_RST - */ #define SOFT_RST_SDRST 0x00000001UL -/** @brief SD_CLK_CTRL - */ #define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL #define SD_CLK_CTRL_SCLKEN 0x00000100UL #define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL @@ -145,14 +121,9 @@ #define SD_CLK_WRITE_MASK 0x000003FFUL #define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL -/** @brief SD_OPTION - */ #define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL -/** @brief MMC Clock Frequency - * 200MHz * 1/x = output clock - */ #define MMC_CLK_OFF 0UL /* Clock output is disabled */ #define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */ #define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */ @@ -167,8 +138,6 @@ #define MMC_FREQ_20MHZ 20000000UL -/** @brief MMC Clock DIV - */ #define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */ #define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ #define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */ @@ -182,33 +151,21 @@ #define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */ #define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */ -/** @brief DM_CM_DTRAN_MODE - */ #define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */ #define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */ #define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL -/** @brief CC_EXT_MODE - */ #define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */ #define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */ -/** @brief DM_CM_INFO_MASK - */ #define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL #define DM_CM_INFO_CH0_ENABLE 0x00010001UL #define DM_CM_INFO_CH1_ENABLE 0x00020001UL -/** @brief DM_DTRAN_ADDR - */ #define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL -/** @brief DM_CM_DTRAN_CTRL - */ #define DM_CM_DTRAN_CTRL_START 0x00000001UL -/** @brief SYSC Registers - */ #define CPG_MSTP_MMC 0x00001000UL //MMC0:0x00001000 MMC1:0x00000800 diff --git a/include/emmc_std.h b/include/emmc_std.h index 47686e1..42735bf 100644 --- a/include/emmc_std.h +++ b/include/emmc_std.h @@ -1,39 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file emmc_std.h - * @brief eMMC boot is expecting this header file - * - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #ifndef __EMMC_STD_H__ #define __EMMC_STD_H__ @@ -42,103 +28,36 @@ /* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ -/** @brief 64bit registers - **/ #define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v)) #define GETR_64(r) (*(volatile uint64_t *)(r)) -/** @brief 32bit registers - **/ #define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v)) #define GETR_32(r) (*(volatile uint32_t *)(r)) -/** @brief 16bit registers - */ #define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v)) #define GETR_16(r) (*(volatile uint16_t *)(r)) -/** @brief 8bit registers - */ #define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v)) #define GETR_8(r) (*(volatile uint8_t *)(r)) -/** @brief CSD register Macros - */ #define EMMC_GET_CID(x,y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y))) -#if 0 -#define EMMC_CID_MID() (EMMC_GET_CID(127,120)) -#define EMMC_CID_CBX() (EMMC_GET_CID(113,112)) -#define EMMC_CID_OID() (EMMC_GET_CID(111,104)) -#define EMMC_CID_PNM1() (EMMC_GET_CID(103,88)) -#define EMMC_CID_PNM2() (EMMC_GET_CID(87,56)) -#define EMMC_CID_PRV() (EMMC_GET_CID(55,48)) -#define EMMC_CID_PSN() (EMMC_GET_CID(47,16)) -#define EMMC_CID_MDT() (EMMC_GET_CID(15,8)) -#define EMMC_CID_CRC() (EMMC_GET_CID(7,1)) -#endif - - -/** @brief CSD register Macros - */ #define EMMC_GET_CSD(x,y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y))) #define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125,122)) #define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103,96)) -#if 0 -#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127,126)) -#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125,122)) -#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119,112)) -#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111,104)) -#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103,96)) -#define EMMC_CSD_CCC() (EMMC_GET_CSD(95,84)) -#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83,80)) -#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79,79)) -#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78,78)) -#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77,77)) -#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76,76)) -#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73,62)) -#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61,59)) -#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58,56)) -#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55,53)) -#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52,50)) -#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49,47)) -#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46,42)) -#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41,37)) -#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36,32)) -#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31,31)) -#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30,29)) -#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28,26)) -#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25,22)) -#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21,21)) -#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16,16)) -#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15,15)) -#define EMMC_CSD_COPY() (EMMC_GET_CSD(14,14)) -#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13,13)) -#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12,12)) -#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11,10)) -#define EMMC_CSD_ECC() (EMMC_GET_CSD(9,8)) -#define EMMC_CSD_CRC() (EMMC_GET_CSD(7,1)) -#endif - -/** @brief for sector access - */ #define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003 /* 4Bytes boundary check mask */ #define EMMC_SECTOR_SIZE_SHIFT 9 /* 512 = 2^9 */ #define EMMC_SECTOR_SIZE 512 #define EMMC_BLOCK_LENGTH 512 #define EMMC_BLOCK_LENGTH_DW 128 -/** @brief eMMC specification clock - */ #define EMMC_CLOCK_SPEC_400K 400000UL /**< initialize clock 400KHz */ #define EMMC_CLOCK_SPEC_20M 20000000UL /**< normal speed 20MHz */ #define EMMC_CLOCK_SPEC_26M 26000000UL /**< high speed 26MHz */ #define EMMC_CLOCK_SPEC_52M 52000000UL /**< high speed 52MHz */ #define EMMC_CLOCK_SPEC_100M 100000000UL /**< high speed 100MHz */ -/** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN) - */ typedef enum { EMMC_ERR = 0, /**< unknown error */ @@ -169,7 +88,6 @@ typedef enum EMMC_ERR_INFO2 /**< exec cmd error info2 */ } EMMC_ERROR_CODE; -/** @brief Function number */ #define EMMC_FUNCNO_NONE 0 #define EMMC_FUNCNO_DRIVER_INIT 1 #define EMMC_FUNCNO_CARD_POWER_ON 2 @@ -188,9 +106,6 @@ typedef enum #define EMMC_FUNCNO_WRITE_SECTOR 15 #define EMMC_FUNCNO_ERASE_SECTOR 16 -/** @brief Response - */ -/** R1 */ #define EMMC_R1_ERROR_MASK 0xFDBFE080UL /* Type 'E' bit and bit14(must be 0). ignore bit22 */ #define EMMC_R1_STATE_MASK 0x00001E00UL /* [12:9] */ #define EMMC_R1_READY 0x00000100UL /* bit8 */ @@ -355,21 +270,17 @@ typedef enum #define EMMC_MAX_CSD_LENGTH 16 #define EMMC_MAX_EXT_CSD_LENGTH 512 -/** @brief for TAAC mask - */ #define TAAC_TIME_UNIT_MASK (0x07) #define TAAC_MULTIPLIER_FACTOR_MASK (0x0F) /* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ -/** @brief Partition id - */ typedef enum { PARTITION_ID_USER = 0x0, /**< User Area */ - PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */ - PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */ + PARTITION_ID_BOOT_0 = 0x1, /**< boot partition 0 */ + PARTITION_ID_BOOT_1 = 0x2, /**< boot partition 1 */ PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */ PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */ PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */ @@ -378,8 +289,6 @@ typedef enum PARTITION_ID_MASK = 0x7 /**< [2:0] */ } EMMC_PARTITION_ID; -/** @brief card state in R1 response [12:9] - */ typedef enum { EMMC_R1_STATE_IDLE = 0, @@ -410,8 +319,6 @@ typedef enum{ ESTATE_END }EMMC_INT_STATE; -/** @brief eMMC boot driver error information - */ typedef struct { uint16_t num; /**< error no */ uint16_t code; /**< error code */ @@ -424,8 +331,6 @@ typedef struct { } st_error_info; -/** @brief Command information - */ typedef struct { HAL_MEMCARD_COMMAND cmd; /**< Command information */ uint32_t arg; /**< argument */ @@ -434,8 +339,6 @@ typedef struct { } st_command_info; -/** @brief MMC driver base - */ typedef struct { st_error_info error_info; /**< error information */ st_command_info cmd_info; /**< command information */ diff --git a/include/init_scif.h b/include/init_scif.h index 23e9ec1..0177947 100644 --- a/include/init_scif.h +++ b/include/init_scif.h @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #ifndef INITSCIF_H #define INITSCIF_H diff --git a/include/main.h b/include/main.h index 4122995..ab1303a 100644 --- a/include/main.h +++ b/include/main.h @@ -1,36 +1,27 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ void Main(void); -void InitMain(void); void StartMess( void ); void DecCom(void); long CmpCom(char *str); diff --git a/include/micro_wait.h b/include/micro_wait.h deleted file mode 100644 index 2199764..0000000 --- a/include/micro_wait.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef MICRO_WAIT_H__ -#define MICRO_WAIT_H__ - -#define TMU3_MEASUREMENT (0) /* for time measurement */ - -#ifndef __ASSEMBLY__ -void micro_wait(uint32_t count_us); - -/* Time measurement function using the TMU3. */ -#if (TMU3_MEASUREMENT == 1) -void init_TMU3(void); -void start_TMU3(void); -uint32_t snapshot_TCNT3(void); -void stop_TMU3(void); -#endif /* TMU3_MEASUREMENT */ - -#endif /* __ASSEMBLY__ */ - -#endif /* MICRO_TWAIT_H__ */ diff --git a/include/mmio.h b/include/mmio.h deleted file mode 100644 index 75bf30d..0000000 --- a/include/mmio.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __MMIO_H__ -#define __MMIO_H__ - -#include - -static inline void mmio_write_8(uintptr_t addr, uint8_t value) -{ - *(volatile uint8_t*)addr = value; -} - -static inline uint8_t mmio_read_8(uintptr_t addr) -{ - return *(volatile uint8_t*)addr; -} - -static inline void mmio_write_16(uintptr_t addr, uint16_t value) -{ - *(volatile uint16_t*)addr = value; -} - -static inline uint16_t mmio_read_16(uintptr_t addr) -{ - return *(volatile uint16_t*)addr; -} - -static inline void mmio_write_32(uintptr_t addr, uint32_t value) -{ - *(volatile uint32_t*)addr = value; -} - -static inline uint32_t mmio_read_32(uintptr_t addr) -{ - return *(volatile uint32_t*)addr; -} - -static inline void mmio_write_64(uintptr_t addr, uint64_t value) -{ - *(volatile uint64_t*)addr = value; -} - -static inline uint64_t mmio_read_64(uintptr_t addr) -{ - return *(volatile uint64_t*)addr; -} - -static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear) -{ - mmio_write_32(addr, mmio_read_32(addr) & ~clear); -} - -static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) -{ - mmio_write_32(addr, mmio_read_32(addr) | set); -} - -static inline void mmio_clrsetbits_32(uintptr_t addr, - uint32_t clear, - uint32_t set) -{ - mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set); -} - -#endif /* __MMIO_H__ */ diff --git a/include/ramckmdl.h b/include/ramckmdl.h index e1f1f48..a9cf3d5 100644 --- a/include/ramckmdl.h +++ b/include/ramckmdl.h @@ -1,32 +1,24 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ int32_t FillData32Bit( uint32_t *startAddr, uint32_t *endAddr, uint32_t writeData ); diff --git a/include/rdk_cmn_cpg.h b/include/rdk_cmn_cpg.h new file mode 100644 index 0000000..60766dd --- /dev/null +++ b/include/rdk_cmn_cpg.h @@ -0,0 +1,304 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_cmn_cpg.h + * Description : register and API information for CPG + ******************************************************************************/ + +#ifndef RDK_CMN_CPG_H +#define RDK_CMN_CPG_H + +/* CPG */ +#define CPG_BASE_ADDRESS (0x0A3500000ULL) + +/** Registor Offset */ +#define CPG_PLL1_STBY (0x0000) +#define CPG_PLL1_CLK1 (0x0004) +#define CPG_PLL1_CLK2 (0x0008) +#define CPG_PLL1_MON (0x000C) +#define CPG_PLL2_STBY (0x0010) +#define CPG_PLL2_CLK1 (0x0014) +#define CPG_PLL2_CLK2 (0x0018) +#define CPG_PLL2_MON (0x001C) +#define CPG_PLL3_STBY (0x0020) +#define CPG_PLL3_CLK1 (0x0024) +#define CPG_PLL3_CLK2 (0x0028) +#define CPG_PLL3_MON (0x002C) +#define CPG_PLL6_STBY (0x0030) +#define CPG_PLL6_CLK1 (0x0034) +#define CPG_PLL6_CLK2 (0x0038) +#define CPG_PLL6_MON (0x003C) +#define CPG_PLL7_STBY (0x0040) +#define CPG_PLL7_CLK1 (0x0044) +#define CPG_PLL7_CLK2 (0x0048) +#define CPG_PLL7_MON (0x004C) + + +#define CPG_PLL4_STBY (0x0100) +#define CPG_PLL4_CLK1 (0x0104) +#define CPG_PLL4_CLK2 (0x0108) +#define CPG_PLL4_MON (0x010C) + + +#define CPG_PLL1_CCTRL_RST (0x0180) +#define CPG_PLL2_CCTRL_RST (0x0184) +#define CPG_PLL3_CCTRL_RST (0x0188) +#define CPG_PLL4_CCTRL_RST (0x018C) + +#define CPG_PLL7_CCTRL_RST (0x0198) + +#define CPG_CA53_DDIV (0x0200) +#define CPG_SYS_DDIV (0x0204) +#define CPG_MMCDDI_DDIV (0x0210) +#define CPG_CLK48_DSEL (0x0214) +#define CPG_CLKSTATUS (0x0224) + + +#define CPG_SDIEMM_SSEL (0x0300) +#define CPG_GMCLK_SDIV (0x031C) +#define CPG_GMCLK_SSEL (0x0320) +#define CPG_URT_RCLK_SDIV (0x0328) +#define CPG_URT_RCLK_SSEL (0x032C) +#define CPG_CSI_RCLK_SSEL (0x0330) + + +#define CPG_CLK_ON1 (0x0400) +#define CPG_CLK_ON2 (0x0404) +#define CPG_CLK_ON3 (0x0408) +#define CPG_CLK_ON4 (0x040C) +#define CPG_CLK_ON5 (0x0410) +#define CPG_CLK_ON6 (0x0414) +#define CPG_CLK_ON7 (0x0418) +#define CPG_CLK_ON8 (0x041C) +#define CPG_CLK_ON9 (0x0420) +#define CPG_CLK_ON10 (0x0424) +#define CPG_CLK_ON11 (0x0428) +#define CPG_CLK_ON12 (0x042C) +#define CPG_CLK_ON13 (0x0430) +#define CPG_CLK_ON14 (0x0434) +#define CPG_CLK_ON15 (0x0438) +#define CPG_CLK_ON16 (0x043C) +#define CPG_CLK_ON17 (0x0440) +#define CPG_CLK_ON18 (0x0444) +#define CPG_CLK_ON19 (0x0448) +#define CPG_CLK_ON20 (0x044C) +#define CPG_CLK_ON21 (0x0450) +#define CPG_CLK_ON22 (0x0454) +#define CPG_CLK_ON23 (0x0458) +#define CPG_CLK_ON24 (0x045C) +#define CPG_CLK_ON25 (0x0460) +#define CPG_CLK_ON26 (0x0464) +#define CPG_CLK_ON27 (0x0468) + +#define CPG_RST_MSK (0x0504) + + +#define CPG_RST1 (0x0600) +#define CPG_RST2 (0x0604) +#define CPG_RST3 (0x0608) +#define CPG_RST4 (0x060C) +#define CPG_RST5 (0x0610) +#define CPG_RST6 (0x0614) +#define CPG_RST7 (0x0618) +#define CPG_RST8 (0x061C) +#define CPG_RST9 (0x0620) +#define CPG_RST10 (0x0624) +#define CPG_RST11 (0x0628) +#define CPG_RST12 (0x062C) +#define CPG_RST13 (0x0630) +#define CPG_RST14 (0x0634) +#define CPG_RST15 (0x0638) + + +#define CPG_RST_MON (0x0680) + +#define CPG_PD_RST (0x0800) + + +/** Bit assign */ +#define CPG_PLL_STBY_RESETB (0x00000001) +#define CPG_PLL_STBY_WEN_RESETB (0x00010000) +#define CPG_PLL_STBY_WEN_SSE_EN (0x00040000) +#define CPG_PLL_STBY_WEN_SSC_MODE (0x00100000) + +#define CPG_PLL_MON_RESETB (0x00000001) +#define CPG_PLL_MON_PLL_LOCK (0x00000010) + +#define CPG_PLL1_CCTRL_RST_P1_0_RST (0x00000001) +#define CPG_PLL1_CCTRL_WEN_RST_P1_0_RST (0x00010000) + +#define CPG_CA53_DDIV_DIVA_SET_MIN (0) +#define CPG_CA53_DDIV_WEN_DIVA (0x00010000) + +#define CPG_SYS_DDIV_DIVD_SET_SHIFT (4) +#define CPG_SYS_DDIV_DIVD_SET_MIN (0) +#define CPG_SYS_DDIV_DIVE_SET_SHIFT (8) +#define CPG_SYS_DDIV_DIVE_SET_MIN (0) +#define CPG_SYS_DDIV_WEN_DIVD (0x00100000) +#define CPG_SYS_DDIV_WEN_DIVE (0x01000000) + +#define CPG_MMCDDI_DDIV_DIVX_SET_MSK (0x00000003) +#define CPG_MMCDDI_DDIV_DIVX_SET_SHIFT (0) +#define CPG_MMCDDI_DDIV_DIVX_SET_MAX (2) +#define CPG_MMCDDI_DDIV_DIVX_SET_MIN (0) +#define CPG_MMCDDI_DDIV_WEN_DIVX (0x00010000) + +#define CPG_CLK48_DSEL_SELD (0x00000002) +#define CPG_CLK48_DSEL_SELE (0x00000004) +#define CPG_CLK48_DSEL_WEN_SELD (0x00020000) +#define CPG_CLK48_DSEL_WEN_SELE (0x00040000) + +#define CPG_SDIEMM_SSEL_SELSDI (0x00000001) +#define CPG_SDIEMM_SSEL_WEN_SELSDI (0x00010000) + +#define CPG_URT_RCLK_SSEL_WEN_SELW0 (0x00010000) + +#define CPG_CLKSTATUS_DIVA (0x00000001) +#define CPG_CLKSTATUS_DIVB (0x00000002) +#define CPG_CLKSTATUS_DIVD (0x00000004) +#define CPG_CLKSTATUS_DIVE (0x00000008) +#define CPG_CLKSTATUS_DIVF (0x00000010) +#define CPG_CLKSTATUS_DIVG (0x00000020) +#define CPG_CLKSTATUS_DIVNFI (0x00000040) +#define CPG_CLKSTATUS_DIVX (0x00000080) +#define CPG_CLKSTATUS_DIVH (0x00000100) +#define CPG_CLKSTATUS_DIVI (0x00000200) +#define CPG_CLKSTATUS_DIVJ (0x00000400) +#define CPG_CLKSTATUS_DIVM (0x00000800) +#define CPG_CLKSTATUS_DIVH2 (0x00001000) + +#define CPG_PD_RST_MEM_RSTB (0x00000001) +#define CPG_PD_RST_WEN_MEM_RSTB (0x00010000) + +#define CPG_RST_MON_EMM (0x00000100) +#define CPG_RST_MON_URT (0x04000000) +#define CPG_PD_RST_RFX_RSTB (0x00000010) +#define CPG_PD_RST_WEN_RFX_RSTB (0x00100000) + +#define CPG_PLL_MIN (1) +#define CPG_PLL_MAX (7) + +#define CPG_CLK_ON_REG_MIN (1) +#define CPG_CLK_ON_REG_MAX (27) + +#define CPG_RST_REG_MIN (1) +#define CPG_RST_REG_MAX (15) + +typedef struct +{ + union + { + uint32_t word; + struct + { + uint32_t :2; + uint32_t enable:1; + uint32_t :1; + uint32_t mode:2; + uint32_t :26; + }bit; + }ssc; + union + { + uint32_t word[2]; + struct + { + uint32_t p:6; + uint32_t m:10; + uint32_t k:16; + uint32_t s:3; + uint32_t :5; + uint32_t mrr:6; + uint32_t :2; + uint32_t mfr:8; + uint32_t :8; + } bit; + } clk; +} st_cpg_pll_param_t; + +typedef enum +{ + CPG_ERROR_ARGUMENT = -201, + CPG_ERROR_NO_REGISTER = -202, + CPG_ERROR_NULL_POINTER = -203, + CPG_ERROR_PLL_TURN_MODE_TIMEOUT = -204, + CPG_ERROR_PLL_ACTIVE = -205, + CPG_ERROR_PLL_STANDBY = -206, + CPG_ERROR_TURN_RESET_TIMEOUT = -207, + CPG_ERROR_CLK_CHANGE_TIMEOUT = -208, + CPG_ERROR_PLL_NOT_ACTIVE = -280, + CPG_ERROR_PLL_NOT_STANDBY = -290 +} e_cpg_error_code_t; + +typedef enum +{ + CPG_PLL_1 = 1, + CPG_PLL_2 = 2, + CPG_PLL_3 = 3, + CPG_PLL_4 = 4, + CPG_PLL_6 = 6, + CPG_PLL_7 = 7 +} e_cpg_pll_num_t; + +typedef enum +{ + CPG_DDIV_CA53 = 0, + CPG_DDIV_SYS, + CPG_dmy1, + CPG_dmy2, + CPG_DDIV_MMCDDI, + CPG_DSEL_CLK48, + CPG_dmy3, + CPG_dmy4, + CPG_dmy5, + CPG_SSEL_SDIEMM = 64, + CPG_dmy6, + CPG_dmy7, + CPG_dmy8, + CPG_dmy9, + CPG_dmyA, + CPG_dmyB, + CPG_SDIV_GMCLK, + CPG_SSEL_GMCLK, + CPG_dmyC, + CPG_SDIV_URT_RCLK, + CPG_SSEL_URT_RCLK, + CPG_SSEL_CSI_RCLK +} e_cpg_divsel_t; + +/** prototype defined **/ +uint32_t CPG_ReadReg(uint32_t offset); +void CPG_WriteReg(uint32_t offset, uint32_t value); + +int32_t CPG_MoveToActivePLL(e_cpg_pll_num_t pll_num, st_cpg_pll_param_t *p_set_data); +int32_t CPG_GetStatusPLL(e_cpg_pll_num_t pll_num, uint32_t *p_data); + +void CPG_SetDifClkFreq(e_cpg_divsel_t target_reg, uint16_t target, uint16_t set_value); +int32_t CPG_SetClockCtrl(uint8_t reg_num, uint16_t target, uint16_t set_value); +int32_t CPG_GetClockCtrl(uint8_t reg_num, uint32_t *p_data); +int32_t CPG_SetResetCtrl(uint8_t reg_num, uint16_t target, uint16_t set_value); +int32_t CPG_SetPDResetCtrl(uint16_t target, uint16_t set_value); +int32_t CPG_WaitResetMon(uint32_t timeout_c, uint32_t msk, uint32_t val); +int32_t CPG_WakeUpPLL(e_cpg_pll_num_t pll_num); + +#endif /* RDK_CMN_CPG_H */ diff --git a/include/rdk_cmn_gic.h b/include/rdk_cmn_gic.h new file mode 100644 index 0000000..c926e41 --- /dev/null +++ b/include/rdk_cmn_gic.h @@ -0,0 +1,582 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_cmn_gic.h + * Description : register and API information for GIC + ******************************************************************************/ + +#ifndef RDK_CMN_GIC_H /* prevent circular inclusions */ +#define RDK_CMN_GIC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +/* + * The maximum number of interrupts supported by the hardware. + */ +#define GIC_MAX_NUM_INTR_INPUTS 426U /* Maximum number of interrupt */ + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GIC_MAX_INTR_PRIO_VAL 248U +#define GIC_INTR_PRIO_MASK 0x000000F8U + +/** @name Distributor Interface Register Map + * + * Define the offsets from the base address for all Distributor registers of + * the interrupt controller, some registers may be reserved in the hardware + * device. + * @{ + */ + +#define GIC_BASE_ADDRESS (0x82000000) +#define GIC_CPU_BASE_ADDRESS (0x20000) +#define GIC_DIST_BASE_ADDRESS (0x10000) + +#define GIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable + Register */ +#define GIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller + Type Register */ +#define GIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID + Register */ +#define GIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security + Register */ +#define GIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set + Register */ +#define GIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */ +#define GIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set + Register */ +#define GIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear + Register */ +#define GIC_ACTIVE_SET_OFFSET 0x00000300U /**< Active Status Set Register */ +#define GIC_ACTIVE_CLR_OFFSET 0x00000380U /**< Active Status Clear Register */ +#define GIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */ +#define GIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target + Register 0x800-0x8FB */ +#define GIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration + Register 0xC00-0xCFC */ +#define GIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */ +#define GIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register + 0xd04-0xd7C */ +#define GIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration + Register */ +#define GIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered + Interrupt Register */ +#define GIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */ +#define GIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */ +/* @} */ + +/** @name Distributor Enable Register + * Controls if the distributor response to external interrupt inputs. + * @{ + */ +#define GIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */ +/* @} */ + +/** @name Interrupt Controller Type Register + * @{ + */ +#define GIC_LSPI_MASK 0x0000F800U /**< Number of Lockable + Shared Peripheral + Interrupts*/ +#define GIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/ +#define GIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */ +#define GIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */ +/* @} */ + +/** @name Implementor ID Register + * Implementor and revision information. + * @{ + */ +#define GIC_REV_MASK 0x00FFF000U /**< Revision Number */ +#define GIC_IMPL_MASK 0x00000FFFU /**< Implementor */ +/* @} */ + +/** @name Interrupt Security Registers + * Each bit controls the security level of an interrupt, either secure or non + * secure. These registers can only be accessed using secure read and write. + * There are registers for each of the CPU interfaces at offset 0x080. A + * register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x084. + * @{ + */ +#define GIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Set Register + * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a + * bit to 0. + * There are registers for each of the CPU interfaces at offset 0x100. With up + * to 8 registers aliased to the same address. A register set for the SPI + * interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x104. + * @{ + */ +#define GIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Clear Register + * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and + * sets the corresponding bit to 0. + * There are registers for each of the CPU interfaces at offset 0x180. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x184. + * @{ + */ +#define GIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Set Register + * Each bit controls the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets + * an interrupt to the pending state. + * There are registers for each of the CPU interfaces at offset 0x200. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x204. + * @{ + */ +#define GIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Clear Register + * Each bit can clear the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 + * clears the pending state of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x280. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x284. + * @{ + */ +#define GIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Active Status Register + * Each bit provides the Active status of an interrupt, a + * 0 is not Active, a 1 is Active. This is a read only register. + * There are registers for each of the CPU interfaces at offset 0x300. With up + * to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x380. + * @{ + */ +#define GIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Priority Level Register + * Each byte in a Priority Level Register sets the priority level of an + * interrupt. Reading the register provides the priority level of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x400 through + * 0x41C. With up to 8 registers aliased to each address. + * 0 is highest priority, 0xFF is lowest. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x420. + * @{ + */ +#define GIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an + INT_ID */ +#define GIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority + actually the lowest priority*/ +/* @} */ + +/** @name SPI Target Register 0x800-0x8FB + * Each byte references a separate SPI and programs which of the up to 8 CPU + * interfaces are sent a Pending interrupt. + * There are registers for each of the CPU interfaces at offset 0x800 through + * 0x81C. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x820. + * + * This driver does not support multiple CPU interfaces. These are included + * for complete documentation. + * @{ + */ +#define GIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/ +#define GIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/ +#define GIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/ +#define GIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/ +#define GIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/ +#define GIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/ +#define GIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/ +#define GIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/ +/* @} */ + +/** @name Interrupt Configuration Register 0xC00-0xCFC + * The interrupt configuration registers program an SFI to be active HIGH level + * sensitive or rising edge sensitive. + * Each bit pair describes the configuration for an INT_ID. + * SFI Read Only b10 always + * PPI Read Only depending on how the PPIs are configured. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive + * SPI LSB is read only. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive/ + * There are registers for each of the CPU interfaces at offset 0xC00 through + * 0xC04. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0xC08. + * @{ + */ +#define GIC_INT_CFG_MASK 0x00000003U /**< */ +/* @} */ + +/** @name PPI Status Register + * Enables an external AMBA master to access the status of the PPI inputs. + * A CPU can only read the status of its local PPI signals and cannot read the + * status for other CPUs. + * This register is aliased for each CPU interface. + * @{ + */ +#define GIC_PPI_C15_MASK 0x00008000U /**< PPI Status */ +#define GIC_PPI_C14_MASK 0x00004000U /**< PPI Status */ +#define GIC_PPI_C13_MASK 0x00002000U /**< PPI Status */ +#define GIC_PPI_C12_MASK 0x00001000U /**< PPI Status */ +#define GIC_PPI_C11_MASK 0x00000800U /**< PPI Status */ +#define GIC_PPI_C10_MASK 0x00000400U /**< PPI Status */ +#define GIC_PPI_C09_MASK 0x00000200U /**< PPI Status */ +#define GIC_PPI_C08_MASK 0x00000100U /**< PPI Status */ +#define GIC_PPI_C07_MASK 0x00000080U /**< PPI Status */ +#define GIC_PPI_C06_MASK 0x00000040U /**< PPI Status */ +#define GIC_PPI_C05_MASK 0x00000020U /**< PPI Status */ +#define GIC_PPI_C04_MASK 0x00000010U /**< PPI Status */ +#define GIC_PPI_C03_MASK 0x00000008U /**< PPI Status */ +#define GIC_PPI_C02_MASK 0x00000004U /**< PPI Status */ +#define GIC_PPI_C01_MASK 0x00000002U /**< PPI Status */ +#define GIC_PPI_C00_MASK 0x00000001U /**< PPI Status */ +/* @} */ + +/** @name SPI Status Register 0xd04-0xd7C + * Enables an external AMBA master to access the status of the SPI inputs. + * There are up to 63 registers if the maximum number of SPI inputs are + * configured. + * @{ + */ +#define GIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI + input */ +/* @} */ + +/** @name AHB Configuration Register + * Provides the status of the CFGBIGEND input signal and allows the endianess + * of the GIC to be set. + * @{ + */ +#define GIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian, + 1-GIC uses Big Endian */ +#define GIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control, + 1-use the AHB_END bit */ +#define GIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */ + +/* @} */ + +/** @name Software Triggered Interrupt Register + * Controls issueing of software interrupts. + * @{ + */ +#define GIC_SFI_SELFTRIG_MASK 0x02010000U +#define GIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter + b00-Use the target List + b01-All CPUs except requester + b10-To Requester + b11-reserved */ +#define GIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */ +#define GIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */ +#define GIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID + signaled to the CPU*/ +/* @} */ + +/** @name CPU Interface Register Map + * + * Define the offsets from the base address for all CPU registers of the + * interrupt controller, some registers may be reserved in the hardware device. + * @{ + */ +#define GIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control + Register */ +#define GIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */ +#define GIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */ +#define GIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */ +#define GIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */ +#define GIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */ +#define GIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt + Register */ +#define GIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure + Binary Point Register */ + +#define GIC_CPU_PROPERTY_MSK_STEP16 0xF0U +#define GIC_CPU_PROPERTY_MSK_STEP32 0xF8U +#define GIC_CPU_PROPERTY_MSK_STEP64 0xFCU +#define GIC_CPU_PROPERTY_MSK_STEP128 0xFEU +#define GIC_CPU_PROPERTY_MSK_STEP256 0xFFU + + +/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written + * to. */ +/* @} */ + + +/** @name Control Register + * CPU Interface Control register definitions + * All bits are defined here although some are not available in the non-secure + * mode. + * @{ + */ +#define GIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer, + 0=separate registers, + 1=both use bin_pt_s */ +#define GIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure + interrupts, + 0= use IRQ for both, + 1=Use FIQ for secure, IRQ for non*/ +#define GIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */ +#define GIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */ +#define GIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */ +/* @} */ + +/** @name Priority Mask Register + * Priority Mask register definitions + * The CPU interface does not send interrupt if the level of the interrupt is + * lower than the level of the register. + * @{ + */ +/*#define GIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */ +/* @} */ + +/** @name Binary Point Register + * Binary Point register definitions + * @{ + */ + +#define GIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value + Value Secure Non-secure + b000 0xFE 0xFF + b001 0xFC 0xFE + b010 0xF8 0xFC + b011 0xF0 0xF8 + b100 0xE0 0xF0 + b101 0xC0 0xE0 + b110 0x80 0xC0 + b111 0x00 0x80 + */ +/*@}*/ + +/** @name Interrupt Acknowledge Register + * Interrupt Acknowledge register definitions + * Identifies the current Pending interrupt, and the CPU ID for software + * interrupts. + */ +#define GIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */ +#define GIC_CPUID_MASK 0x00000C00U /**< CPU ID */ +/* @} */ + +/** @name End of Interrupt Register + * End of Interrupt register definitions + * Allows the CPU to signal the GIC when it completes an interrupt service + * routine. + */ +#define GIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */ + +/* @} */ + +/** @name Running Priority Register + * Running Priority register definitions + * Identifies the interrupt priority level of the highest priority active + * interrupt. + */ +#define GIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */ +/* @} */ + +/* + * Highest Pending Interrupt register definitions + * Identifies the interrupt priority of the highest priority pending interupt + */ +#define GIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */ +/*#define GIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */ +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the Interrupt Configuration Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define GIC_INT_CFG_OFFSET_CALC(InterruptID) \ + ((uint32_t)GIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Priority Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define GIC_PRIORITY_OFFSET_CALC(InterruptID) \ + ((uint32_t)GIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the SPI Target Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define GIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ + ((uint32_t)GIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Clear-Enable Register offset for an interrupt ID +* +* @param Register is the register offset for the clear/enable bank. +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define GIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \ + ((Register) + (((InterruptID)/32U) * 4U)) + +/****************************************************************************/ +/** +* +* Write the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void GIC_CPUWriteReg( u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define GIC_CPUWriteReg( RegOffset, Data) \ +(GIC_WriteReg((GIC_CPU_BASE_ADDRESS + RegOffset), ((uint32_t)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 GIC_CPUReadReg( u32 RegOffset) +* +*****************************************************************************/ +#define GIC_CPUReadReg(RegOffset) \ + (GIC_ReadReg((GIC_CPU_BASE_ADDRESS + RegOffset)) + +/****************************************************************************/ +/** +* +* Write the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void GIC_DistWriteReg(u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define GIC_DistWriteReg(RegOffset, Data) \ +(GIC_WriteReg((GIC_DIST_BASE_ADDRESS + RegOffset), ((uint32_t)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 GIC_DistReadReg(u32 RegOffset) +* +*****************************************************************************/ +#define GIC_DistReadReg(RegOffset) \ +(GIC_ReadReg((GIC_DIST_BASE_ADDRESS + RegOffset)) + +/************************** Function Prototypes ******************************/ +uint32_t GIC_ReadReg(uint32_t offset); +void GIC_WriteReg(uint32_t offset, uint32_t value); +void Init_GIC(uint32_t cpu_id); + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/include/rdk_cmn_pmc.h b/include/rdk_cmn_pmc.h new file mode 100644 index 0000000..11af062 --- /dev/null +++ b/include/rdk_cmn_pmc.h @@ -0,0 +1,111 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_cmn_pmc.h + * Description : register and API information for PMC + ******************************************************************************/ + +#ifndef RDK_CMN_PMC_H +#define RDK_CMN_PMC_H + +#define PMC_BASE_ADDRESS (0x0A3600000ULL) + +/** Register offset defines */ +#define PMC_SPLY_ENA (0x0000) +#define PMC_MAIN_STS (0x0004) +#define PMC_PD_RFX_ISOEN (0x0028) + +#define PMC_IDLE_REQ (0x0038) +#define PMC_IDLE_STS (0x003C) +#define PMC_INT_STS (0x0044) +#define PMC_INT_CLR (0x0048) +#define PMC_INT_MSK (0x004C) + +#define PMC_PD_MEM_TIM (0x0014) +#define PMC_PD_ON_TIM (0x0018) +#define PMC_PD_MEM_ISOEN (0x001C) + +/** Bit assign */ +#define PMC_SPLY_ENA_PD_ON (0x00000010) +#define PMC_SPLY_ENA_PD_MEM (0x00000001) +#define PMC_MAIN_STS_PD_MEM (0x00000002) +#define PMC_SPLY_ENA_PD_RFX (0x00000004) + +#define PMC_PD_MEM_TIM_OFF_MASK (0x0000FFFF) +#define PMC_PD_MEM_TIM_ON_MASK (0x0000FFFF) +#define PMC_PD_MEM_TIM_OFF_SHIFT (16) +#define PMC_PD_MEM_TIM_ON_SHIFT (0) + +#define PMC_PD_ON_TIM_MASK (0x0000FFFF) +#define PMC_PD_ON_TIM_SHIFT (0) + +#define PMC_PD_ISO_EN (0x00000001) +#define PMC_PD_ISO_DONE (0x00008000) + +#define PMC_IDLE_REQ_PD_MEM (0x00000002) +#define PMC_IDLE_REQ_WEN_PD_MEM (0x00020000) +#define PMC_IDLE_STS_PD_MEM_IDLE_DONE (0x00000002) +#define PMC_IDLE_STS_PD_MEM_ACT_DONE (0x00000200) + +#define PMC_IDLE_STS_PD_RFX_ACT_DONE (0x00001000) + +#define PMC_INT_STS_PD_DONE (0x00000001) +#define PMC_INT_STS_IDLE_DONE (0x00000002) +#define PMC_INT_STS_L2_STBY (0x00000020) + +#define PMC_INT_CLR_PD_DONE (0x00000001) +#define PMC_INT_CLR_IDLE_DONE (0x00000002) + +#define PMC_IDLE_RAW_IDLE_PD_RFX (0x00100000) + +/** typdef defined */ +typedef enum +{ + PMC_ERROR_POWER_ON_TIMEOUT = -311, + PMC_ERROR_ISOLATION_OFF_TIMEOUT = -312, + PMC_ERROR_CONNECTED_BUS_TIMEOUT = -313, + PMC_ERROR_SEPARATED_BUS_TIMEOUT = -314, + PMC_ERROR_ISOLATION_ON_TIMEOUT = -315, + PMC_ERROR_POWER_OFF_TIMEOUT = -316, + PMC_ERROR_PLL_LOCK_TIMEOUT = -317, + PMC_ERROR_RELEASE_RESET_TIMEOUT = -318, + PMC_ERROR_PLL_STANDBY_TIMEOUT = -319, + PMC_ERROR_HWFFC_CHG_STS_TIMEOUT = -320, + PMC_ERROR_NOT_IDLE_BUS = -321, + PMC_ERROR_PLL3_NOT_STANDBY_MODE = -333, + PMC_ERROR_PLL4_NOT_STANDBY_MODE = -334, + PMC_ERROR_PLL6_NOT_STANDBY_MODE = -336, + PMC_ERROR_NO_EXIST_SPLY = -341, + PMC_ERROR_NO_EXIST_ISOLATION = -342, + PMC_ERROR_NO_EXIST_BUS_CONNECT = -343 +} e_pmc_error_code_t; + +/** prototype defined **/ +uint32_t PMC_ReadReg(uint32_t offset); +void PMC_WriteReg(uint32_t offset, uint32_t value); + + +int32_t PMC_PowerOn_PD_MEM_FromPOR(void); + + +#endif /* RDK_CMN_PMC_H */ diff --git a/include/rdk_common.h b/include/rdk_common.h new file mode 100644 index 0000000..9062be3 --- /dev/null +++ b/include/rdk_common.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_common.h + * Description : information and API for common functions + ******************************************************************************/ + +#ifndef RDK_COMMON_H +#define RDK_COMMON_H + +/* + * Macro definitions + */ +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL ((void*)0) +#endif /* !defined(NULL) */ + +/* + * Global Typedef definitions + */ +typedef enum +{ + CMN_SUCCESS = 0, + CMN_ERROR = -1 +} e_rdk_cmn_error_no_t; + +/****************************************************************************** + Prototype define + *****************************************************************************/ +void CMN_InitSysCnt(void); +void CMN_DelayInUSec(uint64_t us); +uint64_t CMN_GetSysCnt(void); +uint32_t CMN_GetFreq4SysCnt(void); + + +/******************************************************************************* + * Function Name: CMN_REG_Read32 + * Description : read access to Register in uint32_t. + * + * Arguments : addr - + * address for read access + * Return Value : value - + * read data. + ******************************************************************************/ +static inline uint32_t CMN_REG_Read32(uintptr_t addr) +{ + return *((volatile uint32_t *)addr); +} + + +/******************************************************************************* + * Function Name: CMN_REG_Write32 + * Description : write access to Register in uint32_t. + * + * Arguments : addr - + * address for write access + * value - + * write data + * Return Value : non - + * + ******************************************************************************/ +static inline void CMN_REG_Write32(uintptr_t addr, uint32_t value) +{ + /** sizeof(uintptr_t) == sizeof(uint32_t *) */ + *((volatile uint32_t *)addr) = value; +} + +/******************************************************************************* + * Function Name: CMN_DelayInMS + * Description : Does an example task. Making this longer just to see how it + * wraps. + * Arguments : index - + * Where to start looking + * p_output - + * Pointer of where to put the output data + * Return Value : count - + * How many entries were found + ******************************************************************************/ +static inline void CMN_DelayInMS(uint64_t ms) +{ + CMN_DelayInUSec(ms * 1000ULL); +} + +/******************************************************************************* + * Function Name: CMN_DelayInUS + * Description : Does an example task. Making this longer just to see how it + * wraps. + * Arguments : index - + * Where to start looking + * p_output - + * Pointer of where to put the output data + * Return Value : count - + * How many entries were found + ******************************************************************************/ +static inline void CMN_DelayInUS(uint64_t us) +{ + CMN_DelayInUSec(us); +} + + +#endif /* !defined RDK_COMMON_H */ diff --git a/include/rdk_pfc.h b/include/rdk_pfc.h new file mode 100644 index 0000000..4afaee3 --- /dev/null +++ b/include/rdk_pfc.h @@ -0,0 +1,792 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_pfc.h + * Description : register and API information for PFC + ******************************************************************************/ + +#ifndef RDK_PFC_H_ +#define RDK_PFC_H_ + +#define PFC_BASE_ADDRESS (0xB6250000) + +#define PFC_P00_GPIO_DO (0x0000) +#define PFC_P00_GPIO_OE (0x0004) +#define PFC_P00_GPIO_IE (0x0008) +#define PFC_P00_PFSEL0 (0x0010) +#define PFC_P00_PFSEL1 (0x0014) +#define PFC_P00_PFSEL2 (0x0018) +#define PFC_P00_PFSEL3 (0x001C) +#define PFC_P00_DI_MON (0x0020) +#define PFC_P00_PUPD (0x0024) +#define PFC_P00_DRV (0x0028) +#define PFC_P00_SR (0x002C) +#define PFC_P00_DI_MSK (0x0030) +#define PFC_P00_EN_MSK (0x0034) + +#define PFC_P01_GPIO_DO (0x0040) +#define PFC_P01_GPIO_OE (0x0044) +#define PFC_P01_GPIO_IE (0x0048) +#define PFC_P01_PFSEL0 (0x0050) +#define PFC_P01_PFSEL1 (0x0054) +#define PFC_P01_PFSEL2 (0x0058) +#define PFC_P01_PFSEL3 (0x005C) +#define PFC_P01_DI_MON (0x0060) +#define PFC_P01_PUPD (0x0064) +#define PFC_P01_DRV (0x0068) +#define PFC_P01_SR (0x006C) +#define PFC_P01_DI_MSK (0x0070) +#define PFC_P01_EN_MSK (0x0074) + +#define PFC_P02_GPIO_DO (0x0080) +#define PFC_P02_GPIO_OE (0x0084) +#define PFC_P02_GPIO_IE (0x0088) +#define PFC_P02_PFSEL0 (0x0090) +#define PFC_P02_PFSEL1 (0x0094) +#define PFC_P02_DI_MON (0x00A0) +#define PFC_P02_PUPD (0x00A4) +#define PFC_P02_DRV (0x00A8) +#define PFC_P02_SR (0x00AC) +#define PFC_P02_DI_MSK (0x00B0) +#define PFC_P02_EN_MSK (0x00B4) + +#define PFC_P03_GPIO_DO (0x00C0) +#define PFC_P03_GPIO_OE (0x00C4) +#define PFC_P03_GPIO_IE (0x00C8) +#define PFC_P03_PFSEL0 (0x00D0) +#define PFC_P03_PFSEL1 (0x00D4) +#define PFC_P03_PFSEL2 (0x00D8) +#define PFC_P03_PFSEL3 (0x00DC) +#define PFC_P03_DI_MON (0x00E0) +#define PFC_P03_PUPD (0x00E4) +#define PFC_P03_DRV (0x00E8) +#define PFC_P03_SR (0x00EC) +#define PFC_P03_DI_MSK (0x00F0) +#define PFC_P03_EN_MSK (0x00F4) + +#define PFC_P04_GPIO_DO (0x0100) +#define PFC_P04_GPIO_OE (0x0104) +#define PFC_P04_GPIO_IE (0x0108) +#define PFC_P04_PFSEL0 (0x0110) +#define PFC_P04_PFSEL1 (0x0114) +#define PFC_P04_DI_MON (0x0120) +#define PFC_P04_PUPD (0x0124) +#define PFC_P04_DRV (0x0128) +#define PFC_P04_SR (0x012C) +#define PFC_P04_DI_MSK (0x0130) +#define PFC_P04_EN_MSK (0x0134) + +#define PFC_P05_GPIO_DO (0x0140) +#define PFC_P05_GPIO_OE (0x0144) +#define PFC_P05_GPIO_IE (0x0148) +#define PFC_P05_PFSEL0 (0x0150) +#define PFC_P05_DI_MON (0x0160) +#define PFC_P05_PUPD (0x0164) +#define PFC_P05_DRV (0x0168) +#define PFC_P05_SR (0x016C) +#define PFC_P05_DI_MSK (0x0170) +#define PFC_P05_EN_MSK (0x0174) + +#define PFC_P06_GPIO_DO (0x0180) +#define PFC_P06_GPIO_OE (0x0184) +#define PFC_P06_GPIO_IE (0x0188) +#define PFC_P06_PFSEL0 (0x0190) +#define PFC_P06_PFSEL1 (0x0194) +#define PFC_P06_PFSEL2 (0x0198) +#define PFC_P06_DI_MON (0x01A0) +#define PFC_P06_PUPD (0x01A4) +#define PFC_P06_DRV (0x01A8) +#define PFC_P06_SR (0x01AC) +#define PFC_P06_DI_MSK (0x01B0) +#define PFC_P06_EN_MSK (0x01B4) + +#define PFC_P07_GPIO_DO (0x01C0) +#define PFC_P07_GPIO_OE (0x01C4) +#define PFC_P07_GPIO_IE (0x01C8) +#define PFC_P07_PFSEL0 (0x01D0) +#define PFC_P07_PFSEL1 (0x01D4) +#define PFC_P07_DI_MON (0x01E0) +#define PFC_P07_PUPD (0x01E4) +#define PFC_P07_DRV (0x01E8) +#define PFC_P07_SR (0x01EC) +#define PFC_P07_DI_MSK (0x01F0) +#define PFC_P07_EN_MSK (0x01F4) + +#define PFC_P08_GPIO_DO (0x0200) +#define PFC_P08_GPIO_OE (0x0204) +#define PFC_P08_GPIO_IE (0x0208) +#define PFC_P08_PFSEL0 (0x0210) +#define PFC_P08_PFSEL1 (0x0214) +#define PFC_P08_DI_MON (0x0220) +#define PFC_P08_PUPD (0x0224) +#define PFC_P08_DRV (0x0228) +#define PFC_P08_SR (0x022C) +#define PFC_P08_DI_MSK (0x0230) +#define PFC_P08_EN_MSK (0x0234) + +#define PFC_P09_GPIO_DO (0x0240) +#define PFC_P09_GPIO_OE (0x0244) +#define PFC_P09_GPIO_IE (0x0248) +#define PFC_P09_PFSEL0 (0x0250) +#define PFC_P09_PFSEL1 (0x0254) +#define PFC_P09_DI_MON (0x0260) +#define PFC_P09_PUPD (0x0264) +#define PFC_P09_DRV (0x0268) +#define PFC_P09_SR (0x026C) +#define PFC_P09_DI_MSK (0x0270) +#define PFC_P09_EN_MSK (0x0274) + +#define PFC_P10_GPIO_DO (0x0280) +#define PFC_P10_GPIO_OE (0x0284) +#define PFC_P10_GPIO_IE (0x0288) +#define PFC_P10_PFSEL0 (0x0290) +#define PFC_P10_PFSEL1 (0x0294) +#define PFC_P10_PFSEL2 (0x0298) +#define PFC_P10_DI_MON (0x02A0) +#define PFC_P10_PUPD (0x02A4) +#define PFC_P10_DRV (0x02A8) +#define PFC_P10_SR (0x02AC) +#define PFC_P10_DI_MSK (0x02B0) +#define PFC_P10_EN_MSK (0x02B4) + +#define PFC_P11_GPIO_DO (0x02C0) +#define PFC_P11_GPIO_OE (0x02C4) +#define PFC_P11_GPIO_IE (0x02C8) +#define PFC_P11_PFSEL0 (0x02D0) +#define PFC_P11_PFSEL1 (0x02D4) +#define PFC_P11_PFSEL2 (0x02D8) +#define PFC_P11_DI_MON (0x02E0) +#define PFC_P11_PUPD (0x02E4) +#define PFC_P11_DRV (0x02E8) +#define PFC_P11_SR (0x02EC) +#define PFC_P11_DI_MSK (0x02F0) +#define PFC_P11_EN_MSK (0x02F4) + +#define PFC_P12_GPIO_DO (0x0300) +#define PFC_P12_GPIO_OE (0x0304) +#define PFC_P12_GPIO_IE (0x0308) +#define PFC_P12_PFSEL0 (0x0310) +#define PFC_P12_DI_MON (0x0330) +#define PFC_P12_PUPD (0x0334) +#define PFC_P12_DRV (0x0338) +#define PFC_P12_SR (0x033C) +#define PFC_P12_DI_MSK (0x0330) +#define PFC_P12_EN_MSK (0x0334) + +#define PFC_P13_GPIO_DO (0x0340) +#define PFC_P13_GPIO_OE (0x0344) +#define PFC_P13_GPIO_IE (0x0348) +#define PFC_P13_PFSEL0 (0x0350) +#define PFC_P13_PFSEL1 (0x0354) +#define PFC_P13_PFSEL2 (0x0358) +#define PFC_P13_DI_MON (0x0360) +#define PFC_P13_PUPD (0x0364) +#define PFC_P13_DRV (0x0368) +#define PFC_P13_SR (0x036C) +#define PFC_P13_DI_MSK (0x0370) +#define PFC_P13_EN_MSK (0x0374) + +#define PFC_P14_GPIO_DO (0x0380) +#define PFC_P14_GPIO_OE (0x0384) +#define PFC_P14_GPIO_IE (0x0388) +#define PFC_P14_PFSEL0 (0x0390) +#define PFC_P14_PFSEL1 (0x0394) +#define PFC_P14_DI_MON (0x03A0) +#define PFC_P14_PUPD (0x03A4) +#define PFC_P14_DRV (0x03A8) +#define PFC_P14_SR (0x03AC) +#define PFC_P14_DI_MSK (0x03B0) +#define PFC_P14_EN_MSK (0x03B4) + +#define PFC_P15_GPIO_DO (0x03C0) +#define PFC_P15_GPIO_OE (0x03C4) +#define PFC_P15_GPIO_IE (0x03C8) +#define PFC_P15_PFSEL0 (0x03D0) +#define PFC_P15_PFSEL1 (0x03D4) +#define PFC_P15_PFSEL2 (0x03D8) +#define PFC_P15_PFSEL3 (0x03DC) +#define PFC_P15_DI_MON (0x03E0) +#define PFC_P15_PUPD (0x03E4) +#define PFC_P15_DRV (0x03E8) +#define PFC_P15_SR (0x03EC) +#define PFC_P15_DI_MSK (0x03F0) +#define PFC_P15_EN_MSK (0x03F4) + +#define PFC_P16_GPIO_DO (0x0400) +#define PFC_P16_GPIO_OE (0x0404) +#define PFC_P16_GPIO_IE (0x0408) +#define PFC_P16_PFSEL0 (0x0410) +#define PFC_P16_PFSEL1 (0x0414) +#define PFC_P16_PFSEL2 (0x0418) +#define PFC_P16_PFSEL3 (0x041C) +#define PFC_P16_DI_MON (0x0420) +#define PFC_P16_PUPD (0x0424) +#define PFC_P16_DRV (0x0428) +#define PFC_P16_SR (0x042C) +#define PFC_P16_DI_MSK (0x0430) +#define PFC_P16_EN_MSK (0x0434) + +#define PFC_P17_GPIO_DO (0x0440) +#define PFC_P17_GPIO_OE (0x0444) +#define PFC_P17_GPIO_IE (0x0448) +#define PFC_P17_PFSEL0 (0x0450) +#define PFC_P17_DI_MON (0x0460) +#define PFC_P17_PUPD (0x0464) +#define PFC_P17_DRV (0x0468) +#define PFC_P17_SR (0x046C) +#define PFC_P17_DI_MSK (0x0470) +#define PFC_P17_EN_MSK (0x0474) + +#define PFC_P20_GPIO_DO (0x0500) +#define PFC_P20_GPIO_OE (0x0504) +#define PFC_P20_GPIO_IE (0x0508) +#define PFC_P20_PFSEL0 (0x0510) +#define PFC_P20_DI_MON (0x0520) +#define PFC_P20_DRV (0x0528) +#define PFC_P20_DI_MSK (0x0530) +#define PFC_P20_EN_MSK (0x0534) + +#define PFC_P21_GPIO_DO (0x0540) +#define PFC_P21_GPIO_OE (0x0544) +#define PFC_P21_GPIO_IE (0x0548) +#define PFC_P21_DI_MON (0x0560) +#define PFC_P21_DRV (0x0568) +#define PFC_P21_SR (0x056C) + +#define PFC_CSRXD_SEL (0x0580) +#define PFC_ROP_DI_SEL (0x0584) + +#define PFC_PEX0_DRV (0x0590) +#define PFC_PEX0_SR (0x0594) + +#define PFC_EXTINT_INV0 (0x05A0) +#define PFC_EXTINT_INV1 (0x05A4) +#define PFC_EXTINT_INV2 (0x05A8) + +#define PFC_EXTINT_MSK0 (0x05B0) +#define PFC_EXTINT_MSK1 (0x05B4) +#define PFC_EXTINT_MSK2 (0x05B8) + + +/** Bit assign **/ +#define PFC_PORT_PIN00 (0x00000001) +#define PFC_PORT_PIN01 (0x00000002) +#define PFC_PORT_PIN02 (0x00000004) +#define PFC_PORT_PIN03 (0x00000008) +#define PFC_PORT_PIN04 (0x00000010) +#define PFC_PORT_PIN05 (0x00000020) +#define PFC_PORT_PIN06 (0x00000040) +#define PFC_PORT_PIN07 (0x00000080) +#define PFC_PORT_PIN08 (0x00000100) +#define PFC_PORT_PIN09 (0x00000200) +#define PFC_PORT_PIN10 (0x00000400) +#define PFC_PORT_PIN11 (0x00000800) +#define PFC_PORT_PIN12 (0x00001000) +#define PFC_PORT_PIN13 (0x00002000) +#define PFC_PORT_PIN14 (0x00004000) +#define PFC_PORT_PIN15 (0x00008000) + +#define PFC_CSRXD_RXD0_RXD0 (0x00000000) +#define PFC_CSRXD_RXD1_RXD1 (0x00000000) +#define PFC_CSRXD_RXD2_RXD2 (0x00000000) +#define PFC_CSRXD_RXD3_RXD3 (0x00000000) +#define PFC_CSRXD_RXD4_RXD4 (0x00000000) +#define PFC_CSRXD_RXD5_RXD5 (0x00000000) +#define PFC_CSRXD_RXD0_TXD0 (0x00000001) +#define PFC_CSRXD_RXD1_TXD1 (0x00000002) +#define PFC_CSRXD_RXD2_TXD2 (0x00000004) +#define PFC_CSRXD_RXD3_TXD3 (0x00000008) +#define PFC_CSRXD_RXD4_TXD4 (0x00000010) +#define PFC_CSRXD_RXD5_TXD5 (0x00000020) + +#define PFC_CSRXD_RXD0_WE (0x00010000) +#define PFC_CSRXD_RXD1_WE (0x00020000) +#define PFC_CSRXD_RXD2_WE (0x00040000) +#define PFC_CSRXD_RXD3_WE (0x00080000) +#define PFC_CSRXD_RXD4_WE (0x00100000) +#define PFC_CSRXD_RXD5_WE (0x00200000) + +#define PFC_CSRXD_RXD0 (0x0001) +#define PFC_CSRXD_RXD1 (0x0002) +#define PFC_CSRXD_RXD2 (0x0004) +#define PFC_CSRXD_RXD3 (0x0008) +#define PFC_CSRXD_RXD4 (0x0010) +#define PFC_CSRXD_RXD5 (0x0020) + + +#define PFC_ROP_DI_SEL9_PM1 (0x00000000) +#define PFC_ROP_DI_SEL9_P0609 (0x00000100) +#define PFC_ROP_DI_SEL9_GETXC (0x00000200) + +#define PFC_PEX0_NAWPN (0x00000001) +#define PFC_PEX0_IM0CLK (0x00000002) +#define PFC_PEX0_IM1CLK (0x00000004) +#define PFC_PEX0_DETDO (0x00000020) +#define PFC_PEX0_DETMS (0x00000040) +#define PFC_PEX0_PCCLKREQB (0x00000800) +#define PFC_PEX0_PCRSTOUTB (0x00001000) +#define PFC_PEX0_USPWEN (0x00004000) + +typedef enum +{ + PFC_SUCCESSED = CMN_SUCCESS, + PFC_ERROR_GENERAL = -100, + PFC_ERROR_NO_EXIST_REG = -101, + PFC_ERROR_NULL_POINTER = -102, + PFC_ERROR_INVALID_ARG = -103 +} e_pfc_result_t; + +typedef union +{ + struct + { + uint8_t sel[8]; + } byte; + struct + { + uint16_t sel[4]; + } half; + struct + { + uint32_t sel[2]; + } word; + struct + { + uint32_t pin00:3; + uint32_t :1; + uint32_t pin01:3; + uint32_t :1; + uint32_t pin02:3; + uint32_t :1; + uint32_t pin03:3; + uint32_t :1; + uint32_t pin04:3; + uint32_t :1; + uint32_t pin05:3; + uint32_t :1; + uint32_t pin06:3; + uint32_t :1; + uint32_t pin07:3; + uint32_t :1; + uint32_t pin08:3; + uint32_t :1; + uint32_t pin09:3; + uint32_t :1; + uint32_t pin10:3; + uint32_t :1; + uint32_t pin11:3; + uint32_t :1; + uint32_t pin12:3; + uint32_t :1; + uint32_t pin13:3; + uint32_t :1; + uint32_t pin14:3; + uint32_t :1; + uint32_t pin15:3; + uint32_t :1; + } func_sel; +} u_pfc_pfsel_t; + +typedef union +{ + struct + { + uint8_t drv_sel[4]; + } byte; + struct + { + uint16_t drv_sel[2]; + } half; + struct + { + uint32_t drv_sel[1]; + } word; + struct + { + uint32_t pin00:2; + uint32_t pin01:2; + uint32_t pin02:2; + uint32_t pin03:2; + uint32_t pin04:2; + uint32_t pin05:2; + uint32_t pin06:2; + uint32_t pin07:2; + uint32_t pin08:2; + uint32_t pin09:2; + uint32_t pin10:2; + uint32_t pin11:2; + uint32_t pin12:2; + uint32_t pin13:2; + uint32_t pin14:2; + uint32_t pin15:2; + } drv_sel; +} u_pfc_drvsel_t; + +typedef union +{ + struct + { + uint8_t pupd[4]; + } byte; + struct + { + uint16_t pupd[2]; + } half; + struct + { + uint32_t pupd[1]; + } word; + struct + { + uint32_t pin00:2; + uint32_t pin01:2; + uint32_t pin02:2; + uint32_t pin03:2; + uint32_t pin04:2; + uint32_t pin05:2; + uint32_t pin06:2; + uint32_t pin07:2; + uint32_t pin08:2; + uint32_t pin09:2; + uint32_t pin10:2; + uint32_t pin11:2; + uint32_t pin12:2; + uint32_t pin13:2; + uint32_t pin14:2; + uint32_t pin15:2; + } pupd; +} u_pfc_pupd_t; + +typedef union +{ + struct + { + uint8_t pin[4]; + } byte; + struct + { + uint16_t pin[2]; + } half; + struct + { + uint32_t pin[1]; + } word; + struct + { + uint32_t pin00:1; + uint32_t pin01:1; + uint32_t pin02:1; + uint32_t pin03:1; + uint32_t pin04:1; + uint32_t pin05:1; + uint32_t pin06:1; + uint32_t pin07:1; + uint32_t pin08:1; + uint32_t pin09:1; + uint32_t pin10:1; + uint32_t pin11:1; + uint32_t pin12:1; + uint32_t pin13:1; + uint32_t pin14:1; + uint32_t pin15:1; + } bit; +} u_pfc_port_t; + +typedef union +{ + u_pfc_pfsel_t func_sel; + u_pfc_drvsel_t drv_sel; + u_pfc_pupd_t pupd; + u_pfc_port_t pin; + uint32_t uw_data; + uint16_t uh_data; +} u_pfc_data_t; + +typedef enum +{ + PFC_PORT00 = 0, + PFC_PORT01 = 1, + PFC_PORT02 = 2, + PFC_PORT03 = 3, + PFC_PORT04 = 4, + PFC_PORT05 = 5, + PFC_PORT06 = 6, + PFC_PORT07 = 7, + PFC_PORT08 = 8, + PFC_PORT09 = 9, + PFC_PORT10 = 10, + PFC_PORT11 = 11, + PFC_PORT12 = 12, + PFC_PORT13 = 13, + PFC_PORT14 = 14, + PFC_PORT15 = 15, + PFC_PORT16 = 16, + PFC_PORT17 = 17, + PFC_PORT20 = 20, + PFC_PORT21 = 21 +} e_pfc_port_num_t; + +typedef enum +{ + PFC_PORT_GPIO_DO = 0, + PFC_PORT_GPIO_OE, + PFC_PORT_GPIO_IE, + PFC_PORT_PFSEL, + PFC_PORT_DI_MON, + PFC_PORT_PUPD, + PFC_PORT_DRV, + PFC_PORT_SR, + PFC_PORT_DI_MSK, + PFC_PORT_EN_MSK +} e_pfc_kind_reg_t; + +typedef union +{ + struct + { + uint8_t drv[4]; + } byte; + struct + { + uint16_t drv[2]; + } half; + struct + { + uint32_t drv[1]; + } word; + struct + { + uint32_t nawpn:2; + uint32_t im0clk:2; + uint32_t im1clk:2; + uint32_t :4; + uint32_t detdo:2; + uint32_t detms:2; + uint32_t :8; + uint32_t pcclkreqb:2; + uint32_t pcrstoutb:2; + uint32_t :2; + uint32_t uspwen:2; + uint32_t :2; + } drv; +} u_pfc_pex_drv_t; + +typedef union +{ + struct + { + uint8_t pin[4]; + } byte; + struct + { + uint16_t pin[2]; + } half; + struct + { + uint32_t pin[1]; + } word; + struct + { + uint32_t nawpn:1; + uint32_t im0clk:1; + uint32_t im1clk:1; + uint32_t :2; + uint32_t detdo:1; + uint32_t detms:1; + uint32_t :4; + uint32_t pcclkreqb:1; + uint32_t pcrstoutb:1; + uint32_t :1; + uint32_t uspwen:1; + uint32_t :1; + } pin; +} u_pfc_pex_t; + +typedef enum +{ + PFC_EXTINT0_INV = 0, + PFC_EXTINT1_INV = 1, + PFC_EXTINT2_INV = 2, + PFC_EXTINT0_MSK = 4, + PFC_EXTINT1_MSK = 5, + PFC_EXTINT2_MSK = 6 +} e_pfc_extint_reg_num_t; + +typedef enum +{ + PFC_SELECT_EMM = 0, + PFC_SELECT_URT0, + PFC_SELECT_NUM +} e_pfc_select_ip_t; + +uint32_t PFC_ReadReg(uint32_t offset); +void PFC_WriteReg(uint32_t offset, uint32_t value); + +int32_t PFC_SetPortParam(e_pfc_port_num_t port_num, e_pfc_kind_reg_t kind_reg, + uint16_t target, u_pfc_data_t *p_set_data); +int32_t PFC_GetPortParam(e_pfc_port_num_t port_num, e_pfc_kind_reg_t kind_reg, + u_pfc_data_t *p_data); +int32_t PFC_SetPortParamH(e_pfc_port_num_t port_num, e_pfc_kind_reg_t kind_reg, + uint16_t target, uint16_t set_data); + +static inline int32_t PFC_SetGPIO_DO(e_pfc_port_num_t port_num, + uint16_t target, uint16_t set_data) +{ + return PFC_SetPortParamH(port_num, PFC_PORT_GPIO_DO, target, set_data); +} + +static inline int32_t PFC_GetGPIO_DO(e_pfc_port_num_t port_num, + uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_GPIO_DO, + (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_SetGPIO_OE(e_pfc_port_num_t port_num, + uint16_t target, uint16_t set_data) +{ + return PFC_SetPortParamH(port_num, PFC_PORT_GPIO_OE, target, set_data); +} + +static inline int32_t PFC_GetGPIO_OE(e_pfc_port_num_t port_num, + uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_GPIO_OE, + (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_SetGPIO_IE(e_pfc_port_num_t port_num, + uint16_t target, uint16_t set_data) +{ + return PFC_SetPortParamH(port_num, PFC_PORT_GPIO_IE, target, set_data); +} + +static inline int32_t PFC_GetGPIO_IE(e_pfc_port_num_t port_num, + uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_GPIO_OE, + (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_SetPFSEL(e_pfc_port_num_t port_num, + uint16_t target, u_pfc_pfsel_t *p_set_data) +{ + return PFC_SetPortParam(port_num, PFC_PORT_PFSEL, target, + (u_pfc_data_t *)p_set_data); +} + +static inline int32_t PFC_GetPFSEL(e_pfc_port_num_t port_num, + u_pfc_pfsel_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_PFSEL, + (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_GetDI_MON(e_pfc_port_num_t port_num, + uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_DI_MON, + (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_SetPUPD(e_pfc_port_num_t port_num, + uint16_t target, u_pfc_pupd_t *p_set_data) +{ + return PFC_SetPortParam(port_num, PFC_PORT_PUPD, target, + (u_pfc_data_t *)p_set_data); +} + +static inline int32_t PFC_GetPUPD(e_pfc_port_num_t port_num, uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_PUPD, + (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_SetDRV(e_pfc_port_num_t port_num, + uint16_t target, u_pfc_drvsel_t *p_set_data) +{ + return PFC_SetPortParam(port_num, PFC_PORT_DRV, target, + (u_pfc_data_t *)p_set_data); +} + +static inline int32_t PFC_GetDRV(e_pfc_port_num_t port_num, uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_DRV, (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_SetSR(e_pfc_port_num_t port_num, + uint16_t target, uint16_t set_data) +{ + return PFC_SetPortParamH(port_num, PFC_PORT_SR, target, set_data); +} + +static inline int32_t PFC_GetSR(e_pfc_port_num_t port_num, uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_SR, (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_SetDI_MSK(e_pfc_port_num_t port_num, + uint16_t target, uint16_t set_data) +{ + return PFC_SetPortParamH(port_num, PFC_PORT_DI_MSK, target, set_data); +} + +static inline int32_t PFC_GetDI_MSK(e_pfc_port_num_t port_num, + uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_DI_MSK, + (u_pfc_data_t *)p_data); +} + +static inline int32_t PFC_SetEN_MSK(e_pfc_port_num_t port_num, + uint16_t target, uint16_t set_data) +{ + return PFC_SetPortParamH(port_num, PFC_PORT_EN_MSK, target, set_data); +} + +static inline int32_t PFC_GetEN_MSK(e_pfc_port_num_t port_num, + uint32_t *p_data) +{ + return PFC_GetPortParam(port_num, PFC_PORT_EN_MSK, + (u_pfc_data_t *)p_data); +} + + +int32_t PFC_SetCXRXD_SEL(uint16_t target, uint16_t set_data); +int32_t PFC_GetCXRXD_SEL(uint16_t *p_data); + +int32_t PFC_SetROP_DI_SEL(uint32_t set_data); +int32_t PFC_GetROP_DI_SEL(uint32_t *p_data); + +int32_t PFC_SetPEXDRV(uint16_t target, u_pfc_pex_drv_t *p_set_data); +int32_t PFC_GetPEXDRV(uint32_t *p_data); + +int32_t PFC_SetPEXSR(uint16_t target, uint16_t set_data); +int32_t PFC_GetPEXSR(uint32_t *p_data); + +int32_t PFC_SetEXTINT(e_pfc_extint_reg_num_t reg_num, uint16_t target_pin, + uint16_t set_data); +int32_t PFC_GetEXTINT(e_pfc_extint_reg_num_t reg_num, uint32_t *p_data); + +int32_t PFC_SetPinFunc(e_pfc_select_ip_t tgt_ip); +#endif /* !defined(RDK_PFC_H_) */ diff --git a/include/reg_rzg2.h b/include/reg_rzg2.h deleted file mode 100644 index 317da1a..0000000 --- a/include/reg_rzg2.h +++ /dev/null @@ -1,1400 +0,0 @@ -/* - * Copyright (c) 2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -//CPG -#define CPG_CPGWPCR 0xE6150904 // R/W 32 CPG Write Protect Control Register -#define CPG_CPGWPR 0xE6150900 // R/W 32 CPG Write Protect Register -#define CPG_FRQCRB 0xE6150004 // R/W 32 Frequency control register B -#define CPG_FRQCRC 0xE61500E0 // R/W 32 Frequency control register C -#define CPG_PLLECR 0xE61500D0 // R/W 32 PLL Enable Control Register -#define CPG_PLL0CR 0xE61500D8 // R/W 32 PLL0 control register -#define CPG_PLL2CR 0xE615002C // R/W 32 PLL2 control register -#define CPG_PLL3CR 0xE61500DC // R/W 32 PLL2 control register -#define CPG_PLL0STPCR 0xE61500F0 // R/W 32 PLL0 Stop Condition Register -#define CPG_PLL2STPCR 0xE61500F8 // R/W 32 PLL2 Stop Condition Register -#define CPG_PLL3STPCR 0xE61500FC // R/W 32 PLL3 Stop Condition Register -#define CPG_PLL4STPCR 0xE61501F8 // R/W 32 PLL4 Stop Condition Register -#define CPG_SD0CKCR 0xE6150074 // R/W 32 SD-IF0 clock frequency control register -#define CPG_SD1CKCR 0xE6150078 // R/W 32 SD-IF1 clock frequency control register -#define CPG_SD2CKCR 0xE6150268 // R/W 32 SD-IF2 clock frequency control register -#define CPG_SD3CKCR 0xE615026C // R/W 32 SD-IF3 clock frequency control register -#define CPG_RPCCKCR 0xE6150238 // R/W 32 RPC clock frequency control register -#define CPG_SSPSRCCKCR 0xE6150248 // R/W 32 SSPSRC clock frequency control register -#define CPG_SSPRSCKCR 0xE615024C // R/W 32 SSPRS clock frequency control register -#define CPG_CANFDCKCR 0xE6150244 // R/W 32 CAN-FD clock frequency control register -#define CPG_MSOCKCR 0xE6150014 // R/W 32 MSIOF clock frequency control register -#define CPG_HDMICKCR 0xE6150250 // R/W 32 HDMI-IF clock frequency control register -#define CPG_CSI0CKCR 0xE615000C // R/W 32 CSI0 clock frequency control register -#define CPG_CSIREFCKCR 0xE6150034 // R/W 32 CSIREF clock frequency control register -#define CPG_RCKCR 0xE6150240 // R/W 32 RCLK frequency control register -#define CPG_DVFSCR0 0xE6150058 // R/W 32 DVFS control register 0 -#define CPG_DVFSCR1 0xE615005C // R/W 32 DVFS control register 1 -#define CPG_FSAPBR 0xE6150700 // R/W 32 Functional safety of APB bus interface register -#define CPG_FSCLKCSR 0xE6150704 // R/W 32 Functional safety of clocks control/status register -#define CPG_FSCNTCHKH0 0xE6150710 // R/W 32 Functional safety of clocks counter check H register 0 -#define CPG_FSCNTCHKH1 0xE6150714 // R/W 32 Functional safety of clocks counter check H register 1 -#define CPG_FSCNTCHKH2 0xE6150718 // R/W 32 Functional safety of clocks counter check H register 2 -#define CPG_FSCNTCHKH3 0xE615071C // R/W 32 Functional safety of clocks counter check H register 3 -#define CPG_FSCNTCHKH4 0xE6150720 // R/W 32 Functional safety of clocks counter check H register 4 -#define CPG_FSCNTCHKH5 0xE6150724 // R/W 32 Functional safety of clocks counter check H register 5 -#define CPG_FSCNTCHKH6 0xE6150728 // R/W 32 Functional safety of clocks counter check H register 6 -#define CPG_FSCNTCHKL0 0xE6150730 // R/W 32 Functional safety of clocks counter check L register 0 -#define CPG_FSCNTCHKL1 0xE6150734 // R/W 32 Functional safety of clocks counter check L register 1 -#define CPG_FSCNTCHKL2 0xE6150738 // R/W 32 Functional safety of clocks counter check L register 2 -#define CPG_FSCNTCHKL3 0xE615073C // R/W 32 Functional safety of clocks counter check L register 3 -#define CPG_FSCNTCHKL4 0xE6150740 // R/W 32 Functional safety of clocks counter check L register 4 -#define CPG_FSCNTCHKL5 0xE6150744 // R/W 32 Functional safety of clocks counter check L register 5 -#define CPG_FSCNTCHKL6 0xE6150748 // R/W 32 Functional safety of clocks counter check L register 6 -#define CPG_FSCNTMON0 0xE6150750 // R 32 Functional safety of clocks monitor register 0 -#define CPG_FSCNTMON1 0xE6150754 // R 32 Functional safety of clocks monitor register 1 -#define CPG_FSCNTMON2 0xE6150758 // R 32 Functional safety of clocks monitor register 2 -#define CPG_FSCNTMON3 0xE615075C // R 32 Functional safety of clocks monitor register 3 -#define CPG_FSCNTMON4 0xE6150760 // R 32 Functional safety of clocks monitor register 4 -#define CPG_FSCNTMON5 0xE6150764 // R 32 Functional safety of clocks monitor register 5 -#define CPG_FSCNTMON6 0xE6150768 // R 32 Functional safety of clocks monitor register 6 -#define CPG_FSRCHKRA0 0xE6150A00 // R 32 Functional safety reset check register A 0 -#define CPG_FSRCHKRA1 0xE6150A04 // R 32 Functional safety reset check register A 1 -#define CPG_FSRCHKRA2 0xE6150A08 // R 32 Functional safety reset check register A 2 -#define CPG_FSRCHKRA3 0xE6150A0C // R 32 Functional safety reset check register A 3 -#define CPG_FSRCHKRA4 0xE6150A10 // R 32 Functional safety reset check register A 4 -#define CPG_FSRCHKRA5 0xE6150A14 // R 32 Functional safety reset check register A 5 -#define CPG_FSRCHKRA6 0xE6150A18 // R 32 Functional safety reset check register A 6 -#define CPG_FSRCHKRA7 0xE6150A1C // R 32 Functional safety reset check register A 7 -#define CPG_FSRCHKRA8 0xE6150A20 // R 32 Functional safety reset check register A 8 -#define CPG_FSRCHKRA9 0xE6150A24 // R 32 Functional safety reset check register A 9 -#define CPG_FSRCHKRA10 0xE6150A28 // R 32 Functional safety reset check register A 10 -#define CPG_FSRCHKRA11 0xE6150A2C // R 32 Functional safety reset check register A 11 -#define CPG_FSRCHKRA12 0xE6150A30 // R 32 Functional safety reset check register A 12 -#define CPG_FSRCHKRA13 0xE6150A34 // R 32 Functional safety reset check register A 13 -#define CPG_FSRCHKRA14 0xE6150A38 // R 32 Functional safety reset check register A 14 -#define CPG_FSRCHKRA15 0xE6150A3C // R 32 Functional safety reset check register A 15 -#define CPG_FSRCHKRA16 0xE6150B50 // R 32 Functional safety reset check register A 16 -#define CPG_FSRCHKRA17 0xE6150B54 // R 32 Functional safety reset check register A 17 -#define CPG_FSRCHKRA18 0xE6150B58 // R 32 Functional safety reset check register A 18 -#define CPG_FSRCHKRB0 0xE6150A30 // R 32 Functional safety reset check register B 0 -#define CPG_FSRCHKRB1 0xE6150A34 // R 32 Functional safety reset check register B 1 -#define CPG_FSRCHKRB2 0xE6150A38 // R 32 Functional safety reset check register B 2 -#define CPG_FSRCHKRB3 0xE6150A3C // R 32 Functional safety reset check register B 3 -#define CPG_FSRCHKRB4 0xE6150A40 // R 32 Functional safety reset check register B 4 -#define CPG_FSRCHKRB5 0xE6150A44 // R 32 Functional safety reset check register B 5 -#define CPG_FSRCHKRB6 0xE6150A48 // R 32 Functional safety reset check register B 6 -#define CPG_FSRCHKRB7 0xE6150A4C // R 32 Functional safety reset check register B 7 -#define CPG_FSRCHKRB8 0xE6150A50 // R 32 Functional safety reset check register B 8 -#define CPG_FSRCHKRB9 0xE6150A54 // R 32 Functional safety reset check register B 9 -#define CPG_FSRCHKRB10 0xE6150A58 // R 32 Functional safety reset check register B 10 -#define CPG_FSRCHKRB11 0xE6150A5C // R 32 Functional safety reset check register B 11 -#define CPG_FSRCHKRB13 0xE6150A74 // R 32 Functional safety reset check register B 13 -#define CPG_FSRCHKSETR0 0xE6150A60 // W 32 Functional safety reset check set register 0 -#define CPG_FSRCHKSETR1 0xE6150A64 // W 32 Functional safety reset check set register 1 -#define CPG_FSRCHKSETR2 0xE6150A68 // W 32 Functional safety reset check set register 2 -#define CPG_FSRCHKSETR3 0xE6150A6C // W 32 Functional safety reset check set register 3 -#define CPG_FSRCHKSETR4 0xE6150A70 // W 32 Functional safety reset check set register 4 -#define CPG_FSRCHKSETR5 0xE6150A74 // W 32 Functional safety reset check set register 5 -#define CPG_FSRCHKSETR6 0xE6150A78 // W 32 Functional safety reset check set register 6 -#define CPG_FSRCHKSETR7 0xE6150A7C // W 32 Functional safety reset check set register 7 -#define CPG_FSRCHKSETR8 0xE6150A80 // W 32 Functional safety reset check set register 8 -#define CPG_FSRCHKSETR9 0xE6150A84 // W 32 Functional safety reset check set register 9 -#define CPG_FSRCHKSETR10 0xE6150A88 // W 32 Functional safety reset check set register 10 -#define CPG_FSRCHKSETR11 0xE6150A8C // W 32 Functional safety reset check set register 11 -#define CPG_FSRCHKSETR12 0xE6150AB0 // W 32 Functional safety reset check set register 12 -#define CPG_FSRCHKSETR13 0xE6150AB4 // W 32 Functional safety reset check set register 13 -#define CPG_FSRCHKSETR14 0xE6150AB8 // W 32 Functional safety reset check set register 14 -#define CPG_FSRCHKSETR15 0xE6150ABC // W 32 Functional safety reset check set register 15 -#define CPG_FSRCHKSETR16 0xE6150B60 // W 32 Functional safety reset check set register 16 -#define CPG_FSRCHKSETR17 0xE6150B64 // W 32 Functional safety reset check set register 17 -#define CPG_FSRCHKSETR18 0xE6150B68 // W 32 Functional safety reset check set register 18 -#define CPG_FSRCHKCLRR0 0xE6150A90 // W 32 Functional safety reset check clear register 0 -#define CPG_FSRCHKCLRR1 0xE6150A94 // W 32 Functional safety reset check clear register 1 -#define CPG_FSRCHKCLRR2 0xE6150A98 // W 32 Functional safety reset check clear register 2 -#define CPG_FSRCHKCLRR3 0xE6150A9C // W 32 Functional safety reset check clear register 3 -#define CPG_FSRCHKCLRR4 0xE6150AA0 // W 32 Functional safety reset check clear register 4 -#define CPG_FSRCHKCLRR5 0xE6150AA4 // W 32 Functional safety reset check clear register 5 -#define CPG_FSRCHKCLRR6 0xE6150AA8 // W 32 Functional safety reset check clear register 6 -#define CPG_FSRCHKCLRR7 0xE6150AAC // W 32 Functional safety reset check clear register 7 -#define CPG_FSRCHKCLRR8 0xE6150AB0 // W 32 Functional safety reset check clear register 8 -#define CPG_FSRCHKCLRR9 0xE6150AB4 // W 32 Functional safety reset check clear register 9 -#define CPG_FSRCHKCLRR10 0xE6150AB8 // W 32 Functional safety reset check clear register 10 -#define CPG_FSRCHKCLRR11 0xE6150ABC // W 32 Functional safety reset check clear register 11 -#define CPG_FSRCHKCLRR12 0xE6150AF0 // W 32 Functional safety reset check clear register 12 -#define CPG_FSRCHKCLRR13 0xE6150AF4 // W 32 Functional safety reset check clear register 13 -#define CPG_FSRCHKCLRR14 0xE6150AF8 // W 32 Functional safety reset check clear register 14 -#define CPG_FSRCHKCLRR15 0xE6150AFC // W 32 Functional safety reset check clear register 15 -#define CPG_FSRCHKCLRR16 0xE6150B70 // W 32 Functional safety reset check clear register 16 -#define CPG_FSRCHKCLRR17 0xE6150B74 // W 32 Functional safety reset check clear register 17 -#define CPG_FSRCHKCLRR18 0xE6150B78 // W 32 Functional safety reset check clear register 18 -#define CPG_FSSEQCHKR 0xE6150AF0 // R 32 Functional safety Power on sequence Check Register -#define CPG_FSSEQCHKCSR 0xE6150AF4 // R/W 32 Functional safety Power on sequence Check Control/Status Register - -//GPIO -#define GPIO_IOINTSEL0 0xE6050000 // R/W 32 General IO/interrupt switching register 0 -#define GPIO_INOUTSEL0 0xE6050004 // R/W 32 General input/output switching register 0 -#define GPIO_OUTDT0 0xE6050008 // R/W 32 General output register 0 -#define GPIO_INDT0 0xE605000C // R 32 General input register 0 -#define GPIO_INTDT0 0xE6050010 // R 32 Interrupt display register 0 -#define GPIO_INTCLR0 0xE6050014 // R/W 32 Interrupt clear register 0 -#define GPIO_INTMSK0 0xE6050018 // R/W 32 Interrupt mask register 0 -#define GPIO_MSKCLR0 0xE605001C // R/W 32 Interrupt mask clear register 0 -#define GPIO_POSNEG0 0xE6050020 // R/W 32 Positive/negative logic select register 0 -#define GPIO_EDGLEVEL0 0xE6050024 // R/W 32 Edge/level select register 0 -#define GPIO_FILONOFF0 0xE6050028 // R/W 32 Chattering prevention on/off register 0 -#define GPIO_INTMSKS0 0xE6050038 // R/W 32 Interrupt sub mask register 0 -#define GPIO_MSKCLRS0 0xE605003C // R/W 32 Interrupt sub mask clear register 0 -#define GPIO_OUTDTSEL0 0xE6050040 // R/W 32 Output data select register 0 -#define GPIO_OUTDTH0 0xE6050044 // R/W 32 Output data high register 0 -#define GPIO_OUTDTL0 0xE6050048 // R/W 32 Output data low register 0 -#define GPIO_BOTHEDGE0 0xE605004C // R/W 32 One edge/both edge select register 0 -#define GPIO_IOINTSEL1 0xE6051000 // R/W 32 General IO/interrupt switching register 1 -#define GPIO_INOUTSEL1 0xE6051004 // R/W 32 General input/output switching register 1 -#define GPIO_OUTDT1 0xE6051008 // R/W 32 General output register 1 -#define GPIO_INDT1 0xE605100C // R 32 General input register 1 -#define GPIO_INTDT1 0xE6051010 // R 32 Interrupt display register 1 -#define GPIO_INTCLR1 0xE6051014 // R/W 32 Interrupt clear register 1 -#define GPIO_INTMSK1 0xE6051018 // R/W 32 Interrupt mask register 1 -#define GPIO_MSKCLR1 0xE605101C // R/W 32 Interrupt mask clear register 1 -#define GPIO_POSNEG1 0xE6051020 // R/W 32 Positive/negative logic select register 1 -#define GPIO_EDGLEVEL1 0xE6051024 // R/W 32 Edge/level select register 1 -#define GPIO_FILONOFF1 0xE6051028 // R/W 32 Chattering prevention on/off register 1 -#define GPIO_INTMSKS1 0xE6051038 // R/W 32 Interrupt sub mask register 1 -#define GPIO_MSKCLRS1 0xE605103C // R/W 32 Interrupt sub mask clear register 1 -#define GPIO_OUTDTSEL1 0xE6051040 // R/W 32 Output data select register 1 -#define GPIO_OUTDTH1 0xE6051044 // R/W 32 Output data high register 1 -#define GPIO_OUTDTL1 0xE6051048 // R/W 32 Output data low register 1 -#define GPIO_BOTHEDGE1 0xE605104C // R/W 32 One edge/both edge select register 1 -#define GPIO_IOINTSEL2 0xE6052000 // R/W 32 General IO/interrupt switching register 2 -#define GPIO_INOUTSEL2 0xE6052004 // R/W 32 General input/output switching register 2 -#define GPIO_OUTDT2 0xE6052008 // R/W 32 General output register 2 -#define GPIO_INDT2 0xE605200C // R 32 General input register 2 -#define GPIO_INTDT2 0xE6052010 // R 32 Interrupt display register 2 -#define GPIO_INTCLR2 0xE6052014 // R/W 32 Interrupt clear register 2 -#define GPIO_INTMSK2 0xE6052018 // R/W 32 Interrupt mask register 2 -#define GPIO_MSKCLR2 0xE605201C // R/W 32 Interrupt mask clear register 2 -#define GPIO_POSNEG2 0xE6052020 // R/W 32 Positive/negative logic select register 2 -#define GPIO_EDGLEVEL2 0xE6052024 // R/W 32 Edge/level select register 2 -#define GPIO_FILONOFF2 0xE6052028 // R/W 32 Chattering prevention on/off register 2 -#define GPIO_INTMSKS2 0xE6052038 // R/W 32 Interrupt sub mask register 2 -#define GPIO_MSKCLRS2 0xE605203C // R/W 32 Interrupt sub mask clear register 2 -#define GPIO_OUTDTSEL2 0xE6052040 // R/W 32 Output data select register 2 -#define GPIO_OUTDTH2 0xE6052044 // R/W 32 Output data high register 2 -#define GPIO_OUTDTL2 0xE6052048 // R/W 32 Output data low register 2 -#define GPIO_BOTHEDGE2 0xE605204C // R/W 32 One edge/both edge select register 2 -#define GPIO_IOINTSEL3 0xE6053000 // R/W 32 General IO/interrupt switching register 3 -#define GPIO_INOUTSEL3 0xE6053004 // R/W 32 General input/output switching register 3 -#define GPIO_OUTDT3 0xE6053008 // R/W 32 General output register 3 -#define GPIO_INDT3 0xE605300C // R 32 General input register 3 -#define GPIO_INTDT3 0xE6053010 // R 32 Interrupt display register 3 -#define GPIO_INTCLR3 0xE6053014 // R/W 32 Interrupt clear register 3 -#define GPIO_INTMSK3 0xE6053018 // R/W 32 Interrupt mask register 3 -#define GPIO_MSKCLR3 0xE605301C // R/W 32 Interrupt mask clear register 3 -#define GPIO_POSNEG3 0xE6053020 // R/W 32 Positive/negative logic select register 3 -#define GPIO_EDGLEVEL3 0xE6053024 // R/W 32 Edge/level select register 3 -#define GPIO_FILONOFF3 0xE6053028 // R/W 32 Chattering prevention on/off register 3 -#define GPIO_INTMSKS3 0xE6053038 // R/W 32 Interrupt sub mask register 3 -#define GPIO_MSKCLRS3 0xE605303C // R/W 32 Interrupt sub mask clear register 3 -#define GPIO_OUTDTSEL3 0xE6053040 // R/W 32 Output data select register 3 -#define GPIO_OUTDTH3 0xE6053044 // R/W 32 Output data high register 3 -#define GPIO_OUTDTL3 0xE6053048 // R/W 32 Output data low register 3 -#define GPIO_BOTHEDGE3 0xE605304C // R/W 32 One edge/both edge select register 3 -#define GPIO_IOINTSEL4 0xE6054000 // R/W 32 General IO/interrupt switching register 4 -#define GPIO_INOUTSEL4 0xE6054004 // R/W 32 General input/output switching register 4 -#define GPIO_OUTDT4 0xE6054008 // R/W 32 General output register 4 -#define GPIO_INDT4 0xE605400C // R 32 General input register 4 -#define GPIO_INTDT4 0xE6054010 // R 32 Interrupt display register 4 -#define GPIO_INTCLR4 0xE6054014 // R/W 32 Interrupt clear register 4 -#define GPIO_INTMSK4 0xE6054018 // R/W 32 Interrupt mask register 4 -#define GPIO_MSKCLR4 0xE605401C // R/W 32 Interrupt mask clear register 4 -#define GPIO_POSNEG4 0xE6054020 // R/W 32 Positive/negative logic select register 4 -#define GPIO_EDGLEVEL4 0xE6054024 // R/W 32 Edge/level select register 4 -#define GPIO_FILONOFF4 0xE6054028 // R/W 32 Chattering prevention on/off register 4 -#define GPIO_INTMSKS4 0xE6054038 // R/W 32 Interrupt sub mask register 4 -#define GPIO_MSKCLRS4 0xE605403C // R/W 32 Interrupt sub mask clear register 4 -#define GPIO_OUTDTSEL4 0xE6054040 // R/W 32 Output data select register 4 -#define GPIO_OUTDTH4 0xE6054044 // R/W 32 Output data high register 4 -#define GPIO_OUTDTL4 0xE6054048 // R/W 32 Output data low register 4 -#define GPIO_BOTHEDGE4 0xE605404C // R/W 32 One edge/both edge select register 4 -#define GPIO_IOINTSEL5 0xE6055000 // R/W 32 General IO/interrupt switching register 5 -#define GPIO_INOUTSEL5 0xE6055004 // R/W 32 General input/output switching register 5 -#define GPIO_OUTDT5 0xE6055008 // R/W 32 General output register 5 -#define GPIO_INDT5 0xE605500C // R 32 General input register 5 -#define GPIO_INTDT5 0xE6055010 // R 32 Interrupt display register 5 -#define GPIO_INTCLR5 0xE6055014 // R/W 32 Interrupt clear register 5 -#define GPIO_INTMSK5 0xE6055018 // R/W 32 Interrupt mask register 5 -#define GPIO_MSKCLR5 0xE605501C // R/W 32 Interrupt mask clear register 5 -#define GPIO_POSNEG5 0xE6055020 // R/W 32 Positive/negative logic select register 5 -#define GPIO_EDGLEVEL5 0xE6055024 // R/W 32 Edge/level select register 5 -#define GPIO_FILONOFF5 0xE6055028 // R/W 32 Chattering prevention on/off register 5 -#define GPIO_INTMSKS5 0xE6055038 // R/W 32 Interrupt sub mask register 5 -#define GPIO_MSKCLRS5 0xE605503C // R/W 32 Interrupt sub mask clear register 5 -#define GPIO_OUTDTSEL5 0xE6055040 // R/W 32 Output data select register 5 -#define GPIO_OUTDTH5 0xE6055044 // R/W 32 Output data high register 5 -#define GPIO_OUTDTL5 0xE6055048 // R/W 32 Output data low register 5 -#define GPIO_BOTHEDGE5 0xE605504C // R/W 32 One edge/both edge select register 5 -#define GPIO_IOINTSEL6 0xE6055400 // R/W 32 General IO/interrupt switching register 6 -#define GPIO_INOUTSEL6 0xE6055404 // R/W 32 General input/output switching register 6 -#define GPIO_OUTDT6 0xE6055408 // R/W 32 General output register 6 -#define GPIO_INDT6 0xE605540C // R 32 General input register 6 -#define GPIO_INTDT6 0xE6055410 // R 32 Interrupt display register 6 -#define GPIO_INTCLR6 0xE6055414 // R/W 32 Interrupt clear register 6 -#define GPIO_INTMSK6 0xE6055418 // R/W 32 Interrupt mask register 6 -#define GPIO_MSKCLR6 0xE605541C // R/W 32 Interrupt mask clear register 6 -#define GPIO_POSNEG6 0xE6055420 // R/W 32 Positive/negative logic select register 6 -#define GPIO_EDGLEVEL6 0xE6055424 // R/W 32 Edge/level select register 6 -#define GPIO_FILONOFF6 0xE6055428 // R/W 32 Chattering prevention on/off register 6 -#define GPIO_INTMSKS6 0xE6055438 // R/W 32 Interrupt sub mask register 6 -#define GPIO_MSKCLRS6 0xE605543C // R/W 32 Interrupt sub mask clear register 6 -#define GPIO_OUTDTSEL6 0xE6055440 // R/W 32 Output data select register 6 -#define GPIO_OUTDTH6 0xE6055444 // R/W 32 Output data high register 6 -#define GPIO_OUTDTL6 0xE6055448 // R/W 32 Output data low register 6 -#define GPIO_BOTHEDGE6 0xE605544C // R/W 32 One edge/both edge select register 6 -#define GPIO_IOINTSEL7 0xE6055800 // R/W 32 General IO/interrupt switching register 7 -#define GPIO_INOUTSEL7 0xE6055804 // R/W 32 General input/output switching register 7 -#define GPIO_OUTDT7 0xE6055808 // R/W 32 General output register 7 -#define GPIO_INDT7 0xE605580C // R 32 General input register 7 -#define GPIO_INTDT7 0xE6055810 // R 32 Interrupt display register 7 -#define GPIO_INTCLR7 0xE6055814 // R/W 32 Interrupt clear register 7 -#define GPIO_INTMSK7 0xE6055818 // R/W 32 Interrupt mask register 7 -#define GPIO_MSKCLR7 0xE605581C // R/W 32 Interrupt mask clear register 7 -#define GPIO_POSNEG7 0xE6055820 // R/W 32 Positive/negative logic select register 7 -#define GPIO_EDGLEVEL7 0xE6055824 // R/W 32 Edge/level select register 7 -#define GPIO_FILONOFF7 0xE6055828 // R/W 32 Chattering prevention on/off register 7 -#define GPIO_INTMSKS7 0xE6055838 // R/W 32 Interrupt sub mask register 7 -#define GPIO_MSKCLRS7 0xE605583C // R/W 32 Interrupt sub mask clear register 7 -#define GPIO_OUTDTSEL7 0xE6055840 // R/W 32 Output data select register 7 -#define GPIO_OUTDTH7 0xE6055844 // R/W 32 Output data high register 7 -#define GPIO_OUTDTL7 0xE6055848 // R/W 32 Output data low register 7 -#define GPIO_BOTHEDGE7 0xE605584C // R/W 32 One edge/both edge select register 7 - -//LBSC.h -#define LBSC_CS0CTRL 0xEE220200 // R/W 32 Area 0 control register -#define LBSC_CS1CTRL 0xEE220204 // R/W 32 Area 1 control register -#define LBSC_CSWCR0 0xEE220230 // R/W 32 Area 0 RD/WE pulse control register -#define LBSC_CSWCR1 0xEE220234 // R/W 32 Area 1 RD/WE pulse control register -#define LBSC_CSPWCR0 0xEE220280 // R/W 32 Area 0 external wait control register -#define LBSC_CSPWCR1 0xEE220284 // R/W 32 Area 1 external wait control register -#define LBSC_EXWTSYNC 0xEE2202A0 // R/W 32 External wait input control register -#define LBSC_CS0BSTCTL 0xEE2202B0 // R/W 32 Area 0 burst control register -#define LBSC_CS0BTPH 0xEE2202B4 // R/W 32 Area 0 burst pitch set register -#define LBSC_CS1GDST 0xEE2202C0 // R/W 32 Area 1 guard setting register -#define LBSC_BCINTSR 0xEE220330 // R 32 BSC interrupt source status register -#define LBSC_BCINTCR 0xEE220334 // -/WC1 32 BSC interrupt source clear register -#define LBSC_BCINTMR 0xEE220338 // R/W 32 BSC interrupt enable register -#define LBSC_EXWTSTS 0xEE220344 // R 32 External wait status register -#define LBSC_EXBCT 0xEE2203C0 // R/W 32 EX-BUS wait timeout detection base counter register -#define LBSC_EXTCT 0xEE2203C4 // R/W 32 EX-BUS wait timeout detection counter register -#define LBSC_EXTSR 0xEE220010 // R/WC1 32 EX-BUS wait timeout detection access source indication register -#define LBSC_EXTADR 0xEE220014 // R/W 32 EX-BUS wait timeout detection address indication register - -//MSTPRST -#define CPG_MSTPSR0 0xE6150030 // R 32 Module stop status register 0 -#define CPG_MSTPSR1 0xE6150038 // R 32 Module stop status register 1 -#define CPG_MSTPSR2 0xE6150040 // R 32 Module stop status register 2 -#define CPG_MSTPSR3 0xE6150048 // R 32 Module stop status register 3 -#define CPG_MSTPSR4 0xE615004C // R 32 Module stop status register 4 -#define CPG_MSTPSR5 0xE615003C // R 32 Module stop status register 5 -#define CPG_MSTPSR6 0xE61501C0 // R 32 Module stop status register 6 -#define CPG_MSTPSR7 0xE61501C4 // R 32 Module stop status register 7 -#define CPG_MSTPSR8 0xE61509A0 // R 32 Module stop status register 8 -#define CPG_MSTPSR9 0xE61509A4 // R 32 Module stop status register 9 -#define CPG_MSTPSR10 0xE61509A8 // R 32 Module stop status register 10 -#define CPG_MSTPSR11 0xE61509AC // R 32 Module stop status register 11 -#define CPG_RMSTPCR0 0xE6150110 // R/W 32 Realtime module stop control register 0 -#define CPG_RMSTPCR1 0xE6150114 // R/W 32 Realtime module stop control register 1 -#define CPG_RMSTPCR2 0xE6150118 // R/W 32 Realtime module stop control register 2 -#define CPG_RMSTPCR3 0xE615011C // R/W 32 Realtime module stop control register 3 -#define CPG_RMSTPCR4 0xE6150120 // R/W 32 Realtime module stop control register 4 -#define CPG_RMSTPCR5 0xE6150124 // R/W 32 Realtime module stop control register 5 -#define CPG_RMSTPCR6 0xE6150128 // R/W 32 Realtime module stop control register 6 -#define CPG_RMSTPCR7 0xE615012C // R/W 32 Realtime module stop control register 7 -#define CPG_RMSTPCR8 0xE6150980 // R/W 32 Realtime module stop control register 8 -#define CPG_RMSTPCR9 0xE6150984 // R/W 32 Realtime module stop control register 9 -#define CPG_RMSTPCR10 0xE6150988 // R/W 32 Realtime module stop control register 10 -#define CPG_RMSTPCR11 0xE615098C // R/W 32 Realtime module stop control register 11 -#define CPG_SMSTPCR0 0xE6150130 // R/W 32 System module stop control register 0 -#define CPG_SMSTPCR1 0xE6150134 // R/W 32 System module stop control register 1 -#define CPG_SMSTPCR2 0xE6150138 // R/W 32 System module stop control register 2 -#define CPG_SMSTPCR3 0xE615013C // R/W 32 System module stop control register 3 -#define CPG_SMSTPCR4 0xE6150140 // R/W 32 System module stop control register 4 -#define CPG_SMSTPCR5 0xE6150144 // R/W 32 System module stop control register 5 -#define CPG_SMSTPCR6 0xE6150148 // R/W 32 System module stop control register 6 -#define CPG_SMSTPCR7 0xE615014C // R/W 32 System module stop control register 7 -#define CPG_SMSTPCR8 0xE6150990 // R/W 32 System module stop control register 8 -#define CPG_SMSTPCR9 0xE6150994 // R/W 32 System module stop control register 9 -#define CPG_SMSTPCR10 0xE6150998 // R/W 32 System module stop control register 10 -#define CPG_SMSTPCR11 0xE615099C // R/W 32 System module stop control register 11 -#define CPG_SRCR0 0xE61500A0 // R/W 32 Software reset register 0 -#define CPG_SRCR1 0xE61500A8 // R/W 32 Software reset register 1 -#define CPG_SRCR2 0xE61500B0 // R/W 32 Software reset register 2 -#define CPG_SRCR3 0xE61500B8 // R/W 32 Software reset register 3 -#define CPG_SRCR4 0xE61500BC // R/W 32 Software reset register 4 -#define CPG_SRCR5 0xE61500C4 // R/W 32 Software reset register 5 -#define CPG_SRCR6 0xE61501C8 // R/W 32 Software reset register 6 -#define CPG_SRCR7 0xE61501CC // R/W 32 Software reset register 7 -#define CPG_SRCR8 0xE6150920 // R/W 32 Software reset register 8 -#define CPG_SRCR9 0xE6150924 // R/W 32 Software reset register 9 -#define CPG_SRCR10 0xE6150928 // R/W 32 Software reset register 10 -#define CPG_SRCR11 0xE615092C // R/W 32 Software reset register 11 -#define CPG_SRSTCLR0 0xE6150940 // W 32 Software reset clearing register 0 -#define CPG_SRSTCLR1 0xE6150944 // W 32 Software reset clearing register 1 -#define CPG_SRSTCLR2 0xE6150948 // W 32 Software reset clearing register 2 -#define CPG_SRSTCLR3 0xE615094C // W 32 Software reset clearing register 3 -#define CPG_SRSTCLR4 0xE6150950 // W 32 Software reset clearing register 4 -#define CPG_SRSTCLR5 0xE6150954 // W 32 Software reset clearing register 5 -#define CPG_SRSTCLR6 0xE6150958 // W 32 Software reset clearing register 6 -#define CPG_SRSTCLR7 0xE615095C // W 32 Software reset clearing register 7 -#define CPG_SRSTCLR8 0xE6150960 // W 32 Software reset clearing register 8 -#define CPG_SRSTCLR9 0xE6150964 // W 32 Software reset clearing register 9 -#define CPG_SRSTCLR10 0xE6150968 // W 32 Software reset clearing register 10 -#define CPG_SRSTCLR11 0xE615096C // W 32 Software reset clearing register 11 -#define CPG_SAMSTPCR0 0xE6150C20 // R/W 32 Safety Module Stop Control Register 0 -#define CPG_SAMSTPCR1 0xE6150C24 // R/W 32 Safety Module Stop Control Register 1 -#define CPG_SAMSTPCR2 0xE6150C28 // R/W 32 Safety Module Stop Control Register 2 -#define CPG_SAMSTPCR3 0xE6150C2C // R/W 32 Safety Module Stop Control Register 3 -#define CPG_SAMSTPCR4 0xE6150C30 // R/W 32 Safety Module Stop Control Register 4 -#define CPG_SAMSTPCR5 0xE6150C34 // R/W 32 Safety Module Stop Control Register 5 -#define CPG_SAMSTPCR6 0xE6150C38 // R/W 32 Safety Module Stop Control Register 6 -#define CPG_SAMSTPCR7 0xE6150C3C // R/W 32 Safety Module Stop Control Register 7 -#define CPG_SAMSTPCR8 0xE6150C40 // R/W 32 Safety Module Stop Control Register 8 -#define CPG_SAMSTPCR9 0xE6150C44 // R/W 32 Safety Module Stop Control Register 9 -#define CPG_SAMSTPCR10 0xE6150C48 // R/W 32 Safety Module Stop Control Register 10 -#define CPG_SAMSTPCR11 0xE6150C4C // R/W 32 Safety Module Stop Control Register 11 -#define CPG_SASRSTECR0 0xE6150C80 // R/W 32 Safety Software Reset Access Enable Control Register 0 -#define CPG_SASRSTECR1 0xE6150C84 // R/W 32 Safety Software Reset Access Enable Control Register 1 -#define CPG_SASRSTECR2 0xE6150C88 // R/W 32 Safety Software Reset Access Enable Control Register 2 -#define CPG_SASRSTECR3 0xE6150C8C // R/W 32 Safety Software Reset Access Enable Control Register 3 -#define CPG_SASRSTECR4 0xE6150C90 // R/W 32 Safety Software Reset Access Enable Control Register 4 -#define CPG_SASRSTECR5 0xE6150C94 // R/W 32 Safety Software Reset Access Enable Control Register 5 -#define CPG_SASRSTECR6 0xE6150C98 // R/W 32 Safety Software Reset Access Enable Control Register 6 -#define CPG_SASRSTECR7 0xE6150C9C // R/W 32 Safety Software Reset Access Enable Control Register 7 -#define CPG_SASRSTECR8 0xE6150CA0 // R/W 32 Safety Software Reset Access Enable Control Register 8 -#define CPG_SASRSTECR9 0xE6150CA4 // R/W 32 Safety Software Reset Access Enable Control Register 9 -#define CPG_SASRSTECR10 0xE6150CA8 // R/W 32 Safety Software Reset Access Enable Control Register 10 -#define CPG_SASRSTECR11 0xE6150CAC // R/W 32 Safety Software Reset Access Enable Control Register 11 -#define CPG_SAPTCSR 0xE6150C00 // R/W 32 Safety Protect Control/Status Register -#define CPG_SAERMIDR 0xE6150C04 // R 32 Safety Error Master ID Register -#define CPG_SAERADR 0xE6150C08 // R 32 Safety Error Address Regsiter - -//PFC -#define PFC_PMMR 0xE6060000 // R/W 32 LSI Multiplexed Pin Setting Mask Register -#define PFC_GPSR0 0xE6060100 // R/W 32 GPIO/Peripheral Function Select register 0 -#define PFC_GPSR1 0xE6060104 // R/W 32 GPIO/Peripheral Function Select register 1 -#define PFC_GPSR2 0xE6060108 // R/W 32 GPIO/Peripheral_Function Select register 2 -#define PFC_GPSR3 0xE606010C // R/W 32 GPIO/Peripheral Function Select register 3 -#define PFC_GPSR4 0xE6060110 // R/W 32 GPIO/Peripheral Function Select register 4 -#define PFC_GPSR5 0xE6060114 // R/W 32 GPIO/Peripheral Function Select register 5 -#define PFC_GPSR6 0xE6060118 // R/W 32 GPIO/Peripheral Function Select register 6 -#define PFC_GPSR7 0xE606011C // R/W 32 GPIO/Peripheral Function Select register 7 -#define PFC_IPSR0 0xE6060200 // R/W 32 Peripheral Function Select register 0 -#define PFC_IPSR1 0xE6060204 // R/W 32 Peripheral Function Select register 1 -#define PFC_IPSR2 0xE6060208 // R/W 32 Peripheral Function Select register 2 -#define PFC_IPSR3 0xE606020C // R/W 32 Peripheral Function Select register 3 -#define PFC_IPSR4 0xE6060210 // R/W 32 Peripheral Function Select register 4 -#define PFC_IPSR5 0xE6060214 // R/W 32 Peripheral Function Select register 5 -#define PFC_IPSR6 0xE6060218 // R/W 32 Peripheral Function Select register 6 -#define PFC_IPSR7 0xE606021C // R/W 32 Peripheral Function Select register 7 -#define PFC_IPSR8 0xE6060220 // R/W 32 Peripheral Function Select register 8 -#define PFC_IPSR9 0xE6060224 // R/W 32 Peripheral Function Select register 9 -#define PFC_IPSR10 0xE6060228 // R/W 32 Peripheral Function Select register 10 -#define PFC_IPSR11 0xE606022C // R/W 32 Peripheral Function Select register 11 -#define PFC_IPSR12 0xE6060230 // R/W 32 Peripheral Function Select register 12 -#define PFC_IPSR13 0xE6060234 // R/W 32 Peripheral Function Select register 13 -#define PFC_IPSR14 0xE6060238 // R/W 32 Peripheral Function Select register 14 -#define PFC_IPSR15 0xE606023C // R/W 32 Peripheral Function Select register 15 -#define PFC_IPSR16 0xE6060240 // R/W 32 Peripheral Function Select register 16 -#define PFC_IPSR17 0xE6060244 // R/W 32 Peripheral Function Select register 17 -#define PFC_IPSR18 0xE6060248 // R/W 32 Peripheral Function Select register 18 -#define PFC_DRVCTRL0 0xE6060300 // R/W 32 DRV control register0 -#define PFC_DRVCTRL1 0xE6060304 // R/W 32 DRV control register1 -#define PFC_DRVCTRL2 0xE6060308 // R/W 32 DRV control register2 -#define PFC_DRVCTRL3 0xE606030C // R/W 32 DRV control register3 -#define PFC_DRVCTRL4 0xE6060310 // R/W 32 DRV control register4 -#define PFC_DRVCTRL5 0xE6060314 // R/W 32 DRV control register5 -#define PFC_DRVCTRL6 0xE6060318 // R/W 32 DRV control register6 -#define PFC_DRVCTRL7 0xE606031C // R/W 32 DRV control register7 -#define PFC_DRVCTRL8 0xE6060320 // R/W 32 DRV control register8 -#define PFC_DRVCTRL9 0xE6060324 // R/W 32 DRV control register9 -#define PFC_DRVCTRL10 0xE6060328 // R/W 32 DRV control register10 -#define PFC_DRVCTRL11 0xE606032C // R/W 32 DRV control register11 -#define PFC_DRVCTRL12 0xE6060330 // R/W 32 DRV control register12 -#define PFC_DRVCTRL13 0xE6060334 // R/W 32 DRV control register13 -#define PFC_DRVCTRL14 0xE6060338 // R/W 32 DRV control register14 -#define PFC_DRVCTRL15 0xE606033C // R/W 32 DRV control register15 -#define PFC_DRVCTRL16 0xE6060340 // R/W 32 DRV control register16 -#define PFC_DRVCTRL17 0xE6060344 // R/W 32 DRV control register17 -#define PFC_DRVCTRL18 0xE6060348 // R/W 32 DRV control register18 -#define PFC_DRVCTRL19 0xE606034C // R/W 32 DRV control register19 -#define PFC_DRVCTRL20 0xE6060350 // R/W 32 DRV control register20 -#define PFC_DRVCTRL21 0xE6060354 // R/W 32 DRV control register21 -#define PFC_DRVCTRL22 0xE6060358 // R/W 32 DRV control register22 -#define PFC_DRVCTRL23 0xE606035C // R/W 32 DRV control register23 -#define PFC_DRVCTRL24 0xE6060360 // R/W 32 DRV control register24 -#define PFC_POCCTRL0 0xE6060380 // R/W 32 POC control register0 -#define PFC_TDSELCTRL0 0xE60603C0 // R/W 32 TDSEL control register0 -#define PFC_IOCTRL 0xE60603E0 // R/W 32 IO cell control for IICDVFS -#define PFC_FUSEMON 0xE60603E4 // R 32 Fuse Monitor register0 -#define PFC_PUEN0 0xE6060400 // R/W 32 LSI pin pull-enable register 0 -#define PFC_PUEN1 0xE6060404 // R/W 32 LSI pin pull-enable register 1 -#define PFC_PUEN2 0xE6060408 // R/W 32 LSI pin pull-enable register 2 -#define PFC_PUEN3 0xE606040C // R/W 32 LSI pin pull-enable register 3 -#define PFC_PUEN4 0xE6060410 // R/W 32 LSI pin pull-enable register 4 -#define PFC_PUEN5 0xE6060414 // R/W 32 LSI pin pull-enable register 5 -#define PFC_PUEN6 0xE6060418 // R/W 32 LSI pin pull-enable register 6 -#define PFC_PUD0 0xE6060440 // R/W 32 LSI pin pull-up/down control register 0 -#define PFC_PUD1 0xE6060444 // R/W 32 LSI pin pull-up/down control register 1 -#define PFC_PUD2 0xE6060448 // R/W 32 LSI pin pull-up/down control register 2 -#define PFC_PUD3 0xE606044C // R/W 32 LSI pin pull-up/down control register 3 -#define PFC_PUD4 0xE6060450 // R/W 32 LSI pin pull-up/down control register 4 -#define PFC_PUD5 0xE6060454 // R/W 32 LSI pin pull-up/down control register 5 -#define PFC_PUD6 0xE6060458 // R/W 32 LSI pin pull-up/down control register 6 -#define PFC_MOD_SEL0 0xE6060500 // R/W 32 Module select register 0 -#define PFC_MOD_SEL1 0xE6060504 // R/W 32 Module select register 1 -#define PFC_MOD_SEL2 0xE6060508 // R/W 32 Module select register 2 - -#define PFC_IOCTRL30 0xE6060380 // R/W 32 MPOC control register 0 -#define PFC_IOCTRL31 0xE6060384 // R/W 32 MPOC control register 0 -#define PFC_IOCTRL32 0xE6060388 // R/W 32 MPOC control register 0 -#define PFC_IOCTRL40 0xE60603C0 // R/W 32 MPOC control register 0 - -//RPC -#define RPC_CMNCR 0xEE200000 // R/W -#define RPC_SSLDR 0xEE200004 // R/W -#define RPC_DRCR 0xEE20000C // R/W -#define RPC_DRCMR 0xEE200010 // R/W -#define RPC_DREAR 0xEE200014 // R/W -#define RPC_DROPR 0xEE200018 // R/W -#define RPC_DRENR 0xEE20001C // R/W -#define RPC_SMCR 0xEE200020 // R/W -#define RPC_SMCMR 0xEE200024 // R/W -#define RPC_SMADR 0xEE200028 // R/W -#define RPC_SMOPR 0xEE20002C // R/W -#define RPC_SMENR 0xEE200030 // R/W -#define RPC_SMRDR0 0xEE200038 // R -#define RPC_SMRDR1 0xEE20003C // R -#define RPC_SMWDR0 0xEE200040 // R/W -#define RPC_SMWDR1 0xEE200044 // R/W -#define RPC_CMNSR 0xEE200048 // R -#define RPC_DRDMCR 0xEE200058 // R/W -#define RPC_DRDRENR 0xEE20005C // R/W -#define RPC_SMDMCR 0xEE200060 // R/W -#define RPC_SMDRENR 0xEE200064 // R/W -#define RPC_PHYCNT 0xEE20007C // R/W -#define RPC_OFFSET1 0xEE200080 // -#define RPC_PHYINT 0xEE200088 // R/W -#define RPC_SEC_CONF 0xEE2000B8 // -#define RPC_WRBUF 0xEE208000 // W RPC Write buffer (Access size=4/8/16/32/64Byte) - -//RST -#define RST_MODEMR 0xE6160060 // R 32 Mode Monitor Register -#define RST_CA57RESCNT 0xE6160040 // R/W 32 CA57 Reset Control Register -#define RST_CA53RESCNT 0xE6160044 // R/W 32 CA53 Reset Control Register -#define RST_WDTRSTCR 0xE6160054 // R/W 32 Watchdog Timer Reset Control Register -#define RST_RSTOUTCR 0xE6160058 // R/W 32 PRESETOUT# Control Register -#define RST_SBAR 0xE6160010 // R/W 32 SYS Boot Address Register -#define RST_SBAR2 0xE6160014 // R/W 32 SYS Boot Address Register2 -#define RST_CA53BAR 0xE6160030 // R/W 32 CA53 Boot Address Register -#define RST_CA53BAR2 0xE6160034 // R/W 32 CA53 Boot Address Register2 -#define RST_CA57BAR 0xE6160020 // R/W 32 CA57 Boot Address Register -#define RST_CA57BAR2 0xE6160024 // R/W 32 CA57 Boot Address Register2 -#define RST_CR7BAR 0xE6160070 // R/W 32 CR7 Boot Address Register -#define RST_CR7BAR2 0xE6160074 // R/W 32 CR7 Boot Address Register2 -#define RST_CA57CPU0BARH 0xE61600C0 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode H -#define RST_CA57CPU0BARL 0xE61600C4 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode L -#define RST_CA57CPU1BARH 0xE61600D0 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode H -#define RST_CA57CPU1BARL 0xE61600D4 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode L -#define RST_CA57CPU2BARH 0xE61600E0 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode H -#define RST_CA57CPU2BARL 0xE61600E4 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode L -#define RST_CA57CPU3BARH 0xE61600F0 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode H -#define RST_CA57CPU3BARL 0xE61600F4 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode L -#define RST_CA53CPU0BARH 0xE6160080 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode H -#define RST_CA53CPU0BARL 0xE6160084 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode L -#define RST_CA53CPU1BARH 0xE6160090 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode H -#define RST_CA53CPU1BARL 0xE6160094 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode L -#define RST_CA53CPU2BARH 0xE61600A0 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode H -#define RST_CA53CPU2BARL 0xE61600A4 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode L -#define RST_CA53CPU3BARH 0xE61600B0 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode H -#define RST_CA53CPU3BARL 0xE61600B4 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode L -#define RST_APBSFTYCHKR 0xE616005C // R/W 32 APB bus Safety Check Register -#define RST_STBCHR0 0xE6160100 // R/W 32 Standby Flag Register 0 -#define RST_STBCHR1 0xE6160104 // R/W 32 Standby Flag Register 1 -#define RST_STBCHR2 0xE6160108 // R/W 32 Standby Flag Register 2 -#define RST_STBCHR3 0xE616010C // R/W 32 Standby Flag Register 3 -#define RST_STBCHR4 0xE6160120 // R/W 32 Standby Flag Register 4 -#define RST_STBCHR5 0xE6160124 // R/W 32 Standby Flag Register 5 -#define RST_STBCHR6 0xE6160128 // R/W 32 Standby Flag Register 6 -#define RST_STBCHR7 0xE616012C // R/W 32 Standby Flag Register 7 -#define RST_SRESCR 0xE6160110 // R/W 32 Soft Power On Reset Control Register -#define RST_RRSTFR 0xE6160114 // R/W 32 RT Reset Flag Register -#define RST_SRSTFR 0xE6160118 // R/W 32 SYS Reset Flag Register -#define RST_SCPTCSR 0xE6160180 // R/W 32 Secure Protect Control/Status Register -#define RST_SCERMIDR 0xE6160184 // R 32 Secure Error Master ID Register -#define RST_SCERADR 0xE6160188 // R 32 Secure Error Address Register -#define RST_SAPTCSR 0xE6160190 // R/W 32 Safety Protect Control/Status Register -#define RST_SAERMIDR 0xE6160194 // R 32 Safety Error Master ID Register -#define RST_SAERADR 0xE6160198 // R 32 Safety Error Address Register - -//RWDT -#define RWDT_RWTCNT 0xE6020000 // R/W 16/32* RCLK watchdog timer counter -#define RWDT_RWTCSRA 0xE6020004 // R/W 8/32* RCLK watchdog timer control/status register A -#define RWDT_RWTCSRB 0xE6020008 // R/W 8/32* RCLK watchdog timer control/status register B - -//SCIF2 -#define SCIF2_SCSMR 0xE6E88000 // R/W 16 Serial mode register -#define SCIF2_SCBRR 0xE6E88004 // R/W 8 Bit rate register -#define SCIF2_SCSCR 0xE6E88008 // R/W 16 Serial control register -#define SCIF2_SCFTDR 0xE6E8800C // W 8 Transmit FIFO data register -#define SCIF2_SCFSR 0xE6E88010 // R/W 16 Serial status register -#define SCIF2_SCFRDR 0xE6E88014 // R 8 Receive FIFO data register -#define SCIF2_SCFCR 0xE6E88018 // R/W 16 FIFO control register -#define SCIF2_SCFDR 0xE6E8801C // R 16 FIFO data count register -#define SCIF2_SCSPTR 0xE6E88020 // R/W 16 Serial port register -#define SCIF2_SCLSR 0xE6E88024 // R/W 16 Line status register -#define SCIF2_DL 0xE6E88030 // R/W 16 Frequency division register -#define SCIF2_CKS 0xE6E88034 // R/W 16 Clock Select register - -//SYSDMAC -#define SYSDMAC_DMAISTA_0 0xE6700020 // R 32 DMA interrupt status register (for channels 0 to 15) -#define SYSDMAC_DMASEC_0 0xE6700030 // R/W 32 DMA secure control register (for channels 0 to 15) -#define SYSDMAC_DMAOR_0 0xE6700060 // R/W 16 DMA operation register (for channels 0 to 15) -#define SYSDMAC_DMACHCLR_0 0xE6700080 // W 32 DMA channel clear register (for channels 0 to 15) -#define SYSDMAC_DMADPSEC_0 0xE67000A0 // R/W 32 DPRAM secure control register (for channels 0 to 15) -#define SYSDMAC_DMASAR_0 0xE6708000 // R/W 32 DMA source address register_0 -#define SYSDMAC_DMADAR_0 0xE6708004 // R/W 32 DMA destination address register_0 -#define SYSDMAC_DMATCR_0 0xE6708008 // R/W 32 DMA transfer count register_0 -#define SYSDMAC_DMATSR_0 0xE6708028 // R/W 32 DMA transfer size register_0 -#define SYSDMAC_DMACHCR_0 0xE670800C // R/W 32 DMA channel control register_0 -#define SYSDMAC_DMATCRB_0 0xE6708018 // R/W 32 DMA transfer count register B_0 -#define SYSDMAC_DMATSRB_0 0xE6708038 // R/W 32 DMA transfer size register B_0 -#define SYSDMAC_DMACHCRB_0 0xE670801C // R/W 32 DMA channel control register B_0 -#define SYSDMAC_DMARS_0 0xE6708040 // R/W 16 DMA extended resource selector_0 -#define SYSDMAC_DMABUFCR_0 0xE6708048 // R/W 32 DMA buffer control register_0 -#define SYSDMAC_DMADPBASE_0 0xE6708050 // R/W 32 DMA descriptor base address register_0 -#define SYSDMAC_DMADPCR_0 0xE6708054 // R/W 32 DMA descriptor control register_0 -#define SYSDMAC_DMAFIXSAR_0 0xE6708010 // R/W 32 DMA fixed source address register_0 -#define SYSDMAC_DMAFIXDAR_0 0xE6708014 // R/W 32 DMA fixed destination address register_0 -#define SYSDMAC_DMAFIXDPBASE_0 0xE6708060 // R/W 32 DMA fixed descriptor base address register_0 -#define SYSDMAC_DMASAR_1 0xE6708080 // R/W 32 DMA source address register_1 -#define SYSDMAC_DMADAR_1 0xE6708084 // R/W 32 DMA destination address register_1 -#define SYSDMAC_DMATCR_1 0xE6708088 // R/W 32 DMA transfer count register_1 -#define SYSDMAC_DMATSR_1 0xE67080A8 // R/W 32 DMA transfer size register_1 -#define SYSDMAC_DMACHCR_1 0xE670808C // R/W 32 DMA channel control register_1 -#define SYSDMAC_DMATCRB_1 0xE6708098 // R/W 32 DMA transfer count register B_1 -#define SYSDMAC_DMATSRB_1 0xE67080B8 // R/W 32 DMA transfer size register B_1 -#define SYSDMAC_DMACHCRB_1 0xE670809C // R/W 32 DMA channel control register B_1 -#define SYSDMAC_DMARS_1 0xE67080C0 // R/W 16 DMA extended resource selector_1 -#define SYSDMAC_DMABUFCR_1 0xE67080C8 // R/W 32 DMA buffer control register_1 -#define SYSDMAC_DMADPBASE_1 0xE67080D0 // R/W 32 DMA descriptor base address register_1 -#define SYSDMAC_DMADPCR_1 0xE67080D4 // R/W 32 DMA descriptor control register_1 -#define SYSDMAC_DMAFIXDPBASE_1 0xE67080E0 // R/W 32 DMA fixed descriptor base address register_1 -#define SYSDMAC_DMAFIXSAR_1 0xE6708090 // R/W 32 DMA fixed source address register_1 -#define SYSDMAC_DMAFIXDAR_1 0xE6708094 // R/W 32 DMA fixed destination address register_1 -#define SYSDMAC_DMASAR_2 0xE6708100 // R/W 32 DMA source address register_2 -#define SYSDMAC_DMADAR_2 0xE6708104 // R/W 32 DMA destination address register_2 -#define SYSDMAC_DMATCR_2 0xE6708108 // R/W 32 DMA transfer count register_2 -#define SYSDMAC_DMATSR_2 0xE6708128 // R/W 32 DMA transfer size register_2 -#define SYSDMAC_DMACHCR_2 0xE670810C // R/W 32 DMA channel control register_2 -#define SYSDMAC_DMATCRB_2 0xE6708118 // R/W 32 DMA transfer count register B_2 -#define SYSDMAC_DMATSRB_2 0xE6708138 // R/W 32 DMA transfer size register B_2 -#define SYSDMAC_DMACHCRB_2 0xE670811C // R/W 32 DMA channel control register B_2 -#define SYSDMAC_DMARS_2 0xE6708140 // R/W 16 DMA extended resource selector_2 -#define SYSDMAC_DMABUFCR_2 0xE6708148 // R/W 32 DMA buffer control register_2 -#define SYSDMAC_DMADPBASE_2 0xE6708150 // R/W 32 DMA descriptor base address register_2 -#define SYSDMAC_DMADPCR_2 0xE6708154 // R/W 32 DMA descriptor control register_2 -#define SYSDMAC_DMAFIXSAR_2 0xE6708110 // R/W 32 DMA fixed source address register_2 -#define SYSDMAC_DMAFIXDAR_2 0xE6708114 // R/W 32 DMA fixed destination address register_2 -#define SYSDMAC_DMAFIXDPBASE_2 0xE6708160 // R/W 32 DMA fixed descriptor base address register_2 -#define SYSDMAC_DMASAR_3 0xE6708180 // R/W 32 DMA source address register_3 -#define SYSDMAC_DMADAR_3 0xE6708184 // R/W 32 DMA destination address register_3 -#define SYSDMAC_DMATCR_3 0xE6708188 // R/W 32 DMA transfer count register_3 -#define SYSDMAC_DMATSR_3 0xE67081A8 // R/W 32 DMA transfer size register_3 -#define SYSDMAC_DMACHCR_3 0xE670818C // R/W 32 DMA channel control register_3 -#define SYSDMAC_DMATCRB_3 0xE6708198 // R/W 32 DMA transfer count register B_3 -#define SYSDMAC_DMATSRB_3 0xE67081B8 // R/W 32 DMA transfer size register B_3 -#define SYSDMAC_DMACHCRB_3 0xE670819C // R/W 32 DMA channel control register B_3 -#define SYSDMAC_DMARS_3 0xE67081C0 // R/W 16 DMA extended resource selector_3 -#define SYSDMAC_DMABUFCR_3 0xE67081C8 // R/W 32 DMA buffer control register_3 -#define SYSDMAC_DMADPBASE_3 0xE67081D0 // R/W 32 DMA descriptor base address register_3 -#define SYSDMAC_DMADPCR_3 0xE67081D4 // R/W 32 DMA descriptor control register_3 -#define SYSDMAC_DMAFIXSAR_3 0xE6708190 // R/W 32 DMA fixed source address register_3 -#define SYSDMAC_DMAFIXDAR_3 0xE6708194 // R/W 32 DMA fixed destination address register_3 -#define SYSDMAC_DMAFIXDPBASE_3 0xE67081E0 // R/W 32 DMA fixed descriptor base address register_3 -#define SYSDMAC_DMASAR_4 0xE6708200 // R/W 32 DMA source address register_4 -#define SYSDMAC_DMADAR_4 0xE6708204 // R/W 32 DMA destination address register_4 -#define SYSDMAC_DMATCR_4 0xE6708208 // R/W 32 DMA transfer count register_4 -#define SYSDMAC_DMATSR_4 0xE6708228 // R/W 32 DMA transfer size register_4 -#define SYSDMAC_DMACHCR_4 0xE670820C // R/W 32 DMA channel control register_4 -#define SYSDMAC_DMATCRB_4 0xE6708218 // R/W 32 DMA transfer count register B_4 -#define SYSDMAC_DMATSRB_4 0xE6708238 // R/W 32 DMA transfer size register B_4 -#define SYSDMAC_DMACHCRB_4 0xE670821C // R/W 32 DMA channel control register B_4 -#define SYSDMAC_DMARS_4 0xE6708240 // R/W 16 DMA extended resource selector_4 -#define SYSDMAC_DMABUFCR_4 0xE6708248 // R/W 32 DMA buffer control register_4 -#define SYSDMAC_DMADPBASE_4 0xE6708250 // R/W 32 DMA descriptor base address register_4 -#define SYSDMAC_DMADPCR_4 0xE6708254 // R/W 32 DMA descriptor control register_4 -#define SYSDMAC_DMAFIXSAR_4 0xE6708210 // R/W 32 DMA fixed source address register_4 -#define SYSDMAC_DMAFIXDAR_4 0xE6708214 // R/W 32 DMA fixed destination address register_4 -#define SYSDMAC_DMAFIXDPBASE_4 0xE6708260 // R/W 32 DMA fixed descriptor base address register_4 -#define SYSDMAC_DMASAR_5 0xE6708280 // R/W 32 DMA source address register_5 -#define SYSDMAC_DMADAR_5 0xE6708284 // R/W 32 DMA destination address register_5 -#define SYSDMAC_DMATCR_5 0xE6708288 // R/W 32 DMA transfer count register_5 -#define SYSDMAC_DMATSR_5 0xE67082A8 // R/W 32 DMA transfer size register_5 -#define SYSDMAC_DMACHCR_5 0xE670828C // R/W 32 DMA channel control register_5 -#define SYSDMAC_DMATCRB_5 0xE6708298 // R/W 32 DMA transfer count register B_5 -#define SYSDMAC_DMATSRB_5 0xE67082B8 // R/W 32 DMA transfer size register B_5 -#define SYSDMAC_DMACHCRB_5 0xE670829C // R/W 32 DMA channel control register B_5 -#define SYSDMAC_DMARS_5 0xE67082C0 // R/W 16 DMA extended resource selector_5 -#define SYSDMAC_DMABUFCR_5 0xE67082C8 // R/W 32 DMA buffer control register_5 -#define SYSDMAC_DMADPBASE_5 0xE67082D0 // R/W 32 DMA descriptor base address register_5 -#define SYSDMAC_DMADPCR_5 0xE67082D4 // R/W 32 DMA descriptor control register_5 -#define SYSDMAC_DMAFIXSAR_5 0xE6708290 // R/W 32 DMA fixed source address register_5 -#define SYSDMAC_DMAFIXDAR_5 0xE6708294 // R/W 32 DMA fixed destination address register_5 -#define SYSDMAC_DMAFIXDPBASE_5 0xE67082E0 // R/W 32 DMA fixed descriptor base address register_5 -#define SYSDMAC_DMASAR_6 0xE6708300 // R/W 32 DMA source address register_6 -#define SYSDMAC_DMADAR_6 0xE6708304 // R/W 32 DMA destination address register_6 -#define SYSDMAC_DMATCR_6 0xE6708308 // R/W 32 DMA transfer count register_6 -#define SYSDMAC_DMATSR_6 0xE6708328 // R/W 32 DMA transfer size register_6 -#define SYSDMAC_DMACHCR_6 0xE670830C // R/W 32 DMA channel control register_6 -#define SYSDMAC_DMATCRB_6 0xE6708318 // R/W 32 DMA transfer count register B_6 -#define SYSDMAC_DMATSRB_6 0xE6708338 // R/W 32 DMA transfer size register B_6 -#define SYSDMAC_DMACHCRB_6 0xE670831C // R/W 32 DMA channel control register B_6 -#define SYSDMAC_DMARS_6 0xE6708340 // R/W 16 DMA extended resource selector_6 -#define SYSDMAC_DMABUFCR_6 0xE6708348 // R/W 32 DMA buffer control register_6 -#define SYSDMAC_DMADPBASE_6 0xE6708350 // R/W 32 DMA descriptor base address register_6 -#define SYSDMAC_DMADPCR_6 0xE6708354 // R/W 32 DMA descriptor control register_6 -#define SYSDMAC_DMAFIXSAR_6 0xE6708310 // R/W 32 DMA fixed source address register_6 -#define SYSDMAC_DMAFIXDAR_6 0xE6708314 // R/W 32 DMA fixed destination address register_6 -#define SYSDMAC_DMAFIXDPBASE_6 0xE6708360 // R/W 32 DMA fixed descriptor base address register_6 -#define SYSDMAC_DMASAR_7 0xE6708380 // R/W 32 DMA source address register_7 -#define SYSDMAC_DMADAR_7 0xE6708384 // R/W 32 DMA destination address register_7 -#define SYSDMAC_DMATCR_7 0xE6708388 // R/W 32 DMA transfer count register_7 -#define SYSDMAC_DMATSR_7 0xE67083A8 // R/W 32 DMA transfer size register_7 -#define SYSDMAC_DMACHCR_7 0xE670838C // R/W 32 DMA channel control register_7 -#define SYSDMAC_DMATCRB_7 0xE6708398 // R/W 32 DMA transfer count register B_7 -#define SYSDMAC_DMATSRB_7 0xE67083B8 // R/W 32 DMA transfer size register B_7 -#define SYSDMAC_DMACHCRB_7 0xE670839C // R/W 32 DMA channel control register B_7 -#define SYSDMAC_DMARS_7 0xE67083C0 // R/W 16 DMA extended resource selector_7 -#define SYSDMAC_DMABUFCR_7 0xE67083C8 // R/W 32 DMA buffer control register_7 -#define SYSDMAC_DMADPBASE_7 0xE67083D0 // R/W 32 DMA descriptor base address register_7 -#define SYSDMAC_DMADPCR_7 0xE67083D4 // R/W 32 DMA descriptor control register_7 -#define SYSDMAC_DMAFIXSAR_7 0xE6708390 // R/W 32 DMA fixed source address register_7 -#define SYSDMAC_DMAFIXDAR_7 0xE6708394 // R/W 32 DMA fixed destination address register_7 -#define SYSDMAC_DMAFIXDPBASE_7 0xE67083E0 // R/W 32 DMA fixed descriptor base address register_7 -#define SYSDMAC_DMASAR_8 0xE6708400 // R/W 32 DMA source address register_8 -#define SYSDMAC_DMADAR_8 0xE6708404 // R/W 32 DMA destination address register_8 -#define SYSDMAC_DMATCR_8 0xE6708408 // R/W 32 DMA transfer count register_8 -#define SYSDMAC_DMATSR_8 0xE6708428 // R/W 32 DMA transfer size register_8 -#define SYSDMAC_DMACHCR_8 0xE670840C // R/W 32 DMA channel control register_8 -#define SYSDMAC_DMATCRB_8 0xE6708418 // R/W 32 DMA transfer count register B_8 -#define SYSDMAC_DMATSRB_8 0xE6708438 // R/W 32 DMA transfer size register B_8 -#define SYSDMAC_DMACHCRB_8 0xE670841C // R/W 32 DMA channel control register B_8 -#define SYSDMAC_DMARS_8 0xE6708440 // R/W 16 DMA extended resource selector_8 -#define SYSDMAC_DMABUFCR_8 0xE6708448 // R/W 32 DMA buffer control register_8 -#define SYSDMAC_DMADPBASE_8 0xE6708450 // R/W 32 DMA descriptor base address register_8 -#define SYSDMAC_DMADPCR_8 0xE6708454 // R/W 32 DMA descriptor control register_8 -#define SYSDMAC_DMAFIXSAR_8 0xE6708410 // R/W 32 DMA fixed source address register_8 -#define SYSDMAC_DMAFIXDAR_8 0xE6708414 // R/W 32 DMA fixed destination address register_8 -#define SYSDMAC_DMAFIXDPBASE_8 0xE6708460 // R/W 32 DMA fixed descriptor base address register_8 -#define SYSDMAC_DMASAR_9 0xE6708480 // R/W 32 DMA source address register_9 -#define SYSDMAC_DMADAR_9 0xE6708484 // R/W 32 DMA destination address register_9 -#define SYSDMAC_DMATCR_9 0xE6708488 // R/W 32 DMA transfer count register_9 -#define SYSDMAC_DMATSR_9 0xE67084A8 // R/W 32 DMA transfer size register_9 -#define SYSDMAC_DMACHCR_9 0xE670848C // R/W 32 DMA channel control register_9 -#define SYSDMAC_DMATCRB_9 0xE6708498 // R/W 32 DMA transfer count register B_9 -#define SYSDMAC_DMATSRB_9 0xE67084B8 // R/W 32 DMA transfer size register B_9 -#define SYSDMAC_DMACHCRB_9 0xE670849C // R/W 32 DMA channel control register B_9 -#define SYSDMAC_DMARS_9 0xE67084C0 // R/W 16 DMA extended resource selector_9 -#define SYSDMAC_DMABUFCR_9 0xE67084C8 // R/W 32 DMA buffer control register_9 -#define SYSDMAC_DMADPBASE_9 0xE67084D0 // R/W 32 DMA descriptor base address register_9 -#define SYSDMAC_DMADPCR_9 0xE67084D4 // R/W 32 DMA descriptor control register_9 -#define SYSDMAC_DMAFIXSAR_9 0xE6708490 // R/W 32 DMA fixed source address register_9 -#define SYSDMAC_DMAFIXDAR_9 0xE6708494 // R/W 32 DMA fixed destination address register_9 -#define SYSDMAC_DMAFIXDPBASE_9 0xE67084E0 // R/W 32 DMA fixed descriptor base address register_9 -#define SYSDMAC_DMASAR_10 0xE6708500 // R/W 32 DMA source address register_10 -#define SYSDMAC_DMADAR_10 0xE6708504 // R/W 32 DMA destination address register_10 -#define SYSDMAC_DMATCR_10 0xE6708508 // R/W 32 DMA transfer count register_10 -#define SYSDMAC_DMATSR_10 0xE6708528 // R/W 32 DMA transfer size register_10 -#define SYSDMAC_DMACHCR_10 0xE670850C // R/W 32 DMA channel control register_10 -#define SYSDMAC_DMATCRB_10 0xE6708518 // R/W 32 DMA transfer count register B_10 -#define SYSDMAC_DMATSRB_10 0xE6708538 // R/W 32 DMA transfer size register B_10 -#define SYSDMAC_DMACHCRB_10 0xE670851C // R/W 32 DMA channel control register B_10 -#define SYSDMAC_DMARS_10 0xE6708540 // R/W 16 DMA extended resource selector_10 -#define SYSDMAC_DMABUFCR_10 0xE6708548 // R/W 32 DMA buffer control register_10 -#define SYSDMAC_DMADPBASE_10 0xE6708550 // R/W 32 DMA descriptor base address register_10 -#define SYSDMAC_DMADPCR_10 0xE6708554 // R/W 32 DMA descriptor control register_10 -#define SYSDMAC_DMAFIXSAR_10 0xE6708510 // R/W 32 DMA fixed source address register_10 -#define SYSDMAC_DMAFIXDAR_10 0xE6708514 // R/W 32 DMA fixed destination address register_10 -#define SYSDMAC_DMAFIXDPBASE_10 0xE6708560 // R/W 32 DMA fixed descriptor base address register_10 -#define SYSDMAC_DMASAR_11 0xE6708580 // R/W 32 DMA source address register_11 -#define SYSDMAC_DMADAR_11 0xE6708584 // R/W 32 DMA destination address register_11 -#define SYSDMAC_DMATCR_11 0xE6708588 // R/W 32 DMA transfer count register_11 -#define SYSDMAC_DMATSR_11 0xE67085A8 // R/W 32 DMA transfer size register_11 -#define SYSDMAC_DMACHCR_11 0xE670858C // R/W 32 DMA channel control register_11 -#define SYSDMAC_DMATCRB_11 0xE6708598 // R/W 32 DMA transfer count register B_11 -#define SYSDMAC_DMATSRB_11 0xE67085B8 // R/W 32 DMA transfer size register B_11 -#define SYSDMAC_DMACHCRB_11 0xE670859C // R/W 32 DMA channel control register B_11 -#define SYSDMAC_DMARS_11 0xE67085C0 // R/W 16 DMA extended resource selector_11 -#define SYSDMAC_DMABUFCR_11 0xE67085C8 // R/W 32 DMA buffer control register_11 -#define SYSDMAC_DMADPBASE_11 0xE67085D0 // R/W 32 DMA descriptor base address register_11 -#define SYSDMAC_DMADPCR_11 0xE67085D4 // R/W 32 DMA descriptor control register_11 -#define SYSDMAC_DMAFIXSAR_11 0xE6708590 // R/W 32 DMA fixed source address register_11 -#define SYSDMAC_DMAFIXDAR_11 0xE6708594 // R/W 32 DMA fixed destination address register_11 -#define SYSDMAC_DMAFIXDPBASE_11 0xE67085E0 // R/W 32 DMA fixed descriptor base address register_11 -#define SYSDMAC_DMASAR_12 0xE6708600 // R/W 32 DMA source address register_12 -#define SYSDMAC_DMADAR_12 0xE6708604 // R/W 32 DMA destination address register_12 -#define SYSDMAC_DMATCR_12 0xE6708608 // R/W 32 DMA transfer count register_12 -#define SYSDMAC_DMATSR_12 0xE6708628 // R/W 32 DMA transfer size register_12 -#define SYSDMAC_DMACHCR_12 0xE670860C // R/W 32 DMA channel control register_12 -#define SYSDMAC_DMATCRB_12 0xE6708618 // R/W 32 DMA transfer count register B_12 -#define SYSDMAC_DMATSRB_12 0xE6708638 // R/W 32 DMA transfer size register B_12 -#define SYSDMAC_DMACHCRB_12 0xE670861C // R/W 32 DMA channel control register B_12 -#define SYSDMAC_DMARS_12 0xE6708640 // R/W 16 DMA extended resource selector_12 -#define SYSDMAC_DMABUFCR_12 0xE6708648 // R/W 32 DMA buffer control register_12 -#define SYSDMAC_DMADPBASE_12 0xE6708650 // R/W 32 DMA descriptor base address register_12 -#define SYSDMAC_DMADPCR_12 0xE6708654 // R/W 32 DMA descriptor control register_12 -#define SYSDMAC_DMAFIXSAR_12 0xE6708610 // R/W 32 DMA fixed source address register_12 -#define SYSDMAC_DMAFIXDAR_12 0xE6708614 // R/W 32 DMA fixed destination address register_12 -#define SYSDMAC_DMAFIXDPBASE_12 0xE6708660 // R/W 32 DMA fixed descriptor base address register_12 -#define SYSDMAC_DMASAR_13 0xE6708680 // R/W 32 DMA source address register_13 -#define SYSDMAC_DMADAR_13 0xE6708684 // R/W 32 DMA destination address register_13 -#define SYSDMAC_DMATCR_13 0xE6708688 // R/W 32 DMA transfer count register_13 -#define SYSDMAC_DMATSR_13 0xE67086A8 // R/W 32 DMA transfer size register_13 -#define SYSDMAC_DMACHCR_13 0xE670868C // R/W 32 DMA channel control register_13 -#define SYSDMAC_DMATCRB_13 0xE6708698 // R/W 32 DMA transfer count register B_13 -#define SYSDMAC_DMATSRB_13 0xE67086B8 // R/W 32 DMA transfer size register B_13 -#define SYSDMAC_DMACHCRB_13 0xE670869C // R/W 32 DMA channel control register B_13 -#define SYSDMAC_DMARS_13 0xE67086C0 // R/W 16 DMA extended resource selector_13 -#define SYSDMAC_DMABUFCR_13 0xE67086C8 // R/W 32 DMA buffer control register_13 -#define SYSDMAC_DMADPBASE_13 0xE67086D0 // R/W 32 DMA descriptor base address register_13 -#define SYSDMAC_DMADPCR_13 0xE67086D4 // R/W 32 DMA descriptor control register_13 -#define SYSDMAC_DMAFIXSAR_13 0xE6708690 // R/W 32 DMA fixed source address register_13 -#define SYSDMAC_DMAFIXDAR_13 0xE6708694 // R/W 32 DMA fixed destination address register_13 -#define SYSDMAC_DMAFIXDPBASE_13 0xE67086E0 // R/W 32 DMA fixed descriptor base address register_13 -#define SYSDMAC_DMASAR_14 0xE6708700 // R/W 32 DMA source address register_14 -#define SYSDMAC_DMADAR_14 0xE6708704 // R/W 32 DMA destination address register_14 -#define SYSDMAC_DMATCR_14 0xE6708708 // R/W 32 DMA transfer count register_14 -#define SYSDMAC_DMATSR_14 0xE6708728 // R/W 32 DMA transfer size register_14 -#define SYSDMAC_DMACHCR_14 0xE670870C // R/W 32 DMA channel control register_14 -#define SYSDMAC_DMATCRB_14 0xE6708718 // R/W 32 DMA transfer count register B_14 -#define SYSDMAC_DMATSRB_14 0xE6708738 // R/W 32 DMA transfer size register B_14 -#define SYSDMAC_DMACHCRB_14 0xE670871C // R/W 32 DMA channel control register B_14 -#define SYSDMAC_DMARS_14 0xE6708740 // R/W 16 DMA extended resource selector_14 -#define SYSDMAC_DMABUFCR_14 0xE6708748 // R/W 32 DMA buffer control register_14 -#define SYSDMAC_DMADPBASE_14 0xE6708750 // R/W 32 DMA descriptor base address register_14 -#define SYSDMAC_DMADPCR_14 0xE6708754 // R/W 32 DMA descriptor control register_14 -#define SYSDMAC_DMAFIXSAR_14 0xE6708710 // R/W 32 DMA fixed source address register_14 -#define SYSDMAC_DMAFIXDAR_14 0xE6708714 // R/W 32 DMA fixed destination address register_14 -#define SYSDMAC_DMAFIXDPBASE_14 0xE6708760 // R/W 32 DMA fixed descriptor base address register_14 -#define SYSDMAC_DMASAR_15 0xE6708780 // R/W 32 DMA source address register_15 -#define SYSDMAC_DMADAR_15 0xE6708784 // R/W 32 DMA destination address register_15 -#define SYSDMAC_DMATCR_15 0xE6708788 // R/W 32 DMA transfer count register_15 -#define SYSDMAC_DMATSR_15 0xE67087A8 // R/W 32 DMA transfer size register_15 -#define SYSDMAC_DMACHCR_15 0xE670878C // R/W 32 DMA channel control register_15 -#define SYSDMAC_DMATCRB_15 0xE6708798 // R/W 32 DMA transfer count register B_15 -#define SYSDMAC_DMATSRB_15 0xE67087B8 // R/W 32 DMA transfer size register B_15 -#define SYSDMAC_DMACHCRB_15 0xE670879C // R/W 32 DMA channel control register B_15 -#define SYSDMAC_DMARS_15 0xE67087C0 // R/W 16 DMA extended resource selector_15 -#define SYSDMAC_DMABUFCR_15 0xE67087C8 // R/W 32 DMA buffer control register_15 -#define SYSDMAC_DMADPBASE_15 0xE67087D0 // R/W 32 DMA descriptor base address register_15 -#define SYSDMAC_DMADPCR_15 0xE67087D4 // R/W 32 DMA descriptor control register_15 -#define SYSDMAC_DMAFIXSAR_15 0xE6708790 // R/W 32 DMA fixed source address register_15 -#define SYSDMAC_DMAFIXDAR_15 0xE6708794 // R/W 32 DMA fixed destination address register_15 -#define SYSDMAC_DMAFIXDPBASE_15 0xE67087E0 // R/W 32 DMA fixed descriptor base address register_15 -#define SYSDMAC_DescriptorMEM_0_15 0xE670A000 // R/W 32 Descriptor memory (for channels 0 to 15) -#define SYSDMAC_DMASES_0 0xE67000C0 // R/W 32 Secure function Secure Status register (for channels 0 to 15) -#define SYSDMAC_DMASEA_0 0xE67000C4 // R/W 32 Secure function Slave Error Address register (for channels 0 to 15) -#define SYSDMAC_DMAEMID_0 0xE67000C8 // R/W 32 Secure function Error Master ID register (for channels 0 to 15) -#define SYSDMAC_DMAISTA_1 0xE7300020 // R 32 DMA interrupt status register (for channels 16 to 31) -#define SYSDMAC_DMASEC_1 0xE7300030 // R/W 32 DMA secure control register (for channels 16 to 31) -#define SYSDMAC_DMAOR_1 0xE7300060 // R/W 16 DMA operation register (for channels 16 to 31) -#define SYSDMAC_DMACHCLR_1 0xE7300080 // W 32 DMA channel clear register (for channels 16 to 31) -#define SYSDMAC_DMADPSEC_1 0xE73000A0 // R/W 32 DPRAM secure control register (for channels 16 to 31) -#define SYSDMAC_DMASAR_16 0xE7308000 // R/W 32 DMA source address register_16 -#define SYSDMAC_DMADAR_16 0xE7308004 // R/W 32 DMA destination address register_16 -#define SYSDMAC_DMATCR_16 0xE7308008 // R/W 32 DMA transfer count register_16 -#define SYSDMAC_DMATSR_16 0xE7308028 // R/W 32 DMA transfer size register_16 -#define SYSDMAC_DMACHCR_16 0xE730800C // R/W 32 DMA channel control register_16 -#define SYSDMAC_DMATCRB_16 0xE7308018 // R/W 32 DMA transfer count register B_16 -#define SYSDMAC_DMATSRB_16 0xE7308038 // R/W 32 DMA transfer size register B_16 -#define SYSDMAC_DMACHCRB_16 0xE730801C // R/W 32 DMA channel control register B_16 -#define SYSDMAC_DMARS_16 0xE7308040 // R/W 16 DMA extended resource selector_16 -#define SYSDMAC_DMABUFCR_16 0xE7308048 // R/W 32 DMA buffer control register_16 -#define SYSDMAC_DMADPBASE_16 0xE7308050 // R/W 32 DMA descriptor base address register_16 -#define SYSDMAC_DMADPCR_16 0xE7308054 // R/W 32 DMA descriptor control register_16 -#define SYSDMAC_DMAFIXSAR_16 0xE7308010 // R/W 32 DMA fixed source address register_16 -#define SYSDMAC_DMAFIXDAR_16 0xE7308014 // R/W 32 DMA fixed destination address register_16 -#define SYSDMAC_DMAFIXDPBASE_16 0xE7308060 // R/W 32 DMA fixed descriptor base address register_16 -#define SYSDMAC_DMASAR_17 0xE7308080 // R/W 32 DMA source address register_17 -#define SYSDMAC_DMADAR_17 0xE7308084 // R/W 32 DMA destination address register_17 -#define SYSDMAC_DMATCR_17 0xE7308088 // R/W 32 DMA transfer count register_17 -#define SYSDMAC_DMATSR_17 0xE73080A8 // R/W 32 DMA transfer size register_17 -#define SYSDMAC_DMACHCR_17 0xE730808C // R/W 32 DMA channel control register_17 -#define SYSDMAC_DMATCRB_17 0xE7308098 // R/W 32 DMA transfer count register B_17 -#define SYSDMAC_DMATSRB_17 0xE73080B8 // R/W 32 DMA transfer size register B_17 -#define SYSDMAC_DMACHCRB_17 0xE730809C // R/W 32 DMA channel control register B_17 -#define SYSDMAC_DMARS_17 0xE73080C0 // R/W 16 DMA extended resource selector_17 -#define SYSDMAC_DMABUFCR_17 0xE73080C8 // R/W 32 DMA buffer control register_17 -#define SYSDMAC_DMADPBASE_17 0xE73080D0 // R/W 32 DMA descriptor base address register_17 -#define SYSDMAC_DMADPCR_17 0xE73080D4 // R/W 32 DMA descriptor control register_17 -#define SYSDMAC_DMAFIXDPBASE_17 0xE73080E0 // R/W 32 DMA fixed descriptor base address register_17 -#define SYSDMAC_DMAFIXSAR_17 0xE7308090 // R/W 32 DMA fixed source address register_17 -#define SYSDMAC_DMAFIXDAR_17 0xE7308094 // R/W 32 DMA fixed destination address register_17 -#define SYSDMAC_DMASAR_18 0xE7308100 // R/W 32 DMA source address register_18 -#define SYSDMAC_DMADAR_18 0xE7308104 // R/W 32 DMA destination address register_18 -#define SYSDMAC_DMATCR_18 0xE7308108 // R/W 32 DMA transfer count register_18 -#define SYSDMAC_DMATSR_18 0xE7308128 // R/W 32 DMA transfer size register_18 -#define SYSDMAC_DMACHCR_18 0xE730810C // R/W 32 DMA channel control register_18 -#define SYSDMAC_DMATCRB_18 0xE7308118 // R/W 32 DMA transfer count register B_18 -#define SYSDMAC_DMATSRB_18 0xE7308138 // R/W 32 DMA transfer size register B_18 -#define SYSDMAC_DMACHCRB_18 0xE730811C // R/W 32 DMA channel control register B_18 -#define SYSDMAC_DMARS_18 0xE7308140 // R/W 16 DMA extended resource selector_18 -#define SYSDMAC_DMABUFCR_18 0xE7308148 // R/W 32 DMA buffer control register_18 -#define SYSDMAC_DMADPBASE_18 0xE7308150 // R/W 32 DMA descriptor base address register_18 -#define SYSDMAC_DMADPCR_18 0xE7308154 // R/W 32 DMA descriptor control register_18 -#define SYSDMAC_DMAFIXSAR_18 0xE7308110 // R/W 32 DMA fixed source address register_18 -#define SYSDMAC_DMAFIXDAR_18 0xE7308114 // R/W 32 DMA fixed destination address register_18 -#define SYSDMAC_DMAFIXDPBASE_18 0xE7308160 // R/W 32 DMA fixed descriptor base address register_18 -#define SYSDMAC_DMASAR_19 0xE7308180 // R/W 32 DMA source address register_19 -#define SYSDMAC_DMADAR_19 0xE7308184 // R/W 32 DMA destination address register_19 -#define SYSDMAC_DMATCR_19 0xE7308188 // R/W 32 DMA transfer count register_19 -#define SYSDMAC_DMATSR_19 0xE73081A8 // R/W 32 DMA transfer size register_19 -#define SYSDMAC_DMACHCR_19 0xE730818C // R/W 32 DMA channel control register_19 -#define SYSDMAC_DMATCRB_19 0xE7308198 // R/W 32 DMA transfer count register B_19 -#define SYSDMAC_DMATSRB_19 0xE73081B8 // R/W 32 DMA transfer size register B_19 -#define SYSDMAC_DMACHCRB_19 0xE730819C // R/W 32 DMA channel control register B_19 -#define SYSDMAC_DMARS_19 0xE73081C0 // R/W 16 DMA extended resource selector_19 -#define SYSDMAC_DMABUFCR_19 0xE73081C8 // R/W 32 DMA buffer control register_19 -#define SYSDMAC_DMADPBASE_19 0xE73081D0 // R/W 32 DMA descriptor base address register_19 -#define SYSDMAC_DMADPCR_19 0xE73081D4 // R/W 32 DMA descriptor control register_19 -#define SYSDMAC_DMAFIXSAR_19 0xE7308190 // R/W 32 DMA fixed source address register_19 -#define SYSDMAC_DMAFIXDAR_19 0xE7308194 // R/W 32 DMA fixed destination address register_19 -#define SYSDMAC_DMAFIXDPBASE_19 0xE73081E0 // R/W 32 DMA fixed descriptor base address register_19 -#define SYSDMAC_DMASAR_20 0xE7308200 // R/W 32 DMA source address register_20 -#define SYSDMAC_DMADAR_20 0xE7308204 // R/W 32 DMA destination address register_20 -#define SYSDMAC_DMATCR_20 0xE7308208 // R/W 32 DMA transfer count register_20 -#define SYSDMAC_DMATSR_20 0xE7308228 // R/W 32 DMA transfer size register_20 -#define SYSDMAC_DMACHCR_20 0xE730820C // R/W 32 DMA channel control register_20 -#define SYSDMAC_DMATCRB_20 0xE7308218 // R/W 32 DMA transfer count register B_20 -#define SYSDMAC_DMATSRB_20 0xE7308238 // R/W 32 DMA transfer size register B_20 -#define SYSDMAC_DMACHCRB_20 0xE730821C // R/W 32 DMA channel control register B_20 -#define SYSDMAC_DMARS_20 0xE7308240 // R/W 16 DMA extended resource selector_20 -#define SYSDMAC_DMABUFCR_20 0xE7308248 // R/W 32 DMA buffer control register_20 -#define SYSDMAC_DMADPBASE_20 0xE7308250 // R/W 32 DMA descriptor base address register_20 -#define SYSDMAC_DMADPCR_20 0xE7308254 // R/W 32 DMA descriptor control register_20 -#define SYSDMAC_DMAFIXSAR_20 0xE7308210 // R/W 32 DMA fixed source address register_20 -#define SYSDMAC_DMAFIXDAR_20 0xE7308214 // R/W 32 DMA fixed destination address register_20 -#define SYSDMAC_DMAFIXDPBASE_20 0xE7308260 // R/W 32 DMA fixed descriptor base address register_20 -#define SYSDMAC_DMASAR_21 0xE7308280 // R/W 32 DMA source address register_21 -#define SYSDMAC_DMADAR_21 0xE7308284 // R/W 32 DMA destination address register_21 -#define SYSDMAC_DMATCR_21 0xE7308288 // R/W 32 DMA transfer count register_21 -#define SYSDMAC_DMATSR_21 0xE73082A8 // R/W 32 DMA transfer size register_21 -#define SYSDMAC_DMACHCR_21 0xE730828C // R/W 32 DMA channel control register_21 -#define SYSDMAC_DMATCRB_21 0xE7308298 // R/W 32 DMA transfer count register B_21 -#define SYSDMAC_DMATSRB_21 0xE73082B8 // R/W 32 DMA transfer size register B_21 -#define SYSDMAC_DMACHCRB_21 0xE730829C // R/W 32 DMA channel control register B_21 -#define SYSDMAC_DMARS_21 0xE73082C0 // R/W 16 DMA extended resource selector_21 -#define SYSDMAC_DMABUFCR_21 0xE73082C8 // R/W 32 DMA buffer control register_21 -#define SYSDMAC_DMADPBASE_21 0xE73082D0 // R/W 32 DMA descriptor base address register_21 -#define SYSDMAC_DMADPCR_21 0xE73082D4 // R/W 32 DMA descriptor control register_21 -#define SYSDMAC_DMAFIXSAR_21 0xE7308290 // R/W 32 DMA fixed source address register_21 -#define SYSDMAC_DMAFIXDAR_21 0xE7308294 // R/W 32 DMA fixed destination address register_21 -#define SYSDMAC_DMAFIXDPBASE_21 0xE73082E0 // R/W 32 DMA fixed descriptor base address register_21 -#define SYSDMAC_DMASAR_22 0xE7308300 // R/W 32 DMA source address register_22 -#define SYSDMAC_DMADAR_22 0xE7308304 // R/W 32 DMA destination address register_22 -#define SYSDMAC_DMATCR_22 0xE7308308 // R/W 32 DMA transfer count register_22 -#define SYSDMAC_DMATSR_22 0xE7308328 // R/W 32 DMA transfer size register_22 -#define SYSDMAC_DMACHCR_22 0xE730830C // R/W 32 DMA channel control register_22 -#define SYSDMAC_DMATCRB_22 0xE7308318 // R/W 32 DMA transfer count register B_22 -#define SYSDMAC_DMATSRB_22 0xE7308338 // R/W 32 DMA transfer size register B_22 -#define SYSDMAC_DMACHCRB_22 0xE730831C // R/W 32 DMA channel control register B_22 -#define SYSDMAC_DMARS_22 0xE7308340 // R/W 16 DMA extended resource selector_22 -#define SYSDMAC_DMABUFCR_22 0xE7308348 // R/W 32 DMA buffer control register_22 -#define SYSDMAC_DMADPBASE_22 0xE7308350 // R/W 32 DMA descriptor base address register_22 -#define SYSDMAC_DMADPCR_22 0xE7308354 // R/W 32 DMA descriptor control register_22 -#define SYSDMAC_DMAFIXSAR_22 0xE7308310 // R/W 32 DMA fixed source address register_22 -#define SYSDMAC_DMAFIXDAR_22 0xE7308314 // R/W 32 DMA fixed destination address register_22 -#define SYSDMAC_DMAFIXDPBASE_22 0xE7308360 // R/W 32 DMA fixed descriptor base address register_22 -#define SYSDMAC_DMASAR_23 0xE7308380 // R/W 32 DMA source address register_23 -#define SYSDMAC_DMADAR_23 0xE7308384 // R/W 32 DMA destination address register_23 -#define SYSDMAC_DMATCR_23 0xE7308388 // R/W 32 DMA transfer count register_23 -#define SYSDMAC_DMATSR_23 0xE73083A8 // R/W 32 DMA transfer size register_23 -#define SYSDMAC_DMACHCR_23 0xE730838C // R/W 32 DMA channel control register_23 -#define SYSDMAC_DMATCRB_23 0xE7308398 // R/W 32 DMA transfer count register B_23 -#define SYSDMAC_DMATSRB_23 0xE73083B8 // R/W 32 DMA transfer size register B_23 -#define SYSDMAC_DMACHCRB_23 0xE730839C // R/W 32 DMA channel control register B_23 -#define SYSDMAC_DMARS_23 0xE73083C0 // R/W 16 DMA extended resource selector_23 -#define SYSDMAC_DMABUFCR_23 0xE73083C8 // R/W 32 DMA buffer control register_23 -#define SYSDMAC_DMADPBASE_23 0xE73083D0 // R/W 32 DMA descriptor base address register_23 -#define SYSDMAC_DMADPCR_23 0xE73083D4 // R/W 32 DMA descriptor control register_23 -#define SYSDMAC_DMAFIXSAR_23 0xE7308390 // R/W 32 DMA fixed source address register_23 -#define SYSDMAC_DMAFIXDAR_23 0xE7308394 // R/W 32 DMA fixed destination address register_23 -#define SYSDMAC_DMAFIXDPBASE_23 0xE73083E0 // R/W 32 DMA fixed descriptor base address register_23 -#define SYSDMAC_DMASAR_24 0xE7308400 // R/W 32 DMA source address register_24 -#define SYSDMAC_DMADAR_24 0xE7308404 // R/W 32 DMA destination address register_24 -#define SYSDMAC_DMATCR_24 0xE7308408 // R/W 32 DMA transfer count register_24 -#define SYSDMAC_DMATSR_24 0xE7308428 // R/W 32 DMA transfer size register_24 -#define SYSDMAC_DMACHCR_24 0xE730840C // R/W 32 DMA channel control register_24 -#define SYSDMAC_DMATCRB_24 0xE7308418 // R/W 32 DMA transfer count register B_24 -#define SYSDMAC_DMATSRB_24 0xE7308438 // R/W 32 DMA transfer size register B_24 -#define SYSDMAC_DMACHCRB_24 0xE730841C // R/W 32 DMA channel control register B_24 -#define SYSDMAC_DMARS_24 0xE7308440 // R/W 16 DMA extended resource selector_24 -#define SYSDMAC_DMABUFCR_24 0xE7308448 // R/W 32 DMA buffer control register_24 -#define SYSDMAC_DMADPBASE_24 0xE7308450 // R/W 32 DMA descriptor base address register_24 -#define SYSDMAC_DMADPCR_24 0xE7308454 // R/W 32 DMA descriptor control register_24 -#define SYSDMAC_DMAFIXSAR_24 0xE7308410 // R/W 32 DMA fixed source address register_24 -#define SYSDMAC_DMAFIXDAR_24 0xE7308414 // R/W 32 DMA fixed destination address register_24 -#define SYSDMAC_DMAFIXDPBASE_24 0xE7308460 // R/W 32 DMA fixed descriptor base address register_24 -#define SYSDMAC_DMASAR_25 0xE7308480 // R/W 32 DMA source address register_25 -#define SYSDMAC_DMADAR_25 0xE7308484 // R/W 32 DMA destination address register_25 -#define SYSDMAC_DMATCR_25 0xE7308488 // R/W 32 DMA transfer count register_25 -#define SYSDMAC_DMATSR_25 0xE73084A8 // R/W 32 DMA transfer size register_25 -#define SYSDMAC_DMACHCR_25 0xE730848C // R/W 32 DMA channel control register_25 -#define SYSDMAC_DMATCRB_25 0xE7308498 // R/W 32 DMA transfer count register B_25 -#define SYSDMAC_DMATSRB_25 0xE73084B8 // R/W 32 DMA transfer size register B_25 -#define SYSDMAC_DMACHCRB_25 0xE730849C // R/W 32 DMA channel control register B_25 -#define SYSDMAC_DMARS_25 0xE73084C0 // R/W 16 DMA extended resource selector_25 -#define SYSDMAC_DMABUFCR_25 0xE73084C8 // R/W 32 DMA buffer control register_25 -#define SYSDMAC_DMADPBASE_25 0xE73084D0 // R/W 32 DMA descriptor base address register_25 -#define SYSDMAC_DMADPCR_25 0xE73084D4 // R/W 32 DMA descriptor control register_25 -#define SYSDMAC_DMAFIXSAR_25 0xE7308490 // R/W 32 DMA fixed source address register_25 -#define SYSDMAC_DMAFIXDAR_25 0xE7308494 // R/W 32 DMA fixed destination address register_25 -#define SYSDMAC_DMAFIXDPBASE_25 0xE73084E0 // R/W 32 DMA fixed descriptor base address register_25 -#define SYSDMAC_DMASAR_26 0xE7308500 // R/W 32 DMA source address register_26 -#define SYSDMAC_DMADAR_26 0xE7308504 // R/W 32 DMA destination address register_26 -#define SYSDMAC_DMATCR_26 0xE7308508 // R/W 32 DMA transfer count register_26 -#define SYSDMAC_DMATSR_26 0xE7308528 // R/W 32 DMA transfer size register_26 -#define SYSDMAC_DMACHCR_26 0xE730850C // R/W 32 DMA channel control register_26 -#define SYSDMAC_DMATCRB_26 0xE7308518 // R/W 32 DMA transfer count register B_26 -#define SYSDMAC_DMATSRB_26 0xE7308538 // R/W 32 DMA transfer size register B_26 -#define SYSDMAC_DMACHCRB_26 0xE730851C // R/W 32 DMA channel control register B_26 -#define SYSDMAC_DMARS_26 0xE7308540 // R/W 16 DMA extended resource selector_26 -#define SYSDMAC_DMABUFCR_26 0xE7308548 // R/W 32 DMA buffer control register_26 -#define SYSDMAC_DMADPBASE_26 0xE7308550 // R/W 32 DMA descriptor base address register_26 -#define SYSDMAC_DMADPCR_26 0xE7308554 // R/W 32 DMA descriptor control register_26 -#define SYSDMAC_DMAFIXSAR_26 0xE7308510 // R/W 32 DMA fixed source address register_26 -#define SYSDMAC_DMAFIXDAR_26 0xE7308514 // R/W 32 DMA fixed destination address register_26 -#define SYSDMAC_DMAFIXDPBASE_26 0xE7308560 // R/W 32 DMA fixed descriptor base address register_26 -#define SYSDMAC_DMASAR_27 0xE7308580 // R/W 32 DMA source address register_27 -#define SYSDMAC_DMADAR_27 0xE7308584 // R/W 32 DMA destination address register_27 -#define SYSDMAC_DMATCR_27 0xE7308588 // R/W 32 DMA transfer count register_27 -#define SYSDMAC_DMATSR_27 0xE73085A8 // R/W 32 DMA transfer size register_27 -#define SYSDMAC_DMACHCR_27 0xE730858C // R/W 32 DMA channel control register_27 -#define SYSDMAC_DMATCRB_27 0xE7308598 // R/W 32 DMA transfer count register B_27 -#define SYSDMAC_DMATSRB_27 0xE73085B8 // R/W 32 DMA transfer size register B_27 -#define SYSDMAC_DMACHCRB_27 0xE730859C // R/W 32 DMA channel control register B_27 -#define SYSDMAC_DMARS_27 0xE73085C0 // R/W 16 DMA extended resource selector_27 -#define SYSDMAC_DMABUFCR_27 0xE73085C8 // R/W 32 DMA buffer control register_27 -#define SYSDMAC_DMADPBASE_27 0xE73085D0 // R/W 32 DMA descriptor base address register_27 -#define SYSDMAC_DMADPCR_27 0xE73085D4 // R/W 32 DMA descriptor control register_27 -#define SYSDMAC_DMAFIXSAR_27 0xE7308590 // R/W 32 DMA fixed source address register_27 -#define SYSDMAC_DMAFIXDAR_27 0xE7308594 // R/W 32 DMA fixed destination address register_27 -#define SYSDMAC_DMAFIXDPBASE_27 0xE73085E0 // R/W 32 DMA fixed descriptor base address register_27 -#define SYSDMAC_DMASAR_28 0xE7308600 // R/W 32 DMA source address register_28 -#define SYSDMAC_DMADAR_28 0xE7308604 // R/W 32 DMA destination address register_28 -#define SYSDMAC_DMATCR_28 0xE7308608 // R/W 32 DMA transfer count register_28 -#define SYSDMAC_DMATSR_28 0xE7308628 // R/W 32 DMA transfer size register_28 -#define SYSDMAC_DMACHCR_28 0xE730860C // R/W 32 DMA channel control register_28 -#define SYSDMAC_DMATCRB_28 0xE7308618 // R/W 32 DMA transfer count register B_28 -#define SYSDMAC_DMATSRB_28 0xE7308638 // R/W 32 DMA transfer size register B_28 -#define SYSDMAC_DMACHCRB_28 0xE730861C // R/W 32 DMA channel control register B_28 -#define SYSDMAC_DMARS_28 0xE7308640 // R/W 16 DMA extended resource selector_28 -#define SYSDMAC_DMABUFCR_28 0xE7308648 // R/W 32 DMA buffer control register_28 -#define SYSDMAC_DMADPBASE_28 0xE7308650 // R/W 32 DMA descriptor base address register_28 -#define SYSDMAC_DMADPCR_28 0xE7308654 // R/W 32 DMA descriptor control register_28 -#define SYSDMAC_DMAFIXSAR_28 0xE7308610 // R/W 32 DMA fixed source address register_28 -#define SYSDMAC_DMAFIXDAR_28 0xE7308614 // R/W 32 DMA fixed destination address register_28 -#define SYSDMAC_DMAFIXDPBASE_28 0xE7308660 // R/W 32 DMA fixed descriptor base address register_28 -#define SYSDMAC_DMASAR_29 0xE7308680 // R/W 32 DMA source address register_29 -#define SYSDMAC_DMADAR_29 0xE7308684 // R/W 32 DMA destination address register_29 -#define SYSDMAC_DMATCR_29 0xE7308688 // R/W 32 DMA transfer count register_29 -#define SYSDMAC_DMATSR_29 0xE73086A8 // R/W 32 DMA transfer size register_29 -#define SYSDMAC_DMACHCR_29 0xE730868C // R/W 32 DMA channel control register_29 -#define SYSDMAC_DMATCRB_29 0xE7308698 // R/W 32 DMA transfer count register B_29 -#define SYSDMAC_DMATSRB_29 0xE73086B8 // R/W 32 DMA transfer size register B_29 -#define SYSDMAC_DMACHCRB_29 0xE730869C // R/W 32 DMA channel control register B_29 -#define SYSDMAC_DMARS_29 0xE73086C0 // R/W 16 DMA extended resource selector_29 -#define SYSDMAC_DMABUFCR_29 0xE73086C8 // R/W 32 DMA buffer control register_29 -#define SYSDMAC_DMADPBASE_29 0xE73086D0 // R/W 32 DMA descriptor base address register_29 -#define SYSDMAC_DMADPCR_29 0xE73086D4 // R/W 32 DMA descriptor control register_29 -#define SYSDMAC_DMAFIXSAR_29 0xE7308690 // R/W 32 DMA fixed source address register_29 -#define SYSDMAC_DMAFIXDAR_29 0xE7308694 // R/W 32 DMA fixed destination address register_29 -#define SYSDMAC_DMAFIXDPBASE_29 0xE73086E0 // R/W 32 DMA fixed descriptor base address register_29 -#define SYSDMAC_DMASAR_30 0xE7308700 // R/W 32 DMA source address register_30 -#define SYSDMAC_DMADAR_30 0xE7308704 // R/W 32 DMA destination address register_30 -#define SYSDMAC_DMATCR_30 0xE7308708 // R/W 32 DMA transfer count register_30 -#define SYSDMAC_DMATSR_30 0xE7308728 // R/W 32 DMA transfer size register_30 -#define SYSDMAC_DMACHCR_30 0xE730870C // R/W 32 DMA channel control register_30 -#define SYSDMAC_DMATCRB_30 0xE7308718 // R/W 32 DMA transfer count register B_30 -#define SYSDMAC_DMATSRB_30 0xE7308738 // R/W 32 DMA transfer size register B_30 -#define SYSDMAC_DMACHCRB_30 0xE730871C // R/W 32 DMA channel control register B_30 -#define SYSDMAC_DMARS_30 0xE7308740 // R/W 16 DMA extended resource selector_30 -#define SYSDMAC_DMABUFCR_30 0xE7308748 // R/W 32 DMA buffer control register_30 -#define SYSDMAC_DMADPBASE_30 0xE7308750 // R/W 32 DMA descriptor base address register_30 -#define SYSDMAC_DMADPCR_30 0xE7308754 // R/W 32 DMA descriptor control register_30 -#define SYSDMAC_DMAFIXSAR_30 0xE7308710 // R/W 32 DMA fixed source address register_30 -#define SYSDMAC_DMAFIXDAR_30 0xE7308714 // R/W 32 DMA fixed destination address register_30 -#define SYSDMAC_DMAFIXDPBASE_30 0xE7308760 // R/W 32 DMA fixed descriptor base address register_30 -#define SYSDMAC_DMASAR_31 0xE7308780 // R/W 32 DMA source address register_31 -#define SYSDMAC_DMADAR_31 0xE7308784 // R/W 32 DMA destination address register_31 -#define SYSDMAC_DMATCR_31 0xE7308788 // R/W 32 DMA transfer count register_31 -#define SYSDMAC_DMATSR_31 0xE73087A8 // R/W 32 DMA transfer size register_31 -#define SYSDMAC_DMACHCR_31 0xE730878C // R/W 32 DMA channel control register_31 -#define SYSDMAC_DMATCRB_31 0xE7308798 // R/W 32 DMA transfer count register B_31 -#define SYSDMAC_DMATSRB_31 0xE73087B8 // R/W 32 DMA transfer size register B_31 -#define SYSDMAC_DMACHCRB_31 0xE730879C // R/W 32 DMA channel control register B_31 -#define SYSDMAC_DMARS_31 0xE73087C0 // R/W 16 DMA extended resource selector_31 -#define SYSDMAC_DMABUFCR_31 0xE73087C8 // R/W 32 DMA buffer control register_31 -#define SYSDMAC_DMADPBASE_31 0xE73087D0 // R/W 32 DMA descriptor base address register_31 -#define SYSDMAC_DMADPCR_31 0xE73087D4 // R/W 32 DMA descriptor control register_31 -#define SYSDMAC_DMAFIXSAR_31 0xE7308790 // R/W 32 DMA fixed source address register_31 -#define SYSDMAC_DMAFIXDAR_31 0xE7308794 // R/W 32 DMA fixed destination address register_31 -#define SYSDMAC_DMAFIXDPBASE_31 0xE73087E0 // R/W 32 DMA fixed descriptor base address register_31 -#define SYSDMAC_DescriptorMEM_16_31 0xE730A000 // R/W 32 Descriptor memory (for channels 16 to 31) -#define SYSDMAC_DMASES_1 0xE73000C0 // R/W 32 Secure function Secure Status register (for channels 16 to 31) -#define SYSDMAC_DMASEA_1 0xE73000C4 // R/W 32 Secure function Slave Error Address register (for channels 16 to 31) -#define SYSDMAC_DMAEMID_1 0xE73000C8 // R/W 32 Secure function Error Master ID register (for channels 16 to 31) -#define SYSDMAC_DMAISTA_2 0xE7310020 // R 32 DMA interrupt status register (for channels 32 to 47) -#define SYSDMAC_DMASEC_2 0xE7310030 // R/W 32 DMA secure control register (for channels 32 to 47) -#define SYSDMAC_DMAOR_2 0xE7310060 // R/W 16 DMA operation register (for channels 32 to 47) -#define SYSDMAC_DMACHCLR_2 0xE7310080 // W 32 DMA channel clear register (for channels 32 to 47) -#define SYSDMAC_DMADPSEC_2 0xE73100A0 // R/W 32 DPRAM secure control register (for channels 32 to 47) -#define SYSDMAC_DMASAR_32 0xE7318000 // R/W 32 DMA source address register_32 -#define SYSDMAC_DMADAR_32 0xE7318004 // R/W 32 DMA destination address register_32 -#define SYSDMAC_DMATCR_32 0xE7318008 // R/W 32 DMA transfer count register_32 -#define SYSDMAC_DMATSR_32 0xE7318028 // R/W 32 DMA transfer size register_32 -#define SYSDMAC_DMACHCR_32 0xE731800C // R/W 32 DMA channel control register_32 -#define SYSDMAC_DMATCRB_32 0xE7318018 // R/W 32 DMA transfer count register B_32 -#define SYSDMAC_DMATSRB_32 0xE7318038 // R/W 32 DMA transfer size register B_32 -#define SYSDMAC_DMACHCRB_32 0xE731801C // R/W 32 DMA channel control register B_32 -#define SYSDMAC_DMARS_32 0xE7318040 // R/W 16 DMA extended resource selector_32 -#define SYSDMAC_DMABUFCR_32 0xE7318048 // R/W 32 DMA buffer control register_32 -#define SYSDMAC_DMADPBASE_32 0xE7318050 // R/W 32 DMA descriptor base address register_32 -#define SYSDMAC_DMADPCR_32 0xE7318054 // R/W 32 DMA descriptor control register_32 -#define SYSDMAC_DMAFIXSAR_32 0xE7318010 // R/W 32 DMA fixed source address register_32 -#define SYSDMAC_DMAFIXDAR_32 0xE7318014 // R/W 32 DMA fixed destination address register_32 -#define SYSDMAC_DMAFIXDPBASE_32 0xE7318060 // R/W 32 DMA fixed descriptor base address register_32 -#define SYSDMAC_DMASAR_33 0xE7318080 // R/W 32 DMA source address register_33 -#define SYSDMAC_DMADAR_33 0xE7318084 // R/W 32 DMA destination address register_33 -#define SYSDMAC_DMATCR_33 0xE7318088 // R/W 32 DMA transfer count register_33 -#define SYSDMAC_DMATSR_33 0xE73180A8 // R/W 32 DMA transfer size register_33 -#define SYSDMAC_DMACHCR_33 0xE731808C // R/W 32 DMA channel control register_33 -#define SYSDMAC_DMATCRB_33 0xE7318098 // R/W 32 DMA transfer count register B_33 -#define SYSDMAC_DMATSRB_33 0xE73180B8 // R/W 32 DMA transfer size register B_33 -#define SYSDMAC_DMACHCRB_33 0xE731809C // R/W 32 DMA channel control register B_33 -#define SYSDMAC_DMARS_33 0xE73180C0 // R/W 16 DMA extended resource selector_33 -#define SYSDMAC_DMABUFCR_33 0xE73180C8 // R/W 32 DMA buffer control register_33 -#define SYSDMAC_DMADPBASE_33 0xE73180D0 // R/W 32 DMA descriptor base address register_33 -#define SYSDMAC_DMADPCR_33 0xE73180D4 // R/W 32 DMA descriptor control register_33 -#define SYSDMAC_DMAFIXDPBASE_33 0xE73180E0 // R/W 32 DMA fixed descriptor base address register_33 -#define SYSDMAC_DMAFIXSAR_33 0xE7318090 // R/W 32 DMA fixed source address register_33 -#define SYSDMAC_DMAFIXDAR_33 0xE7318094 // R/W 32 DMA fixed destination address register_33 -#define SYSDMAC_DMASAR_34 0xE7318100 // R/W 32 DMA source address register_34 -#define SYSDMAC_DMADAR_34 0xE7318104 // R/W 32 DMA destination address register_34 -#define SYSDMAC_DMATCR_34 0xE7318108 // R/W 32 DMA transfer count register_34 -#define SYSDMAC_DMATSR_34 0xE7318128 // R/W 32 DMA transfer size register_34 -#define SYSDMAC_DMACHCR_34 0xE731810C // R/W 32 DMA channel control register_34 -#define SYSDMAC_DMATCRB_34 0xE7318118 // R/W 32 DMA transfer count register B_34 -#define SYSDMAC_DMATSRB_34 0xE7318138 // R/W 32 DMA transfer size register B_34 -#define SYSDMAC_DMACHCRB_34 0xE731811C // R/W 32 DMA channel control register B_34 -#define SYSDMAC_DMARS_34 0xE7318140 // R/W 16 DMA extended resource selector_34 -#define SYSDMAC_DMABUFCR_34 0xE7318148 // R/W 32 DMA buffer control register_34 -#define SYSDMAC_DMADPBASE_34 0xE7318150 // R/W 32 DMA descriptor base address register_34 -#define SYSDMAC_DMADPCR_34 0xE7318154 // R/W 32 DMA descriptor control register_34 -#define SYSDMAC_DMAFIXSAR_34 0xE7318110 // R/W 32 DMA fixed source address register_34 -#define SYSDMAC_DMAFIXDAR_34 0xE7318114 // R/W 32 DMA fixed destination address register_34 -#define SYSDMAC_DMAFIXDPBASE_34 0xE7318160 // R/W 32 DMA fixed descriptor base address register_34 -#define SYSDMAC_DMASAR_35 0xE7318180 // R/W 32 DMA source address register_35 -#define SYSDMAC_DMADAR_35 0xE7318184 // R/W 32 DMA destination address register_35 -#define SYSDMAC_DMATCR_35 0xE7318188 // R/W 32 DMA transfer count register_35 -#define SYSDMAC_DMATSR_35 0xE73181A8 // R/W 32 DMA transfer size register_35 -#define SYSDMAC_DMACHCR_35 0xE731818C // R/W 32 DMA channel control register_35 -#define SYSDMAC_DMATCRB_35 0xE7318198 // R/W 32 DMA transfer count register B_35 -#define SYSDMAC_DMATSRB_35 0xE73181B8 // R/W 32 DMA transfer size register B_35 -#define SYSDMAC_DMACHCRB_35 0xE731819C // R/W 32 DMA channel control register B_35 -#define SYSDMAC_DMARS_35 0xE73181C0 // R/W 16 DMA extended resource selector_35 -#define SYSDMAC_DMABUFCR_35 0xE73181C8 // R/W 32 DMA buffer control register_35 -#define SYSDMAC_DMADPBASE_35 0xE73181D0 // R/W 32 DMA descriptor base address register_35 -#define SYSDMAC_DMADPCR_35 0xE73181D4 // R/W 32 DMA descriptor control register_35 -#define SYSDMAC_DMAFIXSAR_35 0xE7318190 // R/W 32 DMA fixed source address register_35 -#define SYSDMAC_DMAFIXDAR_35 0xE7318194 // R/W 32 DMA fixed destination address register_35 -#define SYSDMAC_DMAFIXDPBASE_35 0xE73181E0 // R/W 32 DMA fixed descriptor base address register_35 -#define SYSDMAC_DMASAR_36 0xE7318200 // R/W 32 DMA source address register_36 -#define SYSDMAC_DMADAR_36 0xE7318204 // R/W 32 DMA destination address register_36 -#define SYSDMAC_DMATCR_36 0xE7318208 // R/W 32 DMA transfer count register_36 -#define SYSDMAC_DMATSR_36 0xE7318228 // R/W 32 DMA transfer size register_36 -#define SYSDMAC_DMACHCR_36 0xE731820C // R/W 32 DMA channel control register_36 -#define SYSDMAC_DMATCRB_36 0xE7318218 // R/W 32 DMA transfer count register B_36 -#define SYSDMAC_DMATSRB_36 0xE7318238 // R/W 32 DMA transfer size register B_36 -#define SYSDMAC_DMACHCRB_36 0xE731821C // R/W 32 DMA channel control register B_36 -#define SYSDMAC_DMARS_36 0xE7318240 // R/W 16 DMA extended resource selector_36 -#define SYSDMAC_DMABUFCR_36 0xE7318248 // R/W 32 DMA buffer control register_36 -#define SYSDMAC_DMADPBASE_36 0xE7318250 // R/W 32 DMA descriptor base address register_36 -#define SYSDMAC_DMADPCR_36 0xE7318254 // R/W 32 DMA descriptor control register_36 -#define SYSDMAC_DMAFIXSAR_36 0xE7318210 // R/W 32 DMA fixed source address register_36 -#define SYSDMAC_DMAFIXDAR_36 0xE7318214 // R/W 32 DMA fixed destination address register_36 -#define SYSDMAC_DMAFIXDPBASE_36 0xE7318260 // R/W 32 DMA fixed descriptor base address register_36 -#define SYSDMAC_DMASAR_37 0xE7318280 // R/W 32 DMA source address register_37 -#define SYSDMAC_DMADAR_37 0xE7318284 // R/W 32 DMA destination address register_37 -#define SYSDMAC_DMATCR_37 0xE7318288 // R/W 32 DMA transfer count register_37 -#define SYSDMAC_DMATSR_37 0xE73182A8 // R/W 32 DMA transfer size register_37 -#define SYSDMAC_DMACHCR_37 0xE731828C // R/W 32 DMA channel control register_37 -#define SYSDMAC_DMATCRB_37 0xE7318298 // R/W 32 DMA transfer count register B_37 -#define SYSDMAC_DMATSRB_37 0xE73182B8 // R/W 32 DMA transfer size register B_37 -#define SYSDMAC_DMACHCRB_37 0xE731829C // R/W 32 DMA channel control register B_37 -#define SYSDMAC_DMARS_37 0xE73182C0 // R/W 16 DMA extended resource selector_37 -#define SYSDMAC_DMABUFCR_37 0xE73182C8 // R/W 32 DMA buffer control register_37 -#define SYSDMAC_DMADPBASE_37 0xE73182D0 // R/W 32 DMA descriptor base address register_37 -#define SYSDMAC_DMADPCR_37 0xE73182D4 // R/W 32 DMA descriptor control register_37 -#define SYSDMAC_DMAFIXSAR_37 0xE7318290 // R/W 32 DMA fixed source address register_37 -#define SYSDMAC_DMAFIXDAR_37 0xE7318294 // R/W 32 DMA fixed destination address register_37 -#define SYSDMAC_DMAFIXDPBASE_37 0xE73182E0 // R/W 32 DMA fixed descriptor base address register_37 -#define SYSDMAC_DMASAR_38 0xE7318300 // R/W 32 DMA source address register_38 -#define SYSDMAC_DMADAR_38 0xE7318304 // R/W 32 DMA destination address register_38 -#define SYSDMAC_DMATCR_38 0xE7318308 // R/W 32 DMA transfer count register_38 -#define SYSDMAC_DMATSR_38 0xE7318328 // R/W 32 DMA transfer size register_38 -#define SYSDMAC_DMACHCR_38 0xE731830C // R/W 32 DMA channel control register_38 -#define SYSDMAC_DMATCRB_38 0xE7318318 // R/W 32 DMA transfer count register B_38 -#define SYSDMAC_DMATSRB_38 0xE7318338 // R/W 32 DMA transfer size register B_38 -#define SYSDMAC_DMACHCRB_38 0xE731831C // R/W 32 DMA channel control register B_38 -#define SYSDMAC_DMARS_38 0xE7318340 // R/W 16 DMA extended resource selector_38 -#define SYSDMAC_DMABUFCR_38 0xE7318348 // R/W 32 DMA buffer control register_38 -#define SYSDMAC_DMADPBASE_38 0xE7318350 // R/W 32 DMA descriptor base address register_38 -#define SYSDMAC_DMADPCR_38 0xE7318354 // R/W 32 DMA descriptor control register_38 -#define SYSDMAC_DMAFIXSAR_38 0xE7318310 // R/W 32 DMA fixed source address register_38 -#define SYSDMAC_DMAFIXDAR_38 0xE7318314 // R/W 32 DMA fixed destination address register_38 -#define SYSDMAC_DMAFIXDPBASE_38 0xE7318360 // R/W 32 DMA fixed descriptor base address register_38 -#define SYSDMAC_DMASAR_39 0xE7318380 // R/W 32 DMA source address register_39 -#define SYSDMAC_DMADAR_39 0xE7318384 // R/W 32 DMA destination address register_39 -#define SYSDMAC_DMATCR_39 0xE7318388 // R/W 32 DMA transfer count register_39 -#define SYSDMAC_DMATSR_39 0xE73183A8 // R/W 32 DMA transfer size register_39 -#define SYSDMAC_DMACHCR_39 0xE731838C // R/W 32 DMA channel control register_39 -#define SYSDMAC_DMATCRB_39 0xE7318398 // R/W 32 DMA transfer count register B_39 -#define SYSDMAC_DMATSRB_39 0xE73183B8 // R/W 32 DMA transfer size register B_39 -#define SYSDMAC_DMACHCRB_39 0xE731839C // R/W 32 DMA channel control register B_39 -#define SYSDMAC_DMARS_39 0xE73183C0 // R/W 16 DMA extended resource selector_39 -#define SYSDMAC_DMABUFCR_39 0xE73183C8 // R/W 32 DMA buffer control register_39 -#define SYSDMAC_DMADPBASE_39 0xE73183D0 // R/W 32 DMA descriptor base address register_39 -#define SYSDMAC_DMADPCR_39 0xE73183D4 // R/W 32 DMA descriptor control register_39 -#define SYSDMAC_DMAFIXSAR_39 0xE7318390 // R/W 32 DMA fixed source address register_39 -#define SYSDMAC_DMAFIXDAR_39 0xE7318394 // R/W 32 DMA fixed destination address register_39 -#define SYSDMAC_DMAFIXDPBASE_39 0xE73183E0 // R/W 32 DMA fixed descriptor base address register_39 -#define SYSDMAC_DMASAR_40 0xE7318400 // R/W 32 DMA source address register_40 -#define SYSDMAC_DMADAR_40 0xE7318404 // R/W 32 DMA destination address register_40 -#define SYSDMAC_DMATCR_40 0xE7318408 // R/W 32 DMA transfer count register_40 -#define SYSDMAC_DMATSR_40 0xE7318428 // R/W 32 DMA transfer size register_40 -#define SYSDMAC_DMACHCR_40 0xE731840C // R/W 32 DMA channel control register_40 -#define SYSDMAC_DMATCRB_40 0xE7318418 // R/W 32 DMA transfer count register B_40 -#define SYSDMAC_DMATSRB_40 0xE7318438 // R/W 32 DMA transfer size register B_40 -#define SYSDMAC_DMACHCRB_40 0xE731841C // R/W 32 DMA channel control register B_40 -#define SYSDMAC_DMARS_40 0xE7318440 // R/W 16 DMA extended resource selector_40 -#define SYSDMAC_DMABUFCR_40 0xE7318448 // R/W 32 DMA buffer control register_40 -#define SYSDMAC_DMADPBASE_40 0xE7318450 // R/W 32 DMA descriptor base address register_40 -#define SYSDMAC_DMADPCR_40 0xE7318454 // R/W 32 DMA descriptor control register_40 -#define SYSDMAC_DMAFIXSAR_40 0xE7318410 // R/W 32 DMA fixed source address register_40 -#define SYSDMAC_DMAFIXDAR_40 0xE7318414 // R/W 32 DMA fixed destination address register_40 -#define SYSDMAC_DMAFIXDPBASE_40 0xE7318460 // R/W 32 DMA fixed descriptor base address register_40 -#define SYSDMAC_DMASAR_41 0xE7318480 // R/W 32 DMA source address register_41 -#define SYSDMAC_DMADAR_41 0xE7318484 // R/W 32 DMA destination address register_41 -#define SYSDMAC_DMATCR_41 0xE7318488 // R/W 32 DMA transfer count register_41 -#define SYSDMAC_DMATSR_41 0xE73184A8 // R/W 32 DMA transfer size register_41 -#define SYSDMAC_DMACHCR_41 0xE731848C // R/W 32 DMA channel control register_41 -#define SYSDMAC_DMATCRB_41 0xE7318498 // R/W 32 DMA transfer count register B_41 -#define SYSDMAC_DMATSRB_41 0xE73184B8 // R/W 32 DMA transfer size register B_41 -#define SYSDMAC_DMACHCRB_41 0xE731849C // R/W 32 DMA channel control register B_41 -#define SYSDMAC_DMARS_41 0xE73184C0 // R/W 16 DMA extended resource selector_41 -#define SYSDMAC_DMABUFCR_41 0xE73184C8 // R/W 32 DMA buffer control register_41 -#define SYSDMAC_DMADPBASE_41 0xE73184D0 // R/W 32 DMA descriptor base address register_41 -#define SYSDMAC_DMADPCR_41 0xE73184D4 // R/W 32 DMA descriptor control register_41 -#define SYSDMAC_DMAFIXSAR_41 0xE7318490 // R/W 32 DMA fixed source address register_41 -#define SYSDMAC_DMAFIXDAR_41 0xE7318494 // R/W 32 DMA fixed destination address register_41 -#define SYSDMAC_DMAFIXDPBASE_41 0xE73184E0 // R/W 32 DMA fixed descriptor base address register_41 -#define SYSDMAC_DMASAR_42 0xE7318500 // R/W 32 DMA source address register_42 -#define SYSDMAC_DMADAR_42 0xE7318504 // R/W 32 DMA destination address register_42 -#define SYSDMAC_DMATCR_42 0xE7318508 // R/W 32 DMA transfer count register_42 -#define SYSDMAC_DMATSR_42 0xE7318528 // R/W 32 DMA transfer size register_42 -#define SYSDMAC_DMACHCR_42 0xE731850C // R/W 32 DMA channel control register_42 -#define SYSDMAC_DMATCRB_42 0xE7318518 // R/W 32 DMA transfer count register B_42 -#define SYSDMAC_DMATSRB_42 0xE7318538 // R/W 32 DMA transfer size register B_42 -#define SYSDMAC_DMACHCRB_42 0xE731851C // R/W 32 DMA channel control register B_42 -#define SYSDMAC_DMARS_42 0xE7318540 // R/W 16 DMA extended resource selector_42 -#define SYSDMAC_DMABUFCR_42 0xE7318548 // R/W 32 DMA buffer control register_42 -#define SYSDMAC_DMADPBASE_42 0xE7318550 // R/W 32 DMA descriptor base address register_42 -#define SYSDMAC_DMADPCR_42 0xE7318554 // R/W 32 DMA descriptor control register_42 -#define SYSDMAC_DMAFIXSAR_42 0xE7318510 // R/W 32 DMA fixed source address register_42 -#define SYSDMAC_DMAFIXDAR_42 0xE7318514 // R/W 32 DMA fixed destination address register_42 -#define SYSDMAC_DMAFIXDPBASE_42 0xE7318560 // R/W 32 DMA fixed descriptor base address register_42 -#define SYSDMAC_DMASAR_43 0xE7318580 // R/W 32 DMA source address register_43 -#define SYSDMAC_DMADAR_43 0xE7318584 // R/W 32 DMA destination address register_43 -#define SYSDMAC_DMATCR_43 0xE7318588 // R/W 32 DMA transfer count register_43 -#define SYSDMAC_DMATSR_43 0xE73185A8 // R/W 32 DMA transfer size register_43 -#define SYSDMAC_DMACHCR_43 0xE731858C // R/W 32 DMA channel control register_43 -#define SYSDMAC_DMATCRB_43 0xE7318598 // R/W 32 DMA transfer count register B_43 -#define SYSDMAC_DMATSRB_43 0xE73185B8 // R/W 32 DMA transfer size register B_43 -#define SYSDMAC_DMACHCRB_43 0xE731859C // R/W 32 DMA channel control register B_43 -#define SYSDMAC_DMARS_43 0xE73185C0 // R/W 16 DMA extended resource selector_43 -#define SYSDMAC_DMABUFCR_43 0xE73185C8 // R/W 32 DMA buffer control register_43 -#define SYSDMAC_DMADPBASE_43 0xE73185D0 // R/W 32 DMA descriptor base address register_43 -#define SYSDMAC_DMADPCR_43 0xE73185D4 // R/W 32 DMA descriptor control register_43 -#define SYSDMAC_DMAFIXSAR_43 0xE7318590 // R/W 32 DMA fixed source address register_43 -#define SYSDMAC_DMAFIXDAR_43 0xE7318594 // R/W 32 DMA fixed destination address register_43 -#define SYSDMAC_DMAFIXDPBASE_43 0xE73185E0 // R/W 32 DMA fixed descriptor base address register_43 -#define SYSDMAC_DMASAR_44 0xE7318600 // R/W 32 DMA source address register_44 -#define SYSDMAC_DMADAR_44 0xE7318604 // R/W 32 DMA destination address register_44 -#define SYSDMAC_DMATCR_44 0xE7318608 // R/W 32 DMA transfer count register_44 -#define SYSDMAC_DMATSR_44 0xE7318628 // R/W 32 DMA transfer size register_44 -#define SYSDMAC_DMACHCR_44 0xE731860C // R/W 32 DMA channel control register_44 -#define SYSDMAC_DMATCRB_44 0xE7318618 // R/W 32 DMA transfer count register B_44 -#define SYSDMAC_DMATSRB_44 0xE7318638 // R/W 32 DMA transfer size register B_44 -#define SYSDMAC_DMACHCRB_44 0xE731861C // R/W 32 DMA channel control register B_44 -#define SYSDMAC_DMARS_44 0xE7318640 // R/W 16 DMA extended resource selector_44 -#define SYSDMAC_DMABUFCR_44 0xE7318648 // R/W 32 DMA buffer control register_44 -#define SYSDMAC_DMADPBASE_44 0xE7318650 // R/W 32 DMA descriptor base address register_44 -#define SYSDMAC_DMADPCR_44 0xE7318654 // R/W 32 DMA descriptor control register_44 -#define SYSDMAC_DMAFIXSAR_44 0xE7318610 // R/W 32 DMA fixed source address register_44 -#define SYSDMAC_DMAFIXDAR_44 0xE7318614 // R/W 32 DMA fixed destination address register_44 -#define SYSDMAC_DMAFIXDPBASE_44 0xE7318660 // R/W 32 DMA fixed descriptor base address register_44 -#define SYSDMAC_DMASAR_45 0xE7318680 // R/W 32 DMA source address register_45 -#define SYSDMAC_DMADAR_45 0xE7318684 // R/W 32 DMA destination address register_45 -#define SYSDMAC_DMATCR_45 0xE7318688 // R/W 32 DMA transfer count register_45 -#define SYSDMAC_DMATSR_45 0xE73186A8 // R/W 32 DMA transfer size register_45 -#define SYSDMAC_DMACHCR_45 0xE731868C // R/W 32 DMA channel control register_45 -#define SYSDMAC_DMATCRB_45 0xE7318698 // R/W 32 DMA transfer count register B_45 -#define SYSDMAC_DMATSRB_45 0xE73186B8 // R/W 32 DMA transfer size register B_45 -#define SYSDMAC_DMACHCRB_45 0xE731869C // R/W 32 DMA channel control register B_45 -#define SYSDMAC_DMARS_45 0xE73186C0 // R/W 16 DMA extended resource selector_45 -#define SYSDMAC_DMABUFCR_45 0xE73186C8 // R/W 32 DMA buffer control register_45 -#define SYSDMAC_DMADPBASE_45 0xE73186D0 // R/W 32 DMA descriptor base address register_45 -#define SYSDMAC_DMADPCR_45 0xE73186D4 // R/W 32 DMA descriptor control register_45 -#define SYSDMAC_DMAFIXSAR_45 0xE7318690 // R/W 32 DMA fixed source address register_45 -#define SYSDMAC_DMAFIXDAR_45 0xE7318694 // R/W 32 DMA fixed destination address register_45 -#define SYSDMAC_DMAFIXDPBASE_45 0xE73186E0 // R/W 32 DMA fixed descriptor base address register_45 -#define SYSDMAC_DMASAR_46 0xE7318700 // R/W 32 DMA source address register_46 -#define SYSDMAC_DMADAR_46 0xE7318704 // R/W 32 DMA destination address register_46 -#define SYSDMAC_DMATCR_46 0xE7318708 // R/W 32 DMA transfer count register_46 -#define SYSDMAC_DMATSR_46 0xE7318728 // R/W 32 DMA transfer size register_46 -#define SYSDMAC_DMACHCR_46 0xE731870C // R/W 32 DMA channel control register_46 -#define SYSDMAC_DMATCRB_46 0xE7318718 // R/W 32 DMA transfer count register B_46 -#define SYSDMAC_DMATSRB_46 0xE7318738 // R/W 32 DMA transfer size register B_46 -#define SYSDMAC_DMACHCRB_46 0xE731871C // R/W 32 DMA channel control register B_46 -#define SYSDMAC_DMARS_46 0xE7318740 // R/W 16 DMA extended resource selector_46 -#define SYSDMAC_DMABUFCR_46 0xE7318748 // R/W 32 DMA buffer control register_46 -#define SYSDMAC_DMADPBASE_46 0xE7318750 // R/W 32 DMA descriptor base address register_46 -#define SYSDMAC_DMADPCR_46 0xE7318754 // R/W 32 DMA descriptor control register_46 -#define SYSDMAC_DMAFIXSAR_46 0xE7318710 // R/W 32 DMA fixed source address register_46 -#define SYSDMAC_DMAFIXDAR_46 0xE7318714 // R/W 32 DMA fixed destination address register_46 -#define SYSDMAC_DMAFIXDPBASE_46 0xE7318760 // R/W 32 DMA fixed descriptor base address register_46 -#define SYSDMAC_DMASAR_47 0xE7318780 // R/W 32 DMA source address register_47 -#define SYSDMAC_DMADAR_47 0xE7318784 // R/W 32 DMA destination address register_47 -#define SYSDMAC_DMATCR_47 0xE7318788 // R/W 32 DMA transfer count register_47 -#define SYSDMAC_DMATSR_47 0xE73187A8 // R/W 32 DMA transfer size register_47 -#define SYSDMAC_DMACHCR_47 0xE731878C // R/W 32 DMA channel control register_47 -#define SYSDMAC_DMATCRB_47 0xE7318798 // R/W 32 DMA transfer count register B_47 -#define SYSDMAC_DMATSRB_47 0xE73187B8 // R/W 32 DMA transfer size register B_47 -#define SYSDMAC_DMACHCRB_47 0xE731879C // R/W 32 DMA channel control register B_47 -#define SYSDMAC_DMARS_47 0xE73187C0 // R/W 16 DMA extended resource selector_47 -#define SYSDMAC_DMABUFCR_47 0xE73187C8 // R/W 32 DMA buffer control register_47 -#define SYSDMAC_DMADPBASE_47 0xE73187D0 // R/W 32 DMA descriptor base address register_47 -#define SYSDMAC_DMADPCR_47 0xE73187D4 // R/W 32 DMA descriptor control register_47 -#define SYSDMAC_DMAFIXSAR_47 0xE7318790 // R/W 32 DMA fixed source address register_47 -#define SYSDMAC_DMAFIXDAR_47 0xE7318794 // R/W 32 DMA fixed destination address register_47 -#define SYSDMAC_DMAFIXDPBASE_47 0xE73187E0 // R/W 32 DMA fixed descriptor base address register_47 -#define SYSDMAC_DescriptorMEM_32_47 0xE731A000 // R/W 32 Descriptor memory (for channels 32 to 47) -#define SYSDMAC_DMASES_2 0xE73100C0 // R/W 32 Secure function Secure Status register (for channels 32 to 47) -#define SYSDMAC_DMASEA_2 0xE73100C4 // R/W 32 Secure function Slave Error Address register (for channels 32 to 47) -#define SYSDMAC_DMAEMID_2 0xE73100C8 // R/W 32 Secure function Error Master ID register (for channels 32 to 47) -#define SYSDMAC_FDSDM_ENABLE 0xE73000D0 // R/W 32 Failure detection function enable register -#define SYSDMAC_FDSDM_STATUS 0xE73000D4 // R/W 32 Failure detection error status register - -//TMU -#define TMU_TSTR0 0xE61E0004 // R/W 8 Timer start register 0 -#define TMU_TCOR0 0xE61E0008 // R/W 32 Timer constant register 0 -#define TMU_TCNT0 0xE61E000C // R/W 32 Timer counter 0 -#define TMU_TCR0 0xE61E0010 // R/W 16 Timer control register 0 -#define TMU_TCOR1 0xE61E0014 // R/W 32 Timer constant register 1 -#define TMU_TCNT1 0xE61E0018 // R/W 32 Timer counter 1 -#define TMU_TCR1 0xE61E001C // R/W 16 Timer control register 1 -#define TMU_TCOR2 0xE61E0020 // R/W 32 Timer constant register 2 -#define TMU_TCNT2 0xE61E0024 // R/W 32 Timer counter 2 -#define TMU_TCR2 0xE61E0028 // R/W 16 Timer control register 2 -#define TMU_TSTR1 0xE6FC0004 // R/W 8 Timer start register 1 -#define TMU_TCOR3 0xE6FC0008 // R/W 32 Timer constant register 3 -#define TMU_TCNT3 0xE6FC000C // R/W 32 Timer counter 3 -#define TMU_TCR3 0xE6FC0010 // R/W 16 Timer control register 3 -#define TMU_TCOR4 0xE6FC0014 // R/W 32 Timer constant register 4 -#define TMU_TCNT4 0xE6FC0018 // R/W 32 Timer counter 4 -#define TMU_TCR4 0xE6FC001C // R/W 16 Timer control register 4 -#define TMU_TCOR5 0xE6FC0020 // R/W 32 Timer constant register 5 -#define TMU_TCNT5 0xE6FC0024 // R/W 32 Timer counter 5 -#define TMU_TCR5 0xE6FC0028 // R/W 16 Timer control register 5 -#define TMU_TCPR5 0xE6FC002C // R 32 Input capture register 5 -#define TMU_TSTR2 0xE6FD0004 // R/W 8 Timer start register 2 -#define TMU_TCOR6 0xE6FD0008 // R/W 32 Timer constant register 6 -#define TMU_TCNT6 0xE6FD000C // R/W 32 Timer counter 6 -#define TMU_TCR6 0xE6FD0010 // R/W 16 Timer control register 6 -#define TMU_TCOR7 0xE6FD0014 // R/W 32 Timer constant register 7 -#define TMU_TCNT7 0xE6FD0018 // R/W 32 Timer counter 7 -#define TMU_TCR7 0xE6FD001C // R/W 16 Timer control register 7 -#define TMU_TCOR8 0xE6FD0020 // R/W 32 Timer constant register 8 -#define TMU_TCNT8 0xE6FD0024 // R/W 32 Timer counter 8 -#define TMU_TCR8 0xE6FD0028 // R/W 16 Timer control register 8 -#define TMU_TCPR8 0xE6FD002C // R 32 Input capture register 8 -#define TMU_TSTR3 0xE6FE0004 // R/W 8 Timer start register 3 -#define TMU_TCOR9 0xE6FE0008 // R/W 32 Timer constant register 9 -#define TMU_TCNT9 0xE6FE000C // R/W 32 Timer counter 9 -#define TMU_TCR9 0xE6FE0010 // R/W 16 Timer control register 9 -#define TMU_TCOR10 0xE6FE0014 // R/W 32 Timer constant register 10 -#define TMU_TCNT10 0xE6FE0018 // R/W 32 Timer counter 10 -#define TMU_TCR10 0xE6FE001C // R/W 16 Timer control register 10 -#define TMU_TCOR11 0xE6FE0020 // R/W 32 Timer constant register 11 -#define TMU_TCNT11 0xE6FE0024 // R/W 32 Timer counter 11 -#define TMU_TCR11 0xE6FE0028 // R/W 16 Timer control register 11 -#define TMU_TCPR11 0xE6FE002C // R 32 Input capture register 11 -#define TMU_TSTR4 0xFFC00004 // R/W 8 Timer start register 12 -#define TMU_TCOR12 0xFFC00008 // R/W 32 Timer constant register 12 -#define TMU_TCNT12 0xFFC0000C // R/W 32 Timer counter 12 -#define TMU_TCR12 0xFFC00010 // R/W 16 Timer control register 12 -#define TMU_TCOR13 0xFFC00014 // R/W 32 Timer constant register 13 -#define TMU_TCNT13 0xFFC00018 // R/W 32 Timer counter 13 -#define TMU_TCR13 0xFFC0001C // R/W 16 Timer control register 13 -#define TMU_TCOR14 0xFFC00020 // R/W 32 Timer constant register 14 -#define TMU_TCNT14 0xFFC00024 // R/W 32 Timer counter 14 -#define TMU_TCR14 0xFFC00028 // R/W 16 Timer control register 14 - -// Appendix A. -#define PRR (0xFFF00044U) // R 32 Product Register -#define PRR_PRODUCT_MASK (0x00007F00U) -#define PRR_CUT_MASK (0x000000FFU) -#define PRR_PRODUCT_G2H (0x00004F00U) /* RZ/G2H */ -#define PRR_PRODUCT_G2M (0x00005200U) /* RZ/G2M */ -#define PRR_PRODUCT_G2N (0x00005500U) /* RZ/G2N */ -#define PRR_PRODUCT_G2E (0x00005700U) /* RZ/G2E */ - -#define PRR_CUT_10 (0x00U) /* Ver.1.0 */ -#define PRR_CUT_11 (0x01U) /* Ver.1.1 */ -#define PRR_CUT_20 (0x10U) /* Ver.2.0 */ -#define PRR_CUT_30 (0x20U) /* Ver.3.0 */ - -#define RZG2M_CUT_11 (0x10) /* Ver.1.1/1.2 */ diff --git a/include/rpcqspidrv.h b/include/rpcqspidrv.h deleted file mode 100644 index aa37778..0000000 --- a/include/rpcqspidrv.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2015-2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#define SPI_IOADDRESS_TOP 0x08000000 //RPC memory space 0x08000000-0x0BFFFFFF = 64MBytes -#define RPC_CLK_40M 0x01 -#define RPC_CLK_80M 0x02 -#define RPC_CLK_160M 0x03 - - -void InitRPC_QspiFlashQuadExtMode(void); -void InitRPC_QspiFlash4FastReadExtMode(void); -void InitRPC_QspiFlash(uint32_t rpcclk); -void ReadConfigRegQspiFlash(uint32_t *cnfigReg); -void WriteRegisterQspiFlash(uint32_t statusReg, uint32_t configReg); -void WriteRegisterQspiFlash_Byte2(uint32_t statusReg, uint32_t configReg); -void SectorEraseQspiFlash(uint32_t sector_addr); -void SectorErase4QspiFlash(uint32_t sector_addr); -void WriteData4ppWithBufferQspiFlash(uint32_t addr, uint32_t source_addr); -void WriteData4ppQspiFlash(uint32_t addr, uint32_t writeData); -void WriteData4ppQspiFlash_CsCont(uint32_t addr, uint32_t *writeData,uint32_t cnt); -void WriteData4qppQspiFlash(uint32_t addr, uint32_t writeData); -uint32_t SingleFastReadQspiFlashData4Byte(uint32_t addr, uint32_t *readData); //for QSPIx1ch -uint32_t SingleFastReadQspiFlashData1Byte(uint32_t addr, uint32_t *readData); //for QSPIx1ch -uint32_t ReadAnyRegisterQspiFlash(uint32_t addr, unsigned char *readData); // Add24bit,Data8bit -void WriteAnyRegisterQspiFlash(uint32_t addr, unsigned char writeData); // Add24bit,Data8bit -void SetRPC_ClockMode(uint32_t mode); -void WaitRpcTxEnd(void); - -void InitRPC_QspiFlashFastReadExtMode(void); -void WriteDataPpWithBufferQspiFlash(uint32_t addr, uint32_t source_addr); - -void ParameterSectorErase3QspiFlash(uint32_t sector_addr); -void ParameterSectorErase4QspiFlash(uint32_t sector_addr); -void ResetRPC(void); -//void SetResetRPC(void); -//void ClearResetRPC(void); -void SetRPC_SSL_Delay(void); - -void PowerOnRPC(void); -uint32_t ReadQspiFlashID(uint32_t *readData); //for QSPIx1ch -uint32_t ReadStatusQspiFlash(uint32_t *readData); //for QSPIx1ch -void WriteCommandQspiFlash(uint32_t command); //for QSPIx1ch -void WriteDataWithBufferQspiFlash(uint32_t addr, uint32_t source_addr); //for QSPIx1ch -void SectorEraseQspiFlash(uint32_t sector_addr); //for QSPIx1ch -void InitRPC_ExtMode_QuadIORead(void); //for QSPIx1ch -void EnableQuadModeQspiFlashS25fs128s(void); diff --git a/include/scifdrv.h b/include/scifdrv.h index 9679861..4fcacd7 100644 --- a/include/scifdrv.h +++ b/include/scifdrv.h @@ -1,44 +1,325 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + +#ifndef SCIFDRV_H_ +#define SCIFDRV_H_ + +typedef enum +{ + serCOM1, + serCOM2, + serCOM3, + serCOM4, + serCOM5, + serCOM6, + serCOM7, + serCOM8 +} eCOMPort; + +typedef enum +{ + serNO_PARITY, + serODD_PARITY, + serEVEN_PARITY, + serMARK_PARITY, + serSPACE_PARITY +} eParity; + +typedef enum +{ + serSTOP_1, + serSTOP_2 +} eStopBits; + +typedef enum +{ + serBITS_5, + serBITS_6, + serBITS_7, + serBITS_8 +} eDataBits; + +typedef enum +{ + ser50, + ser75, + ser110, + ser134, + ser150, + ser200, + ser300, + ser600, + ser1200, + ser1800, + ser2400, + ser4800, + ser9600, + ser19200, + ser38400, + ser57600, + ser115200 +} eBaud; + +/* UART Source Clock (48MHz / FPGA:81MHz) */ +#define SCLK 48000000 +#define UART_BAUDRATE 115200 + +/*-------------------*/ +/* UART Register */ +/*-------------------*/ +typedef volatile struct UART_reg_t { /* UART Register */ + volatile unsigned int RBR_THR; // RxB Reg or TxB Reg + volatile unsigned int IER; // Int. Enable Reg + volatile unsigned int IIR; // Int. ID Reg + volatile unsigned int FCR; // FIFO Ctl. Reg + volatile unsigned int LCR; // Line Ctl. Reg + volatile unsigned int MCR; // Modem Ctl. Reg + volatile unsigned int LSR; // Line Status Reg + volatile unsigned int MSR; // Modem Status Reg + volatile unsigned int SCR; // Scratch Pad Reg + volatile unsigned int DLL; // Divisor Latch(Low) Reg + volatile unsigned int DLM; // Divisor Latch(Hi) Reg + volatile unsigned int HCR0; // H/W Control Reg + volatile unsigned int HCR2; // H/W Status Reg-2 + volatile unsigned int HCR3; // H/W Status Reg-3 +} st_UART_REG_t; + + +/*-------------------*/ +/* UART Control */ +/*-------------------*/ +typedef volatile struct uart_ctrl_t { + st_UART_REG_t *g_uART_cReg; // UART Control Regster Top Pointer + uint32_t cMode; // UART software control mode. + uint32_t cStatus; // UART Line Status + eBaud eWantedBaud; + eParity eWantedParity; + eDataBits eWantedDataBits; + eStopBits eWantedStopBits; + uint32_t uxBufferLength; +} st_UART_CTRL_t; + + +#define UART_CH0_BASE (0xA4040000UL) + +// UART software control Modes Define +// 1=Polling,2=Interrupt,3=DMA(&Interrupt) +#define UART_CTL_NODEF 0 +#define UART_CTL_POL 1 +#define UART_CTL_INT 2 +#define UART_CTL_TX_DMA 3 +#define UART_CTL_RX_DMA 4 + +// +// UART Control Flag +// +#define UART_ERR 0x80000000 +#define UART_RX_END 0x00800000 +#define UART_TX_END 0x00400000 +#define UART_TRX_END 0x00C00000 +#define UART_RX_EN 0x00000001 +#define UART_TX_EN 0x00000002 +#define UART_TRX_EN 0x00000003 +// +// For IP +// +#define UART_IER_RX_EN 0x0001 +#define UART_IER_TX_EN 0x0002 +#define UART_IER_TRX_EN 0x0003 + +// +// UART Max Ch., UART Tx/Rx Buffer Max Size +// +#define UART_MAX 4 +#define UART_RBFSZ 512 +#define UART_TEST_LEN 256 + +// +// UART Define +// + +// SCLK=24MHz BPS=38461 +#define BIT_RATE_CONST 39 + +// 8bit Data,1 Stop bit,Parity Disable,Select Data Register +#define UART_MODE_CONST_LCR 0x0003 + +#define UART_MODE_CONST_FCR_RST 0x0007 // Tx,Rx FIFO Reset + +// UART_CTL_POLL +#define UART_MODE_CONST_IER_P 0x0000 // All Disable +#define UART_MODE_CONST_FCR_P 0x0006 // FIFO Trg=1Byte,Clear FIFO&Enable + +//#define UART_MODE_CONST_FCR_PE 0x00a7 // FIFO Trg=8Byte&64B FIFO,Clear FIFO&Enable +#define UART_MODE_CONST_FCR_PE 0x0087 // FIFO Trg=8Byte,Clear FIFO&Enable + +#define UART_MODE_CONST_MCR_P 0x000F // DTR OFF,Auto Flow Disable + +// UART_CTL_INT +#define UART_MODE_CONST_IER_I 0x0007 // Rx Status,Rxrdy,Txrdy(IE2,IE1,IE0) Enable +#define UART_MODE_CONST_FCR_I 0x0006 // FIFO Trg=1Byte,Clear FIFO&Disable + +//#define UART_MODE_CONST_FCR_IE 0x0027 // FIFO Trg=1Byte,64B FIFO,Clear FIFO&Enable +//#define UART_MODE_CONST_FCR_IE 0x00e7 // FIFO Trg=56Byte,64B FIFO,Clear FIFO&Enable +//#define UART_MODE_CONST_FCR_IE 0x00c7 // FIFO Trg=14Byte,Clear FIFO&Enable +//#define UART_MODE_CONST_FCR_IE 0x0047 // FIFO Trg=4Byte,Clear FIFO&Enable +//#define UART_MODE_CONST_FCR_IE 0x0007 // FIFO Trg=1Byte,Clear FIFO&Enable +#define UART_MODE_CONST_FCR_IE 0x0087 // FIFO Trg=8Byte,Clear FIFO&Enable + +#define UART_MODE_CONST_MCR_I 0x000F // DTR OFF,Auto Flow Disable + +// UART_CTL_TX_DMA +#define UART_MODE_CONST_IER_DT 0x0005 // Rx Status,Rxrdy(IE2,IE0) Enable +#define UART_MODE_CONST_FCR_DT 0x0006 // FIFO Trg=1Byte,Clear FIFO&Disable + +#define UART_MODE_CONST_FCR_DTE 0x0027 // FIFO Trg=1Byte,64B FIFO,Clear FIFO&Enable +//#define UART_MODE_CONST_FCR_DTE 0x0087 // FIFO Trg=8Byte,Clear FIFO&Enable +//#define UART_MODE_CONST_FCR_DTE 0x0007 // FIFO Trg=1Byte,Clear FIFO&Enable + +#define UART_MODE_CONST_MCR_DT 0x000F // DTR OFF,Auto Flow Disable + +// UART_CTL_RX_DMA +#define UART_MODE_CONST_IER_DR 0x0006 // Rx Status,Txrdy(IE2,IE1) Enable +#define UART_MODE_CONST_FCR_DR 0x0006 // FIFO Trg=1Byte,Clear FIFO&Disable + +#define UART_MODE_CONST_FCR_DRE 0x0027 // FIFO Trg=1Byte,64B FIFO,Clear FIFO&Enable +//#define UART_MODE_CONST_FCR_DRE 0x0087 // FIFO Trg=8Byte,Clear FIFO&Enable +//#define UART_MODE_CONST_FCR_DRE 0x0007 // FIFO Trg=1Byte,Clear FIFO&Enable + +#define UART_MODE_CONST_MCR_DR 0x000F // DTR OFF,Auto Flow Disable + +/*Line status*/ +/*! + * Receiver FIFO Error. This status indicates that one or more parity + * error, framing error, or break indication exists in the receiver FIFO. + * It is only set when FIFO is enabled. This status cleared when line + * status is read, the character with the issue is at the top of the FIFO, + * and when no other issues exist in the FIFO. + */ +#define UART_16550_LINE_STATUS_RFE (1 << 7) + +/*! + * Transmitter EMpTy (Empty). This status indicates that transmitter shift + * register is empty. If FIFOs are enabled, the status is set when the + * transmitter FIFO is also empty. This status is cleared when the + * transmitter shift registers is loaded by writing to the UART + * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is + * done by calling alt_16550_write() and alt_16550_fifo_write() + * respectively. + */ +#define UART_16550_LINE_STATUS_TEMT (1 << 6) + +/*! + * Transmitter Holding Register Empty. This status indicates that the + * transmitter will run out of data soon. The definition of soon depends + * on whether the FIFOs are enabled. + * + * If FIFOs are disabled, this status indicates that the transmitter will + * run out of data to send after the current transmit shift register + * completes. In this case, this status is cleared when the data is + * written to the UART. This can be done by calling alt_16550_write(). + * + * If FIFOs are enabled, this status indicates that the transmitter FIFO + * level is below the transmitter trigger level specified. In this case, + * this status is cleared by writing a sufficiently large buffer to the + * transmitter FIFO such that the FIFO is filled above the transmitter + * trigger level specified by calling alt_16550_fifo_write() or by + * adjusting the transmitter trigger level appropriately by calling + * alt_16550_fifo_trigger_set_tx(). + * + * \internal + * The implementation of the UART driver always ensures that IER[7] is + * set. This means that the UART always has Programmable THRE (Transmitter + * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled. + * \endinternal + */ +#define UART_16550_LINE_STATUS_THRE (1 << 5) + +/*! + * Break Interrupt. This status indicates that a break interrupt sequence + * is detected in the incoming serial data. This happens when the the data + * is 0 for longer than a frame would normally be transmitted. The break + * interrupt status is cleared by reading the line status by calling + * alt_16550_line_status_get(). * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * If FIFOs are enabled, this status will be set when the character with + * the break interrupt status is at the top of the receiver FIFO. + */ +#define UART_16550_LINE_STATUS_BI (1 << 4) + +/*! + * Framing Error. This status indicates that a framing error occurred in + * the receiver. This happens when the receiver detects a missing or + * incorrect number of stopbit(s). * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. + * If FIFOs are enabled, this status will be set when the character with + * the framing error is at the top of the FIFO. When a framing error + * occurs, the UART attempts to resynchronize with the transmitting UART. + * This status is also set if break interrupt occurred. + */ +#define UART_16550_LINE_STATUS_FE (1 << 3) + +/*! + * Parity Error. This status indicates that a parity error occurred in the + * receiver. * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * If FIFOs are enabled, this status will be set when the character with + * the parity error is at the top of the receiver FIFO. This status is + * also set if a break interrupt occurred. + */ +#define UART_16550_LINE_STATUS_PE (1 << 2) + +/*! + * Overrun Error. This status indicates that an overrun occurred in the + * receiver. * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. + * If FIFOs are disabled, the arriving character will overwrite the + * existing character in the receiver. Any previously existing + * character(s) will be lost. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * If FIFOs are disabled, the arriving character will be discarded. The + * buffer will continue to contain the preexisting characters. */ +#define UART_16550_LINE_STATUS_OE (1 << 1) + +/*! + * Data Ready. This status indicates that the receiver or receiver FIFO + * contains at least one character. + */ +#define UART_16550_LINE_STATUS_DR (1 << 0) + + + +#ifndef MIN +#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#endif int32_t PutCharSCIF2(char outChar); int32_t GetCharSCIF2(char *inChar); +int32_t GetCharTimeOutSCIF2(char *inChar, uint64_t us); void PowerOnScif2(void); void WaitPutScif2SendEnd(void); -#ifdef RZG2_HIHOPE void InitScif2_SCIFCLK(void); -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 -void InitScif2_SCIFCLK_G2E(void); -#endif /* RZG2_EK874 */ -void SetScif2_DL(uint16_t setData); -void SetScif2_BRR(uint8_t setData); uint32_t SCIF_TerminalInputCheck(char* str); + +#endif /*SCIFDRV_H_*/ diff --git a/include/spiflash1drv.h b/include/spiflash1drv.h deleted file mode 100644 index a0a857d..0000000 --- a/include/spiflash1drv.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#define SPIREG_CR3V 0x00800004 //Volatile Status and Configuration Registers (CR3V) - -void Fast4RdQspiFlash(uint32_t sourceSpiAdd,uint32_t destinationAdd,uint32_t byteCount); -void FastRdQspiFlash(uint32_t sourceSpiAdd,uint32_t destinationAdd,uint32_t byteCount); -int32_t BulkEraseQspiFlash(void); -void PageProgramWithBuffeQspiFlash(uint32_t addr, uint32_t source_addr); -void ParameterSectorErase4kbQspiFlash(uint32_t addr); -void SaveDataWithBuffeQspiFlash(uint32_t srcAdd,uint32_t svFlashAdd,uint32_t svSize); -void SectorEraseQspi_Flash(uint32_t EraseStatAdd, uint32_t EraseEndAdd); -void ParameterSectorEraseQspiFlash(uint32_t EraseStatAdd,uint32_t EraseEndAdd); -void SectorRdQspiFlash(uint32_t spiStatAdd, uint32_t distRamAdd); diff --git a/include/types.h b/include/types.h index 16194ef..4097ccf 100644 --- a/include/types.h +++ b/include/types.h @@ -1,33 +1,25 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #ifndef TYPES_H #define TYPES_H @@ -74,26 +66,6 @@ typedef signed char BYTE; typedef signed short WORD; typedef signed long DWORD; -#if 0 -typedef unsigned long uint32; -typedef long int32; -typedef unsigned short uint16; -typedef short int16; -typedef unsigned char uint8; -typedef char int8; -typedef unsigned int uint; -typedef unsigned char bool8; -typedef unsigned long long uint64; - -typedef signed char int8_t; -typedef unsigned char uint8_t; -typedef signed short int16_t; -typedef unsigned short uint16_t; -typedef signed long int32_t; -typedef unsigned long uint32_t; -typedef unsigned long long int uint64_t; -#endif - typedef signed char B; /* signed 8-bit integer */ typedef long W; /* signed 32-bit integer */ typedef unsigned char UB; /* unsigned 8-bit integer */ diff --git a/include/usb_lib.h b/include/usb_lib.h deleted file mode 100644 index 3bee7b3..0000000 --- a/include/usb_lib.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef USB_LIB_H_ -#define USB_LIB_H_ - -/* return value for USB_GET_STATUS function */ -typedef enum { - ATTACHED, - POWERED, - DEFAULT, - ADDRESS, - CONFIGURED, - SUSPENDED -} State; - - -int32_t USB_Init(void); -int32_t USB_TerminalInputCheck(uint8_t *command_area); -void USB_IntCheck(void); -int USB_ReadCount(void); -int USB_ReadData(uint8_t *pBuff, int iDataSize); -int USB_WriteData(uint8_t *pBuff, int iDataSize); -void USB_ReadDataWithDMA(unsigned long bufferAddress, uint32_t totalDownloadSize); -State USB_Get_Status(void); - -#endif /* USB_LIB_H_ */ diff --git a/init_scif.c b/init_scif.c index 9f72003..35d7093 100644 --- a/init_scif.c +++ b/init_scif.c @@ -1,35 +1,26 @@ -/* - * Copyright (c) 2018-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ -#include "reg_rzg2.h" #include "common.h" #include "scifdrv.h" #include "init_scif.h" @@ -37,24 +28,6 @@ void InitScif(void) { - uint32_t product; + InitScif2_SCIFCLK(); - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - switch(product) - { -#ifdef RZG2_HIHOPE - case PRR_PRODUCT_G2H: - case PRR_PRODUCT_G2M: - case PRR_PRODUCT_G2N: - InitScif2_SCIFCLK(); - break; -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - case PRR_PRODUCT_G2E: - InitScif2_SCIFCLK_G2E(); - break; -#endif /* RZG2_EK874 */ - default: - break; - } } diff --git a/main.c b/main.c index d58cd41..fbcb1b5 100644 --- a/main.c +++ b/main.c @@ -1,208 +1,92 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ #include "common.h" #include "main.h" #include "dgtable.h" #include "bit.h" -#include "cpudrv.h" -#if EMMC == 1 #include "dgemmc.h" -#endif /* EMMC == 1 */ +#include "rdk_cmn_gic.h" #include "scifdrv.h" #include "devdrv.h" -#include "boardid.h" -#include "reg_rzg2.h" -#if USB_ENABLE == 1 -#include "usb_lib.h" -#endif /* USB_ENABLE == 1 */ +#include "init_scif.h" +#include "HardwareSetup.h" -#define WRITER_VERSION " V1.04" /* Software Version */ -#define WRITER_DATE " Dec.02,2020" /* Release date */ - -/* This definition sets the delay time in 10 milliseconds unit from */ -/* USB enumeration completion until the message is displayed. */ -#define USB_BANNER_DELAY_TIME (10 * 50) /* 5000ms */ +#define WRITER_VERSION " V1.00" /* Software Version */ +#define WRITER_DATE " July 9, 2021" /* Release date */ extern const com_menu MonCom[COMMAND_UNIT]; -extern uint8_t gCOMMAND_Area[COMMAND_BUFFER_SIZE]; char gKeyBuf[64]; int32_t gComNo; void Main(void) { - CheckBoard(); - InitMain(); + /* Initialize the GIC for core0 */ + Init_GIC(0); + + /* Set Pin Function */ + InitPFC(); + /* Initialize for CPG */ + InitCPG(); + + /* Initialize for System ram with RAMB */ + PowerOnRAMB(); + + /* Initialize for UART */ + InitScif(); + + /* Initialize for eMM */ + dg_init_emmc(); + + /* Output the stating messages */ StartMess(); + + /* Main routine */ DecCom(); } -void InitMain(void) -{ -#if EMMC == 1 - dg_init_emmc(); -#endif /* EMMC == 1 */ -#if USB_ENABLE == 1 - USB_Init(); -#endif /* USB_ENABLE == 1 */ -} void StartMess( void ) { uint32_t product; - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; PutStr(" ",1); PutStr("Flash writer for ",0); - switch (product) - { - case PRR_PRODUCT_G2H: - PutStr("RZ/G2H", 0); - break; - case PRR_PRODUCT_G2M: - PutStr("RZ/G2M", 0); - break; - case PRR_PRODUCT_G2N: - PutStr("RZ/G2N", 0); - break; - case PRR_PRODUCT_G2E: - PutStr("RZ/G2E", 0); - break; - default: - break; - } + PutStr("RZ/V2M", 0); PutStr(WRITER_VERSION, 0); PutStr(WRITER_DATE,1); PutStr(">", 0); } -#if USB_ENABLE == 1 -void StartMessUSB( void ) -{ - uint32_t product; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - PutStrUSB("Flash writer for ",0); - switch (product) - { - case PRR_PRODUCT_G2H: - PutStrUSB("RZ/G2H", 0); - break; - case PRR_PRODUCT_G2M: - PutStrUSB("RZ/G2M", 0); - break; - case PRR_PRODUCT_G2N: - PutStrUSB("RZ/G2N", 0); - break; - case PRR_PRODUCT_G2E: - PutStrUSB("RZ/G2E", 0); - break; - default: - break; - } - PutStrUSB(WRITER_VERSION, 0); - PutStrUSB(WRITER_DATE,1); -} -#endif - void DecCom(void) { char tmp[64], chCnt, chPtr; uint32_t rtn = 0; - uint32_t res; chCnt = 1; -#if USB_ENABLE == 1 - State usb_state; /* current USB state */ - State usb_state_before; /* lase USB state */ - int USB_banner = 0; /* 0:no display 1:display 2:displayed */ - int cnt; - - usb_state = USB_Get_Status(); - usb_state_before = usb_state; -#endif /* USB_ENABLE == 1 */ while (rtn == 0) { -#if USB_ENABLE == 1 - /* Display the boot message for USB connection */ - usb_state = USB_Get_Status(); - if (usb_state != usb_state_before) - { - usb_state_before = usb_state; - if (usb_state == CONFIGURED) - { - if (USB_banner == 0) - { - USB_banner = 1; - } - } - } - else if (usb_state == CONFIGURED) - { - if (USB_banner == 1) - { - StartTMU0(1); /* 10msec delay */ - cnt++; - /* Wait for specified time after USB connection is detected */ - if (cnt >= USB_BANNER_DELAY_TIME) - { - USB_banner = 2; - - PutStrUSB(" ",1); - StartMessUSB(); - PutStrUSB(">", 0); - } - } - } - - /* Confirm key input from USB */ - rtn = USB_TerminalInputCheck(gCOMMAND_Area); - if (rtn > 0) - { - gTerminal = USB_TERMINAL; - gKeyBuf[0] = gCOMMAND_Area[0]; - if (USB_banner == 1) - { - USB_banner = 2; - - PutStrUSB(" ",1); - StartMessUSB(); - PutStrUSB(">", 0); - } - } - USB_IntCheck(); - -#endif /* USB_ENABLE == 1 */ - if (rtn == 0) { rtn = SCIF_TerminalInputCheck(gKeyBuf); @@ -242,9 +126,6 @@ void DecCom(void) } PutStr(">",0); chCnt=0; -#if USB_ENABLE == 1 - USB_IntCheck(); -#endif /* USB_ENABLE == 1 */ } } diff --git a/makefile b/makefile deleted file mode 100644 index 0a590e0..0000000 --- a/makefile +++ /dev/null @@ -1,275 +0,0 @@ -# -# Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# Neither the name of ARM nor the names of its contributors may be used -# to endorse or promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -#/* Select BOARD("HIHOPE"or"EK874" )************** -ifeq ("$(BOARD)", "") -BOARD = HIHOPE -endif - -#/* Select USB("ENABLE"or"DISABLE" )******************************************** -ifeq ("$(USB)", "") -ifeq ("$(BOARD)", "EK874") -USB = DISABLE -else -USB = ENABLE -endif -endif - -#/* Select BOOT("WRITER"or"WRITER_WITH_CERT" )************************* -ifeq ("$(BOOT)", "") -BOOT = WRITER_WITH_CERT -endif - -#/* Select SERIAL_FLASH("ENABLE"or"DISABLE" )*********************************** -ifeq ("$(SERIAL_FLASH)", "") -SERIAL_FLASH = ENABLE -endif - -#/* Select EMMC("ENABLE"or"DISABLE" )******************************************* -ifeq ("$(EMMC)", "") -ifeq ("$(BOARD)", "EK874") -EMMC = DISABLE -else -EMMC = ENABLE -endif -endif - -#CPU -CPU = -march=armv8-a -AArch = 64 -THUMB = -AS_NEON = -CC_NEON = -mgeneral-regs-only -ALIGN = -mstrict-align -AArch32_64 = AArch64 -BOOTDIR = AArch64_boot -OUTPUT_DIR = AArch64_output -OBJECT_DIR = AArch64_obj -CROSS_COMPILE ?= aarch64-elf- - -ifeq ("$(BOARD)", "EK874") - BOARD_NAME = EK874 - FILENAME_ADD = _ek874 - CFLAGS += -DRZG2_EK874=1 -else - BOARD_NAME = HIHOPE - FILENAME_ADD = _hihope - CFLAGS += -DRZG2_HIHOPE=1 -endif - -ifeq ("$(BOOT)", "WRITER") - BOOT_DEF = Writer - FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Flash_writer_SCIF_E6304000$(FILENAME_ADD) -ifeq ("$(BOARD)", "EK874") - MEMORY_DEF = memory_writer_small.def -else - MEMORY_DEF = memory_writer.def -endif -endif - -ifeq ("$(BOOT)", "WRITER_WITH_CERT") - BOOT_DEF = Writer - FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Flash_writer_SCIF_DUMMY_CERT_E6300400$(FILENAME_ADD) -ifeq ("$(BOARD)", "EK874") - MEMORY_DEF = memory_writer_small_with_cert.def -else - MEMORY_DEF = memory_writer_with_cert.def -endif -endif - -ifeq ("$(USB)", "ENABLE") - CFLAGS += -DUSB_ENABLE=1 -endif - -ifeq ("$(USB)", "DISABLE") - CFLAGS += -DUSB_ENABLE=0 -endif - -ifeq ("$(SERIAL_FLASH)", "ENABLE") - CFLAGS += -DSERIAL_FLASH=1 -else - CFLAGS += -DSERIAL_FLASH=0 -endif - -ifeq ("$(EMMC)", "ENABLE") - CFLAGS += -DEMMC=1 -else - CFLAGS += -DEMMC=0 -endif - -DDR_DEF = ddr_qos_init_setting - -LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc -LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc -ifeq ("$(USB)", "ENABLE") -LIBS += -L./AArch64_lib/ -lusb -endif - -INCLUDE_DIR = include -DDR_DIR = ddr -TOOL_DEF = "REWRITE_TOOL" - -OUTPUT_FILE = $(FILE_NAME).axf - -#Object file -OBJ_FILE_BOOT = \ - $(OBJECT_DIR)/boot_mon.o \ - $(OBJECT_DIR)/stack.o - -SRC_FILE := \ - main.c \ - init_scif.c \ - scifdrv.c \ - devdrv.c \ - common.c \ - dgtable.c \ - dgmodul1.c \ - Message.c \ - dmaspi.c \ - ramckmdl.c \ - cpudrv.c \ - boardid.c \ - boot_init_lbsc.c \ - boot_init_port.c \ - boot_init_gpio.c \ - micro_wait.c \ - ddrcheck.c - -ifeq ("$(SERIAL_FLASH)", "ENABLE") -SRC_FILE += \ - dgmodul4.c \ - rpcqspidrv.c \ - spiflash1drv.c -endif - -ifeq ("$(EMMC)", "ENABLE") -SRC_FILE += \ - dg_emmc_config.c \ - dg_emmc_access.c \ - emmc_cmd.c \ - emmc_init.c \ - emmc_interrupt.c \ - emmc_mount.c \ - emmc_write.c \ - emmc_erase.c \ - emmc_utility.c -endif - -ifeq ("$(BOOT)", "WRITER_WITH_CERT") - SRC_FILE += cert_param.c -endif - -ifeq ("$(BOARD)", "EK874") -include ddr/ddr3l/ddr.mk -else -include ddr/lpddr4/ddr.mk -endif - -OBJ_FILE := $(addprefix $(OBJECT_DIR)/,$(patsubst %.c,%.o,$(SRC_FILE))) - -#Dependency File -DEPEND_FILE = $(patsubst %.lib, ,$(OBJ_FILE:%.o=%.d)) - -################################################### -#C compiler -CC ?= $(CROSS_COMPILE)gcc -#Assembler -AS ?= $(CROSS_COMPILE)as -#Linker -LD ?= $(CROSS_COMPILE)ld -#Liblary -AR ?= $(CROSS_COMPILE)ar -#Object dump -OBJDUMP ?= $(CROSS_COMPILE)objdump -#Object copy -OBJCOPY ?= $(CROSS_COMPILE)objcopy - -#clean -CL = rm -rf - -################################################### -# Suffixes -.SUFFIXES : .s .c .o - -################################################### -# Command - -.PHONY: all -all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OBJ_FILE_BOOT) $(OBJ_FILE) $(OUTPUT_FILE) - -#------------------------------------------ -# Make Directory -#------------------------------------------ -$(OBJECT_DIR): - -mkdir "$(OBJECT_DIR)" - -$(OUTPUT_DIR): - -mkdir "$(OUTPUT_DIR)" - -#------------------------------------------ -# Compile -#------------------------------------------ -$(OBJECT_DIR)/%.o:$(BOOTDIR)/%.s - $(AS) -g $(CPU) $(AS_NEON) --MD $(patsubst %.o,%.d,$@) -I $(BOOTDIR) -I $(INCLUDE_DIR) -I $(DDR_DIR) $< -o $@ --defsym $(AArch32_64)=0 --defsym $(BOOT_DEF)=0 --defsym $(TOOL_DEF)=0 - -$(OBJECT_DIR)/%.o:%.c - @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi - $(CC) -g -Os $(ALIGN) $(CPU) $(CC_NEON) $(THUMB) -MMD -MP -c -I $(BOOTDIR) -I $(INCLUDE_DIR) -I $(DDR_DIR) $< -o $@ -D$(AArch32_64)=0 -D$(BOOT_DEF)=0 -D$(TOOL_DEF)=0 $(CFLAGS) -D$(DDR_DEF)=0 - -#------------------------------------------ -# Linker -#------------------------------------------ -$(OUTPUT_FILE): $(OBJ_FILE_BOOT) $(OBJ_FILE) $(MEMORY_DEF) - $(LD) $(OBJ_FILE_BOOT) $(OBJ_FILE) \ - -T '$(MEMORY_DEF)' \ - -o '$(OUTPUT_FILE)' \ - -Map '$(FILE_NAME).map' \ - -static \ - $(LIBS) - -# Make MOT file - $(OBJCOPY) -O srec --srec-forceS3 "$(OUTPUT_FILE)" "$(FILE_NAME).mot" - -# Make Binary file - $(OBJCOPY) -O binary "$(OUTPUT_FILE)" "$(FILE_NAME).bin" - -# Dis assemble - $(OBJDUMP) -d -S "$(OUTPUT_FILE)" > "$(FILE_NAME)_disasm.txt" - -# Time Stamp - @echo ========== %date% %time% ========== - @echo ========== !!! Compile Complete !!! ========== - - -.PHONY: clean -clean: - $(CL) $(OBJECT_DIR)/* $(OUTPUT_DIR)/* - --include $(DEPEND_FILE) diff --git a/makefile.linaro b/makefile.linaro index 48728db..6dd9a53 100644 --- a/makefile.linaro +++ b/makefile.linaro @@ -1,65 +1,24 @@ +# DISCLAIMER +# This software is supplied by Renesas Electronics Corporation and is only +# intended for use with Renesas products. No other uses are authorized. This +# software is owned by Renesas Electronics Corporation and is protected under +# all applicable laws, including copyright laws. +# THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +# THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +# LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +# AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +# TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +# ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +# FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +# ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +# BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# Renesas reserves the right, without notice, to make changes to this software +# and to discontinue the availability of this software. By using this software, +# you agree to the additional terms and conditions found by accessing the +# following link: +# http://www.renesas.com/disclaimer +# Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved.# # -# Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# Neither the name of ARM nor the names of its contributors may be used -# to endorse or promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -#/* Select BOARD("HIHOPE"or"EK874" )************** -ifeq ("$(BOARD)", "") -BOARD = HIHOPE -endif - -#/* Select USB("ENABLE"or"DISABLE" )******************************************** -ifeq ("$(USB)", "") -ifeq ("$(BOARD)", "EK874") -USB = DISABLE -else -USB = ENABLE -endif -endif - -#/* Select BOOT("WRITER"or"WRITER_WITH_CERT" )************************* -ifeq ("$(BOOT)", "") -BOOT = WRITER_WITH_CERT -endif - -#/* Select SERIAL_FLASH("ENABLE"or"DISABLE" )*********************************** -ifeq ("$(SERIAL_FLASH)", "") -SERIAL_FLASH = ENABLE -endif - -#/* Select EMMC("ENABLE"or"DISABLE" )******************************************* -ifeq ("$(EMMC)", "") -ifeq ("$(BOARD)", "EK874") -EMMC = DISABLE -else -EMMC = ENABLE -endif -endif #CPU CPU = -march=armv8-a @@ -74,123 +33,50 @@ OUTPUT_DIR = AArch64_output OBJECT_DIR = AArch64_obj CROSS_COMPILE ?= aarch64-elf- -ifeq ("$(BOARD)", "EK874") - BOARD_NAME = EK874 - FILENAME_ADD = _ek874 - CFLAGS += -DRZG2_EK874=1 -else - BOARD_NAME = HIHOPE - FILENAME_ADD = _hihope - CFLAGS += -DRZG2_HIHOPE=1 -endif - -ifeq ("$(BOOT)", "WRITER") - BOOT_DEF = Writer - FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Flash_writer_SCIF_E6304000$(FILENAME_ADD) -ifeq ("$(BOARD)", "EK874") - MEMORY_DEF = memory_writer_small.def -else - MEMORY_DEF = memory_writer.def -endif -endif - -ifeq ("$(BOOT)", "WRITER_WITH_CERT") - BOOT_DEF = Writer - FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Flash_writer_SCIF_DUMMY_CERT_E6300400$(FILENAME_ADD) -ifeq ("$(BOARD)", "EK874") - MEMORY_DEF = memory_writer_small_with_cert.def -else - MEMORY_DEF = memory_writer_with_cert.def -endif -endif +BOOT_DEF = Writer +FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_RZV2M_Flash_writer -ifeq ("$(USB)", "ENABLE") - CFLAGS += -DUSB_ENABLE=1 -endif - -ifeq ("$(USB)", "DISABLE") - CFLAGS += -DUSB_ENABLE=0 -endif - -ifeq ("$(SERIAL_FLASH)", "ENABLE") - CFLAGS += -DSERIAL_FLASH=1 -else - CFLAGS += -DSERIAL_FLASH=0 -endif - -ifeq ("$(EMMC)", "ENABLE") - CFLAGS += -DEMMC=1 -else - CFLAGS += -DEMMC=0 -endif - -DDR_DEF = ddr_qos_init_setting +MEMORY_DEF = memory_writer.def +CFLAGS += -DEMMC=1 LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc -ifeq ("$(USB)", "ENABLE") -LIBS += -L./AArch64_lib/ -lusb -endif INCLUDE_DIR = include -DDR_DIR = ddr TOOL_DEF = "REWRITE_TOOL" OUTPUT_FILE = $(FILE_NAME).axf #Object file OBJ_FILE_BOOT = \ - $(OBJECT_DIR)/boot_mon.o \ + $(OBJECT_DIR)/boot_mon.o \ + $(OBJECT_DIR)/vectors.o \ $(OBJECT_DIR)/stack.o SRC_FILE := \ main.c \ + devdrv.c \ init_scif.c \ scifdrv.c \ - devdrv.c \ common.c \ dgtable.c \ - dgmodul1.c \ Message.c \ - dmaspi.c \ ramckmdl.c \ - cpudrv.c \ - boardid.c \ - boot_init_lbsc.c \ - boot_init_port.c \ - boot_init_gpio.c \ - micro_wait.c \ - ddrcheck.c - -ifeq ("$(SERIAL_FLASH)", "ENABLE") -SRC_FILE += \ - dgmodul4.c \ - rpcqspidrv.c \ - spiflash1drv.c -endif - -ifeq ("$(EMMC)", "ENABLE") -SRC_FILE += \ - dg_emmc_config.c \ - dg_emmc_access.c \ + rdk_cmn_cpg.c \ + rdk_cmn_pmc.c \ + rdk_common.c \ + rdk_intc.c \ + rdk_pfc.c \ + HardwareSetup.c \ + dg_emmc_config.c \ + dg_emmc_access.c \ emmc_cmd.c \ emmc_init.c \ - emmc_interrupt.c \ - emmc_mount.c \ - emmc_write.c \ - emmc_erase.c \ + emmc_interrupt.c \ + emmc_mount.c \ + emmc_write.c \ + emmc_erase.c \ emmc_utility.c -endif - -ifeq ("$(BOOT)", "WRITER_WITH_CERT") - SRC_FILE += cert_param.c -endif - -ifeq ("$(BOARD)", "EK874") -include ddr/ddr3l/ddr.mk -else -include ddr/lpddr4/ddr.mk -endif OBJ_FILE := $(addprefix $(OBJECT_DIR)/,$(patsubst %.c,%.o,$(SRC_FILE))) @@ -211,6 +97,10 @@ OBJDMP = $(CROSS_COMPILE)objdump #Object copy OBJCOPY = $(CROSS_COMPILE)objcopy +#PYTHON +EXE_PYTHON = python3 +PY_FILE = gen_128Kbin/sumzero.py + #clean CL = rm -rf @@ -237,11 +127,11 @@ $(OUTPUT_DIR): # Compile #------------------------------------------ $(OBJECT_DIR)/%.o:$(BOOTDIR)/%.s - $(AS) -g $(CPU) $(AS_NEON) --MD $(patsubst %.o,%.d,$@) -I $(BOOTDIR) -I $(INCLUDE_DIR) -I $(DDR_DIR) $< -o $@ --defsym $(AArch32_64)=0 --defsym $(BOOT_DEF)=0 --defsym $(TOOL_DEF)=0 + $(AS) -g $(CPU) $(AS_NEON) --MD $(patsubst %.o,%.d,$@) -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ --defsym $(AArch32_64)=0 --defsym $(BOOT_DEF)=0 --defsym $(TOOL_DEF)=0 $(OBJECT_DIR)/%.o:%.c @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi - $(CC) -g -Os $(ALIGN) $(CPU) $(CC_NEON) $(THUMB) -MMD -MP -c -I $(BOOTDIR) -I $(INCLUDE_DIR) -I $(DDR_DIR) $< -o $@ -D$(AArch32_64)=0 -D$(BOOT_DEF)=0 -D$(TOOL_DEF)=0 $(CFLAGS) -D$(DDR_DEF)=0 + $(CC) -g -Os $(ALIGN) $(CPU) $(CC_NEON) $(THUMB) -MMD -MP -c -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ -D$(AArch32_64)=0 -D$(BOOT_DEF)=0 -D$(TOOL_DEF)=0 $(CFLAGS) #------------------------------------------ # Linker @@ -259,10 +149,12 @@ $(OUTPUT_FILE): $(OBJ_FILE_BOOT) $(OBJ_FILE) $(MEMORY_DEF) # Make Binary file $(OBJCOPY) -O binary "$(OUTPUT_FILE)" "$(FILE_NAME).bin" + $(EXE_PYTHON) $(PY_FILE) $(FILE_NAME).bin $(OUTPUT_DIR)/B2_intSW.bin + # Dis assemble $(OBJDMP) -d -S "$(OUTPUT_FILE)" > "$(FILE_NAME)_disasm.txt" - + # Time Stamp @echo ========== %date% %time% ========== @echo ========== !!! Compile Complete !!! ========== diff --git a/memory_writer.def b/memory_writer.def index e6419ac..66af5cd 100644 --- a/memory_writer.def +++ b/memory_writer.def @@ -1,70 +1,75 @@ -/* - * Copyright (c) 2015-2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/* DISCLAIMER +# This software is supplied by Renesas Electronics Corporation and is only +# intended for use with Renesas products. No other uses are authorized. This +# software is owned by Renesas Electronics Corporation and is protected under +# all applicable laws, including copyright laws. +# THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +# THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +# LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +# AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +# TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +# ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +# FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +# ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +# BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# Renesas reserves the right, without notice, to make changes to this software +# and to discontinue the availability of this software. By using this software, +# you agree to the additional terms and conditions found by accessing the +# following link: +# http://www.renesas.com/disclaimer +# Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved.# +*/ +EL3_STACK_SIZE = DEFINED(_EL3_STACK_SIZE) ? _EL3_STACK_SIZE : 0x2000; MEMORY { - RAM (rwxa): ORIGIN = 0xE6304000, LENGTH = 0x0002A800 - RAM2 (rwxa): ORIGIN = 0xE632E800, LENGTH = 0x00031800 + RAMA (rw) : ORIGIN = 0x80100000, LENGTH = 0x00032000 } +ENTRY(_boot) + SECTIONS { + .vect : ALIGN(4096) { + KEEP (*(.vectors)) + } > RAMA + + .boot : { + KEEP (*(.boot)) + } > RAMA + .text : { *(.text*) *(.rodata*) . = NEXT(64); __RO_END__ = .; - } > RAM + } > RAMA .data : { __DATA_START__ = .; *(.data) . = NEXT(64); __DATA_END__ = .; - } > RAM + } > RAMA __DATA_SIZE__ = SIZEOF(.data); - .bss : { - __BSS_START__ = .; - *(.bss) - *(COMMON) - . = NEXT(64); - __BSS_END__ = .; - } > RAM2 + .bss (NOLOAD) : ALIGN( 0x20 ) { + __bss_start = .; + _fbss = . ; + * (.bss .bss.*) + * (COMMON) + . = ALIGN( 0x8 ); + __bss_end = .; + _end = . ; + _heap = . ; + } > RAMA stacks (NOLOAD) : ALIGN(64) { - __STACKS_START__ = .; - KEEP(*(writer_stack)) - __STACKS_END__ = .; - } > RAM2 + . = ALIGN(64); + _el3_stack_end = .; + . += EL3_STACK_SIZE; + __el3_stack = .; + } > RAMA __BSS_SIZE__ = SIZEOF(.bss); } diff --git a/memory_writer_small.def b/memory_writer_small.def deleted file mode 100644 index 8c17987..0000000 --- a/memory_writer_small.def +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -MEMORY { - RAM (rwxa): ORIGIN = 0xE6304000, LENGTH = 0x00014000 - RAM2 (rwxa): ORIGIN = 0xE6318000, LENGTH = 0x00008000 -} - -SECTIONS -{ - .text : { - *(.text*) - *(.rodata*) - . = NEXT(64); - __RO_END__ = .; - } > RAM - - .data : { - __DATA_START__ = .; - *(.data) - . = NEXT(64); - __DATA_END__ = .; - } > RAM - - __DATA_SIZE__ = SIZEOF(.data); - - .bss : { - __BSS_START__ = .; - *(.bss) - *(COMMON) - . = NEXT(64); - __BSS_END__ = .; - } > RAM2 - - stacks (NOLOAD) : ALIGN(64) { - __STACKS_START__ = .; - KEEP(*(writer_stack)) - __STACKS_END__ = .; - } > RAM2 - - __BSS_SIZE__ = SIZEOF(.bss); -} diff --git a/memory_writer_small_with_cert.def b/memory_writer_small_with_cert.def deleted file mode 100644 index 484f086..0000000 --- a/memory_writer_small_with_cert.def +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -MEMORY { - CERT (rwxa): ORIGIN = 0xE6300400, LENGTH = 0x00003C00 - RAM (rwxa): ORIGIN = 0xE6304000, LENGTH = 0x00014000 - RAM2 (rwxa): ORIGIN = 0xE6318000, LENGTH = 0x00008000 -} - -SECTIONS -{ - .cert : { - . = 0x00000000; - KEEP(*(.boot_param)) - . = 0x0000008C; - KEEP(*(.cert_offset)) - . = 0x000001D4; - KEEP(*(.cert_addr)) - . = 0x000002E4; - KEEP(*(.cert_size)) - . = 0x00000D54; - KEEP(*(.cert_addr2)) - . = 0x00000E64; - KEEP(*(.cert_size2)) - } > CERT - - .text : { - *(.text*) - *(.rodata*) - . = NEXT(64); - __RO_END__ = .; - } > RAM - - .data : { - __DATA_START__ = .; - *(.data) - . = NEXT(64); - __DATA_END__ = .; - } > RAM - - __DATA_SIZE__ = SIZEOF(.data); - - .bss : { - __BSS_START__ = .; - *(.bss) - *(COMMON) - . = NEXT(64); - __BSS_END__ = .; - } > RAM2 - - stacks (NOLOAD) : ALIGN(64) { - __STACKS_START__ = .; - KEEP(*(writer_stack)) - __STACKS_END__ = .; - } > RAM2 - - __BSS_SIZE__ = SIZEOF(.bss); -} diff --git a/memory_writer_with_cert.def b/memory_writer_with_cert.def deleted file mode 100644 index 3294ad1..0000000 --- a/memory_writer_with_cert.def +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2015-2018, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -MEMORY { - CERT (rwxa): ORIGIN = 0xE6300400, LENGTH = 0x00003C00 - RAM (rwxa): ORIGIN = 0xE6304000, LENGTH = 0x0002A800 - RAM2 (rwxa): ORIGIN = 0xE632E800, LENGTH = 0x00031800 -} - -SECTIONS -{ - .cert : { - . = 0x00000000; - KEEP(*(.boot_param)) - . = 0x0000008C; - KEEP(*(.cert_offset)) - . = 0x000001D4; - KEEP(*(.cert_addr)) - . = 0x000002E4; - KEEP(*(.cert_size)) - . = 0x00000D54; - KEEP(*(.cert_addr2)) - . = 0x00000E64; - KEEP(*(.cert_size2)) - } > CERT - - .text : { - *(.text*) - *(.rodata*) - . = NEXT(64); - __RO_END__ = .; - } > RAM - - .data : { - __DATA_START__ = .; - *(.data) - . = NEXT(64); - __DATA_END__ = .; - } > RAM - - __DATA_SIZE__ = SIZEOF(.data); - - .bss : { - __BSS_START__ = .; - *(.bss) - *(COMMON) - . = NEXT(64); - __BSS_END__ = .; - } > RAM2 - - stacks (NOLOAD) : ALIGN(64) { - __STACKS_START__ = .; - KEEP(*(writer_stack)) - __STACKS_END__ = .; - } > RAM2 - - __BSS_SIZE__ = SIZEOF(.bss); -} diff --git a/micro_wait.c b/micro_wait.c deleted file mode 100644 index f6ea666..0000000 --- a/micro_wait.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "mmio.h" -/** add for debug_env*/ -#define GPIO_INDT1 (0xE605100CU) -void micro_wait(uint32_t count_us){ - int32_t i; - volatile uint32_t tmp; - // for(i=0;i +#include + +#include "rdk_common.h" +#include "rdk_cmn_cpg.h" + +#define CPG_NO_REGISTER_OFFSET (0xFFFFFFFF) +#define CPG_TIMEOUT_UNIT_IS_US (10) + +typedef struct +{ + uint32_t pll_used_cnt[CPG_PLL_MAX+1]; +} st_cpg_priv_t; + +static st_cpg_priv_t gl_cpg_priv = +{ + .pll_used_cnt = { 0 }, +}; + +static st_cpg_pll_param_t pll1_param = +{ + .ssc.word = 0x00000004, + .clk.word[0] = 0x000014C2, + .clk.word[1] = 0x00150801 +}; + +static st_cpg_pll_param_t pll2_param = +{ + .ssc.word = 0x00000004, + .clk.word[0] = 0x00001903, + .clk.word[1] = 0x000E0E00 +}; + +/** 600MHz w/o SSCG */ +static st_cpg_pll_param_t pll3_param = +{ + .ssc.word = 0x00000000, + .clk.word[0] = 0x00001903, + .clk.word[1] = 0x00100800 +}; + +static st_cpg_pll_param_t pll4_param = +{ + .ssc.word = 0x00000000, + .clk.word[0] = 0x00001802, + .clk.word[1] = 0x00000002 +}; + +static st_cpg_pll_param_t pll6_param = +{ + .ssc.word = 0x00000000, + .clk.word[0] = 0x00001A42, + .clk.word[1] = 0x00150A01 +}; + +static st_cpg_pll_param_t pll7_param = +{ + .ssc.word = 0x00000004, + .clk.word[0] = 0x000018C2, + .clk.word[1] = 0x00150A01 +}; + +static st_cpg_pll_param_t * const gl_priv_pll_param_tbl[CPG_PLL_MAX+1] = +{ + NULL, + &pll1_param, + &pll2_param, + &pll3_param, + &pll4_param, + NULL, + &pll6_param, + &pll7_param +}; + +static const uint32_t gl_priv_pll_top_offset_table[CPG_PLL_MAX+1] = +{ + CPG_NO_REGISTER_OFFSET, + CPG_PLL1_STBY, + CPG_PLL2_STBY, + CPG_PLL3_STBY, + CPG_PLL4_STBY, + CPG_NO_REGISTER_OFFSET, + CPG_PLL6_STBY, + CPG_PLL7_STBY, +}; + +#define CPG_REG_WEN_SHIFT (16) +#define CPG_SET_DATA_MASK (0x0000FFFFUL) + +#define CPG_PLLN_STBY_OFFSET (0x00) +#define CPG_PLLN_CLK1_OFFSET (0x04) +#define CPG_PLLN_CLK2_OFFSET (0x08) +#define CPG_PLLN_MON_OFFSET (0x0C) + +#define CPG_PLL_CCTRL_REG_EXIT_FLAGS (0x0000009E) + +#define CPG_TIMEOUT_UNIT_IN_US (10) +#define CPG_PLL_TURN_MODE_TIMEOUT (500000) +#define CPG_CLK_FINISH_CHANGE_TIMEOUT (500000) +#define CPG_PLL_LOCKED (CPG_PLL_MON_PLL_LOCK) + + +#define CPG_WAIT_EVENT_PLL(m_pll, m_toc, m_err_code, m_condition, m_rslt) \ + { \ + uint32_t count = (m_toc); \ + uint32_t data; \ + while (true) { \ + CPG_GetStatusPLL((m_pll), &data); \ + if ((m_condition) == (data & CPG_PLL_LOCKED)) { \ + (m_rslt) = CMN_SUCCESS; \ + break; \ + } \ + if ((0 == (m_toc)) || (0 < count)) { \ + CMN_DelayInUS(CPG_TIMEOUT_UNIT_IN_US); \ + count--; \ + } else { \ + (m_rslt) = (m_err_code); \ + break; \ + } \ + } \ + } + +#define CPG_WAIT_EVENT(m_toc, m_err_code, m_condition, m_rslt) \ + { \ + uint32_t count = (m_toc)/CPG_TIMEOUT_UNIT_IN_US; \ + while (true) { \ + if ((m_condition)) { \ + (m_rslt) = CMN_SUCCESS; \ + break; \ + } \ + if ((0 == (m_toc)) || (0 < count)) { \ + CMN_DelayInUS(CPG_TIMEOUT_UNIT_IN_US); \ + count--; \ + } else { \ + (m_rslt) = (m_err_code); \ + break; \ + } \ + } \ + } + +uint32_t CPG_ReadReg(uint32_t offset) +{ + return (CMN_REG_Read32(CPG_BASE_ADDRESS + offset)); +} + +void CPG_WriteReg(uint32_t offset, uint32_t value) +{ + CMN_REG_Write32((CPG_BASE_ADDRESS + offset), value); +} + + +int32_t CPG_MoveToActivePLL(e_cpg_pll_num_t pll_num, st_cpg_pll_param_t *p_set_data) +{ + uint32_t offset; + uint32_t value; + + if ((pll_num < CPG_PLL_MIN) || (CPG_PLL_MAX < pll_num)) + { + return (CPG_ERROR_NO_REGISTER); + } + + offset = gl_priv_pll_top_offset_table[pll_num]; + if (CPG_NO_REGISTER_OFFSET == offset) + { + return (CPG_ERROR_NO_REGISTER); + } + + value = CPG_ReadReg(offset+CPG_PLLN_MON_OFFSET); + if (0 != (value & CPG_PLL_MON_RESETB)) + { + return (CPG_ERROR_PLL_ACTIVE); + } + + if (NULL != p_set_data) + { + value = p_set_data->clk.word[0]; + CPG_WriteReg(offset+CPG_PLLN_CLK1_OFFSET, value); + value = p_set_data->clk.word[1]; + CPG_WriteReg(offset+CPG_PLLN_CLK2_OFFSET, value); + value = p_set_data->ssc.word; + }else + { + value = CPG_ReadReg(offset+CPG_PLLN_STBY_OFFSET); + } + + if (4 == pll_num) + { + value = 0x00010001; + }else + { + value |= 0x00150001; + value = 0x00050001; /* Setting up 1chip sim environment */ + } + + CPG_WriteReg(offset+CPG_PLLN_STBY_OFFSET, value); + + return (CMN_SUCCESS); +} + +int32_t CPG_GetStatusPLL(e_cpg_pll_num_t pll_num, uint32_t *p_data) +{ + uint32_t offset; + if ((pll_num < CPG_PLL_MIN) || (CPG_PLL_MAX < pll_num)) + { + return (CPG_ERROR_NO_REGISTER); + } + + offset = gl_priv_pll_top_offset_table[pll_num]; + if (CPG_NO_REGISTER_OFFSET == offset) + { + return (CPG_ERROR_NO_REGISTER); + } + + if (NULL == p_data) + { + return (CPG_ERROR_NULL_POINTER); + } + + offset += CPG_PLLN_MON_OFFSET; + + *p_data = CPG_ReadReg(offset); + + return (CMN_SUCCESS); +} + + +void CPG_SetDifClkFreq(e_cpg_divsel_t target_reg, uint16_t target, uint16_t set_value) +{ + uint32_t offset = CPG_CA53_DDIV; + uint32_t value; + + while (true) + { + if (0 == (CPG_ReadReg(CPG_CLKSTATUS) & CPG_CLKSTATUS_DIVX)) + { + break; + } + CMN_DelayInUS(CPG_TIMEOUT_UNIT_IN_US); + } + + offset += (target_reg * sizeof(uint32_t)); + + value = ((uint32_t)target << CPG_REG_WEN_SHIFT) + | (set_value & CPG_MMCDDI_DDIV_DIVX_SET_MSK); + + CPG_WriteReg(offset, value); + + while (true) + { + if (0 == (CPG_ReadReg(CPG_CLKSTATUS) & CPG_CLKSTATUS_DIVX)) + { + break; + } + CMN_DelayInUS(CPG_TIMEOUT_UNIT_IN_US); + } +} + + +int32_t CPG_SetClockCtrl(uint8_t reg_num, uint16_t target, uint16_t set_value) +{ + uint32_t offset = CPG_CLK_ON1; + uint32_t value; + + if (reg_num < CPG_CLK_ON_REG_MIN || CPG_CLK_ON_REG_MAX < reg_num) + { + return (CPG_ERROR_NO_REGISTER); + } + + offset += ((reg_num - 1) * sizeof(uint32_t)); + + value = ((uint32_t)target << CPG_REG_WEN_SHIFT) + | (set_value & CPG_SET_DATA_MASK); + + CPG_WriteReg(offset, value); + + return (CMN_SUCCESS); +} + +int32_t CPG_GetClockCtrl(uint8_t reg_num, uint32_t *p_data) +{ + uint32_t offset = CPG_CLK_ON1; + + if (reg_num < CPG_CLK_ON_REG_MIN || CPG_CLK_ON_REG_MAX < reg_num) + { + return (CPG_ERROR_NO_REGISTER); + } + if (NULL == p_data) + { + return (CPG_ERROR_NULL_POINTER); + } + + offset += ((reg_num - 1) * sizeof(uint32_t)); + + *p_data = CPG_ReadReg(offset); + + return (CMN_SUCCESS); +} + + +int32_t CPG_SetResetCtrl(uint8_t reg_num, uint16_t target, uint16_t set_value) +{ + uint32_t offset = CPG_RST1; + uint32_t value; + + if (reg_num < CPG_RST_REG_MIN || CPG_RST_REG_MAX < reg_num) + { + return (CPG_ERROR_NO_REGISTER); + } + + offset += ((reg_num - 1) * sizeof(uint32_t)); + + value = ((uint32_t)target << CPG_REG_WEN_SHIFT) | (set_value & CPG_SET_DATA_MASK); + + CPG_WriteReg(offset, value); + + return (CMN_SUCCESS); +} + + +int32_t CPG_SetPDResetCtrl(uint16_t target, uint16_t set_value) +{ + uint32_t offset = CPG_PD_RST; + uint32_t value; + + value = ((uint32_t)target << CPG_REG_WEN_SHIFT) | (set_value & CPG_SET_DATA_MASK); + + CPG_WriteReg(offset, value); + + return (CMN_SUCCESS); +} + + +int32_t CPG_WaitResetMon(uint32_t timeout_c, uint32_t msk, uint32_t val) +{ + int32_t rslt = CMN_ERROR; + uint32_t count; + + do + { + if (0 == msk) + { + rslt = CMN_SUCCESS; + break; + } + + count = timeout_c; + while (true) + { + if (val == (CPG_ReadReg(CPG_RST_MON) & msk)) + { + rslt = CMN_SUCCESS; + break; + } + if ((0 == timeout_c) || (0 < count)) + { + CMN_DelayInUS(CPG_TIMEOUT_UNIT_IS_US); + count--; + }else + { + rslt = CPG_ERROR_TURN_RESET_TIMEOUT; + break; + } + } + } + while (0); + + return rslt; +} + + +int32_t cpg_resumePLL(e_cpg_pll_num_t pll_num) +{ + int32_t rslt; + uint32_t data; + st_cpg_pll_param_t *p_data = NULL; + + do + { + rslt = CPG_GetStatusPLL(pll_num, &data); + if (CMN_SUCCESS != rslt) + { + break; + } + if (0 != (data & CPG_PLL_LOCKED)) + { + rslt = CPG_ERROR_PLL_NOT_STANDBY | pll_num; + break; + } + + p_data = gl_priv_pll_param_tbl[pll_num]; + rslt = CPG_MoveToActivePLL(pll_num, p_data); + + if (CMN_SUCCESS != rslt) + { + break; + } + + CPG_WAIT_EVENT_PLL(pll_num, CPG_PLL_TURN_MODE_TIMEOUT, CPG_ERROR_PLL_TURN_MODE_TIMEOUT, CPG_PLL_LOCKED, rslt); + + if (CMN_SUCCESS != rslt) + { + break; + } + } + + while (0); + + return rslt; +} + +int32_t CPG_WakeUpPLL(e_cpg_pll_num_t pll_num) +{ + int32_t rslt = CMN_ERROR; + + do + { + if ((pll_num < CPG_PLL_MIN) || (CPG_PLL_MAX < pll_num)) + { + rslt = CPG_ERROR_NO_REGISTER; + break; + } + + if (0 == gl_cpg_priv.pll_used_cnt[pll_num]) + { + rslt = cpg_resumePLL(pll_num); + if (CMN_SUCCESS != rslt) + { + break; + } + gl_cpg_priv.pll_used_cnt[pll_num]++; + }else + { + gl_cpg_priv.pll_used_cnt[pll_num]++; + rslt = CMN_SUCCESS; + } + } + while (0); + + return rslt; +} + + +/*- End of file -*/ diff --git a/rdk_cmn_pmc.c b/rdk_cmn_pmc.c new file mode 100644 index 0000000..2489c9e --- /dev/null +++ b/rdk_cmn_pmc.c @@ -0,0 +1,92 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_cmn_pmc.c + * Version : 0.9 + * Description : operation functions for PMC + ******************************************************************************/ + +#include +#include + +#include "rdk_common.h" +#include "rdk_cmn_pmc.h" +#include "rdk_cmn_cpg.h" + +#define PMC_TIMEOUT_UNIT_IN_US (10) +#define PMC_SEQUENCE_POWER_ON_TIMEOUT (500000) +#define PMC_ISOLATION_OFF_TIMEOUT (500000) +#define PMC_CONNECTED_BUS_TIMEOUT (500000) +#define PMC_SEPARATED_BUS_TIMEOUT (500000) +#define PMC_ISOLATION_ON_TIMEOUT (500000) +#define PMC_SEQUENCE_POWER_OFF_TIMEOUT (500000) +#define PMC_RELEASE_RESET_TIMEOUT (500000) +#define PMC_HWFFC_CHG_STS_TIMEOUT (500000) + +#define PMC_WAIT_EVENT(m_toc, m_err_code, m_condition, m_rslt) \ + { \ + uint32_t count = (m_toc)/PMC_TIMEOUT_UNIT_IN_US; \ + while (true) { \ + if ((m_condition)) { \ + (m_rslt) = CMN_SUCCESS; \ + break; \ + } \ + if ((0 == (m_toc)) || (0 < count)) { \ + CMN_DelayInUS(PMC_TIMEOUT_UNIT_IN_US); \ + count--; \ + } else { \ + (m_rslt) = (m_err_code); \ + break; \ + } \ + } \ + } + +typedef struct +{ + uint8_t reg_num; + uint16_t target; + uint16_t value; +} st_cpg_setting_data_t; + +typedef struct +{ + uint32_t mem_time; + uint16_t pwron_time; +} st_pmc_local_t; + +static st_pmc_local_t gs_pmc_priv = +{ + .mem_time = 0x176F176F, /* PD_MEM External Power On/Off Wait: 2ms/2ms */ + .pwron_time = 0x176F, /* PD External Power On Wait: 2ms */ +}; + +uint32_t PMC_ReadReg(uint32_t offset) +{ + return (CMN_REG_Read32(PMC_BASE_ADDRESS + offset)); +} + +void PMC_WriteReg(uint32_t offset, uint32_t value) +{ + CMN_REG_Write32((PMC_BASE_ADDRESS + offset), value); +} + diff --git a/rdk_common.c b/rdk_common.c new file mode 100644 index 0000000..cb2aa89 --- /dev/null +++ b/rdk_common.c @@ -0,0 +1,120 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_common.c + * Description : operation functions for common + ******************************************************************************/ + +#include +#include "rdk_common.h" + +#define SYSCNT_FREQUENCY (24000000) +#define SYSCNT_BASE_ADDRESS (0xA3F00000) + +#define SYSCNT_CNTCR (0x0000) +#define SYSCNT_CNTCR_EN (1 << 0) +#define SYSCNT_CNTCV (0x0008) +#define SYSCNT_CNTFID0 (0x0020) + + +/******************************************************************************* + * Function Name: cmn_SYC_ReadReg + * Description : read access to System Counter register + * Arguments : uint32_t offset : SYC register offset + * Return Value : uint32_t : read data + ******************************************************************************/ +static inline uint32_t cmn_SYC_ReadReg(uint32_t offset) +{ + return (CMN_REG_Read32(SYSCNT_BASE_ADDRESS + offset)); +} + + +/******************************************************************************* + * Function Name: cmn_SYC_WriteReg + * Description : read access to System Counter register + * Arguments : uint32_t offset : SYC register offset + * : uint32_t value : write data + * Return Value : none + ******************************************************************************/ +static inline void cmn_SYC_WriteReg(uint32_t offset, uint32_t value) +{ + CMN_REG_Write32((SYSCNT_BASE_ADDRESS + offset), value); +} + + +/******************************************************************************* + * Function Name: CMN_InitSysCnt + * Description : initialize system counter + * Arguments : none + * Return Value : none + ******************************************************************************/ +void CMN_InitSysCnt(void) +{ + cmn_SYC_WriteReg(SYSCNT_CNTFID0, SYSCNT_FREQUENCY); + cmn_SYC_WriteReg(SYSCNT_CNTCR, SYSCNT_CNTCR_EN); +} + + +/******************************************************************************* + * Function Name: CMN_GetSysCnt + * Description : get system counter + * Arguments : none + * Return Value : system counter + ******************************************************************************/ +uint64_t CMN_GetSysCnt(void) +{ + return cmn_SYC_ReadReg(SYSCNT_CNTCV); +} + + +/******************************************************************************* + * Function Name: CMN_GetFreq4SysCnt + * Description : get system counter + * Arguments : none + * Return Value : system counter + ******************************************************************************/ +uint32_t CMN_GetFreq4SysCnt(void) +{ + return cmn_SYC_ReadReg(SYSCNT_CNTFID0); +} + + +/******************************************************************************* + * Function Name: CMN_DelayInUSec + * Description : delayed time in microsecond + * Arguments : + * us - + * delay times in microsecond + * Return Value : none + ******************************************************************************/ +void CMN_DelayInUSec(uint64_t us) +{ + uint64_t start = CMN_GetSysCnt(); + uint64_t cycles = (CMN_GetFreq4SysCnt() / 1000000UL) * us; + + while ((CMN_GetSysCnt() - start) < cycles) + { + asm volatile("nop"); + } +} +/*- End of File -*/ diff --git a/rdk_intc.c b/rdk_intc.c new file mode 100644 index 0000000..ae0b1fd --- /dev/null +++ b/rdk_intc.c @@ -0,0 +1,199 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_intc.c + * Version : 0.9 + * Description : operation functions for interrputs + ******************************************************************************/ + +#include + +#include "rdk_cmn_gic.h" +#include "rdk_common.h" + +/******************************************************************************* + * Function Name: CPG_ReadReg + * Description : Read the given GIC register + * + * Arguments : Offset is the register offset to be read + * Return Value : error code - + * + ******************************************************************************/ +uint32_t GIC_ReadReg(uint32_t offset) +{ + return (CMN_REG_Read32(GIC_BASE_ADDRESS + offset)); +} +/******************************************************************************* + End of function CPG_ReadReg + ******************************************************************************/ +/******************************************************************************* + * Function Name: GIC_WriteReg + * Description : Write the given GIC register + * Data is the 32-bit value to write to the register + * + * Arguments : Offset is the register offset to be written + * Return Value : error code - + * + ******************************************************************************/ +void GIC_WriteReg(uint32_t offset, uint32_t value) +{ + CMN_REG_Write32((GIC_BASE_ADDRESS + offset), value); +} +/******************************************************************************* + End of function GIC_WriteReg + ******************************************************************************/ +/*****************************************************************************/ +/** +* +* CfgInitialize a specific interrupt controller instance/driver. The +* initialization entails: +* +* - Initialize fields of the XScuGic structure +* - Initial vector table with stub function calls +* - All interrupt sources are disabled* +* @return +* None +* @note None. +* +******************************************************************************/ +static void GIC_CfgInitialize(uint32_t cpu_id) +{ + + uint32_t int_id; + uint32_t RegValue; + uint32_t local_cpu_id = ((uint32_t)0x1 << cpu_id); + local_cpu_id |= local_cpu_id << 8U; + local_cpu_id |= local_cpu_id << 16U; + + GIC_DistWriteReg(GIC_DIST_EN_OFFSET, 0U); + + for (int_id = 32U; int_id < GIC_MAX_NUM_INTR_INPUTS; + int_id = int_id + 4U) { + /* Remove interrupt target register */ + GIC_DistWriteReg(GIC_SPI_TARGET_OFFSET_CALC(int_id), 0); + + /* Disable all the interrupts */ + GIC_DistWriteReg( + GIC_EN_DIS_OFFSET_CALC(GIC_DISABLE_OFFSET, int_id), + 0xFFFFFFFFU); + } + + /* + * The trigger mode in the int_config register + * Only write to the SPI interrupts, so start at 32 + */ + for (int_id = 32U; int_id < GIC_MAX_NUM_INTR_INPUTS; + int_id = int_id + 16U) { + /* + * Each INT_ID uses two bits, or 16 INT_ID per register + * Set them all to be level sensitive, active HIGH. + */ + GIC_DistWriteReg(GIC_INT_CFG_OFFSET_CALC(int_id), 0U); + } + +#define DEFAULT_PRIORITY 0xa0a0a0a0U + for (int_id = 0U; int_id < GIC_MAX_NUM_INTR_INPUTS; + int_id = int_id + 4U) { + /* + * The priority using int the priority_level register + * The priority_level and spi_target registers use one byte per + * INT_ID. + * Write a default value that can be changed elsewhere. + */ + GIC_DistWriteReg(GIC_PRIORITY_OFFSET_CALC(int_id), + DEFAULT_PRIORITY); + } + + for (int_id = 32U; int_id < GIC_MAX_NUM_INTR_INPUTS; + int_id = int_id + 4U) { + /* + * The CPU interface in the spi_target register + * Only write to the SPI interrupts, so start at 32 + */ + GIC_DistWriteReg(GIC_SPI_TARGET_OFFSET_CALC(int_id), + local_cpu_id); + } + + for (int_id = 0U; int_id < GIC_MAX_NUM_INTR_INPUTS; + int_id = int_id + 32U) { + /* + * Enable the SPI using the enable_set register. Leave all + * disabled for now. + */ + /* clear pending status */ + GIC_DistWriteReg( + GIC_EN_DIS_OFFSET_CALC(GIC_PENDING_CLR_OFFSET, int_id), + 0xFFFFFFFFU); + + /* clear active status */ + GIC_DistWriteReg( + GIC_EN_DIS_OFFSET_CALC(GIC_ACTIVE_CLR_OFFSET, int_id), + 0xFFFFFFFFU); + } + + /* + * Program the priority mask of the CPU using the Priority mask register + */ + GIC_CPUWriteReg( GIC_CPU_PRIOR_OFFSET, GIC_CPU_PROPERTY_MSK_STEP16); + + /* Boot lader doesn't need interrupts via GIC so disable GICD/GICC */ +#if 0 + GIC_CPUWriteReg(GIC_CONTROL_OFFSET, 0x03U); + + GIC_DistWriteReg(GIC_DIST_EN_OFFSET, GIC_EN_INT_MASK); + /* + * If the CPU operates only in the secure domain, setup the + * control_s register. + * EnableGrp0[0] = 1 + * EnableGrp1[1] = 1 + * AckCtl[2] = 0 + * FIQEn[3] = 0 (using IRQ) + */ +#endif +} +/******************************************************************************* + End of function GIC_CfgInitialize + ******************************************************************************/ +/******************************************************************************* + * Function Name: Init_GIC + * Description : Interrupt controller driver initialization + * + * Arguments : cpu_id - interrupt target CPU No + * Return Value : error code - + * + ******************************************************************************/ +void Init_GIC(uint32_t cpu_id) +{ + + GIC_DistWriteReg(GIC_DIST_EN_OFFSET, 0U); + GIC_CPUWriteReg(GIC_BIN_PT_OFFSET, 0x2); + GIC_CPUWriteReg(GIC_CONTROL_OFFSET, 0x0); + GIC_CPUWriteReg(GIC_EOI_OFFSET, 0x0); + + GIC_CfgInitialize(cpu_id); + + return; +} +/******************************************************************************* + End of function INTC_Initalize + ******************************************************************************/ diff --git a/rdk_pfc.c b/rdk_pfc.c new file mode 100644 index 0000000..c806a60 --- /dev/null +++ b/rdk_pfc.c @@ -0,0 +1,685 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * File Name : rdk_pfc.c + * Description : operation functions for PFC + ******************************************************************************/ + +#include + +#include "rdk_common.h" +#include "rdk_pfc.h" + +#define PFC_PORT_NUM (22) +#define PFC_PORT_REGISTER_SIZE (0x00040) +#define PFC_PORT_WE_SHIFT (16) +#define PFC_PORT_PFSEL_PIN_NUM_IN_REG (4) +#define PFC_PORT_PFSEL_REG_NUM (4) + +typedef struct { + uint8_t pin_num; + union { + uint32_t word; + struct { + uint32_t gpio_do:1; + uint32_t gpio_oe:1; + uint32_t gpio_ie:1; + uint32_t :1; + uint32_t pfsel:4; + uint32_t di_mon:1; + uint32_t pupd:1; + uint32_t drv:1; + uint32_t sr:1; + uint32_t di_msk:1; + uint32_t en_msk:1; + } flag; + } exist_reg; +} st_pfc_internal_info_t; + +static const uint8_t g_PFC_flag_bit_position[10] = { + 0, /* PFC_PORT_GPIO_DO */ + 1, /* PFC_PORT_GPIO_OE */ + 2, /* PFC_PORT_GPIO_IE */ + 4, /* PFC_PORT_PFSEL */ + 8, /* PFC_PORT_DI_MON */ + 9, /* PFC_PORT_PUPD */ + 10, /* PFC_PORT_DRV */ + 11, /* PFC_PORT_SR */ + 12, /* PFC_PORT_DI_MSK */ + 13 /* PFC_PORT_EN_MSK */ +}; + +static const st_pfc_internal_info_t g_PFC_Port_Info[PFC_PORT_NUM] = { +{ + /** PORT00 **/ + .pin_num = 14, + .exist_reg.word = 0x3FF7, + }, + { + /** PORT01 **/ + .pin_num = 16, + .exist_reg.word = 0x3FF7, + }, + { + /** PORT02 **/ + .pin_num = 8, + .exist_reg.word = 0x3F37, + }, + { + /** PORT03 **/ + .pin_num = 16, + .exist_reg.word = 0x3FF7, + }, + { + /** PORT04 **/ + .pin_num = 8, + .exist_reg.word = 0x3F37, + }, + { + /** PORT05 **/ + .pin_num = 4, + .exist_reg.word = 0x3F17, + }, + { + /** PORT06 **/ + .pin_num = 12, + .exist_reg.word = 0x3F77, + }, + { + /** PORT07 **/ + .pin_num = 6, + .exist_reg.word = 0x3F37, + }, + { + /** PORT08 **/ + .pin_num = 8, + .exist_reg.word = 0x3F37, + }, + { + /** PORT09 **/ + .pin_num = 8, + .exist_reg.word = 0x3F37, + }, + { + /** PORT10 **/ + .pin_num = 9, + .exist_reg.word = 0x3F77, + }, + { + /** PORT11 **/ + .pin_num = 9, + .exist_reg.word = 0x3F77, + }, + { + /** PORT12 **/ + .pin_num = 4, + .exist_reg.word = 0x3F17, + }, + { + /** PORT13 **/ + .pin_num = 12, + .exist_reg.word = 0x3F77, + }, + { + /** PORT14 **/ + .pin_num = 8, + .exist_reg.word = 0x3F37, + }, + { + /** PORT15 **/ + .pin_num = 16, + .exist_reg.word = 0x3FF7, + }, + { + /** PORT16 **/ + .pin_num = 14, + .exist_reg.word = 0x3FF7, + }, + { + /** PORT17 **/ + .pin_num = 1, + .exist_reg.word = 0x3F17, + }, + { + /** (PORT18) **/ + .pin_num = 0, + .exist_reg.word = 0, + }, + { + /** (PORT19) **/ + .pin_num = 0, + .exist_reg.word = 0, + }, + { + /** PORT20 **/ + .pin_num = 3, + .exist_reg.word = 0x3517, + }, + { + /** PORT21 **/ + .pin_num = 1, + .exist_reg.word = 0x0D07, + }, +}; + + +static uint32_t pfc_GetBitMask(e_pfc_port_num_t port_num) +{ + uint32_t value = 0; + uint32_t shift = 0; + uint32_t pin_num = g_PFC_Port_Info[port_num].pin_num; + + if (0 != (pin_num & 0x010)) { + value |= (0x0FFFF << shift); + shift += 16; + } + if (0 != (pin_num & 0x008)) { + value |= (0x0FF << shift); + shift += 8; + } + if (0 != (pin_num & 0x004)) { + value |= (0x0F << shift); + shift += 4; + } + if (0 != (pin_num & 0x002)) { + value |= (0x03 << shift); + shift += 2; + } + if (0 != (pin_num & 0x001)) { + value |= (0x01 << shift); + shift += 1; + } + + return value; +} + +static uint32_t pfc_Get2BitMask(e_pfc_port_num_t port_num) +{ + uint32_t value = 0; + uint32_t shift = 0; + uint32_t pin_num = g_PFC_Port_Info[port_num].pin_num; + + if (0 != (pin_num & 0x010)) { + value |= (0xFFFFFFFF << shift); + shift += 32; + } + if (0 != (pin_num & 0x008)) { + value |= (0x0FFFF << shift); + shift += 16; + } + if (0 != (pin_num & 0x004)) { + value |= (0x0FF << shift); + shift += 8; + } + if (0 != (pin_num & 0x002)) { + value |= (0x0F << shift); + shift += 4; + } + if (0 != (pin_num & 0x001)) { + value |= (0x03 << shift); + shift += 2; + } + + return value; +} + + +uint32_t PFC_ReadReg(uint32_t offset) +{ + return CMN_REG_Read32(PFC_BASE_ADDRESS + offset); +} + +void PFC_WriteReg(uint32_t offset, uint32_t value) +{ + CMN_REG_Write32((PFC_BASE_ADDRESS + offset), value); +} + +int32_t PFC_SetPortParam(e_pfc_port_num_t port_num, e_pfc_kind_reg_t kind_reg, + uint16_t target, u_pfc_data_t *p_set_data) +{ + uint32_t offset = PFC_P00_GPIO_DO; + uint32_t value[4] = { 0 }; + uint32_t mask[4] = { 0 }; + int32_t rslt = CMN_SUCCESS; + int32_t i; + uint8_t pos; + + pos = g_PFC_flag_bit_position[kind_reg]; + if (0 == (g_PFC_Port_Info[port_num].exist_reg.word & (0x01 << pos))) { + return PFC_ERROR_NO_EXIST_REG; + } + + if (NULL == p_set_data) { + return PFC_ERROR_NULL_POINTER; + } + + offset += (port_num * PFC_PORT_REGISTER_SIZE); + offset += (pos * sizeof(uint32_t)); + + switch (kind_reg) { + case PFC_PORT_GPIO_DO: + case PFC_PORT_GPIO_OE: + case PFC_PORT_GPIO_IE: + case PFC_PORT_SR: + case PFC_PORT_DI_MSK: + case PFC_PORT_EN_MSK: + mask[0] = pfc_GetBitMask(port_num); + value[0] = (p_set_data->uh_data & mask[0]) | + ((target & mask[0]) << PFC_PORT_WE_SHIFT); + PFC_WriteReg(offset, value[0]); + break; + + case PFC_PORT_PFSEL: + for (i = 0; i < g_PFC_Port_Info[port_num].pin_num; i++) { + if (0 != (target & (0x0001 << i))) { + mask[i/PFC_PORT_PFSEL_PIN_NUM_IN_REG] |= + (0x00070007 + << (4 * + (i % PFC_PORT_PFSEL_PIN_NUM_IN_REG))); + } + } + + for (i = 0; i < PFC_PORT_PFSEL_REG_NUM; i++) { + value[i] = + (p_set_data->func_sel.half.sel[i]) | 0xFFFF0000UL; + value[i] &= mask[i]; + + if ((0 != + (g_PFC_Port_Info[port_num].exist_reg.flag.pfsel & + (0x01 << i))) && + 0 != value[i]) { + PFC_WriteReg(offset, value[i]); + } + offset += sizeof(uint32_t); + } + break; + + case PFC_PORT_PUPD: + case PFC_PORT_DRV: + for (i = 0; i < g_PFC_Port_Info[port_num].pin_num; i++) { + if (0 != (target & (0x0001 << i))) { + mask[0] |= (0x00000003 << (2 * i)); + } + } + mask[0] &= pfc_Get2BitMask(port_num); + if (PFC_PORT_PUPD == kind_reg) { + value[0] = p_set_data->pupd.word.pupd[0]; + } else /** if (PFC_PORT_DRV == kind_reg) */ + { + value[0] = p_set_data->drv_sel.word.drv_sel[0]; + } + value[0] &= mask[0]; + value[0] |= (PFC_ReadReg(offset) & (~mask[0])); + PFC_WriteReg(offset, value[0]); + break; + + case PFC_PORT_DI_MON: + default: + rslt = PFC_ERROR_NO_EXIST_REG; + break; + } + + return rslt; +} + +int32_t PFC_GetPortParam(e_pfc_port_num_t port_num, e_pfc_kind_reg_t kind_reg, + u_pfc_data_t *p_data) +{ + uint32_t offset = PFC_P00_GPIO_DO; + int32_t rslt = CMN_SUCCESS; + uint32_t value; + int32_t i; + uint8_t pos; + + pos = g_PFC_flag_bit_position[kind_reg]; + if (0 == (g_PFC_Port_Info[port_num].exist_reg.word & (0x01 << pos))) { + return PFC_ERROR_NO_EXIST_REG; + } + + if (NULL == p_data) { + return PFC_ERROR_NULL_POINTER; + } + + offset += (port_num * PFC_PORT_REGISTER_SIZE); + offset += (pos * 4UL); + + switch (kind_reg) { + case PFC_PORT_GPIO_DO: + case PFC_PORT_GPIO_OE: + case PFC_PORT_GPIO_IE: + case PFC_PORT_DI_MON: + case PFC_PORT_PUPD: + case PFC_PORT_DRV: + case PFC_PORT_SR: + case PFC_PORT_DI_MSK: + case PFC_PORT_EN_MSK: + p_data->uw_data = PFC_ReadReg(offset); + break; + + case PFC_PORT_PFSEL: + p_data->func_sel.word.sel[0] = 0; + p_data->func_sel.word.sel[1] = 0; + for (i = 0; i < PFC_PORT_PFSEL_REG_NUM; i++) { + value = 0; + if (0 != + (g_PFC_Port_Info[port_num].exist_reg.flag.pfsel & + (0x01 << i))) { + value = PFC_ReadReg(offset); + } + p_data->func_sel.half.sel[i] = (value & 0x0FFFF); + offset += sizeof(uint32_t); + } + break; + + default: + rslt = PFC_ERROR_NO_EXIST_REG; + break; + } + + return rslt; +} + +int32_t PFC_SetPortParamH(e_pfc_port_num_t port_num, e_pfc_kind_reg_t kind_reg, + uint16_t target, uint16_t set_data) +{ + int32_t res; + u_pfc_data_t data; + + data.uh_data = set_data; + + res = PFC_SetPortParam(port_num, kind_reg, target, &data); + + return res; +} + +int32_t PFC_SetCXRXD_SEL(uint16_t target, uint16_t set_data) +{ + uint32_t value; + + value = (set_data & target) | (((uint32_t)target) << PFC_PORT_WE_SHIFT); + + PFC_WriteReg( PFC_CSRXD_SEL, value); + + return PFC_SUCCESSED; +} + +int32_t PFC_GetCXRXD_SEL(uint16_t *p_data) +{ + if (NULL == p_data) { + return PFC_ERROR_NULL_POINTER; + } + + *p_data = PFC_ReadReg(PFC_CSRXD_SEL); + + return PFC_SUCCESSED; +} + +int32_t PFC_SetROP_DI_SEL(uint32_t set_data) +{ + PFC_WriteReg( PFC_ROP_DI_SEL, set_data); + + return PFC_SUCCESSED; +} + +int32_t PFC_GetROP_DI_SEL(uint32_t *p_data) +{ + if (NULL == p_data) { + return PFC_ERROR_NULL_POINTER; + } + + *p_data = PFC_ReadReg(PFC_ROP_DI_SEL); + + return PFC_SUCCESSED; +} + +int32_t PFC_SetPEXDRV(uint16_t target, u_pfc_pex_drv_t *p_set_data) +{ + uint32_t i; + uint32_t mask = 0; + uint32_t value; + uint16_t exist_bit = 0x5867; + + if (NULL == p_set_data) { + return PFC_ERROR_NULL_POINTER; + } + + for (i = 0; i < (sizeof(uint16_t) * 8); i++) { + if (0 != ((target & exist_bit) & (0x0001 << i))) { + mask |= (0x00000003 << (2 * i)); + } + } + + value = PFC_ReadReg(PFC_PEX0_DRV); + value &= ~(mask); + value |= (p_set_data->word.drv[0] & mask); + PFC_WriteReg(PFC_PEX0_DRV, value); + + return PFC_SUCCESSED; +} + +int32_t PFC_GetPEXDRV(uint32_t *p_data) +{ + if (NULL == p_data) { + return PFC_ERROR_NULL_POINTER; + } + + *p_data = PFC_ReadReg(PFC_PEX0_DRV); + + return PFC_SUCCESSED; +} + +int32_t PFC_SetPEXSR(uint16_t target, uint16_t set_data) +{ + uint32_t value; + + value = set_data | ((uint32_t)target << PFC_PORT_WE_SHIFT); + PFC_WriteReg(PFC_PEX0_SR, value); + + return PFC_SUCCESSED; +} + +int32_t PFC_GetPEXSR(uint32_t *p_data) +{ + if (NULL == p_data) { + return PFC_ERROR_NULL_POINTER; + } + + *p_data = PFC_ReadReg(PFC_PEX0_SR); + + return PFC_SUCCESSED; +} + +int32_t PFC_SetEXTINT(e_pfc_extint_reg_num_t reg_num, uint16_t target_pin, + uint16_t set_data) +{ + uint32_t offset = PFC_EXTINT_INV0; + uint32_t value; + + offset += reg_num * sizeof(uint32_t); + value = (set_data & target_pin) | + (((uint32_t)target_pin) << PFC_PORT_WE_SHIFT); + + PFC_WriteReg(offset, value); + + return PFC_SUCCESSED; +} + +int32_t PFC_GetEXTINT(e_pfc_extint_reg_num_t reg_num, uint32_t *p_data) +{ + uint32_t offset = PFC_EXTINT_INV0; + + if (NULL == p_data) { + return PFC_ERROR_NULL_POINTER; + } + + offset += reg_num * sizeof(uint32_t); + + *p_data = PFC_ReadReg(offset); + + return PFC_SUCCESSED; +} + +/***************************************************************************** + *****************************************************************************/ + +/* + * Set change pin function procduer + * 1. target pins are set mask to Pmm_DI_MSK + * 2. target pins are set enable mask to Pmm_EN_MSK + * 3. set change function to Pmm_PFSEL0-3 + * 4. target pins are set enable to Pmm_EN_MSK + * 5. target pins are set unmask to Pmm_DI_MSK + */ +/* + * EMM : Port00, pin 0-7 10-11, 2 + * URT0 : Port03, pin 0-3, 2 + */ +/* + * port#, target pin map, select# + */ +typedef struct { + uint32_t pin_pupd; + uint32_t pin_drv; + uint16_t pin_oe; + uint16_t pin_ie; + uint16_t pin_map; + uint16_t pin_sr; + uint8_t port; + uint8_t select; +} st_pfc_select_port_info_t; + +typedef struct { + uint32_t cnt; + const st_pfc_select_port_info_t *p_data; +} st_pfc_select_info_t; + +/* + * [pin_pupd] b00:pull-down / b10:pull-up / bX1:neither + * [pin_driv] b00:X1 / b01:X2 / b10:X4 / b11:X6 + * [pin_sr ] b0:FastSlew / b1:SlowSlew + */ + +static const st_pfc_select_port_info_t gl_pfc_select_emm[] = { + {.port = PFC_PORT00, + .select = 2, + .pin_map = 0x0CFFU, + .pin_oe = 0x0000U, + .pin_ie = 0x0000U, + .pin_pupd = 0x00505555, + .pin_drv = 0x00505555, + .pin_sr = 0x0CFFU}, +}; + +static const st_pfc_select_port_info_t gl_pfc_select_urt0[] = { + {.port = PFC_PORT03, + .select = 2, + .pin_map = 0x000FU, + .pin_oe = 0x0000U, + .pin_ie = 0x0000U, + .pin_pupd = 0x00000055, + .pin_drv = 0x00000055, + .pin_sr = 0x000FU}, +}; + + +#define PFC_SET_SELECT_TBL(m_ip_info) \ + .cnt = (sizeof(m_ip_info)/sizeof(st_pfc_select_port_info_t)), \ + .p_data = m_ip_info + +static const st_pfc_select_info_t gl_pfc_select_tbl[] = { + { PFC_SET_SELECT_TBL(gl_pfc_select_emm) }, + { PFC_SET_SELECT_TBL(gl_pfc_select_urt0) }, +}; + +int32_t PFC_SetPinFunc(e_pfc_select_ip_t tgt_ip) +{ + int32_t rslt; + uint32_t i; + uint32_t j; + const st_pfc_select_port_info_t *p_sel_info; + uint32_t cnt; + uint32_t port_num; + uint32_t pin_cnt; + u_pfc_pfsel_t sel_data; + uint16_t sel_pin; + uint32_t select_num; + u_pfc_pupd_t pupd_data; + u_pfc_drvsel_t drv_data; + uint16_t sr_data; + uint16_t oe_data; + uint16_t ie_data; + + do { + if (PFC_SELECT_NUM <= tgt_ip) { + rslt = PFC_ERROR_INVALID_ARG; + break; + } + + cnt = gl_pfc_select_tbl[tgt_ip].cnt; + p_sel_info = gl_pfc_select_tbl[tgt_ip].p_data; + + for (i = 0; i < cnt; i++) { + port_num = p_sel_info[i].port; + sel_pin = p_sel_info[i].pin_map; + select_num = p_sel_info[i].select; + pin_cnt = g_PFC_Port_Info[port_num].pin_num; + pupd_data.word.pupd[0] = p_sel_info[i].pin_pupd; + drv_data.word.drv_sel[0] = p_sel_info[i].pin_drv; + sr_data = p_sel_info[i].pin_sr; + oe_data = p_sel_info[i].pin_oe; + ie_data = p_sel_info[i].pin_ie; + sel_data.word.sel[0] = 0; + sel_data.word.sel[1] = 0; + for (j = 0; j < pin_cnt; j++) { + if (0 != (sel_pin & (0x01U << j))) { + sel_data.word.sel[j/8] |= + (select_num << (j * 4)); + } + } + + (void)PFC_SetDI_MSK(port_num, sel_pin, sel_pin); + + (void)PFC_SetEN_MSK(port_num, sel_pin, sel_pin); + + (void)PFC_SetPFSEL(port_num, sel_pin, &sel_data); + + (void)PFC_SetGPIO_OE(port_num, sel_pin, oe_data); + + (void)PFC_SetGPIO_IE(port_num, sel_pin, ie_data); + + (void)PFC_SetEN_MSK(port_num, sel_pin, 0); + + (void)PFC_SetDI_MSK(port_num, sel_pin, 0); + + (void)PFC_SetPUPD(port_num, sel_pin, &pupd_data); + + (void)PFC_SetDRV(port_num, sel_pin, &drv_data); + + (void)PFC_SetSR(port_num, sel_pin, sr_data); + } + rslt = CMN_SUCCESS; + } while (0); + + return rslt; +} + diff --git a/rpcqspidrv.c b/rpcqspidrv.c deleted file mode 100644 index 0d96fd5..0000000 --- a/rpcqspidrv.c +++ /dev/null @@ -1,1510 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "rpcqspidrv.h" -#include "reg_rzg2.h" -#include "bit.h" -#include "cpudrv.h" - -void InitRPC_QspiFlashQuadExtMode(void) -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - } - *((volatile uint32_t*)RPC_CMNCR) = 0x01FFF300; - *((volatile uint32_t*)RPC_DRCR) = 0x001F0100; - //bit20-16 RBURST[4:0] = 11111 : 32 continuous data unit - //bit8 RBE = 1 : Burst read - *((volatile uint32_t*)RPC_DRCMR) = 0x006C0000; - //bit23-16 CMD[7:0] = 0x6C : Quad Output Read 4-byte address command - - *((volatile uint32_t*)RPC_DREAR) = 0x00000001; - //bit23-16 EAV[7:0] = 0 : ADR[32:26] output set0 - //bit2-0 EAC[2:0] = 001 : ADR[25:0 ] Enable - - *((volatile uint32_t*)RPC_DRENR) = 0x0002CF00; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 DRDB[1:0] = 10 : 4bit width transfer data (QSPI0_IO0-3) - //bit15 DME = 1 : dummy cycle enable - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) - *((volatile uint32_t*)RPC_DRDMCR) = 0x00000007; - //bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait - *((volatile uint32_t*)RPC_DRDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 DRDRE = 0 : DATA SDR transfer -} - -void InitRPC_QspiFlash4FastReadExtMode(void) -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - } - *((volatile uint32_t*)RPC_CMNCR) = 0x01FFF300; - *((volatile uint32_t*)RPC_DRCR) = 0x001F0100; - //bit20-16 RBURST[4:0] = 11111 : 32 continuous data unit - //bit8 RBE = 1 : Burst read - *((volatile uint32_t*)RPC_DRCMR) = 0x000C0000; - //bit23-16 CMD[7:0] = 0x0C : 4FAST_READ 0Ch Command 4-byte address command - - *((volatile uint32_t*)RPC_DREAR) = 0x00000001; - //bit23-16 EAV[7:0] = 0 : ADR[32:26] output set0 - //bit2-0 EAC[2:0] = 001 : ADR[25:0 ] Enable - - *((volatile uint32_t*)RPC_DRENR) = 0x0000CF00; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 DRDB[1:0] = 00 : 1bit width transfer data (QSPI0_IO0) - //bit15 DME = 1 : dummy cycle enable - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[23:0] output (24 Bit Address) - *((volatile uint32_t*)RPC_DRDMCR) = 0x00000007; - //bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait - *((volatile uint32_t*)RPC_DRDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 DRDRE = 0 : DATA SDR transfer -} - -void InitRPC_QspiFlash(uint32_t rpcclk) -{ - PowerOnRPC(); - - SetRPC_ClockMode(rpcclk); - ResetRPC(); - SetRPC_SSL_Delay(); - - *((volatile uint32_t*)RPC_SEC_CONF) = 0x00000155; - *((volatile uint32_t*)RPC_OFFSET1) = 0x31511144; -} - -void ReadConfigRegQspiFlash(uint32_t *cnfigReg) -{ - uint8_t readData; - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - -// Manual mode / No dummy / On Command / No Address / Data:8bit transfer - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - *((volatile uint32_t*)RPC_SMCMR) = 0x00350000; - //bit23-16 CMD[7:0] = 0x35 : Read Configuration Register (CFG) - - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004008; - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0000 : Address output disable - //bit3-0 SPIDE[3:0] = 1000 : 8bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000005; - //bit2 SPIRE = 1 : Data read enable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - readData = *((volatile uint8_t*)RPC_SMRDR0); //read data[7:0] - *cnfigReg = readData; -} - -void WriteRegisterQspiFlash(uint32_t statusReg, uint32_t configReg) -{ - uint16_t writeData; - uint32_t product; - uint32_t cut; - - writeData = ( (configReg<<8) & 0x0000FF00 ); - writeData |= ( statusReg & 0x000000FF ); - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - } - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00010000; - //bit23-16 CMD[7:0] = 0x01 : Write (Status & Configuration) Register - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x0000400C; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0000 : ADR[23:0] is disable - //bit3-0 SPIDE[3:0] = 1100 : 16bit transfer - *((volatile uint16_t*)RPC_SMWDR0) = writeData; - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030270; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038270; - } - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear - -} -void WriteRegisterQspiFlash_Byte2(uint32_t statusReg, uint32_t configReg) -{ - uint32_t loopf,dataL; - unsigned char writeStatusData,writeConfigData; - uint32_t product; - uint32_t cut; - - writeStatusData = (volatile unsigned char)statusReg; - writeConfigData = (volatile unsigned char)configReg; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - } - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00010000; - //bit23-16 CMD[7:0] = 0x01 : Write (Status & Configuration) Register - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004008; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0000 : ADR[23:0] is disable - //bit3-0 SPIDE[3:0] = 1000 : 8bit transfer - -//First ByteData - *((volatile unsigned char*)RPC_SMWDR0) = writeStatusData; - *((volatile uint32_t*)RPC_SMCR) = 0x00000103; - //bit8 SSLKP = 1 : SSL After the transfer assert continue - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - WaitRpcTxEnd(); - -//Second ByteData - *((volatile uint32_t*)RPC_SMENR) = 0x00000008; - *((volatile unsigned char*)RPC_SMWDR0) = writeConfigData; - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit8 SSLKP = 0 : SSL After the transfer negated - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - WaitRpcTxEnd(); - - loopf = 1; - while(loopf) - { - dataL = *((volatile uint32_t*)RPC_CMNSR); - if( !(dataL & BIT1) ) loopf=0; - } - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030270; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038270; - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - } - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear -} - -//4SE DCh 4-byte address -void SectorErase4QspiFlash(uint32_t sector_addr) -{ - char str[64]; - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00DC0000; - //bit23-16 CMD[7:0] = 0xDC : Sector Erase 4-byte address command - *((volatile uint32_t*)RPC_SMADR) = sector_addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004F00; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) - //bit3-0 SPIDE[3:0] = 0000 : No transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000001; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); -} - -//4P4E 21h 4-byte address -void ParameterSectorErase4QspiFlash(uint32_t sector_addr) -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00210000; - //bit23-16 CMD[7:0] = 0x21 : Parameter 4-kB Sector Erasecommand - *((volatile uint32_t*)RPC_SMADR) = sector_addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004F00; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) - //bit3-0 SPIDE[3:0] = 0000 : No transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000001; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); -} - -//Page Program (4PP:12h) 4-byte address -void WriteData4ppWithBufferQspiFlash(uint32_t addr, uint32_t source_addr) -{ - uintptr_t i=0; - uint32_t product; - uint32_t cut; - - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030274; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038274; - //bit31 CAL = 1 : PHY calibration - //bit2 WBUF = 1 : Write Buffer Enable - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - - for(i = 0; i < 256; i = i+0x4) - { - (*(volatile uint32_t*)(0xEE208000+i)) = (*(volatile uint32_t*)(source_addr+i)); - } - - //bit31 CAL = 1 : PHY calibration - //bit2 WBUF = 1 : Write Buffer Enable - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00120000; - //bit23-16 CMD[7:0] = 0x12 : Page Program 4-byte address - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004F0F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[23:0] is output - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write enable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030273; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038273; - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - } - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear -} - - -//Page Program (PP:02h) 3-byte address -void WriteDataPpWithBufferQspiFlash(uint32_t addr, uint32_t source_addr) -{ - //uint32_t i=0; - uintptr_t i=0; - uint32_t product; - uint32_t cut; - - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030274; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038274; - //bit31 CAL = 1 : PHY calibration - //bit2 WBUF = 1 : Write Buffer Enable - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - - for(i = 0; i < 256; i = i+0x4) - { - (*(volatile uint32_t*)(0xEE208000+i)) = (*(volatile uint32_t*)(source_addr+i)); - } - //bit31 CAL = 1 : PHY calibration - //bit2 WBUF = 1 : Write Buffer Enable - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00020000; - //bit23-16 CMD[7:0] = 0x02 : Page Program 3-byte address - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x0000470F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0111 : ADR[23:0] is output - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write enable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030273; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038273; - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - } - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear -} - - -//Page Program (4PP:12h) 4-byte address -void WriteData4ppQspiFlash(uint32_t addr, uint32_t writeData) -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00120000; - //bit23-16 CMD[7:0] = 0x12 : Page Program 4-byte address - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004F0F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[31:0] is output - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMWDR0) = writeData; - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030273; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038273; - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - } - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear - -} - -void WriteData4ppQspiFlash_CsCont(uint32_t addr, uint32_t *writeData,uint32_t cnt) -{ - uint32_t i,loopf,dataL; - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00120000; - //bit23-16 CMD[7:0] = 0x12 : Page Program 4-byte address - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004F0F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[31:0] is output - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMWDR0) = *((volatile uint32_t*)writeData); - if (cnt == 1) - { - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit8 SSLKP = 0 : SSL After the transfer negated - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - } - else - { - *((volatile uint32_t*)RPC_SMCR) = 0x00000103; - //bit8 SSLKP = 1 : SSL After the transfer assert continue - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - } - WaitRpcTxEnd(); - writeData++; - if (cnt != 1) - { - *((volatile uint32_t*)RPC_SMENR) = 0x0000000F; - for(i = 1; i < cnt; i++) - { - *((volatile uint32_t*)RPC_SMWDR0) = *writeData; - if (i == (cnt - 1)) - { - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - } - else - { - *((volatile uint32_t*)RPC_SMCR) = 0x00000103; - } - WaitRpcTxEnd(); - writeData++; - } - } - - loopf = 1; - while(loopf) - { - dataL = *((volatile uint32_t*)RPC_CMNSR); - if (!(dataL & BIT1)) - { - loopf = 0; - } - } - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030273; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038273; - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - } - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear -} - -//Quad Page Program (4QPP:34h) 4-byte address -void WriteData4qppQspiFlash(uint32_t addr, uint32_t writeData) -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00340000; - //bit23-16 CMD[7:0] = 0x34 : Quad Page Program 4-byte address - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00024F0F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 10 : 4bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[31:0] is output - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMWDR0) = writeData; - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030273; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038273; - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - } - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear - -} - -uint32_t SingleFastReadQspiFlashData4Byte(uint32_t addr, uint32_t *readData) //for QSPIx1ch -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x000C0000; - //bit23-16 CMD[7:0] = 0x0C : Fast Read command (4FAST_READ 0Ch) - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDMCR) = 0x00000007; - //bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x0000CF0F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 1 : dummy cycle enable - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000005; - //bit2 SPIRE = 1 : Data read enable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - readData[0] = *((volatile uint32_t*)RPC_SMRDR0); //read data[31:0] - - return(readData[0]); -} - -uint32_t SingleFastReadQspiFlashData1Byte(uint32_t addr, uint32_t *readData) //for QSPIx1ch -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x000C0000; - //bit23-16 CMD[7:0] = 0x0C : Fast Read command (4FAST_READ 0Ch) - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDMCR) = 0x00000007; - //bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x0000CF08; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 1 : dummy cycle enable - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) - //bit3-0 SPIDE[3:0] = 1000 : 8bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000005; - //bit2 SPIRE = 1 : Data read enable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - *readData = *((volatile unsigned char*)RPC_SMRDR0); //read data[7:0] - -// return(readData[0]); -} - - -//OnBoard QspiFlash(S25FS128S) -//65h Read Any Register command (RADR 65h) -uint32_t ReadAnyRegisterQspiFlash(uint32_t addr, unsigned char *readData) // Add24bit,Data8bit -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00650000; - //bit23-16 CMD[7:0] = 0x65 : Read Any Register command (RADR 65h) - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDMCR) = 0x00000007; - //bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x0000C708; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 1 : dummy cycle enable - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0111 : ADR[23:0] output (24 Bit Address) - //bit3-0 SPIDE[3:0] = 1000 : 8bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000005; - //bit2 SPIRE = 1 : Data read enable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - *readData = *((volatile unsigned char*)RPC_SMRDR0); //read data[7:0] - -// return(readData[0]); -} - -//OnBoard QspiFlash(S25FS128S) -//71h Write Any Register command (WRAR 71h) -void WriteAnyRegisterQspiFlash(uint32_t addr, unsigned char writeData) // Add24bit,Data8bit -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00710000; - //bit23-16 CMD[7:0] = 0x71 : Write Any Register Command (WRAR) - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004708; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0111 : ADR[24:0] is output - //bit3-0 SPIDE[3:0] = 1000 : 8bit transfer - *((volatile unsigned char*)RPC_SMWDR0)= writeData; - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030273; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038273; - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - } - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear -} - -//FAST_READ 0Bh (CR2V[7]=0) is followed by a 3-byte address -void InitRPC_QspiFlashFastReadExtMode(void) -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - } - *((volatile uint32_t*)RPC_CMNCR) = 0x01FFF300; - *((volatile uint32_t*)RPC_DRCR) = 0x001F0100; - //bit20-16 RBURST[4:0] = 11111 : 32 continuous data unit - //bit8 RBE = 1 : Burst read - *((volatile uint32_t*)RPC_DRCMR) = 0x000B0000; - //bit23-16 CMD[7:0] = 0x0B : FAST_READ 0Bh - - *((volatile uint32_t*)RPC_DREAR) = 0x00000000; - //bit23-16 EAV[7:0] = 0 : ADR[32:25] output set0 - //bit2-0 EAC[2:0] = 000 : ADR[24:0 ] Enable - - *((volatile uint32_t*)RPC_DROPR) = 0x00000000; - //bit31-24 OPD3[7:0] = H'0 : Option Data 3 (Set Mode) - - *((volatile uint32_t*)RPC_DRENR) = 0x0000C700; // - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 DRDB[1:0] = 00 : 1bit width transfer data (QSPI0_IO0-3) - //bit15 DME = 1 : dummy cycle enable - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0111 : ADR[23:0] output (24 Bit Address) - *((volatile uint32_t*)RPC_DRDMCR) = 0x00000007; //8 cycle dummy - //bit17-16 DMCYC[2:0] = 10 : 4 bit width - //bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait - //bit2-0 DMCYC[2:0] = 011 : 4 cycle dummy wait - *((volatile uint32_t*)RPC_DRDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 DRDRE = 0 : DATA SDR transfer -} - -void SetRPC_ClockMode(uint32_t mode) -{ - uint32_t dataL=0; - -#ifdef RZG2_HIHOPE - if (mode == RPC_CLK_160M) - { - dataL = 0x00000011; /* RPC clock 160MHz */ - } - else if (mode == RPC_CLK_80M) - { - dataL = 0x00000013; /* RPC clock 80MHz */ - } - else - { - dataL = 0x00000017; /* RPC clock 40MHz */ - } -#endif /* RZG2_HIHOPE */ -#ifdef RZG2_EK874 - if (mode == RPC_CLK_160M) - { - dataL = 0x00000011; /* RPC clock 160MHz */ - } - else if (mode == RPC_CLK_80M) - { - dataL = 0x00000001; /* RPC clock 80MHz */ - } - else - { - dataL = 0x00000003; /* RPC clock 40MHz */ - } -#endif /* RZG2_EK874 */ - - *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; - *((volatile uint32_t*)CPG_RPCCKCR) = dataL; - - SoftDelay(50000); -} - -void WaitRpcTxEnd(void) -{ - uint32_t dataL=0; - - while(1) - { - dataL = *((volatile uint32_t*)RPC_CMNSR); - if(dataL & BIT0) - { - break; - } - // Wait for TEND = 1 - } -} - -void ResetRPC(void) -{ - *((volatile uint32_t*)CPG_CPGWPR) = ~BIT17; - *((volatile uint32_t*)CPG_SRCR9) = BIT17; - //wait: tRLRH Reset# low pulse width 10us - StartTMU0usec(2); // wait 20us - - *((volatile uint32_t*)CPG_CPGWPR) = ~BIT17; - *((volatile uint32_t*)CPG_SRSTCLR9) = BIT17; - //wait: tREADY1(35us) - tRHSL(10us) = 25us - StartTMU0usec(4); // wait 40us -} - -void SetRPC_SSL_Delay(void) -{ - *((volatile uint32_t*)RPC_SSLDR) = 0x00000400; - //bit10-8 SLNDL[2:0] = 100 : 5.5 cycles of QSPIn_SPCLK -} - -void PowerOnRPC(void) -{ - uint32_t dataL=0; - - dataL = *((volatile uint32_t*)CPG_MSTPSR9); - if (dataL & BIT17) - { - // case RPC(QSPI) Standby - dataL &= ~BIT17; - *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; - *((volatile uint32_t*)CPG_SMSTPCR9) = dataL; - while(BIT17 & *((volatile uint32_t*)CPG_MSTPSR9)); // wait bit=0 - } -} - - -uint32_t ReadQspiFlashID(uint32_t *readData) //for QSPIx1ch -{ - char str[64]; - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x009F0000; - //bit23-16 CMD[7:0] = 0x9F : Read ID command (for Palladium QSPI model) - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x0000400F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0000 : Address output disable - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000005; - //bit2 SPIRE = 1 : Data read enable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - readData[0] = *((volatile uint32_t*)RPC_SMRDR0); //read data[31:0] - return(readData[0]); -} - -uint32_t ReadStatusQspiFlash(uint32_t *readData) //for QSPIx1ch -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00050000; - //bit23-16 CMD[7:0] = 0x05 : Status Read command (for Palladium QSPI model) - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x0000400F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0000 : Address output disable - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000005; - //bit2 SPIRE = 1 : Data read enable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - readData[0] = *((volatile uint32_t*)RPC_SMRDR0); //read data[31:0] - - return(readData[0]); -} - - - -void WriteCommandQspiFlash(uint32_t command) //for QSPIx1ch -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = command; - //bit23-16 CMD[7:0] : command - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004000; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0000 : Address output disable - //bit3-0 SPIDE[3:0] = 0000 : No transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000001; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - -} - -void WriteDataWithBufferQspiFlash(uint32_t addr, uint32_t source_addr) //for QSPIx1ch -{ - uintptr_t i=0; - uint32_t product; - uint32_t cut; - - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030274; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038274; - //bit31 CAL = 1 : PHY calibration - //bit2 WBUF = 1 : Write Buffer Enable - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - - for(i = 0; i < 256;i = i+0x4) - { - (*(volatile uint32_t*)(0xEE208000+i)) = (*(volatile uint32_t*)(source_addr+i)); - } - - //bit31 CAL = 1 : PHY calibration - //bit2 WBUF = 1 : Write Buffer Enable - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00020000; - //bit23-16 CMD[7:0] = 0x02 : Write command (for Palladium QSPI model) - *((volatile uint32_t*)RPC_SMADR) = addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x0000470F; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0111 : ADR[23:0] is output - //bit3-0 SPIDE[3:0] = 1111 : 32bit transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000003; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 1 : Data write enable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030273; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038273; - //bit31 CAL = 0 : No PHY calibration - //bit2 WBUF = 0 : Write Buffer Disable - //bit1-0 PHYMEM[1:0] = 11 : HyperFlash - } - *((volatile uint32_t*)RPC_DRCR) = 0x011F0301; - //bit9 RCF = 1 : Read Cache Clear -} - -// SE (4KB) 20h 3-byte address -void ParameterSectorErase3QspiFlash(uint32_t sector_addr) -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00200000; - //bit23-16 CMD[7:0] = 0x20 : Sector Erase command (for Palladium QSPI model) - *((volatile uint32_t*)RPC_SMADR) = sector_addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004700; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0111 : ADR[23:0] output (24 Bit Address) - //bit3-0 SPIDE[3:0] = 0000 : No transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000001; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); -} - -//SE D8h 3-byte address -void SectorEraseQspiFlash(uint32_t sector_addr) //for QSPIx1ch -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x81FFF300; - //bit31 MD = 1 : Manual mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_SMCMR) = 0x00D80000; - //bit23-16 CMD[7:0] = 0xD8 : Sector Erase command (for Palladium QSPI model) - *((volatile uint32_t*)RPC_SMADR) = sector_addr; - *((volatile uint32_t*)RPC_SMDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 SPIDRE = 0 : DATA SDR transfer - *((volatile uint32_t*)RPC_SMENR) = 0x00004700; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) - //bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) - //bit15 DME = 0 : No dummy cycle - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0111 : ADR[23:0] output (24 Bit Address) - //bit3-0 SPIDE[3:0] = 0000 : No transfer - *((volatile uint32_t*)RPC_SMCR) = 0x00000001; - //bit2 SPIRE = 0 : Data read disable - //bit1 SPIWE = 0 : Data write disable - //bit0 SPIE = 1 : SPI transfer start - - WaitRpcTxEnd(); -} - -void InitRPC_ExtMode_QuadIORead(void) //for QSPIx1ch -{ - uint32_t product; - uint32_t cut; - - product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; - cut = *((volatile uint32_t*)PRR) & PRR_CUT_MASK; - - if ((product == PRR_PRODUCT_G2M) && (cut < PRR_CUT_30)) - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00030260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80030260; - } - else - { - *((volatile uint32_t*)RPC_PHYCNT) = 0x00038260; - *((volatile uint32_t*)RPC_PHYCNT) = 0x80038260; - //bit31 CAL = 1 : PHY calibration - //bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR - } - *((volatile uint32_t*)RPC_CMNCR) = 0x01FFF300; - //bit31 MD = 0 : External address space read mode - //bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 - *((volatile uint32_t*)RPC_DRCR) = 0x001F0100; - //bit20-16 RBURST[4:0] = 11111 : 32 continuous data unit - //bit8 RBE = 1 : Burst read - *((volatile uint32_t*)RPC_DRCMR) = 0x00EB0000; - //bit23-16 CMD[7:0] = 0xEB : Quad I/O Read command - *((volatile uint32_t*)RPC_DRENR) = 0x0202C700; - //bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) - //bit25-24 ADB[1:0] = 10 : 4bit width address (QSPI0_IO0-3) - //bit17-16 DRDB[1:0] = 10 : 4bit width transfer data (QSPI0_IO0-3) - //bit15 DME = 1 : dummy cycle enable - //bit14 CDE = 1 : Command enable - //bit11-8 ADE[3:0] = 0111 : ADR[23:0] output (24 Bit Address) - *((volatile uint32_t*)RPC_DRDMCR) = 0x00020009; - //bit17-16 DMCYC[2:0] = 10 : 4 bit width - //bit3-0 DMCYC[3:0] = 0001 : 2 cycle dummy wait - //bit3-0 DMCYC[3:0] = 0011 : 4 cycle dummy wait - //bit3-0 DMCYC[3:0] = 0101 : 6 cycle dummy wait(mode bit:2 cycle + 4 cycle dummy) <= S25FL512(on QSPI Board) - //bit3-0 DMCYC[3:0] = 0111 : 8 cycle dummy wait - //bit3-0 DMCYC[3:0] = 1001 :10 cycle dummy wait(mode bit:2 cycle + 8 cycle dummy) <= S25FS128(on Salvator) - *((volatile uint32_t*)RPC_DRDRENR) = 0x00000000; - //bit8 ADDRE = 0 : Address SDR transfer - //bit0 DRDRE = 0 : DATA SDR transfer -} - -////////////////////////////////////////// -// Qspi:Enable QUAD mode (CR1V bit1) -////////////////////////////////////////// -void EnableQuadModeQspiFlashS25fs128s(void) -{ - uint8_t readDataB[2]; - uint8_t configReg=0; - uint32_t statusReg=0; - - char str[64]; //DEBUG - - ReadAnyRegisterQspiFlash(0x00800002, &configReg); //CR1V - - Data2HexAscii(configReg,str,4); //********************* DEBUG - PutStr("configReg(CR1V) :H' ",0); - PutStr(str,1); //********************* DEBUG - - if (!(configReg & BIT1)) - { - PutStr("QUAD mode set!",1); - - WriteCommandQspiFlash(0x00060000); //WRITE ENABLE - WriteAnyRegisterQspiFlash(0x00800002, (configReg | BIT1)); //CR1V[1]=1 :0=Dual or Serial, 1=Quad - - while(1) - { - ReadStatusQspiFlash(&statusReg); - if (!(statusReg & BIT0)) - { - break; - } - } - } -} diff --git a/scifdrv.c b/scifdrv.c index b49bd5c..ef35bf4 100644 --- a/scifdrv.c +++ b/scifdrv.c @@ -1,86 +1,106 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2021 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ + #include "common.h" #include "scifdrv.h" #include "bit.h" -#include "reg_rzg2.h" +#include "rdk_cmn_cpg.h" #include "devdrv.h" - +#include "rdk_common.h" /************************************************************************/ /* */ /* Debug Seirial(SCIF2) */ /* */ /************************************************************************/ +#define UART_LSR_RXRDY_MASK (UART_16550_LINE_STATUS_DR) +#define UART_LSR_TXRDY_MASK (UART_16550_LINE_STATUS_TEMT | UART_16550_LINE_STATUS_THRE) +#define UART_LSR_READY_MASK (UART_LSR_TXRDY_MASK | UART_LSR_RXRDY_MASK) + +static st_UART_REG_t *gs_uART_cReg = 0; /** UART Control Regster Top Pointer */ + + int32_t PutCharSCIF2(char outChar) { - while(!(0x60 & *((volatile uint16_t*)SCIF2_SCFSR))); - *((volatile unsigned char*)SCIF2_SCFTDR) = outChar; - *((volatile uint16_t*)SCIF2_SCFSR) &= ~0x60; /* TEND,TDFE clear */ + + while(!((UART_16550_LINE_STATUS_THRE | UART_16550_LINE_STATUS_TEMT) & (gs_uART_cReg->LSR))); + gs_uART_cReg->RBR_THR = outChar; + return(0); } int32_t GetCharSCIF2(char *inChar) { + uint16_t sts; + do { - if (0x91 & *((volatile uint16_t *)SCIF2_SCFSR)) + sts = gs_uART_cReg->LSR; /** Read Line Status */ + + if (UART_16550_LINE_STATUS_FE & sts) { - *((volatile uint16_t *)SCIF2_SCFSR) &= ~0x91; + /*Framing Error*/ } - if (0x01 & *((volatile uint16_t *)SCIF2_SCLSR)) + if (UART_16550_LINE_STATUS_OE & sts) { - PutStr("ORER",1); - *((volatile uint16_t *)SCIF2_SCLSR) &= ~0x01; + /*Overrun Error*/ } - } while(!(0x02 & *((volatile uint16_t *)SCIF2_SCFSR))); + } while(!(sts & UART_LSR_RXRDY_MASK)); - *inChar = *((volatile unsigned char*)SCIF2_SCFRDR); - *((volatile uint16_t*)SCIF2_SCFSR) &= ~0x02; + *inChar = gs_uART_cReg->RBR_THR; /** Read Rx data */ return(0); } -void PowerOnScif2(void) +int32_t GetCharTimeOutSCIF2(char *inChar, uint64_t us) { - uint32_t dataL; + uint16_t sts; + int32_t err = 0; + + uint64_t start = CMN_GetSysCnt(); + uint64_t cycles = (CMN_GetFreq4SysCnt() / 1000000UL) * us; - dataL = *((volatile uint32_t*)CPG_MSTPSR3); - if (dataL & BIT10) + do { - /* case SCIF2(IrDA) Standby */ - dataL &= ~BIT10; - *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; - *((volatile uint32_t*)CPG_SMSTPCR3) = dataL; - while(BIT10 & *((volatile uint32_t*)CPG_MSTPSR3)); /* wait bit=0 */ - } + if ((CMN_GetSysCnt() - start) > cycles) { + err = -1; + break; + } + sts = gs_uART_cReg->LSR; /** Read Line Status */ + + if (UART_16550_LINE_STATUS_FE & sts) + { + /*Framing Error*/ + } + if (UART_16550_LINE_STATUS_OE & sts) + { + /*Overrun Error*/ + } + } while(!(sts & UART_LSR_RXRDY_MASK)); + + if (err != -1) //not time out + *inChar = gs_uART_cReg->RBR_THR; /** Read Rx data */ + + return(err); } void WaitPutScif2SendEnd(void) @@ -91,115 +111,64 @@ void WaitPutScif2SendEnd(void) loop=1; while(loop) { - dataW = *((volatile uint16_t*)SCIF2_SCFSR); - if (dataW & BIT6) + dataW = gs_uART_cReg->LSR; + if (dataW & UART_16550_LINE_STATUS_THRE) { loop = 0; } } } -#ifdef RZG2_HIHOPE void InitScif2_SCIFCLK(void) { - volatile uint16_t dataW; - uint32_t prr; - - PowerOnScif2(); - - dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */ - *((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */ - *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */ - - *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ - *((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ - *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ - - *((volatile uint16_t*)SCIF2_SCSCR) = 0x0002; /* external clock, SC_CLK pin used for input pin */ - *((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */ - SoftDelay(100); - - *((volatile uint16_t*)SCIF2_DL) = 0x0091; /* 266.66MHz / (115200*16) = 144.67 */ - *((volatile uint16_t*)SCIF2_CKS) = 0x4000; /* select S3D1-Clock */ - - SoftDelay(100); - *((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ - *((volatile uint16_t*)SCIF2_SCSCR) = 0x0032; /* enable TE, RE; SC_CLK=input */ - - SoftDelay(100); -} -#endif /* RZG2_HIHOPE */ - -#ifdef RZG2_EK874 -void InitScif2_SCIFCLK_G2E(void) -{ - volatile uint16_t dataW; - uint32_t md; - uint32_t sscg; - - PowerOnScif2(); - - md = *((volatile uint32_t*)RST_MODEMR); - sscg = (md & 0x00001000) >> 12; + volatile unsigned long i; + unsigned long bit_rate; + + // UART Target Channel set + gs_uART_cReg = (st_UART_REG_t *)UART_CH0_BASE; - dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */ - *((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */ - *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */ + // UART initialize reset. + gs_uART_cReg->FCR = UART_MODE_CONST_FCR_RST; // Reset Rx,Rx FIFO + gs_uART_cReg->HCR0 |= 0x0080; // S/W Reset + for(i=0; i < 1000; i++); // Delay Over 6*PLCK(For fail soft) + gs_uART_cReg->HCR0 &= ~(0x0080); // S/W Reset release + for(i=0; i < 1000; i++); // Delay Over 6*PLCK(For fail soft) - *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ - *((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ - *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + // UART set bit rate. + gs_uART_cReg->LCR |= 0x0080; // Select Div. Latch Register - *((volatile uint16_t*)SCIF2_SCSCR) = 0x0002; /* external clock, SC_CLK pin used for input pin */ - *((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */ - SoftDelay(100); + bit_rate = SCLK / (UART_BAUDRATE *16); - if (sscg == 0x0) - { - /* MD12=0 (SSCG off) F S3D1C=266.6MHz */ - *((volatile uint16_t*)SCIF2_DL) = 0x0091; /* 266.66MHz / (115200*16) = 144.67 */ - } - else - { /* MD12=1 (SSCG on) F S3D1C=250MHz */ - *((volatile uint16_t*)SCIF2_DL) = 0x0082; /* 240.00MHz / (115200*16) = 130.21 */ - } - *((volatile uint16_t*)SCIF2_CKS) = 0x4000; /* select S3D1-Clock */ - SoftDelay(100); - *((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ - *((volatile uint16_t*)SCIF2_SCSCR) = 0x0032; /* enable TE, RE; SC_CLK=input */ + gs_uART_cReg->DLL = (uint8_t)bit_rate; + gs_uART_cReg->DLM = (uint8_t)(bit_rate>>8); - SoftDelay(100); -} -#endif /* RZG2_EK874 */ + gs_uART_cReg->LCR = UART_MODE_CONST_LCR; // Select Data Buff & Set Parity,etc. -void SetScif2_DL(uint16_t setData) -{ - *((volatile uint16_t*)SCIF2_DL) = setData; -} + gs_uART_cReg->IER = UART_MODE_CONST_IER_P; // Set Int. All Disable + gs_uART_cReg->FCR = UART_MODE_CONST_FCR_P; // Set Int. FIFO Trigger Level,etc. + gs_uART_cReg->MCR = UART_MODE_CONST_MCR_P; // Set Flow Ctl. Enable/Disble,etc. -void SetScif2_BRR(uint8_t setData) -{ - *((volatile uint8_t*)SCIF2_SCBRR) = setData; + // Reset Tx&Rx DMA_REQ + gs_uART_cReg->HCR0 = 0x0000; } - uint32_t SCIF_TerminalInputCheck(char* str) { - char result = 0; + uint32_t result = 0; + uint16_t sts; - if (0x91 & *((volatile uint16_t *)SCIF2_SCFSR)) + sts = gs_uART_cReg->LSR; /** Read Line Status */ + + if (UART_16550_LINE_STATUS_FE & sts) { - *((volatile uint16_t *)SCIF2_SCFSR) &= ~0x91; + /*Framing Error*/ } - if (0x01 & *((volatile uint16_t *)SCIF2_SCLSR)) + if (UART_16550_LINE_STATUS_OE & sts) { - PutStr("ORER",1); - *((volatile uint16_t *)SCIF2_SCLSR) &= ~0x01; + /*Overrun Error*/ } - if (0x02 & *((volatile uint16_t *)SCIF2_SCFSR)) - { - *str = *((volatile unsigned char*)SCIF2_SCFRDR); - *((volatile uint16_t*)SCIF2_SCFSR) &= ~0x02; + if(sts & UART_LSR_RXRDY_MASK){ + *str = gs_uART_cReg->RBR_THR; /** Read Rx data */ result = 1; } return result; diff --git a/spiflash1drv.c b/spiflash1drv.c deleted file mode 100644 index 5f79169..0000000 --- a/spiflash1drv.c +++ /dev/null @@ -1,425 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * - Neither the name of Renesas nor the names of its contributors may be - * used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include "common.h" -#include "bit.h" -#include "spiflash1drv.h" -#include "rpcqspidrv.h" -#include "dgtable.h" -#include "dgmodul4.h" - -#define DEBUG_MSG (0) - -extern uint32_t gManufacturerId; -extern uint32_t gDeviceId; -extern uint32_t gQspi_sa_size; -extern uint32_t gQspi_end_addess; - -////////////////////////////////// -// Qspi:Fast Read (4FAST_READ 0Ch) -////////////////////////////////// -void Fast4RdQspiFlash(uint32_t sourceSpiAdd,uint32_t destinationAdd,uint32_t byteCount) -{ - uint32_t sourceAdd; - -#if (DEBUG_MSG) - PutStr("## Fast4RdQspiFlash", 1); -#endif - InitRPC_QspiFlash4FastReadExtMode(); - - sourceAdd = SPI_IOADDRESS_TOP + sourceSpiAdd; - mem_copy(destinationAdd, sourceAdd, byteCount); -} - -////////////////////////////////// -// Qspi:Fast Read (FAST_READ 0Bh) -////////////////////////////////// -void FastRdQspiFlash(uint32_t sourceSpiAdd,uint32_t destinationAdd,uint32_t byteCount) -{ - uint32_t sourceAdd; - -#if (DEBUG_MSG) - PutStr("## FastRdQspiFlash", 1); -#endif - InitRPC_QspiFlashFastReadExtMode(); - - sourceAdd = SPI_IOADDRESS_TOP + sourceSpiAdd; - mem_copy(destinationAdd, sourceAdd, byteCount); -} - -////////////////////////////////////////// -// Qspi:Sector Erase (64kB) -////////////////////////////////////////// -static void SectorEraseQspiFlashInternal(uint32_t addr) -{ - uint32_t status; - -#if (DEBUG_MSG) - PutStr("## SectorEraseQspiFlashInternal", 1); -#endif - WriteCommandQspiFlash(0x00060000); //WRITE ENABLE - if (gQspi_end_addess <= TOTAL_SIZE_16MB) - { -#if (DEBUG_MSG) - PutStr("## SectorEraseQspiFlash", 1); -#endif - // Sector Erase (D8h) - SectorEraseQspiFlash(addr); - } - else - { -#if (DEBUG_MSG) - PutStr("## SectorErase4QspiFlash", 1); -#endif - // Sector Erase with 4-Byte Address (DCh) - SectorErase4QspiFlash(addr); - } - while(1) - { - ReadStatusQspiFlash(&status); - if (!(status & BIT0)) - { - break; - } - } -} - -////////////////////////////////////////// -// Qspi:Bulk Erase (All) -////////////////////////////////////////// -int32_t BulkEraseQspiFlash(void) -{ - uint32_t status; - -#if (DEBUG_MSG) - PutStr("## BulkEraseQspiFlash", 1); -#endif - - WriteCommandQspiFlash(0x00060000); //WRITE ENABLE - WriteCommandQspiFlash(0x00600000); //Bulk Erase (BE 60h) - while(1) - { - ReadStatusQspiFlash(&status); - if (!(status & BIT0)) - { - break; //BIT0 1:Device Busy 0:Ready Device is in Standby - } - } - return(NORMAL_END); -} - -////////////////////////////////////////// -// Page Program -////////////////////////////////////////// -void PageProgramWithBuffeQspiFlash(uint32_t addr, uint32_t source_addr) -{ - uint32_t status; -#if (DEBUG_MSG) - char str[64]; - - PutStr("## PageProgramWithBuffeQspiFlash", 1); - - PutStr("addr : 0x", 0); - Data2HexAscii(addr, str, 4); - PutStr(str, 1); - PutStr("source_addr : 0x", 0); - Data2HexAscii(source_addr, str, 4); - PutStr(str, 1); -#endif - WriteCommandQspiFlash(0x00060000); //WRITE ENABLE - if (gQspi_end_addess <= TOTAL_SIZE_16MB) - { -#if (DEBUG_MSG) - PutStr("## WriteDataPpWithBuffer", 1); -#endif - //Page Program (PP:02h) 3-byte address - WriteDataPpWithBufferQspiFlash(addr, source_addr); - } - else - { -#if (DEBUG_MSG) - PutStr("## WriteData4ppWithBufferQspiFlash", 1); -#endif - // Page Program with 4-Byte Address (12h) - WriteData4ppWithBufferQspiFlash(addr, source_addr); - } - while(1) - { - ReadStatusQspiFlash(&status); - if (!(status & BIT0)) - { - break; - } - } -} - -/////////////////////////////////////////////// -// Qspi:Parameter 4-kB Sector Erase -/////////////////////////////////////////////// -void ParameterSectorErase4kbQspiFlash(uint32_t addr) -{ - uint32_t status; -#if (DEBUG_MSG) - char str[64]; - - PutStr("## ParameterSectorErase4kbQspiFlash", 1); - PutStr("addr : 0x", 0); - Data2HexAscii(addr, str, 4); - PutStr(str, 1); -#endif - WriteCommandQspiFlash(0x00060000); //WRITE ENABLE - if (gQspi_end_addess <= TOTAL_SIZE_16MB) - { - // 4KB Sector Erase (20h) - ParameterSectorErase3QspiFlash(addr); - } - else - { - // 4KB Sector Erase with 4-Byte Address (21h) - ParameterSectorErase4QspiFlash(addr); - } - while(1) - { - ReadStatusQspiFlash(&status); - if (!(status & BIT0)) - { - break; - } - } -} - -/////////////////////////////////////////////////////////////// -// SetSectorErase256kbQspiFlashCypress -/////////////////////////////////////////////////////////////// -static void SetSectorErase256kbQspiFlashCypress(void) -{ - unsigned char readData; - uint32_t status; - uint32_t addr; - - char str[64]; - - addr = (uint32_t)SPIREG_CR3V; - ReadAnyRegisterQspiFlash(addr, &readData); - - if (!(readData & BIT1)) - { - WriteCommandQspiFlash(0x00060000); - readData |= BIT1; // Bit1=Block Erase Size 1:256KB , 0:64KB - WriteAnyRegisterQspiFlash(addr, readData); - while(1) - { - ReadStatusQspiFlash(&status); - if (!(status & BIT0)) - { - break; - } - } - } -} - -/////////////////////////////////////////////////////////////// -// SetSectorErase64kbQspiFlashCypress -/////////////////////////////////////////////////////////////// -static void SetSectorErase64kbQspiFlashCypress(void) -{ - unsigned char readData; - uint32_t status; - uint32_t addr; - - char str[64]; - - addr = (uint32_t)SPIREG_CR3V; - ReadAnyRegisterQspiFlash(addr, &readData); - - if (readData & BIT1) - { - WriteCommandQspiFlash(0x00060000); - readData &= ~BIT1; // Bit1=Block Erase Size 1:256KB , 0:64KB - WriteAnyRegisterQspiFlash(addr, readData); - while(1) - { - ReadStatusQspiFlash(&status); - if (!(status & BIT0)) - { - break; - } - } - } -} - -////////////////////////////////////////// -// SaveDataWithBuffeQspiFlash -////////////////////////////////////////// -void SaveDataWithBuffeQspiFlash(uint32_t srcAdd, uint32_t svFlashAdd, uint32_t svSize) -{ -#if (DEBUG_MSG) - char str[64]; -#endif - uint32_t flashAdd; - uint32_t writeDataAdd; - -#if (DEBUG_MSG) - PutStr("## SaveDataWithBuffeQspiFlash", 1); - - PutStr("srcAdd : 0x", 0); - Data2HexAscii(srcAdd, str, 4); - PutStr(str, 1); - PutStr("svFlashAdd : 0x", 0); - Data2HexAscii(svFlashAdd, str, 4); - PutStr(str, 1); - PutStr("svSize : 0x", 0); - Data2HexAscii(svSize, str, 4); - PutStr(str, 1); -#endif - WriteCommandQspiFlash(0x00060000); //WRITE ENABLE - - writeDataAdd = srcAdd; - for (flashAdd = svFlashAdd; flashAdd<(svFlashAdd+svSize); flashAdd += 256) - { - // 256byte:RPC Write Buffer size - PageProgramWithBuffeQspiFlash(flashAdd, writeDataAdd); - writeDataAdd = writeDataAdd + 256; - } -} - -////////////////////////////////////////// -// SectorEraseQspi_Flash -////////////////////////////////////////// -void SectorEraseQspi_Flash(uint32_t EraseStatAdd, uint32_t EraseEndAdd) -{ -#if (DEBUG_MSG) - char str[64]; -#endif - uint32_t sectorAd; - uint32_t SectorStatTopAdd, SectorEndTopAdd; - SectorStatTopAdd = EraseStatAdd & ((~gQspi_sa_size) + 1); - SectorEndTopAdd = EraseEndAdd & ((~gQspi_sa_size) + 1); - -#if (DEBUG_MSG) - PutStr("## SectorEraseQspi_Flash", 1); - - PutStr("SectorStatTopAdd : 0x", 0); - Data2HexAscii(SectorStatTopAdd, str, 4); - PutStr(str, 1); - PutStr("SectorEndTopAdd : 0x", 0); - Data2HexAscii(SectorEndTopAdd, str, 4); - PutStr(str, 1); - PutStr("SectorSize : 0x", 0); - Data2HexAscii(gQspi_sa_size, str, 4); - PutStr(str, 1); -#endif - - if ((gManufacturerId == CYPRESS_MANUFACTURER_ID ) && (gDeviceId == DEVICE_ID_S25FS128S)) - { - if (gQspi_sa_size == SA_256KB) - { - PutStr("## 256KB Sector" , 1); - SetSectorErase256kbQspiFlashCypress(); - } - else - { - PutStr("## 64KB Sector" , 1); - SetSectorErase64kbQspiFlashCypress(); - } - } - for (sectorAd = SectorStatTopAdd; sectorAd <= SectorEndTopAdd; sectorAd = sectorAd + gQspi_sa_size) - { - SectorEraseQspiFlashInternal(sectorAd); - PutStr(".",0); - } - PutStr("Erase Completed ",1); -} - -/////////////////////////////////////////////////////// -// ParameterSectorEraseQspiFlash (4KB Sector Erase) -/////////////////////////////////////////////////////// -void ParameterSectorEraseQspiFlash(uint32_t EraseStatAdd,uint32_t EraseEndAdd) -{ -#if (DEBUG_MSG) - char str[64]; -#endif - uint32_t sectorAd; - uint32_t SectorStatTopAdd,SectorEndTopAdd; - - SectorStatTopAdd = EraseStatAdd & 0xFFFFF000; - SectorEndTopAdd = EraseEndAdd & 0xFFFFF000; -#if (DEBUG_MSG) - PutStr("## ParameterSectorEraseQspiFlash", 1); - - PutStr("SectorStatTopAdd : 0x", 0); - Data2HexAscii(SectorStatTopAdd, str, 4); - PutStr(str, 1); - PutStr("SectorEndTopAdd : 0x", 0); - Data2HexAscii(SectorEndTopAdd, str, 4); - PutStr(str, 1); -#endif - - for (sectorAd = SectorStatTopAdd;sectorAd <= SectorEndTopAdd; sectorAd = sectorAd + 0x1000) - { - ParameterSectorErase4kbQspiFlash(sectorAd); - PutStr(".", 0); - } - PutStr("Erase Completed ",1); -} - -////////////////////////////////////////// -// SectorRdQspiFlash -////////////////////////////////////////// -void SectorRdQspiFlash(uint32_t spiStatAdd, uint32_t distRamAdd) -{ -#if (DEBUG_MSG) - char str[64]; -#endif - uint32_t SectorStatTopAdd, readSize; - - SectorStatTopAdd = spiStatAdd & ((~gQspi_sa_size) + 1); - readSize = gQspi_sa_size; - -#if (DEBUG_MSG) - PutStr("## SectorRdQspiFlash", 1); - - PutStr("SectorStatTopAdd : 0x", 0); - Data2HexAscii(SectorStatTopAdd, str, 4); - PutStr(str, 1); - PutStr("readSize : 0x", 0); - Data2HexAscii(readSize, str, 4); - PutStr(str, 1); -#endif - if (gQspi_end_addess <= TOTAL_SIZE_16MB) - { - FastRdQspiFlash(SectorStatTopAdd, distRamAdd, readSize); - } - else - { - Fast4RdQspiFlash(SectorStatTopAdd, distRamAdd, readSize); - } -}