Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Clearence between copper zones distorted #30

Open
der-ule opened this issue Jan 28, 2021 · 3 comments
Open

Clearence between copper zones distorted #30

der-ule opened this issue Jan 28, 2021 · 3 comments

Comments

@der-ule
Copy link

der-ule commented Jan 28, 2021

Hello @realthunder

I have been using your macro indirectly through the KiCAD StepUp Workbench, great stuff, thanks a bunch for it!

However, on my latest board I did notice that some zones where fused together and the space between them was not accurate, I raised the issue back at the KiCAD Forums there @easyw recommended me to raise an issue here to see if you could help.

I followed your installation instruction and loaded my board in FreeCAD using directly your plugin and the problem seems to be still there.

KiCAD
image

fcad_pcb
image

The output of the macro looks pretty normal to me:

09:17:00  A3 available
09:19:01  making copper layer F.Cu...
09:19:01    making pads...
09:19:06      modules: 82
09:19:06      pads: 326, skipped: 41
09:19:06      vias: 117, skipped: 0
09:19:06      total pads added: 402
09:19:28    pads done
09:19:28    making tracks...
09:19:28      making 399 tracks  of width 0.20, (0/535)
09:19:32      making 136 tracks  of width 0.60, (399/535)
09:19:38    tracks done
09:19:38    making zones...
09:19:38      making zone /V_SW...
09:19:38        region 1/1, holes: 0
09:19:38      making zone GND...
09:19:38        region 1/2, holes: 0
09:19:38        region 2/2, holes: 0
09:19:38      making zone GND...
09:19:38        region 1/1, holes: 0
09:19:38      making zone /V_SW...
09:19:38        region 1/1, holes: 0
09:19:38      making zone +3V3...
09:19:38        region 1/1, holes: 31
09:19:39      making zone /V_SW...
09:19:39        region 1/1, holes: 0
09:19:39      making zone "Net-(C503-Pad2)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone /VBAT+...
09:19:39        region 1/1, holes: 0
09:19:39      making zone ""...
09:19:39      making zone "Net-(C206-Pad2)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone "Net-(L203-Pad1)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone "Net-(C207-Pad2)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone "Net-(L204-Pad1)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone GND...
09:19:39        region 1/1, holes: 0
09:19:40      making zone /V_SW...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(C205-Pad2)"...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(C208-Pad2)"...
09:19:40        region 1/1, holes: 4
09:19:40      making zone /V_SW...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(L201-Pad1)"...
09:19:40        region 1/1, holes: 0
09:19:40      making zone GND...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(L202-Pad1)"...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(C205-Pad2)"...
09:19:40        region 1/1, holes: 4
09:19:40      making zone /V_USB...
09:19:40        region 1/1, holes: 0
09:19:40    zones done
09:19:45  done copper layer F.Cu

My FreeCAD version is:

OS: Windows 10 (10.0)
Word size of OS: 64-bit
Word size of FreeCAD: 64-bit
Version: 0.19.23323 (Git)
Build type: Release
Branch: master
Hash: 512d5c6141aec52b6eecc67370336a28fde862a6
Python version: 3.8.6
Qt version: 5.12.5
Coin version: 4.0.0
OCC version: 7.4.0
Locale: German/Germany (de_DE)

Any my KiCAD version is:

Application: Pcbnew
Version: (5.1.8)-1, release build
Libraries:
    wxWidgets 3.0.5
    libcurl/7.71.0 OpenSSL/1.1.1g (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.3.0 libpsl/0.21.0 (+libidn2/2.3.0) libssh2/1.9.0 nghttp2/1.41.0
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    wxWidgets: 3.0.5 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.73.0
    OpenCASCADE Community Edition: 6.9.1
    Curl: 7.71.0
    Compiler: GCC 10.2.0 with C++ ABI 1014

Build settings:
    USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_PYTHON3=OFF
    KICAD_SCRIPTING_WXPYTHON=ON
    KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    KICAD_USE_OCC=OFF
    KICAD_SPICE=ON

Let me know if I can somehow assist you further and once again, thank you for your time and effort!

P.S. I haven't been able to reproduce the problem with a test board, as such here is the original board with the problem:
charger.zip
realthunder added a commit that referenced this issue Jan 29, 2021
@realthunder
Fix zone inflating
b61b8f6 
Related #30
@realthunder
Copy link
Owner

Can you please sync my repo and check if the problem is fixed?

@der-ule
Copy link
Author

der-ule commented Jan 29, 2021

Wow! It worked flawlessly with the latest version!

image

Thanks a lot once again for this magnificent software and your time and dedication!

08:06:01  A3 available
08:10:36  making pcb...
08:10:36    making board...
08:10:36      making 23 lines
08:10:36      making 4 arcs
08:10:36      making 2 polys
08:10:37        making holes...
08:10:37          pad holes: 25, skipped: 0
08:10:37          oval holes: 0
08:10:37          via holes: 117, skipped: 0
08:10:37          total holes added: 142
08:10:37        holes done
08:10:38    board done
08:10:38    making all copper layers...
08:10:38      fetch holes 'holes_wire' from cache
08:10:38      making copper layer F.Cu...
08:10:38        making pads...
08:10:43          modules: 82
08:10:43          pads: 326, skipped: 41
08:10:43          vias: 117, skipped: 0
08:10:43          total pads added: 402
08:10:59        pads done
08:10:59        making tracks...
08:10:59          making 399 tracks  of width 0.20, (0/535)
08:11:03          making 136 tracks  of width 0.60, (399/535)
08:11:07        tracks done
08:11:07        making zones...
08:11:07          making zone /V_SW...
08:11:07            region 1/1, holes: 0
08:11:07          making zone GND...
08:11:07            region 1/2, holes: 0
08:11:07            region 2/2, holes: 0
08:11:07          making zone GND...
08:11:07            region 1/1, holes: 0
08:11:07          making zone /V_SW...
08:11:07            region 1/1, holes: 0
08:11:07          making zone +3V3...
08:11:07            region 1/1, holes: 31
08:11:08          making zone /V_SW...
08:11:08            region 1/1, holes: 0
08:11:08          making zone "Net-(C503-Pad2)"...
08:11:08            region 1/1, holes: 0
08:11:08          making zone /VBAT+...
08:11:08            region 1/1, holes: 0
08:11:08          making zone ""...
08:11:08          making zone "Net-(C206-Pad2)"...
08:11:08            region 1/1, holes: 0
08:11:08          making zone "Net-(L203-Pad1)"...
08:11:08            region 1/1, holes: 0
08:11:08          making zone "Net-(C207-Pad2)"...
08:11:08            region 1/1, holes: 0
08:11:08          making zone "Net-(L204-Pad1)"...
08:11:08            region 1/1, holes: 0
08:11:08          making zone GND...
08:11:08            region 1/1, holes: 0
08:11:08          making zone /V_SW...
08:11:08            region 1/1, holes: 0
08:11:08          making zone "Net-(C205-Pad2)"...
08:11:09            region 1/1, holes: 0
08:11:09          making zone "Net-(C208-Pad2)"...
08:11:09            region 1/1, holes: 4
08:11:09          making zone /V_SW...
08:11:09            region 1/1, holes: 0
08:11:09          making zone "Net-(L201-Pad1)"...
08:11:09            region 1/1, holes: 0
08:11:09          making zone GND...
08:11:09            region 1/1, holes: 0
08:11:09          making zone "Net-(L202-Pad1)"...
08:11:09            region 1/1, holes: 0
08:11:09          making zone "Net-(C205-Pad2)"...
08:11:09            region 1/1, holes: 4
08:11:09          making zone /V_USB...
08:11:09            region 1/1, holes: 0
08:11:17        zones done
08:11:17        making solid
08:11:19        done solid
08:11:19      done copper layer F.Cu
08:11:19      making copper layer B.Cu...
08:11:19        making pads...
08:11:25          modules: 82
08:11:25          pads: 326, skipped: 268
08:11:25          vias: 117, skipped: 0
08:11:25          total pads added: 175
08:11:29        pads done
08:11:29        making tracks...
08:11:29          making 58 tracks  of width 0.20, (0/73)
08:11:30          making 15 tracks  of width 0.60, (58/73)
08:11:30        tracks done
08:11:30        making zones...
08:11:30          making zone GND...
08:11:30            region 1/1, holes: 55
08:11:40        zones done
08:11:40        making solid
08:11:42        done solid
08:11:42      done copper layer B.Cu
08:11:42    done making all copper layers
08:11:45  all done
08:14:04  making copper layer F.Cu...
08:14:04    making pads...
08:14:09      modules: 82
08:14:09      pads: 326, skipped: 41
08:14:09      vias: 117, skipped: 0
08:14:09      total pads added: 402
08:14:45    pads done
08:14:45    making tracks...
08:14:45      making 399 tracks  of width 0.20, (0/535)
08:14:50      making 136 tracks  of width 0.60, (399/535)
08:15:01    tracks done
08:15:01    making zones...
08:15:01      making zone /V_SW...
08:15:01        region 1/1, holes: 0
08:15:01      making zone GND...
08:15:01        region 1/2, holes: 0
08:15:01        region 2/2, holes: 0
08:15:01      making zone GND...
08:15:01        region 1/1, holes: 0
08:15:01      making zone /V_SW...
08:15:01        region 1/1, holes: 0
08:15:01      making zone +3V3...
08:15:01        region 1/1, holes: 31
08:15:02      making zone /V_SW...
08:15:02        region 1/1, holes: 0
08:15:02      making zone "Net-(C503-Pad2)"...
08:15:02        region 1/1, holes: 0
08:15:02      making zone /VBAT+...
08:15:02        region 1/1, holes: 0
08:15:03      making zone ""...
08:15:03      making zone "Net-(C206-Pad2)"...
08:15:03        region 1/1, holes: 0
08:15:03      making zone "Net-(L203-Pad1)"...
08:15:03        region 1/1, holes: 0
08:15:03      making zone "Net-(C207-Pad2)"...
08:15:03        region 1/1, holes: 0
08:15:03      making zone "Net-(L204-Pad1)"...
08:15:03        region 1/1, holes: 0
08:15:03      making zone GND...
08:15:03        region 1/1, holes: 0
08:15:03      making zone /V_SW...
08:15:03        region 1/1, holes: 0
08:15:03      making zone "Net-(C205-Pad2)"...
08:15:03        region 1/1, holes: 0
08:15:03      making zone "Net-(C208-Pad2)"...
08:15:03        region 1/1, holes: 4
08:15:03      making zone /V_SW...
08:15:03        region 1/1, holes: 0
08:15:03      making zone "Net-(L201-Pad1)"...
08:15:03        region 1/1, holes: 0
08:15:03      making zone GND...
08:15:03        region 1/1, holes: 0
08:15:03      making zone "Net-(L202-Pad1)"...
08:15:03        region 1/1, holes: 0
08:15:03      making zone "Net-(C205-Pad2)"...
08:15:03        region 1/1, holes: 4
08:15:04      making zone /V_USB...
08:15:04        region 1/1, holes: 0
08:15:04    zones done
08:15:13  done copper layer F.Cu

p.s. wouldn't it be good idea to output the software version somewhere at the top when loading the plugin ? I wasn't sure if freecad picked up the changes until I saw that there was no error anymore.

@luzpaz
Copy link
Contributor

luzpaz commented Oct 30, 2022

p.s. wouldn't it be good idea to output the software version somewhere at the top when loading the plugin ? I wasn't sure if freecad picked up the changes until I saw that there was no error anymore.

@realthunder do you want a new ticket for this?

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
3 participants
@realthunder @luzpaz @der-ule