From 572929306c1ae5b6a199d425c05c7e2bb8d3d7ca Mon Sep 17 00:00:00 2001
From: Raynel Sanchez <raynelfss@hotmail.com>
Date: Mon, 26 Aug 2024 14:11:24 -0400
Subject: [PATCH] Fix: Remove set collecting all nodes to be connected. - A set
 collecting all the new nodes to connect with a new node was preventing
 additional wires to connect to subsequent nodes.

---
 crates/circuit/src/dag_circuit.rs | 29 +++++++++--------------------
 1 file changed, 9 insertions(+), 20 deletions(-)

diff --git a/crates/circuit/src/dag_circuit.rs b/crates/circuit/src/dag_circuit.rs
index e67e91cb6231..b75ff6b04160 100644
--- a/crates/circuit/src/dag_circuit.rs
+++ b/crates/circuit/src/dag_circuit.rs
@@ -6277,8 +6277,6 @@ impl DAGCircuit {
             let new_node = self.dag.add_node(NodeType::Operation(instr));
             new_nodes.push(new_node);
 
-            // For each qubit and cl_bit retrieve the last_nodes
-            let mut nodes_to_connect: HashSet<NodeIndex> = HashSet::default();
             // Check all the qubits in this instruction.
             for qubit in self.qargs_cache.intern(qubits_id) {
                 // Retrieve each qubit's last node
@@ -6296,11 +6294,8 @@ impl DAGCircuit {
                     predecessor_node
                 };
                 qubit_last_nodes.entry(*qubit).or_insert(new_node);
-                if !nodes_to_connect.contains(&qubit_last_node) {
-                    self.dag
-                        .add_edge(qubit_last_node, new_node, Wire::Qubit(*qubit));
-                    nodes_to_connect.insert(qubit_last_node);
-                }
+                self.dag
+                    .add_edge(qubit_last_node, new_node, Wire::Qubit(*qubit));
             }
 
             // Check all the clbits in this instruction.
@@ -6319,11 +6314,8 @@ impl DAGCircuit {
                     predecessor_node
                 };
                 clbit_last_nodes.entry(clbit).or_insert(new_node);
-                if !nodes_to_connect.contains(&clbit_last_node) {
-                    self.dag
-                        .add_edge(clbit_last_node, new_node, Wire::Clbit(clbit));
-                    nodes_to_connect.insert(clbit_last_node);
-                }
+                self.dag
+                    .add_edge(clbit_last_node, new_node, Wire::Clbit(clbit));
             }
 
             // If available, check all the vars in this instruction
@@ -6345,15 +6337,12 @@ impl DAGCircuit {
                 };
 
                 vars_last_nodes.set_item(var, new_node.index())?;
-                if !nodes_to_connect.contains(&var_last_node) {
-                    if var_last_node == new_node {
-                        // TODO: Fix instances of duplicate nodes for Vars
-                        continue;
-                    }
-                    self.dag
-                        .add_edge(var_last_node, new_node, Wire::Var(var.clone_ref(py)));
-                    nodes_to_connect.insert(var_last_node);
+                if var_last_node == new_node {
+                    // TODO: Fix instances of duplicate nodes for Vars
+                    continue;
                 }
+                self.dag
+                    .add_edge(var_last_node, new_node, Wire::Var(var.clone_ref(py)));
             }
         }