diff --git a/src/rp2350/pico_platform/include/pico/asm_helper.S b/src/rp2350/pico_platform/include/pico/asm_helper.S index 7ff55c44c..b8eeb53c7 100644 --- a/src/rp2350/pico_platform/include/pico/asm_helper.S +++ b/src/rp2350/pico_platform/include/pico/asm_helper.S @@ -6,12 +6,17 @@ #include "pico.h" +#ifdef __riscv +// Get macros for convenient use of Hazard3 instructions without binutils support +#include "hardware/hazard3/instructions.h" +#endif + #if !PICO_ASSEMBLER_IS_CLANG #define apsr_nzcv r15 #endif -# note we don't do this by default in this file for backwards comaptibility with user code -# that may include this file, but not use unified syntax. Note that this macro does equivalent -# setup to the pico_default_asm macro for inline assembly in C code. +// note we don't do this by default in this file for backwards comaptibility with user code +// that may include this file, but not use unified syntax. Note that this macro does equivalent +// setup to the pico_default_asm macro for inline assembly in C code. .macro pico_default_asm_setup #ifndef __riscv .syntax unified @@ -60,28 +65,7 @@ weak_func WRAPPER_FUNC_NAME(\x) .word \func + \offset .endm -# backwards compatibility +// backwards compatibility .macro __pre_init func, priority_string1 __pre_init_with_offset func, 0, priority_string1 .endm - -#ifdef __riscv -// rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits) -.macro h3.bextm rd rs1 rs2 nbits -.if (\nbits < 1) || (\nbits > 8) -.err -.endif - .insn r 0x0b, 0x4, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2 -.endm - -// rd = (rs1 >> shamt) & ~(-1 << nbits) -.macro h3.bextmi rd rs1 shamt nbits -.if (\nbits < 1) || (\nbits > 8) -.err -.endif -.if (\shamt < 0) || (\shamt > 31) -.err -.endif - .insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6) -.endm -#endif \ No newline at end of file diff --git a/src/rp2_common/hardware_hazard3/include/hardware/hazard3.h b/src/rp2_common/hardware_hazard3/include/hardware/hazard3.h index 77272ff80..8484d12db 100644 --- a/src/rp2_common/hardware_hazard3/include/hardware/hazard3.h +++ b/src/rp2_common/hardware_hazard3/include/hardware/hazard3.h @@ -4,13 +4,18 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _HARDWARE_HAZARD3_ -#define _HARDWARE_HAZARD3_ +#ifndef _HARDWARE_HAZARD3_H +#define _HARDWARE_HAZARD3_H #include "pico.h" #include "hardware/riscv.h" + +// This includes both standard and Hazard3 custom CSRs: #include "hardware/regs/rvcsr.h" +#include "hardware/hazard3/features.h" +#include "hardware/hazard3/instructions.h" + /** \file hardware/hazard3.h * \defgroup hardware_hazard3 hardware_hazard3 * @@ -18,87 +23,7 @@ * */ -// Feature detection macros for Hazard3 custom extensions -#if PICO_RP2350 -#define __hazard3_extension_xh3power -#define __hazard3_extension_xh3bextm -#define __hazard3_extension_xh3irq -#define __hazard3_extension_xh3pmpm -#endif - -#ifdef __ASSEMBLER__ - -// Assembly language instruction macros for Hazard3 custom instructions - -// h3.bextm: Extract up to 8 consecutive bits from register rs1, with the -// first bit indexed by rs2, and bit count configured by an immediate value. -// R-format instruction. Pseudocode: -// -// rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits) - -.macro h3.bextm rd rs1 rs2 nbits -.if (\nbits < 1) || (\nbits > 8) -.err -.endif -#ifdef __hazard3_extension_xh3bextm - .insn r 0x0b, 0x4, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2 -#else - srl \rd, \rs1, \rs2 - andi \rd, \rd, ((1 << \nbits) - 1) -#endif -.endm - -// h3.bextmi: Extract up to 8 consecutive bits from register rs1, with the -// first bit index and the number of bits both configured by immediate -// values. I-format instruction. Pseudocode: -// -// rd = (rs1 >> shamt) & ~(-1 << nbits) - -.macro h3.bextmi rd rs1 shamt nbits -.if (\nbits < 1) || (\nbits > 8) -.err -.endif -.if (\shamt < 0) || (\shamt > 31) -.err -.endif -#ifdef __hazard3_extension_xh3bextm - .insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6) -#else - srli \rd, \rs1, \shamt - andi \rd, \rd, ((1 << \nbits) - 1) -#endif -.endm - -// h3.block: enter an idle state until another processor in the same -// multiprocessor complex executes an h3.unblock instruction, or the -// processor is interrupted. Fall through immediately if an h3.unblock has -// been received since the last execution of an h3.block on this processor. -// On RP2350, processors also have their own h3.unblock signals reflected -// back to them. - -.macro h3.block -#ifdef __hazard3_extension_xh3power - slt x0, x0, x0 -#else - nop -#endif -.endm - -// h3.unblock: signal other processors in the same multiprocessor complex to -// exit the idle state entered by an h3.block instruction. On RP2350, this -// signal is also reflected back to the processor that executed the -// h3.unblock, which will cause that processor's next h3.block to fall -// through immediately. - -.macro h3.unblock -#ifdef __hazard3_extension_xh3power - slt x0, x0, x1 -#else - nop -#endif -.endm - -#else // !__ASSEMBLER__ +#ifndef __ASSEMBLER__ #ifdef __cplusplus extern "C" { @@ -128,51 +53,6 @@ extern "C" { #define hazard3_irqarray_clear(csr, index, data) static_assert(false, "Not supported: Xh3irq extension") #endif - -// nbits must be a constant expression -#ifdef __hazard3_extension_xh3bextm -#define __hazard3_bextm(nbits, rs1, rs2) ({\ - uint32_t __h3_bextm_rd; \ - asm (".insn r 0x0b, 0, %3, %0, %1, %2"\ - : "=r" (__h3_bextm_rd) \ - : "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\ - ); \ - __h3_bextm_rd; \ -}) -#else -#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((rs2) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) -#endif - -// nbits and shamt must be constant expressions -#ifdef __hazard3_extension_xh3bextm -#define __hazard3_bextmi(nbits, rs1, shamt) ({\ - uint32_t __h3_bextmi_rd; \ - asm (".insn i 0x0b, 0x4, %0, %1, %2"\ - : "=r" (__h3_bextmi_rd) \ - : "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \ - ); \ - __h3_bextmi_rd; \ -}) -#else -#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((shamt) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) -#endif - -#ifdef __hazard3_extension_xh3power -#define __hazard3_block() asm volatile ("slt x0, x0, x0" : : : "memory") -#else -#define __hazard3_block() do {} while (0) -#endif - -#ifdef __hazard3_extension_xh3power -#define __hazard3_unblock() asm volatile ("slt x0, x0, x1" : : : "memory") -#else -#define __hazard3_unblock() do {} while (0) #endif -#ifdef __cplusplus -} -#endif - -#endif // !__ASSEMBLER__ - #endif diff --git a/src/rp2_common/hardware_hazard3/include/hardware/hazard3/features.h b/src/rp2_common/hardware_hazard3/include/hardware/hazard3/features.h new file mode 100644 index 000000000..25e5d2fba --- /dev/null +++ b/src/rp2_common/hardware_hazard3/include/hardware/hazard3/features.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_HAZARD3_FEATURES_H +#define _HARDWARE_HAZARD3_FEATURES_H + +#include "pico.h" + +/** \file hardware/hazard3/features.h + * \addtogroup hardware_hazard3 + * + * \brief Sets macros for supported Hazard3 custom extensions (features) based on PICO_PLATFORM macros + * + */ + +// Feature detection macros for Hazard3 custom extensions +#if PICO_RP2350 +// Version 1.0 of these four extensions +// (encoded as major * 100 + minor) +#define __hazard3_extension_xh3power 100 +#define __hazard3_extension_xh3bextm 100 +#define __hazard3_extension_xh3irq 100 +#define __hazard3_extension_xh3pmpm 100 +#endif + +#endif diff --git a/src/rp2_common/hardware_hazard3/include/hardware/hazard3/instructions.h b/src/rp2_common/hardware_hazard3/include/hardware/hazard3/instructions.h new file mode 100644 index 000000000..7abeb5ba6 --- /dev/null +++ b/src/rp2_common/hardware_hazard3/include/hardware/hazard3/instructions.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_HAZARD3_INSTRUCTIONS_H +#define _HARDWARE_HAZARD3_INSTRUCTIONS_H + +#include "pico.h" + +// Get list of supported extensions based on platform: +#include "hardware/hazard3/features.h" + +/** \file hardware/hazard3/instructions.h + * \addtogroup hardware_hazard3 + * + * \brief Intrinsics and asm macros for Hazard3 custom instructions + * + * The implementation of these intrinsics depends on the feature macros + * defined in hardware/hazard3/features.h. When the relevant feature is not + * present, the intrinsics fall back on an RV32I equivalent if possible. + * + */ + +#ifdef __ASSEMBLER__ + +// Assembly language instruction macros for Hazard3 custom instructions + +// h3.bextm: Extract up to 8 consecutive bits from register rs1, with the +// first bit indexed by rs2, and bit count configured by an immediate value. +// R-format instruction. Pseudocode: +// +// rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits) + +.macro h3.bextm rd rs1 rs2 nbits +.if (\nbits < 1) || (\nbits > 8) +.err +.endif +#ifdef __hazard3_extension_xh3bextm + .insn r 0x0b, 0x4, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2 +#else + srl \rd, \rs1, \rs2 + andi \rd, \rd, ((1 << \nbits) - 1) +#endif +.endm + +// h3.bextmi: Extract up to 8 consecutive bits from register rs1, with the +// first bit index and the number of bits both configured by immediate +// values. I-format instruction. Pseudocode: +// +// rd = (rs1 >> shamt) & ~(-1 << nbits) + +.macro h3.bextmi rd rs1 shamt nbits +.if (\nbits < 1) || (\nbits > 8) +.err +.endif +.if (\shamt < 0) || (\shamt > 31) +.err +.endif +#ifdef __hazard3_extension_xh3bextm + .insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6) +#else + srli \rd, \rs1, \shamt + andi \rd, \rd, ((1 << \nbits) - 1) +#endif +.endm + +// h3.block: enter an idle state until another processor in the same +// multiprocessor complex executes an h3.unblock instruction, or the +// processor is interrupted. Fall through immediately if an h3.unblock has +// been received since the last execution of an h3.block on this processor. +// On RP2350, processors also have their own h3.unblock signals reflected +// back to them. + +.macro h3.block +#ifdef __hazard3_extension_xh3power + slt x0, x0, x0 +#else + nop +#endif +.endm + +// h3.unblock: signal other processors in the same multiprocessor complex to +// exit the idle state entered by an h3.block instruction. On RP2350, this +// signal is also reflected back to the processor that executed the +// h3.unblock, which will cause that processor's next h3.block to fall +// through immediately. + +.macro h3.unblock +#ifdef __hazard3_extension_xh3power + slt x0, x0, x1 +#else + nop +#endif +.endm + +#else // !__ASSEMBLER__ + +// C language instruction macros for Hazard3 custom instructions + +#ifdef __cplusplus +extern "C" { +#endif + +// nbits must be a constant expression +#ifdef __hazard3_extension_xh3bextm +#define __hazard3_bextm(nbits, rs1, rs2) ({\ + uint32_t __h3_bextm_rd; \ + asm (".insn r 0x0b, 0, %3, %0, %1, %2"\ + : "=r" (__h3_bextm_rd) \ + : "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\ + ); \ + __h3_bextm_rd; \ +}) +#else +#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((rs2) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) +#endif + +// nbits and shamt must be constant expressions +#ifdef __hazard3_extension_xh3bextm +#define __hazard3_bextmi(nbits, rs1, shamt) ({\ + uint32_t __h3_bextmi_rd; \ + asm (".insn i 0x0b, 0x4, %0, %1, %2"\ + : "=r" (__h3_bextmi_rd) \ + : "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \ + ); \ + __h3_bextmi_rd; \ +}) +#else +#define __hazard3_bextm(nbits, rs1, rs2) (((rs1) >> ((shamt) & 0x1f)) & (0xffu >> (7 - (((nbits) - 1) & 0x7)))) +#endif + +#ifdef __hazard3_extension_xh3power +#define __hazard3_block() asm volatile ("slt x0, x0, x0" : : : "memory") +#else +#define __hazard3_block() do {} while (0) +#endif + +#ifdef __hazard3_extension_xh3power +#define __hazard3_unblock() asm volatile ("slt x0, x0, x1" : : : "memory") +#else +#define __hazard3_unblock() do {} while (0) +#endif + +#ifdef __cplusplus +} +#endif + +#endif // !__ASSEMBLER__ + +#endif diff --git a/src/rp2_common/pico_float/CMakeLists.txt b/src/rp2_common/pico_float/CMakeLists.txt index 086628221..7d53274ff 100644 --- a/src/rp2_common/pico_float/CMakeLists.txt +++ b/src/rp2_common/pico_float/CMakeLists.txt @@ -10,11 +10,7 @@ # add alias "default" which is just pico. add_library(pico_float_default INTERFACE) - if (PICO_RISCV) - target_link_libraries(pico_float_default INTERFACE pico_float_compiler) - else() - target_link_libraries(pico_float_default INTERFACE pico_float_pico) - endif() + target_link_libraries(pico_float_default INTERFACE pico_float_pico) set(PICO_DEFAULT_FLOAT_IMPL pico_float_default) @@ -128,6 +124,10 @@ wrap_float_functions(pico_float_pico_vfp NO_WRAP_AEABI) target_link_libraries(pico_float_pico INTERFACE pico_float_pico_vfp) + else() + target_sources(pico_float_pico INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/float_single_hazard3.S + ) endif() diff --git a/src/rp2_common/pico_float/float_single_hazard3.S b/src/rp2_common/pico_float/float_single_hazard3.S new file mode 100644 index 000000000..1e57f1f25 --- /dev/null +++ b/src/rp2_common/pico_float/float_single_hazard3.S @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pico/asm_helper.S" +#include "hardware/hazard3.h" + +// This file reimplements some common single-precision soft float routines +// from libgcc. It targets the RV32IMBZbkb dialect (plus optionally Xh3bextm) +// and is tuned for Hazard3 execution timings. + +// Subnormal values are always flushed to zero on both input and output. +// Rounding is always to nearest (even on tie). + +pico_default_asm_setup + +.macro float_section name +#if PICO_FLOAT_IN_RAM +.section RAM_SECTION_NAME(\name), "ax" +#else +.section SECTION_NAME(\name), "ax" +#endif +.endm + +float_section __addsf3 +.global __subsf3 +.p2align 2 +__subsf3: + binvi a1, a1, 31 +.global __addsf3 +__addsf3: + // Unpack exponent: + h3.bextmi a2, a0, 23, 8 + h3.bextmi a3, a1, 23, 8 + // Flush-to-zero => 0 + y = y applies, including nan, with the sole + // exception of y being subnormal (which also needs to be flushed) + beqz a2, __addsf_return_y_flushed + // Don't have to handle this case for x + 0 = 0 because we already know x + // is nonzero + beqz a3, __addsf_return_x + // Unpack significand, plus 3 extra zeroes for working space: + slli a4, a0, 9 + slli a5, a1, 9 + // check nan/inf on input + li t0, 255 + beq a2, t0, __addsf_x_nan_inf + beq a3, t0, __addsf_y_nan_inf + // (finish unpacking significand) + srli a4, a4, 6 + srli a5, a5, 6 + + // If we're still on the straight path then we are adding two normal + // values. Add implicit one (1.xx...xx000) + bseti a4, a4, 23 + 3 + bseti a5, a5, 23 + 3 + // Negate if sign bit is set + bgez a0, 1f + neg a4, a4 +1: + // (tuck this 16-bit here to avoid alignment penalty) + li t1, 25 + bgez a1, 1f + neg a5, a5 +1: + + bltu a2, a3, __addsf_ye_gt_xe + + // The main body is repeated twice with different register assignments. + // lhs is the more-significant addend: +.macro addsf_core packed_lhs, packed_rhs, sig_lhs, sig_rhs, exp_lhs, exp_rhs, rhs_is_x + sub \packed_rhs, \exp_lhs, \exp_rhs + // If there is a large exponent difference then there is no effect on lhs +.if \rhs_is_x + bgeu \packed_rhs, t1, __addsf_return_y +.else + bgeu \packed_rhs, t1, __addsf_return_x +.endif + // Shift rhs down to correct relative significance + sra \packed_lhs, \sig_rhs, \packed_rhs + // Set sticky bit if ones were shifted out + sll \packed_rhs, \packed_lhs, \packed_rhs + sltu \packed_rhs, \packed_rhs, \sig_rhs + or \packed_lhs, \packed_lhs, \packed_rhs + // Add significands + add \sig_lhs, \sig_lhs, \packed_lhs + // Detect exact cancellation (may be beyond max normalisation shift; also + // IEEE 754 requires +0 for exact cancellation, no matter input signs) + beqz \sig_lhs, __addsf_return_0 + // Convert two's complement back to sign + magnitude + srai \exp_rhs, \sig_lhs, 31 + xor \sig_lhs, \sig_lhs, \exp_rhs + sub \sig_lhs, \sig_lhs, \exp_rhs + // Renormalise significand: bit 31 is now implicit one + clz \packed_lhs, \sig_lhs + sll \sig_lhs, \sig_lhs, \packed_lhs + // Adjust exponent + addi \packed_lhs, \packed_lhs, -5 + sub \exp_lhs, \exp_lhs, \packed_lhs + + // Round to nearest, even on tie (bias upward if above odd number) + bexti \packed_lhs, \sig_lhs, 8 + addi \sig_lhs, \sig_lhs, 127 + add \sig_lhs, \sig_lhs, \packed_lhs + // Exponent may increase by one due to rounding up from all-ones; this is + // detected by clearing of implicit one (there is a carry-out too) + bgez \sig_lhs, 3f +4: + // Detect underflow/overflow + bgeu \exp_lhs, t0, 1f + + // Pack and return + packh \exp_lhs, \exp_lhs, \exp_rhs + slli \exp_lhs, \exp_lhs, 23 + slli \sig_lhs, \sig_lhs, 1 + srli \sig_lhs, \sig_lhs, 9 + add a0, \sig_lhs, \exp_lhs + ret +1: + bgez \exp_lhs, 2f + // Signed zero on underflow + slli a0, \exp_rhs, 31 + ret +2: + // Signed infinity on overflow + packh a0, t0, \exp_rhs + slli a0, a0, 23 + ret +3: + // Exponent increase due to rounding (uncommon) + srli \sig_lhs, \sig_lhs, 1 + addi \exp_lhs, \exp_lhs, 1 + j 4b +.endm + +__addsf_xe_gte_ye: + addsf_core a0, a1, a4, a5, a2, a3, 0 +.p2align 2 +__addsf_ye_gt_xe: + addsf_core a1, a0, a5, a4, a3, a2, 1 + +__addsf_x_nan_inf: + // When at least one operand is nan, we must propagate at least one of + // those nan payloads (sign of nan result is unspecified, which we take + // advantage of by implementing x - y as x + -y). Check x nan vs inf: + bnez a4, __addsf_return_x +__addsf_x_inf: + // If x is +-inf, need to distinguish the following cases: + bne a3, t0, __addsf_return_x // y is neither inf nor nan -> return x (propagate inf) + bnez a5, __addsf_return_y // y is nan: -> return y (propagate nan) + xor a5, a0, a1 + srli a5, a5, 31 + beqz a5, __addsf_return_x // y is inf of same sign -> return either x or y (x is faster) + li a0, -1 // y is inf of different sign -> return nan + ret + +__addsf_y_nan_inf: + // Mirror of __addsf_x_nan_inf + bnez a5, __addsf_return_y +__addsf_y_inf: + bne a2, t0, __addsf_return_y + bnez a4, __addsf_return_x + xor a4, a0, a1 + srli a4, a4, 31 + beqz a4, __addsf_return_x + li a0, -1 + ret + +__addsf_return_y_flushed: + bnez a3, 1f + srli a1, a1, 23 + slli a1, a1, 23 +1: +__addsf_return_y: + mv a0, a1 +__addsf_return_x: + ret +__addsf_return_0: + li a0, 0 + ret + + +float_section __mulsf3 +.global __mulsf3 +.p2align 2 +__mulsf3: + // Force y to be positive (by possibly negating x) *before* unpacking. + // This allows many special cases to be handled without repacking. + bgez a1, 1f + binvi a0, a0, 31 +1: + // Unpack exponent: + h3.bextmi a2, a0, 23, 8 + h3.bextmi a3, a1, 23, 8 + // Check special cases + li t0, 255 + beqz a2, __mulsf_x_0 + beqz a3, __mulsf_y_0 + beq a2, t0, __mulsf_x_nan_inf + beq a3, t0, __mulsf_y_nan_inf + + // Finish unpacking sign + srai a6, a0, 31 + // Unpack significand (with implicit one in MSB) + slli a4, a0, 8 + slli a5, a1, 8 + bseti a4, a4, 31 + bseti a5, a5, 31 + // Get full 64-bit multiply result in a4:a1 (one cycle each half) + // Going from Q1.23 to Q2.46 (both left-justified) + mul a1, a4, a5 + mulhu a4, a4, a5 + // Normalise (shift left by either 0 or 1) -- bit 8 is the LSB of the + // final significand (ignoring rounding) + clz a0, a4 + sll a4, a4, a0 + sub a2, a2, a0 + // After normalising we can calculate the final exponent, since rounding + // cannot increase the exponent for multiplication (unlike addition) + add a2, a2, a3 + // Subtract redundant bias term (127), add 1 for normalisation correction + addi a2, a2, -126 + blez a2, __mulsf_underflow + bge a2, t0, __mulsf_overflow + + // Gather sticky bits from low fraction: + snez a1, a1 + or a4, a4, a1 + // Round to nearest, even on tie (aka bias upward if odd) + bexti a1, a4, 8 + add a4, a4, a1 + addi a4, a4, 127 + // Pack it and ship it + packh a2, a2, a6 + slli a2, a2, 23 + slli a4, a4, 1 + srli a4, a4, 9 + add a0, a4, a2 + ret + +__mulsf_underflow: + // Signed zero + slli a0, a6, 31 + ret +__mulsf_overflow: + // Signed inf + packh a0, t0, a6 + slli a0, a0, 23 + ret + +__mulsf_x_0: + // 0 times nan -> propagate nan + // 0 times inf -> generate nan + // 0 times others -> 0 (need to flush significand too as we are FTZ) + bne a3, t0, __mulsf_return_flushed_x + slli a5, a1, 9 + beqz a5, 1f + // Propagate nan from y +__mulsf_return_y: + mv a0, a1 + ret +1: + // Generate new nan + li a0, -1 + ret + +__mulsf_y_0: + // Mirror image of x_0 except we still return x for signed 0, since the + // signs were already resolved. + bne a2, t0, __mulsf_return_flushed_x + slli a1, a0, 9 + bnez a1, 1f + li a0, -1 +1: + ret + +__mulsf_return_flushed_x: + // If we don't support subnormals we at least need to flush to a canonical + // zero. This is just a sign bit in bit 31. + srli a0, a0, 31 + slli a0, a0, 31 +__mulsf_return_x: + ret + +__mulsf_x_nan_inf: + // We know that y is not zero and is positive. So... + // x is nan -> return x + // else y is nan -> return y + // else y is inf -> return x + // else y is normal -> return x + // (the order of the first two clauses is actually our free choice) + slli a4, a0, 9 + bnez a4, __mulsf_return_x + bne a3, t0, __mulsf_return_x + slli a5, a1, 9 + bnez a5, __mulsf_return_y + ret // return x + +__mulsf_y_nan_inf: + // We know that x is not zero, nan, nor inf. That just leaves normals. + // y is nan -> return y + // y is inf -> return inf * sgn(x) (since we already merged the signs) + slli a5, a1, 9 + bnez a5, __mulsf_return_y + srai a0, a0, 31 + packh a0, t0, a0 + slli a0, a0, 23 + ret + + +// This is a hack to improve soft float performance for the routines we don't +// implement (e.g. libm) in libraries built against a non-Zbb ISA dialect: +float_section __clz2si +.global __clz2si +__clz2si: + clz a0, a0 + ret diff --git a/src/rp2_common/pico_float/include/pico/float.h b/src/rp2_common/pico_float/include/pico/float.h index 70730279d..6cafc83e4 100644 --- a/src/rp2_common/pico_float/include/pico/float.h +++ b/src/rp2_common/pico_float/include/pico/float.h @@ -21,8 +21,8 @@ extern "C" { * * \brief Optimized single-precision floating point functions * -* (Replacement) optimized implementations are provided of the following compiler built-ins -* and math library functions: +* (Replacement) optimized implementations are provided for the following compiler built-ins +* and math library functions on Arm: * * - __aeabi_fadd, __aeabi_fdiv, __aeabi_fmul, __aeabi_frsub, __aeabi_fsub, __aeabi_cfcmpeq, __aeabi_cfrcmple, __aeabi_cfcmple, __aeabi_fcmpeq, __aeabi_fcmplt, __aeabi_fcmple, __aeabi_fcmpge, __aeabi_fcmpgt, __aeabi_fcmpun, __aeabi_i2f, __aeabi_l2f, __aeabi_ui2f, __aeabi_ul2f, __aeabi_f2iz, __aeabi_f2lz, __aeabi_f2uiz, __aeabi_f2ulz, __aeabi_f2d, sqrtf, cosf, sinf, tanf, atan2f, expf, logf * - ldexpf, copysignf, truncf, floorf, ceilf, roundf, asinf, acosf, atanf, sinhf, coshf, tanhf, asinhf, acoshf, atanhf, exp2f, log2f, exp10f, log10f, powf, hypotf, cbrtf, fmodf, dremf, remainderf, remquof, expm1f, log1pf, fmaf @@ -34,11 +34,18 @@ extern "C" { * - float2fix, float2ufix, float2fix64, float2ufix64, float2int, float2uint, float2int64, float2uint64, float2int_z, float2int64_z, float2uint_z, float2uint64_z * - exp10f, sincosf, powintf * -* On RP2350 the following additional functions are available; the _fast methods are faster but do not round correctly +* On RP2350 (Arm) the following additional functions are available; the _fast methods are faster but do not round correctly * * - float2fix64_z, fdiv_fast, fsqrt_fast, +* +* On RP2350 RISC-V, only a small number of compiler runtime functions are overridden with faster implementations: +* +* - __addsf3, __subsf3, __mulsf3 */ +// None of these functions are available on RISC-V: +#if !defined(__riscv) || PICO_COMBINED_DOCS + float int2float(int32_t f); float uint2float(uint32_t f); float int642float(int64_t f); @@ -74,6 +81,8 @@ float fdiv_fast(float n, float d); float fsqrt_fast(float f); #endif +#endif + #ifdef __cplusplus } #endif diff --git a/test/pico_float_test/CMakeLists.txt b/test/pico_float_test/CMakeLists.txt index e0e0a814a..971c2a6d7 100644 --- a/test/pico_float_test/CMakeLists.txt +++ b/test/pico_float_test/CMakeLists.txt @@ -1,7 +1,22 @@ PROJECT(pico_float_test) -# todo revist this test for -if (NOT PICO_RISCV) + +if (PICO_RISCV) + + # Separate, simpler test: currently we only have a few single-precision + # routines for RISC-V soft float (and the other tests are a bit + # AEABI-dependent) + add_executable(pico_float_test + pico_float_test_hazard3.c + ) + target_link_libraries(pico_float_test PRIVATE pico_float pico_stdlib) + target_include_directories(pico_float_test PRIVATE ${CMAKE_CURRENT_LIST_DIR}) + pico_add_extra_outputs(pico_float_test) + + # pico_enable_stdio_usb(pico_float_test 1) + # pico_enable_stdio_uart(pico_float_test 0) + +else () add_executable(pico_float_test pico_float_test.c llvm/call_apsr.S @@ -64,4 +79,4 @@ if (NOT PICO_RISCV) target_link_libraries(m33 pico_double pico_stdlib) pico_add_extra_outputs(m33) endif() -endif() \ No newline at end of file +endif() diff --git a/test/pico_float_test/hazard3_test_gen.c b/test/pico_float_test/hazard3_test_gen.c new file mode 100644 index 000000000..0367513f3 --- /dev/null +++ b/test/pico_float_test/hazard3_test_gen.c @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +// xoroshiro256++ pseudorandom number generator. +// Adapted from: https://prng.di.unimi.it/xoshiro256plusplus.c +// Original copyright notice: + +/* Written in 2019 by David Blackman and Sebastiano Vigna (vigna@acm.org) + +To the extent possible under law, the author has dedicated all copyright +and related and neighboring rights to this software to the public domain +worldwide. This software is distributed without any warranty. + +See . */ + +/* This is xoshiro256++ 1.0, one of our all-purpose, rock-solid generators. + It has excellent (sub-ns) speed, a state (256 bits) that is large + enough for any parallel application, and it passes all tests we are + aware of. + + For generating just floating-point numbers, xoshiro256+ is even faster. + + The state must be seeded so that it is not everywhere zero. If you have + a 64-bit seed, we suggest to seed a splitmix64 generator and use its + output to fill s. */ + +static inline uint64_t xr256_rotl(const uint64_t x, int k) { + return (x << k) | (x >> (64 - k)); +} + +uint64_t xr256_next(uint64_t s[4]) { + const uint64_t result = xr256_rotl(s[0] + s[3], 23) + s[0]; + + const uint64_t t = s[1] << 17; + + s[2] ^= s[0]; + s[3] ^= s[1]; + s[1] ^= s[2]; + s[0] ^= s[3]; + + s[2] ^= t; + + s[3] = xr256_rotl(s[3], 45); + + return result; +} +uint32_t bitcast_f2u(float x) { + // This is UB but then so is every C program + union { + float f; + uint32_t u; + } un; + un.f = x; + return un.u; +} + +float bitcast_u2f(uint32_t x) { + union { + float f; + uint32_t u; + } un; + un.u = x; + return un.f; +} + +bool is_nan_u(uint32_t x) { + return ((x >> 23) & 0xffu) == 0xffu && (x & ~(-1u << 23)); +} + +uint32_t flush_to_zero_u(uint32_t x) { + if (!(x & (0xffu << 23))) { + x &= -1u << 23; + } + return x; +} + +uint32_t model_fadd(uint32_t x, uint32_t y) { + x = flush_to_zero_u(x); + y = flush_to_zero_u(y); + // Use local hardware implementation to perform calculation + uint32_t result = bitcast_f2u(bitcast_u2f(x) + bitcast_u2f(y)); + // Use correct canonical generated nan + if (is_nan_u(result)) { + result = -1u; + } + result = flush_to_zero_u(result); + return result; +} + +uint32_t model_fmul(uint32_t x, uint32_t y) { + x = flush_to_zero_u(x); + y = flush_to_zero_u(y); + // Use local hardware implementation to perform calculation + uint32_t result = bitcast_f2u(bitcast_u2f(x) * bitcast_u2f(y)); + // Use correct canonical generated nan + if (is_nan_u(result)) { + result = -1u; + } + result = flush_to_zero_u(result); + return result; +} + +int main() { + // SHA-256 of a rude word + uint64_t rand_state[4] = { + 0x5891b5b522d5df08u, + 0x6d0ff0b110fbd9d2u, + 0x1bb4fc7163af34d0u, + 0x8286a2e846f6be03u + }; + for (int i = 0; i < 1000; ++i) { + uint32_t x, y; + x = xr256_next(rand_state) & 0xffffffffu; + y = xr256_next(rand_state) & 0xffffffffu; + // Map nan to +-inf (input nans should already be well-covered) + if (is_nan_u(x)) { + x &= -1u << 23; + } + if (is_nan_u(y)) { + y &= -1u << 23; + } +#if 1 + printf("{0x%08xu, 0x%08xu, 0x%08xu},\n", x, y, model_fadd(x, y)); +#else + printf("{0x%08xu, 0x%08xu, 0x%08xu},\n", x, y, model_fmul(x, y)); +#endif + } +} diff --git a/test/pico_float_test/pico_float_test_hazard3.c b/test/pico_float_test/pico_float_test_hazard3.c new file mode 100644 index 000000000..61f2a8e19 --- /dev/null +++ b/test/pico_float_test/pico_float_test_hazard3.c @@ -0,0 +1,209 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "pico/stdlib.h" + +// This test covers the single-precision functions in: +// +// src/pico_float/float_hazard3_single.S +// +// It assumes the canonical generated-NaN value and NaN sign rules used by +// those functions (which are unspecified by IEEE 754). It does not cover +// libgcc/libm functions from outside of that source file. + +typedef struct { + uint32_t x; + uint32_t y; + uint32_t expect; +} test_t; + +test_t add_directed_tests[] = { + // 1 + 1 = 2 + {0x3f800000u, 0x3f800000u, 0x40000000u}, + // 2 + 1 = 3 + {0x40000000u, 0x3f800000u, 0x40400000u}, + // 1 + 2 = 3 + {0x3f800000u, 0x40000000u, 0x40400000u}, + // 1 + -1 = +0 (exact cancellation) + {0x3f800000u, 0xbf800000u, 0x00000000u}, + // -1 + 1 = +0 (exact cancellation) + {0xbf800000u, 0x3f800000u, 0x00000000u}, + // 1 + <<1 ulp = 1 + {0x3f800000u, 0x2f800000u, 0x3f800000u}, + // <<1 ulp + 1 = 1 + {0x2f800000u, 0x3f800000u, 0x3f800000u}, + // -1 + 1.25 = 0.25 + {0xbf800000u, 0x3fa00000u, 0x3e800000u}, + // max normal + 0.5 ulp = +inf + {0x7f7fffffu, 0x73000000u, 0x7f800000u}, + // max normal + max normal = +inf + {0x7f7fffffu, 0x7f7fffffu, 0x7f800000u}, + // min normal - 0.5 ulp = -inf + {0xff7fffffu, 0xf3000000u, 0xff800000u}, + // min normal + min_normal = -inf + {0xff7fffffu, 0xff7fffffu, 0xff800000u}, + // max normal + 0.499... ulp = max normal + {0x7f7fffffu, 0x72ffffffu, 0x7f7fffffu}, + // min normal - 0.499... ulp = min normal + {0xff7fffffu, 0xf2ffffffu, 0xff7fffffu}, + // nan + 0 = same nan + {0xffff1234u, 0x00000000u, 0xffff1234u}, + // 0 + nan = same nan + {0x00000000u, 0xffff1234u, 0xffff1234u}, + // nan + 1 = same nan + {0xffff1234u, 0x3f800000u, 0xffff1234u}, + // 1 + nan = same nan + {0x3f800000u, 0xffff1234u, 0xffff1234u}, + // nan + inf = same nan + {0xffff1234u, 0x7f800000u, 0xffff1234u}, + // inf + nan = same nan + {0x7f800000u, 0xffff1234u, 0xffff1234u}, + // inf + inf = inf + {0x7f800000u, 0x7f800000u, 0x7f800000u}, + // -inf + -inf = -inf + {0xff800000u, 0xff800000u, 0xff800000u}, + // inf + -inf = nan (all-ones is our canonical cheap nan) + {0x7f800000u, 0xff800000u, 0xffffffffu}, + // -inf + inf = nan + {0xff800000u, 0x7f800000u, 0xffffffffu}, + // subnormal + subnormal = exactly 0 + {0x007fffffu, 0x007fffffu, 0x00000000u}, + // -subnormal + -subnormal = exactly -0 + {0x807fffffu, 0x807fffffu, 0x80000000u}, + // Even + 0.5 ulp: round down + {0x3f800002u, 0x33800000u, 0x3f800002u}, + // Even - 0.5 ulp: round up + {0x3f800002u, 0xb3800000u, 0x3f800002u}, + // Odd + 0.5 ulp: round up + {0x3f800001u, 0x33800000u, 0x3f800002u}, + // Odd - 0.5 ulp: round down + {0x3f800001u, 0xb3800000u, 0x3f800000u}, + // All-zeroes significand - 0.5 ulp: no rounding (exact) + {0x3f800000u, 0xb3800000u, 0x3f7fffffu}, + // Very subnormal difference of normals: flushed to zero + {0x03800000u, 0x837fffffu, 0x00000000u}, + // Barely subnormal difference of normals: also flushed (unflushed result is 2^(emin-1)) + {0x03800000u, 0x837e0000u, 0x00000000u}, +}; + +test_t mul_directed_tests[] = { + // -- directed tests -- + // 1 * 1 = 1 + {0x3f800000u, 0x3f800000u, 0x3f800000u}, + // 1 * -1 = -1 + {0x3f800000u, 0xbf800000u, 0xbf800000u}, + // -1 * 1 = -1 + {0xbf800000u, 0x3f800000u, 0xbf800000u}, + // -1 * -1 = 1 + {0xbf800000u, 0xbf800000u, 0x3f800000u}, + // -0 * 0 = -0 + {0x80000000u, 0x00000000u, 0x80000000u}, + // 0 * -0 = - 0 + {0x00000000u, 0x80000000u, 0x80000000u}, + // 1 * 2 = 2 + {0x3f800000u, 0x40000000u, 0x40000000u}, + // 2 * 1 = 2 + {0x40000000u, 0x3f800000u, 0x40000000u}, + // inf * inf = inf + {0x7f800000u, 0x7f800000u, 0x7f800000u}, + // inf * -inf = -inf + {0x7f800000u, 0xff800000u, 0xff800000u}, + // inf * 0 = nan + {0x7f800000u, 0x00000000u, 0xffffffffu}, + // 0 * inf = nan + {0x00000000u, 0x7f800000u, 0xffffffffu}, + // 1 * -inf = -inf + {0x3f800000u, 0xff800000u, 0xff800000u}, + // -inf * 1 = -inf + {0xff800000u, 0x3f800000u, 0xff800000u}, + // -1 * inf = -inf + {0xbf800000u, 0x7f800000u, 0xff800000u}, + // inf * -1 = -inf + {0x7f800000u, 0xbf800000u, 0xff800000u}, + // 1 * nonzero subnormal = exactly 0 + {0x3f800000u, 0x007fffffu, 0x00000000u}, + // nonzero subnormal * -1 = exactly -0 + {0x007fffffu, 0xbf800000u, 0x80000000u}, + // nan * 0 = same nan + {0xffff1234u, 0x00000000u, 0xffff1234u}, + // 0 * nan = same nan + {0x00000000u, 0xffff1234u, 0xffff1234u}, + // nan * 1 = same nan + {0xffff1234u, 0x3f800000u, 0xffff1234u}, + // 1 * nan = same nan + {0x3f800000u, 0xffff1234u, 0xffff1234u}, + // nan * inf = same nan + {0xffff1234u, 0x7f800000u, 0xffff1234u}, + // inf * nan = same nan + {0x7f800000u, 0xffff1234u, 0xffff1234u}, + // (2 - 0.5 ulp) x (2 - 0.5 ulp) = 4 - 0.5 ulp + {0x3fffffffu, 0x3fffffffu, 0x407ffffeu}, + // (2 - 0.5 ulp) x (1 + 1 ulp) = 2 exactly + {0xbfffffffu, 0x3f800001u, 0xc0000000u}, + // 1.666... * 1.333.. = 2.222... + {0x3fd55555u, 0x3faaaaaau, 0x400e38e3u}, + // 1.25 x 2^-63 x 1.25 x 2^-64 = 0 + // (normal inputs with subnormal output, and we claim to be FTZ) + {0x20200000u, 0x1fa00000u, 0x00000000u}, +}; + +#define N_RANDOM_TESTS 1000 +extern test_t add_random_tests[N_RANDOM_TESTS]; +extern test_t mul_random_tests[N_RANDOM_TESTS]; + +uint32_t __addsf3(uint32_t x, uint32_t y); +uint32_t __mulsf3(uint32_t x, uint32_t y); + +int run_tests(test_t *tests, int n_tests, const char *op_str, uint32_t (*func)(uint32_t, uint32_t)) { + int failed = 0; + for (int i = 0; i < n_tests; ++i) { + uint32_t actual = func(tests[i].x, tests[i].y); + if (tests[i].expect != actual) { + printf("%08x %s %08x -> %08x", tests[i].x, op_str, tests[i].y, tests[i].expect); + printf(" FAIL: got %08x\n", actual); + ++failed; + } + } + printf("Passed: %d / %d\n", n_tests - failed, n_tests); + return failed; +} + +int main() { + stdio_init_all(); + int failed = 0; + sleep_ms(3000); + printf("Testing: __addsf3 (directed tests)\n"); + failed += run_tests(add_directed_tests, count_of(add_directed_tests), "+", __addsf3); + printf("Testing: __mulsf3 (directed tests)\n"); + failed += run_tests(mul_directed_tests, count_of(mul_directed_tests), "*", __mulsf3); + if (failed) { + printf("Skipping random tests due to %d test failures\n", failed); + goto done; + } + printf("Testing: __addsf3 (random tests)\n"); + failed += run_tests(add_random_tests, N_RANDOM_TESTS, "+", __addsf3); + printf("Testing: __mulsf3 (random tests)\n"); + failed += run_tests(mul_random_tests, N_RANDOM_TESTS, "*", __mulsf3); + + printf("%d tests failed.\n", failed); + if (failed == 0) { + printf("Well done, you can relax now\n"); + } +done: + while (true) {asm volatile ("wfi\n");} // keep USB stdout alive + return 0; +} + +// Generated using the FPU on my machine (Zen 4) plus FTZ on inputs/outputs +// See hazard3_test_gen.c +test_t add_random_tests[N_RANDOM_TESTS] = { +#include "vectors/hazard3_addsf.inc" +}; + +test_t mul_random_tests[N_RANDOM_TESTS] = { +#include "vectors/hazard3_mulsf.inc" +}; diff --git a/test/pico_float_test/vectors/hazard3_addsf.inc b/test/pico_float_test/vectors/hazard3_addsf.inc new file mode 100644 index 000000000..1e651863d --- /dev/null +++ b/test/pico_float_test/vectors/hazard3_addsf.inc @@ -0,0 +1,1000 @@ +{0xa8c36b34u, 0x420ac26bu, 0x420ac26bu}, +{0xd4cf10fbu, 0x692b079au, 0x692b079au}, +{0xece2254du, 0xf36c2cbbu, 0xf36c33ccu}, +{0x34f22bceu, 0x7c3b1110u, 0x7c3b1110u}, +{0x8b187e6fu, 0xa51e4bfcu, 0xa51e4bfcu}, +{0x0fe7c179u, 0xf0dcc0beu, 0xf0dcc0beu}, +{0x768e7ddbu, 0x2ccdc929u, 0x768e7ddbu}, +{0x06f19a7fu, 0x07562985u, 0x07a77b62u}, +{0xa20ff19cu, 0xa6a951a3u, 0xa6a9999cu}, +{0x64120a7fu, 0x935577e7u, 0x64120a7fu}, +{0x900ed7f5u, 0x970a63d2u, 0x970a660du}, +{0xec7a91c8u, 0x00eb6ee1u, 0xec7a91c8u}, +{0x87e4daa6u, 0xc88e8901u, 0xc88e8901u}, +{0xf005a09du, 0xcbf5a56eu, 0xf005a09du}, +{0x112e23edu, 0x7be85175u, 0x7be85175u}, +{0x04f3339au, 0x3a78a8b1u, 0x3a78a8b1u}, +{0x0a3232f6u, 0xea32f851u, 0xea32f851u}, +{0xc98f9ea4u, 0xebf90ffbu, 0xebf90ffbu}, +{0xed8bd406u, 0x9502d86fu, 0xed8bd406u}, +{0x0ab44d09u, 0x940a9806u, 0x940a97efu}, +{0x53117f9fu, 0x53160ff3u, 0x5393c7c9u}, +{0x455cf9c4u, 0x091efc06u, 0x455cf9c4u}, +{0x9d04dffdu, 0x9edd80dfu, 0x9eee1cdfu}, +{0x90c2fa22u, 0x93b5cbacu, 0x93b8d795u}, +{0x3c093424u, 0x9c303566u, 0x3c093424u}, +{0xd24a550du, 0x407dcb3au, 0xd24a550du}, +{0xd2d5e0d8u, 0xca9b966au, 0xd2d5e174u}, +{0x72d858b8u, 0x4c1960eeu, 0x72d858b8u}, +{0x9a63d2c3u, 0xcb110969u, 0xcb110969u}, +{0xe45bfe13u, 0xfc3a9028u, 0xfc3a9028u}, +{0x57c64c27u, 0x5273314du, 0x57c66a8du}, +{0xa72f1718u, 0xc739117fu, 0xc739117fu}, +{0x90cdb148u, 0x2eabbf2eu, 0x2eabbf2eu}, +{0xb2b429d1u, 0x821353fdu, 0xb2b429d1u}, +{0xe202a662u, 0x62997577u, 0x6230448cu}, +{0xc60df1c6u, 0xed07b0f2u, 0xed07b0f2u}, +{0x471b9543u, 0x08082cefu, 0x471b9543u}, +{0x6455a3a1u, 0x45398a87u, 0x6455a3a1u}, +{0x29186441u, 0x62e3a555u, 0x62e3a555u}, +{0xe2c75f26u, 0x3599d32eu, 0xe2c75f26u}, +{0xf4bebe05u, 0xcb41a1a2u, 0xf4bebe05u}, +{0xc76ef852u, 0xd3598bb3u, 0xd3598bb4u}, +{0xc05c09e9u, 0x632ab30au, 0x632ab30au}, +{0xc2cf6165u, 0xfb0298c1u, 0xfb0298c1u}, +{0xdef32a63u, 0x8cf06bb1u, 0xdef32a63u}, +{0x6309cbb1u, 0xe35417fau, 0xe2949892u}, +{0x6d985555u, 0xf5175c80u, 0xf5175b4fu}, +{0xe9ff5030u, 0x6756d007u, 0xe9f899b0u}, +{0xa422e9a4u, 0xaac9bd17u, 0xaac9c22eu}, +{0x9f73dbe2u, 0xd5eff474u, 0xd5eff474u}, +{0x79b20fb8u, 0x47ac4525u, 0x79b20fb8u}, +{0x79657aebu, 0x1f618dc6u, 0x79657aebu}, +{0x5634c9a9u, 0x7be5371fu, 0x7be5371fu}, +{0xfdee3dc7u, 0x2e8e3e83u, 0xfdee3dc7u}, +{0x5a1ac874u, 0x13a1d923u, 0x5a1ac874u}, +{0x16b2d812u, 0xdd6d97ebu, 0xdd6d97ebu}, +{0x9ed19073u, 0x76251aa0u, 0x76251aa0u}, +{0x8da689c9u, 0x879b3f68u, 0x8da6937du}, +{0x286d1e51u, 0xfa5a7310u, 0xfa5a7310u}, +{0x056fd052u, 0x69d08989u, 0x69d08989u}, +{0xc817e61au, 0xc10685d9u, 0xc817e834u}, +{0xf9f6dd82u, 0x2a8478c0u, 0xf9f6dd82u}, +{0xf8dda0c4u, 0x2199c318u, 0xf8dda0c4u}, +{0x12be4771u, 0x93f7babeu, 0x93c828e2u}, +{0x87025952u, 0x7343aac6u, 0x7343aac6u}, +{0xad1d7a9bu, 0x7719cbf0u, 0x7719cbf0u}, +{0x54f5897bu, 0xb35f912eu, 0x54f5897bu}, +{0xf7e27b8fu, 0x70e0c4d7u, 0xf7e2780cu}, +{0x3d616a83u, 0xde7053eeu, 0xde7053eeu}, +{0x587d62edu, 0x049ebffbu, 0x587d62edu}, +{0x69ca38e3u, 0xa5c40679u, 0x69ca38e3u}, +{0x4c69735du, 0x523e190du, 0x523e27a4u}, +{0x63cd7aafu, 0x5efe2fe2u, 0x63cdba3bu}, +{0xd58fc30fu, 0xbdb01383u, 0xd58fc30fu}, +{0x16c7da66u, 0xee4c113eu, 0xee4c113eu}, +{0x5e04dbefu, 0x6dba378fu, 0x6dba378fu}, +{0xc446094fu, 0x9ec4300du, 0xc446094fu}, +{0xb45c7b1au, 0xbf9add0au, 0xbf9add0cu}, +{0x527a78acu, 0xa9ec462fu, 0x527a78acu}, +{0x9c859f1bu, 0x326a03a0u, 0x326a03a0u}, +{0x1ecdbc33u, 0xd4deca58u, 0xd4deca58u}, +{0xc491b64du, 0xe4999dfbu, 0xe4999dfbu}, +{0xea0d3b6du, 0x152c5167u, 0xea0d3b6du}, +{0x6800639du, 0x9a7c0071u, 0x6800639du}, +{0x4e5ab470u, 0x2524d77fu, 0x4e5ab470u}, +{0xde821748u, 0x9a314294u, 0xde821748u}, +{0xd7d90f91u, 0x9dfddaf5u, 0xd7d90f91u}, +{0x9a6e422fu, 0x11ea2cb0u, 0x9a6e41bau}, +{0xfa305a4du, 0x9f8ef775u, 0xfa305a4du}, +{0x7f800000u, 0x7ecf8ff4u, 0x7f800000u}, +{0xf7dae75au, 0x5b89388du, 0xf7dae75au}, +{0x8ad2ce1bu, 0xfd15989eu, 0xfd15989eu}, +{0x8549054fu, 0x0715aa2fu, 0x070919dau}, +{0x08df8085u, 0x3290efa7u, 0x3290efa7u}, +{0xf9b05b50u, 0x45e3e467u, 0xf9b05b50u}, +{0xd618c7aau, 0x1a21e62eu, 0xd618c7aau}, +{0xb3e9d07du, 0x448a2a2au, 0x448a2a2au}, +{0x0817d23eu, 0x0e17145bu, 0x0e171dd8u}, +{0xf04863cfu, 0xb0dd3e34u, 0xf04863cfu}, +{0x85638413u, 0x621f50a4u, 0x621f50a4u}, +{0x9a347165u, 0x1ecf7f68u, 0x1ecf252fu}, +{0xaf5ada17u, 0x7552e217u, 0x7552e217u}, +{0x21533a8eu, 0x8b0c2dccu, 0x21533a8eu}, +{0x18191651u, 0x6543b033u, 0x6543b033u}, +{0xc571ce01u, 0x53ea5287u, 0x53ea5287u}, +{0xbb28e01cu, 0x473d6337u, 0x473d6336u}, +{0xc8a926bau, 0x4e62c441u, 0x4e62af1cu}, +{0x86e68079u, 0xac7bd4d7u, 0xac7bd4d7u}, +{0x47c8f07cu, 0x3cc49f10u, 0x47c8f07fu}, +{0x51021af4u, 0x5f10c5b9u, 0x5f10c5b9u}, +{0xe4632eb6u, 0x6b2d427fu, 0x6b2d3ef2u}, +{0xedc45634u, 0x5cdda5e6u, 0xedc45634u}, +{0xb84b8830u, 0x5b9592bcu, 0x5b9592bcu}, +{0x8938d3f5u, 0xca4e93a0u, 0xca4e93a0u}, +{0x12719b2bu, 0x9c8e3423u, 0x9c8e341bu}, +{0xb8bd54e7u, 0x7a605659u, 0x7a605659u}, +{0x06ec8b7eu, 0x5db893fbu, 0x5db893fbu}, +{0xf4ebdffeu, 0x40b27058u, 0xf4ebdffeu}, +{0x23350fafu, 0x98728c6au, 0x23350fabu}, +{0x706b89e4u, 0xddcfca5fu, 0x706b89e4u}, +{0xa5d39e54u, 0xdfd530dcu, 0xdfd530dcu}, +{0x1be13ddeu, 0xe872fa18u, 0xe872fa18u}, +{0x77f1e5ccu, 0xcd2aace2u, 0x77f1e5ccu}, +{0x2ba740c0u, 0xcd4f0df0u, 0xcd4f0df0u}, +{0xec00d47au, 0xe8afd26au, 0xec02341fu}, +{0xc4edce44u, 0xfc8ee969u, 0xfc8ee969u}, +{0x9be790c0u, 0x9e5342e7u, 0x9e5a7f6du}, +{0x9c3e0849u, 0xc0407137u, 0xc0407137u}, +{0x74d95ccau, 0x499ec4d6u, 0x74d95ccau}, +{0x4252fc0au, 0xaec0d9ceu, 0x4252fc0au}, +{0x5e1ebb93u, 0xa8859ebdu, 0x5e1ebb93u}, +{0x0d0175c2u, 0x7c008c86u, 0x7c008c86u}, +{0x250b16bdu, 0x407f9125u, 0x407f9125u}, +{0x296e1ea4u, 0x87e1aae2u, 0x296e1ea4u}, +{0xf4aba78eu, 0x2ef60552u, 0xf4aba78eu}, +{0x1d82e696u, 0xdeafc368u, 0xdeafc368u}, +{0xfcad4897u, 0x6b27581fu, 0xfcad4897u}, +{0xb5298a46u, 0x2935b912u, 0xb5298a45u}, +{0x53cc8f9eu, 0xeb6bcce3u, 0xeb6bcce3u}, +{0x554e7b84u, 0x53d11e1eu, 0x55689f48u}, +{0x22688415u, 0x70958cc3u, 0x70958cc3u}, +{0x152672b2u, 0x9a60547fu, 0x9a602ae2u}, +{0x14deaf74u, 0x50655ae7u, 0x50655ae7u}, +{0x4bbb9cf8u, 0xebebf934u, 0xebebf934u}, +{0x164083e6u, 0x4b5d0277u, 0x4b5d0277u}, +{0x1fd0f48bu, 0x92716a0bu, 0x1fd0f48bu}, +{0xd57bc2cdu, 0x7a392010u, 0x7a392010u}, +{0xfe8230beu, 0x3b624f0au, 0xfe8230beu}, +{0x8bce666bu, 0x1324deadu, 0x1324dd10u}, +{0x58961825u, 0x74813fddu, 0x74813fddu}, +{0x9463214bu, 0x3b2f08e5u, 0x3b2f08e5u}, +{0xe701da5fu, 0x8e7b3a11u, 0xe701da5fu}, +{0x0350403eu, 0xf613e135u, 0xf613e135u}, +{0x3b3e2a49u, 0xc31f1bcdu, 0xc31f1b0fu}, +{0xa73d56afu, 0x5ed1c217u, 0x5ed1c217u}, +{0xf9ef302cu, 0x3cea9b94u, 0xf9ef302cu}, +{0x7698bdb0u, 0x4f66c1e6u, 0x7698bdb0u}, +{0xd4ec1ba4u, 0xacc6705au, 0xd4ec1ba4u}, +{0x90e88632u, 0x07c44193u, 0x90e88601u}, +{0x6010566eu, 0x91ac29ffu, 0x6010566eu}, +{0xfa3447b4u, 0xbc8fd826u, 0xfa3447b4u}, +{0xcd4db5c2u, 0xe98c545du, 0xe98c545du}, +{0x77f16de5u, 0xd4ec082eu, 0x77f16de5u}, +{0x541fb093u, 0xfb6de113u, 0xfb6de113u}, +{0x56c1453fu, 0xe86d86ffu, 0xe86d86ffu}, +{0xd81da361u, 0x792a4904u, 0x792a4904u}, +{0x664cd3b5u, 0xc4e298f4u, 0x664cd3b5u}, +{0xc0f9fcceu, 0xcae84da2u, 0xcae84db2u}, +{0xce9ee780u, 0x8d978179u, 0xce9ee780u}, +{0x0e9ce349u, 0x792a101du, 0x792a101du}, +{0x86e2f8beu, 0xcc52355bu, 0xcc52355bu}, +{0x04cf751fu, 0xe5db081eu, 0xe5db081eu}, +{0xf3ef93bcu, 0x422c4ea0u, 0xf3ef93bcu}, +{0x264db607u, 0xd39183beu, 0xd39183beu}, +{0xd6bc3563u, 0x6a6190ccu, 0x6a6190ccu}, +{0xb636fc08u, 0x7eb3e8feu, 0x7eb3e8feu}, +{0xa197dfa7u, 0xaedfa4b6u, 0xaedfa4b6u}, +{0x073b76f1u, 0xeebcaef0u, 0xeebcaef0u}, +{0xe5ee7e35u, 0x1bc60178u, 0xe5ee7e35u}, +{0x1c2744a1u, 0x630a7678u, 0x630a7678u}, +{0x0c497b83u, 0x918c5692u, 0x918c3d63u}, +{0x2a171d73u, 0xc9a434bfu, 0xc9a434bfu}, +{0x823d1dcdu, 0x45f1b213u, 0x45f1b213u}, +{0xc0506450u, 0x4623ebf1u, 0x4623deebu}, +{0x9ae3c913u, 0x91050c92u, 0x9ae3c924u}, +{0xff0ed2e2u, 0x517fcb19u, 0xff0ed2e2u}, +{0xc473b53bu, 0x78092ec6u, 0x78092ec6u}, +{0x82032198u, 0xfb4cf76eu, 0xfb4cf76eu}, +{0x35980202u, 0xced3eeeeu, 0xced3eeeeu}, +{0xe7cedb64u, 0x296fd530u, 0xe7cedb64u}, +{0x277ff958u, 0xe8d7f50eu, 0xe8d7f50eu}, +{0x2cad366bu, 0x9cfbfeb0u, 0x2cad366bu}, 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0xc154f89cu, 0x7538e7c7u}, +{0xd88439a9u, 0x7f800000u, 0x7f800000u}, +{0xf807c86fu, 0x64332c2du, 0xf807c86fu}, +{0x0d069a37u, 0xf4bcd2c4u, 0xf4bcd2c4u}, +{0x5b228456u, 0x2461e3a9u, 0x5b228456u}, +{0xf7ea8fc6u, 0x750ba2fau, 0xf7e632aeu}, +{0xe983653au, 0xb6d81bccu, 0xe983653au}, +{0x7d23c7b8u, 0x972f981bu, 0x7d23c7b8u}, +{0x5c7cd175u, 0xc2e89647u, 0x5c7cd175u}, +{0x23a17884u, 0x7b122c15u, 0x7b122c15u}, +{0xb39b8ba2u, 0xc712e083u, 0xc712e083u}, +{0x40255382u, 0xc90238a9u, 0xc9023880u}, +{0x5bb3f219u, 0x36bcba8eu, 0x5bb3f219u}, +{0x59c1ee8au, 0x1bc4611cu, 0x59c1ee8au}, +{0x6d3963bdu, 0xbbc262f9u, 0x6d3963bdu}, +{0xd34b1140u, 0xaa657972u, 0xd34b1140u}, +{0x795c6228u, 0x9c0b382du, 0x795c6228u}, +{0xf09df3e1u, 0x45960f6cu, 0xf09df3e1u}, +{0xf6977096u, 0xe49abc78u, 0xf6977096u}, +{0x2109367au, 0x0cc85ea1u, 0x2109367au}, +{0xb5d4e11fu, 0x4ae99c90u, 0x4ae99c90u}, +{0x63c2db9eu, 0x41db5e2cu, 0x63c2db9eu}, +{0x62d953ffu, 0xf75229d6u, 0xf75229d6u}, +{0x8204d810u, 0x1ee2fd7eu, 0x1ee2fd7eu}, +{0x482c5c08u, 0x7a7f3625u, 0x7a7f3625u}, +{0x7e81429bu, 0x685db0c6u, 0x7e81429bu}, +{0x4a7106f4u, 0x353042adu, 0x4a7106f4u}, +{0x5db1b2bcu, 0xf32164cdu, 0xf32164cdu}, +{0xf61e6777u, 0x39f57fe2u, 0xf61e6777u}, +{0x3a168e3au, 0xfa8d12d1u, 0xfa8d12d1u}, +{0x7f681678u, 0x0fb87ec1u, 0x7f681678u}, +{0x2c8b126eu, 0x4c4c30a2u, 0x4c4c30a2u}, +{0x1cf4633fu, 0x34c12887u, 0x34c12887u}, +{0x18741a48u, 0x03e26ca5u, 0x18741a48u}, +{0xa2412606u, 0x5a629471u, 0x5a629471u}, +{0x1e961674u, 0x6c5dad58u, 0x6c5dad58u}, +{0xb430b6dcu, 0xed774f63u, 0xed774f63u}, +{0x24c9da46u, 0x6fcda227u, 0x6fcda227u}, +{0x2f1aa222u, 0x86039bcau, 0x2f1aa222u}, +{0xec1cdd4bu, 0x9422a1adu, 0xec1cdd4bu}, +{0xbdb9a3a0u, 0x67f8c966u, 0x67f8c966u}, +{0x73dffa00u, 0x98e66872u, 0x73dffa00u}, +{0xa1ff4e21u, 0x43583386u, 0x43583386u}, +{0x160f7415u, 0x54ed4360u, 0x54ed4360u}, +{0xc8379075u, 0x8dacda32u, 0xc8379075u}, +{0x9aaca607u, 0x6063e2deu, 0x6063e2deu}, +{0x89515730u, 0x7c97d273u, 0x7c97d273u}, +{0x068cd2b0u, 0xa9244fe2u, 0xa9244fe2u}, +{0xefddb149u, 0x01052115u, 0xefddb149u}, +{0x79ea5092u, 0x6c9530b4u, 0x79ea5092u}, +{0x7c2186b4u, 0xc92469f1u, 0x7c2186b4u}, diff --git a/test/pico_float_test/vectors/hazard3_mulsf.inc b/test/pico_float_test/vectors/hazard3_mulsf.inc new file mode 100644 index 000000000..63c6c0a5a --- /dev/null +++ b/test/pico_float_test/vectors/hazard3_mulsf.inc @@ -0,0 +1,1000 @@ +{0xa8c36b34u, 0x420ac26bu, 0xab53d866u}, +{0xd4cf10fbu, 0x692b079au, 0xfe8a567eu}, +{0xece2254du, 0xf36c2cbbu, 0x7f800000u}, +{0x34f22bceu, 0x7c3b1110u, 0x71b0f624u}, +{0x8b187e6fu, 0xa51e4bfcu, 0x00000000u}, +{0x0fe7c179u, 0xf0dcc0beu, 0xc147d8c1u}, +{0x768e7ddbu, 0x2ccdc929u, 0x63e51580u}, +{0x06f19a7fu, 0x07562985u, 0x00000000u}, +{0xa20ff19cu, 0xa6a951a3u, 0x093e68ceu}, +{0x64120a7fu, 0x935577e7u, 0xb7f38e45u}, +{0x900ed7f5u, 0x970a63d2u, 0x00000000u}, +{0xec7a91c8u, 0x00eb6ee1u, 0xade67059u}, +{0x87e4daa6u, 0xc88e8901u, 0x10fed784u}, +{0xf005a09du, 0xcbf5a56eu, 0x7c803910u}, +{0x112e23edu, 0x7be85175u, 0x4d9e07f8u}, +{0x04f3339au, 0x3a78a8b1u, 0x00000000u}, +{0x0a3232f6u, 0xea32f851u, 0xb4f92892u}, +{0xc98f9ea4u, 0xebf90ffbu, 0x760bba45u}, +{0xed8bd406u, 0x9502d86fu, 0x430eefc5u}, +{0x0ab44d09u, 0x940a9806u, 0x80000000u}, +{0x53117f9fu, 0x53160ff3u, 0x66aa93b0u}, +{0x455cf9c4u, 0x091efc06u, 0x0f093bb2u}, +{0x9d04dffdu, 0x9edd80dfu, 0x00000000u}, +{0x90c2fa22u, 0x93b5cbacu, 0x00000000u}, +{0x3c093424u, 0x9c303566u, 0x98bce0eeu}, +{0xd24a550du, 0x407dcb3au, 0xd34896adu}, +{0xd2d5e0d8u, 0xca9b966au, 0x5e01fccdu}, +{0x72d858b8u, 0x4c1960eeu, 0x7f800000u}, +{0x9a63d2c3u, 0xcb110969u, 0x260112c0u}, +{0xe45bfe13u, 0xfc3a9028u, 0x7f800000u}, +{0x57c64c27u, 0x5273314du, 0x6abc6079u}, +{0xa72f1718u, 0xc739117fu, 0x2efd274fu}, +{0x90cdb148u, 0x2eabbf2eu, 0x80000000u}, +{0xb2b429d1u, 0x821353fdu, 0x00000000u}, +{0xe202a662u, 0x62997577u, 0xff800000u}, +{0xc60df1c6u, 0xed07b0f2u, 0x73967938u}, +{0x471b9543u, 0x08082cefu, 0x0fa58535u}, +{0x6455a3a1u, 0x45398a87u, 0x6a1ad6dau}, +{0x29186441u, 0x62e3a555u, 0x4c878351u}, +{0xe2c75f26u, 0x3599d32eu, 0xd8ef98aau}, +{0xf4bebe05u, 0xcb41a1a2u, 0x7f800000u}, +{0xc76ef852u, 0xd3598bb3u, 0x5b4b12e5u}, +{0xc05c09e9u, 0x632ab30au, 0xe412b878u}, +{0xc2cf6165u, 0xfb0298c1u, 0x7e539667u}, +{0xdef32a63u, 0x8cf06bb1u, 0x2c645e08u}, +{0x6309cbb1u, 0xe35417fau, 0xff800000u}, +{0x6d985555u, 0xf5175c80u, 0xff800000u}, +{0xe9ff5030u, 0x6756d007u, 0xff800000u}, +{0xa422e9a4u, 0xaac9bd17u, 0x0f8061c7u}, +{0x9f73dbe2u, 0xd5eff474u, 0x35e49324u}, +{0x79b20fb8u, 0x47ac4525u, 0x7f800000u}, +{0x79657aebu, 0x1f618dc6u, 0x594a301fu}, +{0x5634c9a9u, 0x7be5371fu, 0x7f800000u}, +{0xfdee3dc7u, 0x2e8e3e83u, 0xed046071u}, +{0x5a1ac874u, 0x13a1d923u, 0x2e43b6b4u}, +{0x16b2d812u, 0xdd6d97ebu, 0xb4a5fc2au}, +{0x9ed19073u, 0x76251aa0u, 0xd58727e6u}, +{0x8da689c9u, 0x879b3f68u, 0x00000000u}, +{0x286d1e51u, 0xfa5a7310u, 0xe34a5664u}, +{0x056fd052u, 0x69d08989u, 0x2fc35a19u}, +{0xc817e61au, 0xc10685d9u, 0x499fa3bau}, +{0xf9f6dd82u, 0x2a8478c0u, 0xe4ff7d50u}, +{0xf8dda0c4u, 0x2199c318u, 0xdb051dfbu}, +{0x12be4771u, 0x93f7babeu, 0x80000000u}, +{0x87025952u, 0x7343aac6u, 0xbac741fbu}, +{0xad1d7a9bu, 0x7719cbf0u, 0xe4bd3775u}, +{0x54f5897bu, 0xb35f912eu, 0xc8d66e01u}, +{0xf7e27b8fu, 0x70e0c4d7u, 0xff800000u}, +{0x3d616a83u, 0xde7053eeu, 0xdc539dc2u}, +{0x587d62edu, 0x049ebffbu, 0x1d9d2114u}, +{0x69ca38e3u, 0xa5c40679u, 0xd01ad8abu}, +{0x4c69735du, 0x523e190du, 0x5f2d5a77u}, +{0x63cd7aafu, 0x5efe2fe2u, 0x7f800000u}, +{0xd58fc30fu, 0xbdb01383u, 0x53c5c21fu}, +{0x16c7da66u, 0xee4c113eu, 0xc59f4f7fu}, +{0x5e04dbefu, 0x6dba378fu, 0x7f800000u}, +{0xc446094fu, 0x9ec4300du, 0x2397c44cu}, +{0xb45c7b1au, 0xbf9add0au, 0x3485606du}, +{0x527a78acu, 0xa9ec462fu, 0xbce72beau}, +{0x9c859f1bu, 0x326a03a0u, 0x8f744aa6u}, +{0x1ecdbc33u, 0xd4deca58u, 0xb4330bd1u}, +{0xc491b64du, 0xe4999dfbu, 0x69aedfbfu}, +{0xea0d3b6du, 0x152c5167u, 0xbfbe21acu}, +{0x6800639du, 0x9a7c0071u, 0xc2fcc48eu}, +{0x4e5ab470u, 0x2524d77fu, 0x340cd3b2u}, +{0xde821748u, 0x9a314294u, 0x393427dcu}, +{0xd7d90f91u, 0x9dfddaf5u, 0x36573e09u}, +{0x9a6e422fu, 0x11ea2cb0u, 0x80000000u}, +{0xfa305a4du, 0x9f8ef775u, 0x5a44f91du}, +{0x7f800000u, 0x7ecf8ff4u, 0x7f800000u}, +{0xf7dae75au, 0x5b89388du, 0xff800000u}, +{0x8ad2ce1bu, 0xfd15989eu, 0x48765f44u}, +{0x8549054fu, 0x0715aa2fu, 0x80000000u}, +{0x08df8085u, 0x3290efa7u, 0x00000000u}, +{0xf9b05b50u, 0x45e3e467u, 0xff800000u}, +{0xd618c7aau, 0x1a21e62eu, 0xb0c13de2u}, +{0xb3e9d07du, 0x448a2a2au, 0xb8fc61ccu}, +{0x0817d23eu, 0x0e17145bu, 0x00000000u}, +{0xf04863cfu, 0xb0dd3e34u, 0x61ad2edbu}, +{0x85638413u, 0x621f50a4u, 0xa80d96b3u}, +{0x9a347165u, 0x1ecf7f68u, 0x80000000u}, +{0xaf5ada17u, 0x7552e217u, 0xe534482fu}, +{0x21533a8eu, 0x8b0c2dccu, 0x80000000u}, +{0x18191651u, 0x6543b033u, 0x3dea0abbu}, +{0xc571ce01u, 0x53ea5287u, 0xd9dd5440u}, +{0xbb28e01cu, 0x473d6337u, 0xc2f9ddcfu}, +{0xc8a926bau, 0x4e62c441u, 0xd795d5ddu}, +{0x86e68079u, 0xac7bd4d7u, 0x00000000u}, +{0x47c8f07cu, 0x3cc49f10u, 0x451a54f9u}, +{0x51021af4u, 0x5f10c5b9u, 0x7093274cu}, +{0xe4632eb6u, 0x6b2d427fu, 0xff800000u}, +{0xedc45634u, 0x5cdda5e6u, 0xff800000u}, +{0xb84b8830u, 0x5b9592bcu, 0xd46dd5dau}, +{0x8938d3f5u, 0xca4e93a0u, 0x14152524u}, +{0x12719b2bu, 0x9c8e3423u, 0x80000000u}, +{0xb8bd54e7u, 0x7a605659u, 0xf3a5ea26u}, +{0x06ec8b7eu, 0x5db893fbu, 0x252a8cffu}, +{0xf4ebdffeu, 0x40b27058u, 0xf6246942u}, +{0x23350fafu, 0x98728c6au, 0x80000000u}, +{0x706b89e4u, 0xddcfca5fu, 0xff800000u}, +{0xa5d39e54u, 0xdfd530dcu, 0x46303b1fu}, +{0x1be13ddeu, 0xe872fa18u, 0xc4d5c887u}, +{0x77f1e5ccu, 0xcd2aace2u, 0xff800000u}, +{0x2ba740c0u, 0xcd4f0df0u, 0xb9874676u}, +{0xec00d47au, 0xe8afd26au, 0x7f800000u}, +{0xc4edce44u, 0xfc8ee969u, 0x7f800000u}, +{0x9be790c0u, 0x9e5342e7u, 0x00000000u}, +{0x9c3e0849u, 0xc0407137u, 0x1d0eda41u}, +{0x74d95ccau, 0x499ec4d6u, 0x7f06ce65u}, +{0x4252fc0au, 0xaec0d9ceu, 0xb19ef089u}, +{0x5e1ebb93u, 0xa8859ebdu, 0xc725b3c1u}, +{0x0d0175c2u, 0x7c008c86u, 0x498203e2u}, +{0x250b16bdu, 0x407f9125u, 0x260ada82u}, +{0x296e1ea4u, 0x87e1aae2u, 0x80000000u}, +{0xf4aba78eu, 0x2ef60552u, 0xe424f694u}, +{0x1d82e696u, 0xdeafc368u, 0xbcb3bf17u}, +{0xfcad4897u, 0x6b27581fu, 0xff800000u}, +{0xb5298a46u, 0x2935b912u, 0x9ef0b2a9u}, +{0x53cc8f9eu, 0xeb6bcce3u, 0xff800000u}, +{0x554e7b84u, 0x53d11e1eu, 0x69a8ab21u}, +{0x22688415u, 0x70958cc3u, 0x5387d4bau}, +{0x152672b2u, 0x9a60547fu, 0x80000000u}, +{0x14deaf74u, 0x50655ae7u, 0x25c78205u}, +{0x4bbb9cf8u, 0xebebf934u, 0xf82cefb9u}, +{0x164083e6u, 0x4b5d0277u, 0x222633b8u}, +{0x1fd0f48bu, 0x92716a0bu, 0x80000000u}, +{0xd57bc2cdu, 0x7a392010u, 0xff800000u}, +{0xfe8230beu, 0x3b624f0au, 0xfa662e74u}, +{0x8bce666bu, 0x1324deadu, 0x80000000u}, +{0x58961825u, 0x74813fddu, 0x7f800000u}, +{0x9463214bu, 0x3b2f08e5u, 0x901b4ba6u}, +{0xe701da5fu, 0x8e7b3a11u, 0x35fedd1eu}, +{0x0350403eu, 0xf613e135u, 0xb9f0982eu}, +{0x3b3e2a49u, 0xc31f1bcdu, 0xbeec61d4u}, +{0xa73d56afu, 0x5ed1c217u, 0xc69b2352u}, +{0xf9ef302cu, 0x3cea9b94u, 0xf75b3365u}, +{0x7698bdb0u, 0x4f66c1e6u, 0x7f800000u}, +{0xd4ec1ba4u, 0xacc6705au, 0x42370500u}, +{0x90e88632u, 0x07c44193u, 0x80000000u}, +{0x6010566eu, 0x91ac29ffu, 0xb242237fu}, +{0xfa3447b4u, 0xbc8fd826u, 0x774a988au}, +{0xcd4db5c2u, 0xe98c545du, 0x77618661u}, +{0x77f16de5u, 0xd4ec082eu, 0xff800000u}, +{0x541fb093u, 0xfb6de113u, 0xff800000u}, +{0x56c1453fu, 0xe86d86ffu, 0xff800000u}, +{0xd81da361u, 0x792a4904u, 0xff800000u}, +{0x664cd3b5u, 0xc4e298f4u, 0xebb54d47u}, +{0xc0f9fcceu, 0xcae84da2u, 0x4c62d8eau}, +{0xce9ee780u, 0x8d978179u, 0x1cbc15d5u}, +{0x0e9ce349u, 0x792a101du, 0x4850719du}, +{0x86e2f8beu, 0xcc52355bu, 0x13ba5f5au}, +{0x04cf751fu, 0xe5db081eu, 0xab317fc5u}, +{0xf3ef93bcu, 0x422c4ea0u, 0xf6a140d7u}, +{0x264db607u, 0xd39183beu, 0xba69dbeeu}, +{0xd6bc3563u, 0x6a6190ccu, 0xff800000u}, +{0xb636fc08u, 0x7eb3e8feu, 0xf58098c4u}, +{0xa197dfa7u, 0xaedfa4b6u, 0x1104ad8au}, +{0x073b76f1u, 0xeebcaef0u, 0xb68a2b74u}, +{0xe5ee7e35u, 0x1bc60178u, 0xc23876fbu}, +{0x1c2744a1u, 0x630a7678u, 0x3fb4f0ceu}, +{0x0c497b83u, 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