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flash.h
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flash.h
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#ifndef FLASH_H
#define FLASH_H
/***************************** Include Files *********************************/
#include "xqspips.h" /* QSPI device driver */
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/*
* The following constants define the commands which may be sent to the Flash
* device.
*/
#define WRITE_STATUS_CMD 0x01
#define WRITE_CMD 0x02
#define READ_CMD 0x03
#define WRITE_DISABLE_CMD 0x04
#define READ_STATUS_CMD 0x05
#define WRITE_ENABLE_CMD 0x06
#define FAST_READ_CMD 0x0B
#define DUAL_READ_CMD 0x3B
#define QUAD_READ_CMD 0x6B
#define BULK_ERASE_CMD 0xC7
#define SEC_ERASE_CMD 0xD8
#define READ_ID 0x9F
#define READ_CONFIG_CMD 0x35
#define WRITE_CONFIG_CMD 0x01
#define BANK_REG_RD 0x16
#define BANK_REG_WR 0x17
/* Bank register is called Extended Address Register in Micron */
#define EXTADD_REG_RD 0xC8
#define EXTADD_REG_WR 0xC5
#define DIE_ERASE_CMD 0xC4
#define READ_FLAG_STATUS_CMD 0x70
/*
* The following constants define the offsets within a FlashBuffer data
* type for each kind of data. Note that the read data offset is not the
* same as the write data because the QSPI driver is designed to allow full
* duplex transfers such that the number of bytes received is the number
* sent and received.
*/
#define COMMAND_OFFSET 0 /* Flash instruction */
#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
#define DATA_OFFSET 4 /* Start of Data for Read/Write */
#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
reads */
#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
quad reads */
#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
#define BULK_ERASE_SIZE 1 /* Bulk Erase command size */
#define SEC_ERASE_SIZE 4 /* Sector Erase command + Sector address */
#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
#define RD_CFG_SIZE 2 /* 1 byte Configuration register + RD CFG command*/
#define WR_CFG_SIZE 3 /* WRR command + 1 byte each Status and Config Reg*/
#define DIE_ERASE_SIZE 4 /* Die Erase command + Die address */
/*
* The following constants specify the extra bytes which are sent to the
* Flash on the QSPI interface, that are not data, but control information
* which includes the command and address
*/
#define OVERHEAD_SIZE 4
/*
* Base address of Flash1
*/
#define FLASH1BASE 0x0000000
/*
* Sixteen MB
*/
#define SIXTEENMB 0x1000000
/*
* Mask for quad enable bit in Flash configuration register
*/
#define FLASH_QUAD_EN_MASK 0x02
#define FLASH_SRWD_MASK 0x80
/*
* Bank mask
*/
#define BANKMASK 0xF000000
/*
* Identification of Flash
* Micron:
* Byte 0 is Manufacturer ID;
* Byte 1 is first byte of Device ID - 0xBB or 0xBA
* Byte 2 is second byte of Device ID describes flash size:
* 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
* Spansion:
* Byte 0 is Manufacturer ID;
* Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
* Byte 2 is second byte of Device ID describes flash size:
* 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
*/
#define MICRON_ID_BYTE0 0x20
#define MICRON_ID_BYTE2_128 0x18
#define MICRON_ID_BYTE2_256 0x19
#define MICRON_ID_BYTE2_512 0x20
#define MICRON_ID_BYTE2_1G 0x21
#define SPANSION_ID_BYTE0 0x01
#define SPANSION_ID_BYTE2_128 0x18
#define SPANSION_ID_BYTE2_256 0x19
#define SPANSION_ID_BYTE2_512 0x20
#define WINBOND_ID_BYTE0 0xEF
#define WINBOND_ID_BYTE2_128 0x18
#define MACRONIX_ID_BYTE0 0xC2
#define MACRONIX_ID_BYTE2_256 0x19
#define MACRONIX_ID_BYTE2_512 0x1A
#define MACRONIX_ID_BYTE2_1G 0x1B
#define ISSI_ID_BYTE0 0x9D
#define ISSI_ID_BYTE2_256 0x19
/*
* The index for Flash config table
*/
/* Spansion*/
#define SPANSION_INDEX_START 0
#define FLASH_CFG_TBL_SINGLE_128_SP SPANSION_INDEX_START
#define FLASH_CFG_TBL_STACKED_128_SP (SPANSION_INDEX_START + 1)
#define FLASH_CFG_TBL_PARALLEL_128_SP (SPANSION_INDEX_START + 2)
#define FLASH_CFG_TBL_SINGLE_256_SP (SPANSION_INDEX_START + 3)
#define FLASH_CFG_TBL_STACKED_256_SP (SPANSION_INDEX_START + 4)
#define FLASH_CFG_TBL_PARALLEL_256_SP (SPANSION_INDEX_START + 5)
#define FLASH_CFG_TBL_SINGLE_512_SP (SPANSION_INDEX_START + 6)
#define FLASH_CFG_TBL_STACKED_512_SP (SPANSION_INDEX_START + 7)
#define FLASH_CFG_TBL_PARALLEL_512_SP (SPANSION_INDEX_START + 8)
/* Micron */
#define MICRON_INDEX_START (FLASH_CFG_TBL_PARALLEL_512_SP + 1)
#define FLASH_CFG_TBL_SINGLE_128_MC MICRON_INDEX_START
#define FLASH_CFG_TBL_STACKED_128_MC (MICRON_INDEX_START + 1)
#define FLASH_CFG_TBL_PARALLEL_128_MC (MICRON_INDEX_START + 2)
#define FLASH_CFG_TBL_SINGLE_256_MC (MICRON_INDEX_START + 3)
#define FLASH_CFG_TBL_STACKED_256_MC (MICRON_INDEX_START + 4)
#define FLASH_CFG_TBL_PARALLEL_256_MC (MICRON_INDEX_START + 5)
#define FLASH_CFG_TBL_SINGLE_512_MC (MICRON_INDEX_START + 6)
#define FLASH_CFG_TBL_STACKED_512_MC (MICRON_INDEX_START + 7)
#define FLASH_CFG_TBL_PARALLEL_512_MC (MICRON_INDEX_START + 8)
#define FLASH_CFG_TBL_SINGLE_1GB_MC (MICRON_INDEX_START + 9)
#define FLASH_CFG_TBL_STACKED_1GB_MC (MICRON_INDEX_START + 10)
#define FLASH_CFG_TBL_PARALLEL_1GB_MC (MICRON_INDEX_START + 11)
/* Winbond */
#define WINBOND_INDEX_START (FLASH_CFG_TBL_PARALLEL_1GB_MC + 1)
#define FLASH_CFG_TBL_SINGLE_128_WB WINBOND_INDEX_START
#define FLASH_CFG_TBL_STACKED_128_WB (WINBOND_INDEX_START + 1)
#define FLASH_CFG_TBL_PARALLEL_128_WB (WINBOND_INDEX_START + 2)
/* Macronix */
#define MACRONIX_INDEX_START (FLASH_CFG_TBL_PARALLEL_128_WB + 1 - 3)
#define FLASH_CFG_TBL_SINGLE_256_MX MACRONIX_INDEX_START
#define FLASH_CFG_TBL_STACKED_256_MX (MACRONIX_INDEX_START + 1)
#define FLASH_CFG_TBL_PARALLEL_256_MX (MACRONIX_INDEX_START + 2)
#define FLASH_CFG_TBL_SINGLE_512_MX (MACRONIX_INDEX_START + 3)
#define FLASH_CFG_TBL_STACKED_512_MX (MACRONIX_INDEX_START + 4)
#define FLASH_CFG_TBL_PARALLEL_512_MX (MACRONIX_INDEX_START + 5)
#define FLASH_CFG_TBL_SINGLE_1G_MX (MACRONIX_INDEX_START + 6)
#define FLASH_CFG_TBL_STACKED_1G_MX (MACRONIX_INDEX_START + 7)
#define FLASH_CFG_TBL_PARALLEL_1G_MX (MACRONIX_INDEX_START + 8)
/* ISSI */
#define ISSI_INDEX_START (FLASH_CFG_TBL_PARALLEL_1G_MX + 1)
#define FLASH_CFG_TBL_SINGLE_256_ISSI ISSI_INDEX_START
#define FLASH_CFG_TBL_STACKED_256_ISSI (ISSI_INDEX_START + 1)
#define FLASH_CFG_TBL_PARALLEL_256_ISSI (ISSI_INDEX_START + 2)
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
/*
* The following defines are for dual flash stacked mode interface.
*/
#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
address and return data */
#define DUAL_STACK_CONFIG_WRITE (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define DUAL_QSPI_CONFIG_WRITE (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
/*
* Number of flash pages to be written.
*/
#define PAGE_COUNT 32
/*
* Max page size to initialize write and read buffer
*/
#define MAX_PAGE_SIZE 1024
/*
* Flash address to which data is to be written.
*/
#define TEST_ADDRESS 0x000000
#define UNIQUE_VALUE 0x06
/**************************** Type Definitions *******************************/
typedef struct{
u32 SectSize; /* Individual sector size or
* combined sector size in case of parallel config*/
u32 NumSect; /* Total no. of sectors in one/two flash devices */
u32 PageSize; /* Individual page size or
* combined page size in case of parallel config*/
u32 NumPage; /* Total no. of pages in one/two flash devices */
u32 FlashDeviceSize; /* This is the size of one flash device
* NOT the combination of both devices, if present
*/
u8 ManufacturerID; /* Manufacturer ID - used to identify make */
u8 DeviceIDMemSize; /* Byte of device ID indicating the memory size */
u32 SectMask; /* Mask to get sector start address */
u8 NumDie; /* No. of die forming a single flash */
}FlashInfo;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
u8* get_slice_buffer();
u32 get_slice_buffer_size();
int QspiG128FlashExample(XQspiPs *QspiInstancePtr, u16 QspiDeviceId);
void FlashErase(XQspiPs *QspiPtr, u32 Address, u32 ByteCount, u8 *WriteBfrPtr);
void FlashWrite(XQspiPs *QspiPtr, u32 Address, u32 ByteCount, u8 Command,
u8 *WriteBfrPtr);
int FlashReadID(XQspiPs *QspiPtr, u8 *buffer_ptr);
void FlashRead(XQspiPs *QspiPtr, u32 Address, u32 ByteCount, u8 Command,
u8 *WriteBfrPtr, u8 *ReadBfrPtr);
int SendBankSelect(XQspiPs *QspiPtr, u32 BankSel);
void BulkErase(XQspiPs *QspiPtr, u8 *WriteBfrPtr);
void DieErase(XQspiPs *QspiPtr, u8 *WriteBfrPtr);
u32 GetRealAddr(XQspiPs *QspiPtr, u32 Address);
int QspiFlashDump(XQspiPs *QspiInstancePtr, u32 start_addr, u32 len);
u8* FlashRead2(XQspiPs *QspiInstancePtr, u32 start_addr, u32 len);
int FlashInit(XQspiPs *QspiInstancePtr, u16 QspiDeviceId);
void MemDump(void* ptr, u32 start_addr, u32 len);
int FlashErase2(XQspiPs *QspiPtr, u32 Address, u32 ByteCount);
int FlashEraseAll(XQspiPs *QspiPtr);
void FlashWrite2(XQspiPs *QspiPtr, u32 Address, u32 ByteCount, u8 *WriteBfrPtr);
FlashInfo* GetFlashInfo();
#define DEBUG 10
#define INFO 20
#define WARNING 30
#define ERROR 40
#define VERBOSITY 30
#define verb_printf(type,...) \
if (((type) >= VERBOSITY)) {xil_printf (__VA_ARGS__); }
#endif //FLASH_H