From 66d4e3eb7b9dbd827d69b48dfff98f42b1148d5b Mon Sep 17 00:00:00 2001 From: Yen-Fu Chen Date: Wed, 11 Oct 2023 22:51:25 +0800 Subject: [PATCH] Remove insn_len field in IR structure --- src/decode.c | 4 +--- src/decode.h | 10 ++-------- src/emulate.c | 6 +++--- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/src/decode.c b/src/decode.c index 88de60224..c7111080c 100644 --- a/src/decode.c +++ b/src/decode.c @@ -1726,10 +1726,9 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn) /* If the last 2-bit is one of 0b00, 0b01, and 0b10, it is * a 16-bit instruction. */ - if ((insn & FC_OPCODE) != 3) { + if (CHECK_COMPRESSED_INSN) { insn &= 0x0000FFFF; const uint16_t c_index = (insn & FC_FUNC3) >> 11 | (insn & FC_OPCODE); - ir->insn_len = INSN_16; /* decode instruction (compressed instructions) */ const decode_t op = rvc_jump_table[c_index]; @@ -1740,7 +1739,6 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn) /* standard uncompressed instruction */ const uint32_t index = (insn & INSN_6_2) >> 2; - ir->insn_len = INSN_32; /* decode instruction */ const decode_t op = rv_jump_table[index]; diff --git a/src/decode.h b/src/decode.h index eb5dfb9bf..a8167ce4c 100644 --- a/src/decode.h +++ b/src/decode.h @@ -246,11 +246,6 @@ enum { }; /* clang-format on */ -enum { - INSN_16 = 2, - INSN_32 = 4, -}; - typedef struct { int32_t imm; uint8_t rd, rs1, rs2; @@ -275,9 +270,6 @@ typedef struct rv_insn { uint32_t pc; - /* instruction length */ - uint8_t insn_len; - /* Tail-call optimization (TCO) allows a C function to replace a function * call to another function or itself, followed by a simple return of the * function's result, with a direct jump to the target function. This @@ -308,3 +300,5 @@ typedef struct rv_insn { /* decode the RISC-V instruction */ bool rv_decode(rv_insn_t *ir, const uint32_t insn); + +#define CHECK_COMPRESSED_INSN ((insn & FC_OPCODE) != 3) \ No newline at end of file diff --git a/src/emulate.c b/src/emulate.c index e4cba3c5a..8f6ecfab1 100644 --- a/src/emulate.c +++ b/src/emulate.c @@ -61,7 +61,7 @@ enum { static void rv_exception_default_handler(riscv_t *rv) { - rv->csr_mepc += rv->compressed ? INSN_16 : INSN_32; + rv->csr_mepc += rv->compressed ? 2 : 4; rv->PC = rv->csr_mepc; /* mret */ } @@ -628,14 +628,14 @@ static void block_translate(riscv_t *rv, block_map_t *map, block_t *block) /* decode the instruction */ if (!rv_decode(ir, insn)) { - rv->compressed = (ir->insn_len == INSN_16); + rv->compressed = CHECK_COMPRESSED_INSN; rv_except_illegal_insn(rv, insn); break; } ir->impl = dispatch_table[ir->opcode]; ir->pc = block->pc_end; /* compute the end of pc */ - block->pc_end += ir->insn_len; + block->pc_end += CHECK_COMPRESSED_INSN ? 2 : 4; block->n_insn++; prev_ir = ir; /* stop on branch */