diff --git a/quam/components/ports/analog_inputs.py b/quam/components/ports/analog_inputs.py
index 249722b7..b7d1675a 100644
--- a/quam/components/ports/analog_inputs.py
+++ b/quam/components/ports/analog_inputs.py
@@ -1,5 +1,5 @@
 from abc import ABC
-from typing import Any, ClassVar, Dict
+from typing import Any, ClassVar, Dict, Optional
 
 from quam.components.ports.base_ports import BasePort, FEMPort, OPXPlusPort
 from quam.core import quam_dataclass
@@ -17,16 +17,18 @@
 class LFAnalogInputPort(BasePort, ABC):
     port_type: ClassVar[str] = "analog_input"
 
-    offset: float = 0.0
+    offset: Optional[float] = None
     gain_db: int = 0
     shareable: bool = False
 
     def get_port_properties(self):
-        return {
-            "offset": self.offset,
+        port_cfg = {
             "gain_db": self.gain_db,
             "shareable": self.shareable,
         }
+        if self.offset is not None:
+            port_cfg["offset"] = self.offset
+        return port_cfg
 
 
 @quam_dataclass
diff --git a/quam/components/ports/analog_outputs.py b/quam/components/ports/analog_outputs.py
index c8e28395..1e4a9c3b 100644
--- a/quam/components/ports/analog_outputs.py
+++ b/quam/components/ports/analog_outputs.py
@@ -1,5 +1,4 @@
 from abc import ABC
-from dataclasses import field
 from typing import Any, ClassVar, Dict, List, Literal, Optional
 
 from quam.components.ports.base_ports import BasePort, FEMPort, OPXPlusPort
@@ -18,7 +17,7 @@
 class LFAnalogOutputPort(BasePort, ABC):
     port_type: ClassVar[str] = "analog_output"
 
-    offset: float = 0.0
+    offset: Optional[float] = None
     delay: int = 0
     crosstalk: Optional[Dict[int, float]] = None
     feedforward_filter: Optional[List[float]] = None
diff --git a/quam/components/ports/base_ports.py b/quam/components/ports/base_ports.py
index 201e0585..cef03c05 100644
--- a/quam/components/ports/base_ports.py
+++ b/quam/components/ports/base_ports.py
@@ -54,6 +54,10 @@ class OPXPlusPort(BasePort, ABC):
     controller_id: Union[str, int]
     port_id: int
 
+    @property
+    def port_tuple(self) -> Tuple[Union[str, int], int]:
+        return self.controller_id, self.port_id
+
     def get_port_config(
         self, config: Dict[str, Any], create: bool = True
     ) -> Dict[str, Any]:
@@ -80,6 +84,10 @@ class FEMPort(BasePort, ABC):
     fem_id: int
     port_id: int
 
+    @property
+    def port_tuple(self) -> Tuple[Union[str, int], int, int]:
+        return self.controller_id, self.fem_id, self.port_id
+
     def get_port_config(
         self, config: Dict[str, Any], create: bool = True
     ) -> Dict[str, Any]:
diff --git a/tests/components/ports/test_digital_ports.py b/tests/components/ports/test_digital_ports.py
index 1e0a7956..a14d8db9 100644
--- a/tests/components/ports/test_digital_ports.py
+++ b/tests/components/ports/test_digital_ports.py
@@ -13,11 +13,18 @@ def test_opx_plus_digital_output_port():
     with pytest.raises(TypeError):
         OPXPlusDigitalOutputPort()
 
-    port = OPXPlusDigitalOutputPort(port=("con1", 2))
-    assert port.port == ("con1", 2)
+    port = OPXPlusDigitalOutputPort("con1", 2)
+    assert port.controller_id == "con1"
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 2)
     assert port.port_type == "digital_output"
-    assert port.inverted == False
-    assert port.shareable == False
+    assert port.inverted is False
+    assert port.shareable is False
+
+    assert port.to_dict() == {
+        "controller_id": "con1",
+        "port_id": 2,
+    }
 
     assert port.get_port_properties() == {
         "inverted": False,
@@ -45,14 +52,21 @@ def test_opx_plus_digital_input_port():
     with pytest.raises(TypeError):
         OPXPlusDigitalInputPort()
 
-    port = OPXPlusDigitalInputPort(port=("con1", 2))
-    assert port.port == ("con1", 2)
+    port = OPXPlusDigitalInputPort("con1", 2)
+    assert port.controller_id == "con1"
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 2)
     assert port.port_type == "digital_input"
     assert port.deadtime == 4
     assert port.polarity == "rising"
     assert port.threshold == 2.0
     assert port.shareable == False
 
+    assert port.to_dict() == {
+        "controller_id": "con1",
+        "port_id": 2,
+    }
+
     assert port.get_port_properties() == {
         "deadtime": 4,
         "polarity": "rising",
@@ -83,14 +97,23 @@ def test_fem_digital_output_port():
     with pytest.raises(TypeError):
         FEMDigitalOutputPort()
 
-    port = FEMDigitalOutputPort(port=("con1", 1, 2))
+    port = FEMDigitalOutputPort("con1", 1, 2)
+    assert port.controller_id == "con1"
+    assert port.fem_id == 1
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 1, 2)
 
-    assert port.port == ("con1", 1, 2)
     assert port.port_type == "digital_output"
     assert port.inverted == False
     assert port.shareable == False
     assert port.level == "LVTTL"
 
+    assert port.to_dict() == {
+        "controller_id": "con1",
+        "fem_id": 1,
+        "port_id": 2,
+    }
+
     assert port.get_port_properties() == {
         "inverted": False,
         "shareable": False,
diff --git a/tests/components/ports/test_lf_fem_analog_ports.py b/tests/components/ports/test_lf_fem_analog_ports.py
index 089db71e..193ddb76 100644
--- a/tests/components/ports/test_lf_fem_analog_ports.py
+++ b/tests/components/ports/test_lf_fem_analog_ports.py
@@ -8,24 +8,30 @@ def test_lf_fem_analog_output_port():
     with pytest.raises(TypeError):
         LFFEMAnalogOutputPort()
 
-    port = LFFEMAnalogOutputPort(port=("con1", 1, 2))
-    assert port.port == ("con1", 1, 2)
+    port = LFFEMAnalogOutputPort("con1", 1, 2)
+    assert port.controller_id == "con1"
+    assert port.fem_id == 1
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 1, 2)
     assert port.port_type == "analog_output"
     assert port.offset == None
     assert port.delay == 0
-    assert port.crosstalk == {}
-    assert port.feedforward_filter == []
-    assert port.feedback_filter == []
+    assert port.crosstalk is None
+    assert port.feedforward_filter is None
+    assert port.feedback_filter is None
     assert port.shareable == False
     assert port.output_mode == "direct"
     assert port.sampling_rate == 1e9
     assert port.upsampling_mode == "mw"
 
+    assert port.to_dict() == {
+        "controller_id": "con1",
+        "fem_id": 1,
+        "port_id": 2,
+    }
+
     assert port.get_port_properties() == {
         "delay": 0,
-        "crosstalk": {},
-        "feedforward_filter": [],
-        "feedback_filter": [],
         "shareable": False,
         "output_mode": "direct",
         "sampling_rate": 1e9,
@@ -43,9 +49,6 @@ def test_lf_fem_analog_output_port():
                         "analog_outputs": {
                             2: {
                                 "delay": 0,
-                                "crosstalk": {},
-                                "feedforward_filter": [],
-                                "feedback_filter": [],
                                 "shareable": False,
                                 "output_mode": "direct",
                                 "sampling_rate": 1e9,
@@ -61,9 +64,6 @@ def test_lf_fem_analog_output_port():
     port.offset = 0.1
     assert port.get_port_properties() == {
         "delay": 0,
-        "crosstalk": {},
-        "feedforward_filter": [],
-        "feedback_filter": [],
         "shareable": False,
         "output_mode": "direct",
         "sampling_rate": 1e9,
@@ -76,16 +76,25 @@ def test_lf_fem_analog_input_port():
     with pytest.raises(TypeError):
         LFFEMAnalogInputPort()
 
-    port = LFFEMAnalogInputPort(port=("con1", 1, 2))
-    assert port.port == ("con1", 1, 2)
+    port = LFFEMAnalogInputPort("con1", 1, 2)
+    assert port.controller_id == "con1"
+    assert port.fem_id == 1
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 1, 2)
+
     assert port.port_type == "analog_input"
-    assert port.offset == 0.0
+    assert port.offset is None
     assert port.gain_db == 0
     assert port.shareable == False
     assert port.sampling_rate == 1e9
 
+    assert port.to_dict() == {
+        "controller_id": "con1",
+        "fem_id": 1,
+        "port_id": 2,
+    }
+
     assert port.get_port_properties() == {
-        "offset": 0.0,
         "gain_db": 0,
         "shareable": False,
         "sampling_rate": 1e9,
@@ -101,7 +110,6 @@ def test_lf_fem_analog_input_port():
                     1: {
                         "analog_inputs": {
                             2: {
-                                "offset": 0.0,
                                 "gain_db": 0,
                                 "shareable": False,
                                 "sampling_rate": 1e9,
diff --git a/tests/components/ports/test_mw_fem_analog_ports.py b/tests/components/ports/test_mw_fem_analog_ports.py
index 3b031aee..aae30a92 100644
--- a/tests/components/ports/test_mw_fem_analog_ports.py
+++ b/tests/components/ports/test_mw_fem_analog_ports.py
@@ -9,35 +9,40 @@ def test_mw_fem_analog_output_port():
         MWFEMAnalogOutputPort()
 
     with pytest.raises(TypeError):
-        port = MWFEMAnalogOutputPort(port=("con1", 1, 2))
+        port = MWFEMAnalogOutputPort("con1", 1, 2)
 
-    port = MWFEMAnalogOutputPort(port=("con1", 1, 2), band=1)
-    assert port.port == ("con1", 1, 2)
+    with pytest.raises(ValueError):
+        port = MWFEMAnalogOutputPort("con1", 1, 2, band=1)
+
+    port = MWFEMAnalogOutputPort("con1", 1, 2, band=1, upconverter_frequency=5e9)
+    assert port.controller_id == "con1"
+    assert port.fem_id == 1
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 1, 2)
     assert port.port_type == "analog_output"
     assert port.band == 1
-    assert port.upconverter_frequency is None
+    assert port.upconverter_frequency == 5e9
     assert port.upconverters is None
     assert port.delay == 0
     assert port.shareable == False
     assert port.sampling_rate == 1e9
     assert port.full_scale_power_dbm == -11
 
-    assert port.get_port_properties() == {
+    assert port.to_dict() == {
+        "controller_id": "con1",
+        "fem_id": 1,
+        "port_id": 2,
         "band": 1,
-        "delay": 0,
-        "shareable": False,
-        "sampling_rate": 1e9,
-        "full_scale_power_dbm": -11,
+        "upconverter_frequency": 5e9,
     }
 
-    port.upconverter_frequency = 5e9
     assert port.get_port_properties() == {
         "band": 1,
-        "upconverter_frequency": 5e9,
         "delay": 0,
         "shareable": False,
         "sampling_rate": 1e9,
         "full_scale_power_dbm": -11,
+        "upconverter_frequency": 5e9,
     }
 
     cfg = {"controllers": {}}
@@ -70,19 +75,28 @@ def test_mw_fem_analog_input_ports():
         MWFEMAnalogInputPort()
 
     with pytest.raises(TypeError):
-        port = MWFEMAnalogInputPort(port=("con1", 1, 2))
+        port = MWFEMAnalogInputPort("con1", 1, 2)
 
-    port = MWFEMAnalogInputPort(
-        port=("con1", 1, 2), band=1, downconverter_frequency=5e9
-    )
+    port = MWFEMAnalogInputPort("con1", 1, 2, band=1, downconverter_frequency=5e9)
 
-    assert port.port == ("con1", 1, 2)
+    assert port.controller_id == "con1"
+    assert port.fem_id == 1
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 1, 2)
     assert port.port_type == "analog_input"
     assert port.band == 1
     assert port.downconverter_frequency == 5e9
     assert port.sampling_rate == 1e9
     assert port.shareable == False
 
+    assert port.to_dict() == {
+        "controller_id": "con1",
+        "fem_id": 1,
+        "port_id": 2,
+        "band": 1,
+        "downconverter_frequency": 5e9,
+    }
+
     assert port.get_port_properties() == {
         "band": 1,
         "downconverter_frequency": 5e9,
diff --git a/tests/components/ports/test_opx_ports.py b/tests/components/ports/test_opx_ports.py
index bc6a170f..7334f112 100644
--- a/tests/components/ports/test_opx_ports.py
+++ b/tests/components/ports/test_opx_ports.py
@@ -1,31 +1,31 @@
 import pytest
 from quam.components.ports.analog_inputs import OPXPlusAnalogInputPort
 from quam.components.ports.analog_outputs import OPXPlusAnalogOutputPort
-from quam.components.ports.digital_outputs import (
-    OPXPlusDigitalOutputPort,
-)
 
 
 def test_opx_plus_analog_output_port():
     with pytest.raises(TypeError):
         OPXPlusAnalogOutputPort()
 
-    port = OPXPlusAnalogOutputPort(port=("con1", 2))
-    assert port.port == ("con1", 2)
+    port = OPXPlusAnalogOutputPort("con1", 2)
+    assert port.controller_id == "con1"
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 2)
     assert port.port_type == "analog_output"
-    assert port.offset == 0.0
+    assert port.offset is None
     assert port.delay == 0
-    assert port.crosstalk == {}
-    assert port.feedforward_filter == []
-    assert port.feedback_filter == []
+    assert port.crosstalk is None
+    assert port.feedforward_filter is None
+    assert port.feedback_filter is None
     assert port.shareable == False
 
     assert port.get_port_properties() == {
-        "offset": 0.0,
         "delay": 0,
-        "crosstalk": {},
-        "feedforward_filter": [],
-        "feedback_filter": [],
+        "shareable": False,
+    }
+
+    assert port.get_port_properties() == {
+        "delay": 0,
         "shareable": False,
     }
 
@@ -37,11 +37,7 @@ def test_opx_plus_analog_output_port():
             "con1": {
                 "analog_outputs": {
                     2: {
-                        "offset": 0.0,
                         "delay": 0,
-                        "crosstalk": {},
-                        "feedforward_filter": [],
-                        "feedback_filter": [],
                         "shareable": False,
                     }
                 }
@@ -54,15 +50,21 @@ def test_opx_plus_analog_input_port():
     with pytest.raises(TypeError):
         OPXPlusAnalogInputPort()
 
-    port = OPXPlusAnalogInputPort(port=("con1", 2))
-    assert port.port == ("con1", 2)
+    port = OPXPlusAnalogInputPort("con1", 2)
+    assert port.controller_id == "con1"
+    assert port.port_id == 2
+    assert port.port_tuple == ("con1", 2)
     assert port.port_type == "analog_input"
-    assert port.offset == 0.0
+    assert port.offset is None
     assert port.gain_db == 0
     assert port.shareable == False
 
     assert port.get_port_properties() == {
-        "offset": 0.0,
+        "gain_db": 0,
+        "shareable": False,
+    }
+
+    assert port.get_port_properties() == {
         "gain_db": 0,
         "shareable": False,
     }
@@ -75,7 +77,6 @@ def test_opx_plus_analog_input_port():
             "con1": {
                 "analog_inputs": {
                     2: {
-                        "offset": 0.0,
                         "gain_db": 0,
                         "shareable": False,
                     }