README.md

Awesome Digital IC

A collection of great ASIC/FPGA/VLSI project/tutorial/website.

• 🚩 = Chinese
• 📍 = Github Project
• 📽 = With vedio
• 👶 = Easy to get start with
• ⭐ = Recommended
• 💬 = More Details

Awesome Awesome ⭐

Awesome-lists for digital ic.

• FPGA Tutorial 📍 - A curated list of amazingly FPGA tutorials and projects.
• Awesome Hardware Description Languages 📍 - A curated list of amazingly awesome hardware description language projects.
• Awesome FPGA 📍 - A collection of resources on FPGA devices and development in general.
• Open Hardware Verification 📍 - A curated List of Free and Open Source hardware verification tools and frameworks.
• Awesome Open Source EDA Projects 📍 - A curated list of EDA open source projects.
• List of FPGA boards 📍 - List of Repurposed FPGA boards.
• awesome-hwd-tools 📍 - A curated list of awesome open source hardware design tools with a focus on chip design.
• Awesome Electronics 📍 - A curated list of awesome resources for electronic engineers and hobbyists.
• Awesome Lattice FPGA boards 📍 - A curated list of awesome open-source FPGA boards

Github Topics

• verilog 📍 - Here are 2,566 public repositories matching "verilog" topic...
• vhdl 📍- Here are 1,766 public repositories matching "vhdl" topic...
• fpga 📍 - Here are 3,136 public repositories matching "fpga" topic...

Quora Topics

• verilog 📍 - Here are 2,566 public repositories matching "verilog" topic...
• vhdl 📍- Here are 1,766 public repositories matching "vhdl" topic...
• fpga 📍 - Here are 3,136 public repositories matching "fpga" topic...

Projects and IPs

• OpenCores ⭐ - Free and open source IP cores.
• FreeCores 📍 - A home for open source hardware cores, a fork of almost all cores that was once on OpenCores.org.
• Must-have verilog systemverilog modules 📍 - A collection of verilog systemverilog synthesizable modules.
• fpga4fun - Some projects build on FPGA.
• 32 Verilog Mini Projects 📍 - 32 useful mini verilog projects for beginners.

Communication Technology

• ALEX FORENCICH - Verilog IPs including PCIe/Ethernet/I2C/Uart etc.

• ALEX FORENCICH - AXI 📍 - Collection of AXI4 and AXI4 lite bus components. Most components are fully parametrizable in interface widths.

• TVIP - AXI 📍 - An UVM package of AMBA AXI4 VIP.

• PULP-platform - AXI 📍 - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication.

• ALEX FORENCICH - AXIS 📍 - Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths.

• ALEX FORENCICH - IIC 📍 - I2C interface components. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

• corundum - NIC 📍

• RIFFA - PCIe 📍 - Reusable Integration Framework for FPGA Acceleratorscommunication.

• ALEX FORENCICH - UART 📍 - A basic UART to AXI Stream IP core, written in Verilog with cocotb testbenches.

• zipcpu - UART 📍 - A simple, basic, formally verified UART controller.

• C910 - UART 📍

Information Technology

RISC-V

• RISC-V Instruction Set Manual - This repository contains the LaTeX source for the draft RISC-V Instruction Set Manual.

• RISC-V Exchange: Cores & SoCs - A list of RICS-V cores and SoCs.

• PULP - Open source Parallel Ultra-Low-Power RISC-V core.

• openc910 📍 - OpenXuantie C910 Core.

• XiangShan 📍 - Open-source high-performance RISC-V processor.

• riscv-starship 📍 - Run rocket-chip on FPGA(Xilinx Virtex-7 VC707).

• Wujian100 📍 - A MCU base SoC.

• picorv32 📍 - A Size-Optimized RISC-V CPU.

• Hummingbirdv2 E203 Core and SoC 📍 Docs - A Ultra-Low Power RISC-V Core.

• darkriscv 📍 - A proof of concept for the opensource RISC-V instruction set.

• CVA6 RISC-V CPU 📍 - An application class 6-stage RISC-V CPU capable of booting Linux.

• VexRiscv 📍 - A FPGA friendly 32 bit RISC-V CPU implementation.

Others

• zipcpu ⭐📍 - with detailed comments.
• openmsp430 - The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
• Nyuzi Processor 📍 - GPGPU microprocessor architecture.

Tutorials and Courses 💬Intro

• zipcpu 👶 - Verilog, Formal Verification and Verilator Beginner's Tutorial
• WORLD OF ASIC ⭐ - A great source of detailed VLSI tutorials and examples.

HDL

• More information about hardware description language on Awesome HDL

Verilog Grammar

• Verilog TUTORIAL for beginners 👶 - A tutorial based upon free Icarus Verilog compiler.
• ChipVerify: Verilog Tutorial - A guide for someone new to Verilog.
• Verilog/SystemVerilog Guide 📍 - A guide covering Verilog & SystemVerilog.
• Verilog Tutorial - 菜鸟教程 🚩 - Advanced tutorial for verilog.

VHDL Grammar

• VHDL Guide 📍 - A guide covering VHDL.

Chisel

• Learning Chisel and Scala Part I Part II 🚩📍Github - A tutorial for chisel, no scala knowledge required.
• Chisel/FIRRTL 💬Doc 📍Github - Scala based HDL.

SpinalHDL

• 从 Verilog 到 SpinalHDL 🚩 - A website navigation for SpinalHDL.
• SpinalHDL 📍Github - Scala based HDL.

Verification

• Verification Academy - The most comprehensive resource for verification training.
• Verification Guide - Tutorials with links to example codes on EDA Playground.
• Doulos - Global training solutions for engineers creating the world's electronics products.
• testbench - Some training articals for systemverilog.
• ClueLogic - Providing the clues to solve your verification problems.
• ChipVerify - A simple and complete set of verilog/System Verilog/UVM tutorials.

Build a CPU

• RISC-V Guide 📍 - A guide covering the RISC-V Architecture.
• ARM Guide 📍 - A guide covering ARM architecture.
• nand2tetris - Build an advanced computer from nand gate.
• Building a RISC-V CPU Core - edX 📽 - Build a RISC-V cpu core. No prior knowledge of digital logic design is required.
• Build a Modern Computer from First Principles: From Nand to Tetris - coursera 📽 - Build a modern computer system.

FPGA

• FPGA Tutorial 🚩 📍 - Sharing excellent articles and projects related to FPGA.
• Complex Programmable Logic Device (CPLD) Guide 📍 - A guide covering CPLD.

Tools

• EDA Playground - Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.
• tree-core-ide 📍- A VSCode-based HDL extension.
• WaveDrom - Digital Timing Diagram everywhere
• Icarus Verilog 📍Github - A Verilog simulation and synthesis tool.
• GTKWave - GTKWave is a fully featured GTK+ based wave viewer.
• OpenROAD 💬Doc 📍Github - An RTL-to-GDS Flow
• More information about hardware dv tools on Awesome Open Hardware Verification - Tools and Awesome HWD Tools

Forums

• EETOP 🚩 - The most popular IC bbs in China.
• edaboard - An EE World Online Resource.
• 极术社区 🚩 - A bbs sponsered by Arm China.

Online Judge Platforms

• HDL bits - A collection of small circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL).
• USTC Verilog OJ 🚩 - A verilog online judge service
• nowcoder - Verilog Part - A verilog oj platform.

Games

PC

• MHRD - Become a hardware engineer & Build your own CPU from NAND.

web

• NAND Game - Build a CPU from basic cells by dragging.

Mobile Phone

• 与门 🚩 - Build an adder from nand.

Discuss: QQ Group 830367636 Email [email protected]