diff --git a/src/qililab/digital/circuit_router.py b/src/qililab/digital/circuit_router.py
index b901b87a5..839d5ec3e 100644
--- a/src/qililab/digital/circuit_router.py
+++ b/src/qililab/digital/circuit_router.py
@@ -70,7 +70,7 @@ def __init__(
         # 3) Layout stage, where the initial_layout will be created.
 
     def route(self, circuit: Circuit, iterations: int = 10) -> tuple[Circuit, dict[str, int]]:
-        """Routes the virtual/logical qubits of a circuit, to the chip's physical qubits.
+        """Routes the virtual/logical qubits of a circuit, to the chip's physical qubits. And returns/logs the final layout of the qubits.
 
         **Examples:**
 
@@ -139,7 +139,7 @@ def route(self, circuit: Circuit, iterations: int = 10) -> tuple[Circuit, dict[s
     def _iterate_routing(
         routing_pipeline: Passes, circuit: Circuit, iterations: int = 10
     ) -> tuple[Circuit, dict[str, int], int | None]:
-        """Iterates the routing pipeline, to keep the best stochastic result.
+        """Iterates the routing pipeline, to keep the best stochastic result. And returns/logs the final layout of the qubits.
 
         Args:
             routing_pipeline (Passes): Transpilation pipeline passes.
diff --git a/src/qililab/digital/circuit_transpiler.py b/src/qililab/digital/circuit_transpiler.py
index b3b379877..de0dbf875 100644
--- a/src/qililab/digital/circuit_transpiler.py
+++ b/src/qililab/digital/circuit_transpiler.py
@@ -54,11 +54,16 @@ def transpile_circuits(
         """Transpiles a list of ``qibo.models.Circuit`` to a list of pulse schedules.
 
         First makes a routing and placement of the circuit to the chip's physical qubits. And returns/logs the final layout of the qubits.
+        If passed, this is done, with the `placer`, `router` and `routing_iterations` params (if not, default ones are applied).
 
-        Then translates the circuit to a native gate circuit and applies virtual Z gates and phase corrections for CZ gates.
+        Then translates the circuit to the native gate circuit, of the chip (CZ, RZ, Drag, Wait and M (Measurement).
 
         And finally, it converts the native gate circuit to a pulse schedule using calibrated settings from the runcard.
 
+        If ``optimize=True`` (default behaviour), then it also does some circuit optimization:
+        - cancelling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ and SWAPs).
+        - applying virtual Z gates and phase corrections (adding up several pulses into a single one, commuting them with virtual Zs).
+
         **Examples:**
 
         If we instantiate some ``Circuit``, ``Platform`` and ``CircuitTranspiler`` objects like:
@@ -138,9 +143,9 @@ def route_circuit(
         coupling_map: list[tuple[int, int]] | None = None,
         iterations: int = 10,
     ) -> tuple[Circuit, dict[str, int]]:
-        """Routes the virtual/logical qubits of a circuit, to the chip's physical qubits.
-
+        """Routes the virtual/logical qubits of a circuit, to the chip's physical qubits. And returns/logs the final layout of the qubits.
 
+        If passed, this is done, with the passed `placer`, `router` and `routing_iterations` params (if not, default ones are applied).
 
         **Examples:**
 
@@ -217,7 +222,7 @@ def optimize_circuit(self, circuit: Circuit) -> Circuit:
         return CircuitOptimizer.run_gate_cancellations(circuit)
 
     def circuit_to_native(self, circuit: Circuit) -> Circuit:
-        """Converts circuit with qibo gates to circuit with native gates
+        """Converts circuit with qibo gates to circuit with native gates (CZ, RZ, Drag, Wait and M (Measurement).
 
         Args:
             circuit (Circuit): circuit with qibo gate.
diff --git a/src/qililab/execute_circuit.py b/src/qililab/execute_circuit.py
index cd28855b2..0842473db 100644
--- a/src/qililab/execute_circuit.py
+++ b/src/qililab/execute_circuit.py
@@ -38,6 +38,16 @@ def execute(
     The ``program`` argument is first translated into pulses using the transpilation settings of the runcard and the
     passed placer and router. Then the pulse will be compiled into the runcard machines assembly programs, and executed.
 
+    The transpilation is done with the :class:`CircuitTranspiler`, ``transpile_circuits()`` method, refer to it for more detailed information,
+    but the main stages of this process are:
+    - Making the routing and placement of the circuit into the chip physical connectivity.
+    - Translates the gates into the system native's gates (CZ, RZ, Drag, Wait and M (Measurement).
+    - Converts the native gates to a pulse schedule using calibrated settings from the runcard.
+
+    If ``optimize=True`` (default behaviour), then the transpilation also does some circuit optimization:
+    - cancelling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ and SWAPs).
+    - applying virtual Z gates and phase corrections (adding up several pulses into a single one, commuting them with virtual Zs).
+
     Args:
         circuit (Circuit | list[Circuit]): Qibo Circuit.
         runcard (str | dict): If a string, path to the YAML file containing the serialization of the Platform to be
diff --git a/src/qililab/platform/platform.py b/src/qililab/platform/platform.py
index 92f513bd3..87047c8a9 100644
--- a/src/qililab/platform/platform.py
+++ b/src/qililab/platform/platform.py
@@ -914,6 +914,16 @@ def execute(
 
         To compile to assembly programs, the ``platform.compile()`` method is called; check its documentation for more information.
 
+        The transpilation is done with the :class:`CircuitTranspiler`, ``transpile_circuits()`` method, refer to it for more detailed information,
+        but the main stages of this process are:
+        - Making the routing and placement of the circuit into the chip physical connectivity.
+        - Translates the gates into the system native's gates (CZ, RZ, Drag, Wait and M (Measurement).
+        - Converts the native gates to a pulse schedule using calibrated settings from the runcard.
+
+        If ``optimize=True`` (default behaviour), then the transpilation also does some circuit optimization:
+        - cancelling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ and SWAPs).
+        - applying virtual Z gates and phase corrections (adding up several pulses into a single one, commuting them with virtual Zs).
+
         Args:
             program (:class:`PulseSchedule` | :class:`Circuit`): Circuit or pulse schedule to execute.
             num_avg (int): Number of hardware averages used.
@@ -1041,6 +1051,16 @@ def compile(
         If the ``program`` argument is a :class:`Circuit`, it will first be translated into a :class:`PulseSchedule` using the transpilation
         settings of the platform and passed placer and router. Then the pulse schedules will be compiled into the assembly programs.
 
+        The transpilation is done with the :class:`CircuitTranspiler`, ``transpile_circuits()`` method, refer to it for more detailed information,
+        but the main stages of this process are:
+        - Making the routing and placement of the circuit into the chip physical connectivity.
+        - Translates the gates into the system native's gates (CZ, RZ, Drag, Wait and M (Measurement).
+        - Converts the native gates to a pulse schedule using calibrated settings from the runcard.
+
+        If ``optimize=True`` (default behaviour), then the transpilation also does some circuit optimization:
+        - cancelling adjacent pairs of Hermitian gates (H, X, Y, Z, CNOT, CZ and SWAPs).
+        - applying virtual Z gates and phase corrections (adding up several pulses into a single one, commuting them with virtual Zs).
+
         This methods gets called during the ``platform.execute()`` method, check its documentation for more information.
 
         Args: