diff --git a/Bender.yml b/Bender.yml index 6e6794dd..27d0ec86 100644 --- a/Bender.yml +++ b/Bender.yml @@ -14,40 +14,29 @@ package: dependencies: L2_tcdm_hybrid_interco: { git: "https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git", version: 1.0.0 } - apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.1.0 } + apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.2 } adv_dbg_if: { git: "https://github.com/pulp-platform/adv_dbg_if.git", version: 0.0.2 } apb2per: { git: "https://github.com/pulp-platform/apb2per.git", version: 0.1.0 } apb_adv_timer: { git: "https://github.com/pulp-platform/apb_adv_timer.git", version: 1.0.4 } - apb_fll_if: { git: "https://github.com/pulp-platform/apb_fll_if.git", version: 0.1.3 } - apb_gpio: { git: "https://github.com/pulp-platform/apb_gpio.git", rev: "0e9f142f2f11278445c953ad011fce1c7ed85b66" } - apb_node: { git: "https://github.com/pulp-platform/apb_node.git", version: 0.1.1 } - apb_interrupt_cntrl: { git: "https://github.com/pulp-platform/apb_interrupt_cntrl.git", version: 0.1.1 } - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 } + apb_fll_if: { git: "https://github.com/pulp-platform/apb_fll_if.git", version: 0.2.0 } + apb_interrupt_cntrl: { git: "https://github.com/pulp-platform/apb_interrupt_cntrl.git", version: 0.2.0 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.38.0 } # axi_node: { git: "https://github.com/pulp-platform/axi_node.git", version: 1.1.4 } # deprecated, replaced by axi_xbar (in axi repo) axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.1.1 } fpnew: { git: "https://github.com/pulp-platform/fpnew.git", version: 0.6.6 } - jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", rev: v0.2.0 } + jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.2.0 } cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "pulpissimo-v4.1.0"} ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", version: 1.0.1} - generic_FLL: { git: "https://github.com/pulp-platform/generic_FLL.git", rev: "1c92dc73a940392182fd4cb7b86f35649b349595" } + generic_FLL: { git: "https://github.com/pulp-platform/generic_FLL.git", version: 0.2.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - udma_core: { git: "https://github.com/pulp-platform/udma_core.git", version: 1.1.2 } - udma_uart: { git: "https://github.com/pulp-platform/udma_uart.git", version: 1.0.2 } - udma_i2c: { git: "https://github.com/pulp-platform/udma_i2c.git", version: 2.0.0 } - udma_i2s: { git: "https://github.com/pulp-platform/udma_i2s.git", version: 1.1.2 } - udma_qspi: { git: "https://github.com/pulp-platform/udma_qspi.git", version: 1.0.4 } - udma_sdio: { git: "https://github.com/pulp-platform/udma_sdio.git", version: 1.1.2 } - udma_camera: { git: "https://github.com/pulp-platform/udma_camera.git", version: 1.1.2 } - udma_filter: { git: "https://github.com/pulp-platform/udma_filter.git", version: 1.0.3 } - udma_external_per: { git: "https://github.com/pulp-platform/udma_external_per.git", version: 1.0.4 } - udma_hyper: { git: "https://github.com/pulp-platform/udma_hyper.git", rev: "83ab704f9d1c5f9e5353268c901fe95c36bcea36" } + pulp_io: { git: "https://github.com/pulp-platform/pulp-io.git", rev: v0.1.0-draft } hwpe-mac-engine: { git: "https://github.com/pulp-platform/hwpe-mac-engine.git", version: 1.3.3 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.5.0 } - register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.2 } sources: # pulp_soc @@ -63,8 +52,6 @@ sources: - rtl/pulp_soc/boot_rom.sv - rtl/pulp_soc/l2_ram_multi_bank.sv - rtl/pulp_soc/lint_jtag_wrap.sv - - rtl/pulp_soc/periph_bus_wrap.sv - - rtl/pulp_soc/soc_clk_rst_gen.sv - rtl/pulp_soc/soc_event_arbiter.sv - rtl/pulp_soc/soc_event_generator.sv - rtl/pulp_soc/soc_event_queue.sv @@ -72,10 +59,8 @@ sources: - rtl/pulp_soc/soc_interconnect.sv - rtl/pulp_soc/soc_interconnect_wrap.sv - rtl/pulp_soc/soc_peripherals.sv + - rtl/pulp_soc/jtag_tap_top.sv - rtl/pulp_soc/pulp_soc.sv - # udma_subsystem - - files: - - rtl/udma_subsystem/udma_subsystem.sv # fc - target: rtl defines: diff --git a/rtl/components/apb_soc_ctrl.sv b/rtl/components/apb_soc_ctrl.sv index 13e83f36..72e22744 100644 --- a/rtl/components/apb_soc_ctrl.sv +++ b/rtl/components/apb_soc_ctrl.sv @@ -77,7 +77,7 @@ module apb_soc_ctrl #( output logic PREADY, output logic PSLVERR, - input logic sel_fll_clk_i, + input logic sel_pll_clk_i, input logic boot_l2_i, input logic [1:0] bootsel_i, input logic fc_fetch_en_valid_i, @@ -485,7 +485,7 @@ module apb_soc_ctrl #( `REG_BOOTSEL: PRDATA = {30'h0, r_bootsel}; `REG_CLKSEL: - PRDATA = {31'h0,sel_fll_clk_i}; + PRDATA = {31'h0,sel_pll_clk_i}; `REG_CLUSTER_CTRL: PRDATA = { 29'h0, diff --git a/rtl/components/tb_fs_handler.sv b/rtl/components/tb_fs_handler.sv index 810b4421..b0fbc7b4 100644 --- a/rtl/components/tb_fs_handler.sv +++ b/rtl/components/tb_fs_handler.sv @@ -338,7 +338,7 @@ module tb_fs_handler_debug #( if (SILENT_MODE == "OFF") begin if (FULL_LINE == "ON") begin - $display("[STDOUT-CL%0d_PE%0d] %s", CLUSTER_ID, core_index, + $display("[STDOUT-CL%0d_PE%0d, %t] %s", CLUSTER_ID, core_index, $realtime, LINE_BUFFER[core_index].substr(0, LINE_BUFFER[core_index].len() - 2)); LINE_BUFFER[core_index] = ""; end else begin diff --git a/rtl/fc/fc_hwpe.sv b/rtl/fc/fc_hwpe.sv index 6d4c59b3..7d262104 100644 --- a/rtl/fc/fc_hwpe.sv +++ b/rtl/fc/fc_hwpe.sv @@ -21,7 +21,7 @@ module fc_hwpe input logic test_mode_i, XBAR_TCDM_BUS.Master hwacc_xbar_master[N_MASTER_PORT-1:0], - APB_BUS.Slave hwacc_cfg_slave, + APB.Slave hwacc_cfg_slave, output logic [1:0] evt_o, output logic busy_o diff --git a/rtl/fc/fc_subsystem.sv b/rtl/fc/fc_subsystem.sv index 81f4c4ab..a78eec70 100644 --- a/rtl/fc/fc_subsystem.sv +++ b/rtl/fc/fc_subsystem.sv @@ -33,8 +33,8 @@ module fc_subsystem import cv32e40p_apu_core_pkg::*; #( XBAR_TCDM_BUS.Master l2_data_master, XBAR_TCDM_BUS.Master l2_instr_master, XBAR_TCDM_BUS.Master l2_hwpe_master [NB_HWPE_PORTS-1:0], - APB_BUS.Slave apb_slave_eu, - APB_BUS.Slave apb_slave_hwpe, + APB.Slave apb_slave_eu, + APB.Slave apb_slave_hwpe, input logic fetch_en_i, input logic [31:0] boot_addr_i, @@ -43,7 +43,7 @@ module fc_subsystem import cv32e40p_apu_core_pkg::*; #( input logic event_fifo_valid_i, output logic event_fifo_fulln_o, input logic [EVENT_ID_WIDTH-1:0] event_fifo_data_i, // goes indirectly to core interrupt - input logic [31:0] events_i, // goes directly to core interrupt, should be called irqs + input logic [31:0] interrupts_i, // goes directly to core interrupt, should be called irqs output logic [1:0] hwpe_events_o, output logic supervisor_mode_o @@ -330,7 +330,7 @@ module fc_subsystem import cv32e40p_apu_core_pkg::*; #( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .test_mode_i ( test_en_i ), - .events_i ( events_i ), + .events_i ( interrupts_i ), .event_fifo_valid_i ( event_fifo_valid_i ), .event_fifo_fulln_o ( event_fifo_fulln_o ), .event_fifo_data_i ( event_fifo_data_i ), diff --git a/rtl/pulp_soc/boot_rom.sv b/rtl/pulp_soc/boot_rom.sv index e21cbd0e..ee36360b 100644 --- a/rtl/pulp_soc/boot_rom.sv +++ b/rtl/pulp_soc/boot_rom.sv @@ -42,7 +42,10 @@ module boot_rom #( generic_rom #( .ADDR_WIDTH(ROM_ADDR_WIDTH-2), //The ROM uses 32-bit word addressing while the bus addresses bytes - .DATA_WIDTH(32) + .DATA_WIDTH(32), + .FILE_NAME("./boot/boot_code.cde") // CDE file is looked for in a + // folder relative to the + // simulation folder. ) rom_mem_i ( .CLK ( clk_i ), .CEN ( ~mem_slave.req ), diff --git a/rtl/pulp_soc/jtag_tap_top.sv b/rtl/pulp_soc/jtag_tap_top.sv new file mode 100644 index 00000000..52a8c5c8 --- /dev/null +++ b/rtl/pulp_soc/jtag_tap_top.sv @@ -0,0 +1,119 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + + +module jtag_tap_top #( + parameter logic [31:0] IDCODE_VALUE = 32'h10000db3 +)( + input logic tck_i, + input logic trst_ni, + input logic tms_i, + input logic td_i, + output logic td_o, + + input logic test_clk_i, + input logic test_rstn_i, + + input logic [7:0] soc_jtag_reg_i, + output logic [7:0] soc_jtag_reg_o, + output logic sel_fll_clk_o, + + // tap + output logic jtag_shift_dr_o, + output logic jtag_update_dr_o, + output logic jtag_capture_dr_o, + output logic axireg_sel_o, + + output logic dbg_axi_scan_in_o, + input logic dbg_axi_scan_out_i +); + + logic s_scan_i; + logic [8:0] s_confreg; + logic confscan; + logic confreg_sel; + logic td_o_int; + + logic [7:0] r_soc_reg0; + logic [7:0] r_soc_reg1; + + logic [7:0] s_soc_jtag_reg_sync; + + + + // jtag tap controller + tap_top #( + .IDCODE_VALUE ( IDCODE_VALUE ) + ) tap_top_i ( + .tms_i ( tms_i ), + .tck_i ( tck_i ), + .rst_ni ( trst_ni ), + .td_i ( td_i ), + .td_o ( td_o ), + + .shift_dr_o ( jtag_shift_dr_o ), + .update_dr_o ( jtag_update_dr_o ), + .capture_dr_o ( jtag_capture_dr_o ), + + .memory_sel_o ( axireg_sel_o ), + .fifo_sel_o ( ), + .confreg_sel_o ( confreg_sel ), + .observ_sel_o ( ), + .clk_byp_sel_o ( ), + + .scan_in_o ( s_scan_i ), + + .observ_out_i ( 1'b0 ), + .clk_byp_out_i ( 1'b0 ), + .memory_out_i ( dbg_axi_scan_out_i ), + .fifo_out_i ( 1'b0 ), + .confreg_out_i ( confscan ) + ); + + // pulp configuration register + jtagreg + #( + .JTAGREGSIZE(9), + .SYNC(0) + ) + confreg + ( + .clk_i ( tck_i ), + .rst_ni ( trst_ni ), + .enable_i ( confreg_sel ), + .capture_dr_i ( jtag_capture_dr_o ), + .shift_dr_i ( jtag_shift_dr_o ), + .update_dr_i ( jtag_update_dr_o ), + .jtagreg_in_i ( {1'b0, s_soc_jtag_reg_sync} ), //at sys rst enable the fll + .mode_i ( 1'b1 ), + .scan_in_i ( s_scan_i ), + .jtagreg_out_o ( s_confreg ), + .scan_out_o ( confscan ) + ); + + always_ff @(posedge tck_i or negedge trst_ni) begin + if(~trst_ni) begin + r_soc_reg0 <= 0; + r_soc_reg1 <= 0; + end else begin + r_soc_reg1 <= soc_jtag_reg_i; + r_soc_reg0 <= r_soc_reg1; + end + end + + assign s_soc_jtag_reg_sync =r_soc_reg0; + + assign dbg_axi_scan_in_o = s_scan_i; + + assign soc_jtag_reg_o = s_confreg[7:0]; + + assign sel_fll_clk_o = s_confreg[8]; + +endmodule diff --git a/rtl/pulp_soc/periph_bus_wrap.sv b/rtl/pulp_soc/periph_bus_wrap.sv deleted file mode 100644 index 583cdfee..00000000 --- a/rtl/pulp_soc/periph_bus_wrap.sv +++ /dev/null @@ -1,115 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - - -`include "periph_bus_defines.sv" - -module periph_bus_wrap #( - parameter APB_ADDR_WIDTH = 32, - parameter APB_DATA_WIDTH = 32 -) ( - input logic clk_i, - input logic rst_ni, - APB_BUS.Slave apb_slave, - APB_BUS.Master fll_master, - APB_BUS.Master gpio_master, - APB_BUS.Master udma_master, - APB_BUS.Master soc_ctrl_master, - APB_BUS.Master adv_timer_master, - APB_BUS.Master soc_evnt_gen_master, - APB_BUS.Master eu_master, - APB_BUS.Master mmap_debug_master, - APB_BUS.Master timer_master, - APB_BUS.Master hwpe_master, - APB_BUS.Master stdout_master -); - - localparam NB_MASTER = `NB_MASTER; - - logic [NB_MASTER-1:0][APB_ADDR_WIDTH-1:0] s_start_addr; - logic [NB_MASTER-1:0][APB_ADDR_WIDTH-1:0] s_end_addr; - - APB_BUS - #( - .APB_ADDR_WIDTH(APB_ADDR_WIDTH), - .APB_DATA_WIDTH(APB_DATA_WIDTH) - ) - s_masters[NB_MASTER-1:0](); - - APB_BUS #( - .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ), - .APB_DATA_WIDTH ( APB_DATA_WIDTH ) - ) s_slave (); - - `APB_ASSIGN_SLAVE(s_slave, apb_slave); - - `APB_ASSIGN_MASTER(s_masters[0], fll_master); - assign s_start_addr[0] = `FLL_START_ADDR; - assign s_end_addr[0] = `FLL_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[1], gpio_master); - assign s_start_addr[1] = `GPIO_START_ADDR; - assign s_end_addr[1] = `GPIO_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[2], udma_master); - assign s_start_addr[2] = `UDMA_START_ADDR; - assign s_end_addr[2] = `UDMA_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[3], soc_ctrl_master); - assign s_start_addr[3] = `SOC_CTRL_START_ADDR; - assign s_end_addr[3] = `SOC_CTRL_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[4], adv_timer_master); - assign s_start_addr[4] = `ADV_TIMER_START_ADDR; - assign s_end_addr[4] = `ADV_TIMER_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[5], soc_evnt_gen_master); - assign s_start_addr[5] = `SOC_EVENT_GEN_START_ADDR; - assign s_end_addr[5] = `SOC_EVENT_GEN_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[6], eu_master); - assign s_start_addr[6] = `EU_START_ADDR; - assign s_end_addr[6] = `EU_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[7], timer_master); - assign s_start_addr[7] = `TIMER_START_ADDR; - assign s_end_addr[7] = `TIMER_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[8], hwpe_master); - assign s_start_addr[8] = `HWPE_START_ADDR; - assign s_end_addr[8] = `HWPE_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[9], stdout_master); - assign s_start_addr[9] = `STDOUT_START_ADDR; - assign s_end_addr[9] = `STDOUT_END_ADDR; - - `APB_ASSIGN_MASTER(s_masters[10], mmap_debug_master); - assign s_start_addr[10] = `DEBUG_START_ADDR; - assign s_end_addr[10] = `DEBUG_END_ADDR; - - //******************************************************** - //**************** SOC BUS ******************************* - //******************************************************** - apb_node_wrap #( - .NB_MASTER ( NB_MASTER ), - .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ), - .APB_DATA_WIDTH ( APB_DATA_WIDTH ) - ) apb_node_wrap_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .apb_slave ( s_slave ), - .apb_masters ( s_masters ), - - .start_addr_i ( s_start_addr ), - .end_addr_i ( s_end_addr ) - ); - -endmodule diff --git a/rtl/pulp_soc/pulp_soc.sv b/rtl/pulp_soc/pulp_soc.sv index 3c30ac5b..2dc52f73 100644 --- a/rtl/pulp_soc/pulp_soc.sv +++ b/rtl/pulp_soc/pulp_soc.sv @@ -10,6 +10,7 @@ `include "pulp_soc_defines.sv" +`include "soc_mem_map.svh" `include "axi/typedef.svh" `include "axi/assign.svh" @@ -18,7 +19,6 @@ module pulp_soc import dm::*; #( parameter USE_XPULP = 1, parameter USE_FPU = 1, parameter USE_HWPE = 1, - parameter USE_CLUSTER_EVENT = 1, parameter SIM_STDOUT = 1, parameter AXI_ADDR_WIDTH = 32, parameter AXI_DATA_IN_WIDTH = 64, @@ -32,17 +32,8 @@ module pulp_soc import dm::*; #( parameter EVNT_WIDTH = 8, parameter NB_CORES = 8, parameter NB_HWPE_PORTS = 4, - parameter NGPIO = 43, - parameter NPAD = 64, //Must not be changed as other parts - //downstreams are not parametrci - parameter NBIT_PADCFG = 6, //Must not be changed as other parts - //downstreams are not parametrci - parameter NBIT_PADMUX = 2, - - parameter int unsigned N_UART = 1, - parameter int unsigned N_SPI = 1, - parameter int unsigned N_I2C = 2, parameter USE_ZFINX = 1, + localparam NGPIO = gpio_reg_pkg::GPIOCount, localparam C2S_AW_WIDTH = AXI_ID_IN_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::len_t)+$bits(axi_pkg::size_t)+$bits(axi_pkg::burst_t)+$bits(axi_pkg::cache_t)+$bits(axi_pkg::prot_t)+$bits(axi_pkg::qos_t)+$bits(axi_pkg::region_t)+$bits(axi_pkg::atop_t)+1, localparam C2S_W_WIDTH = AXI_USER_WIDTH+AXI_STRB_WIDTH_IN+AXI_DATA_IN_WIDTH+1, localparam C2S_R_WIDTH = AXI_ID_IN_WIDTH+AXI_DATA_IN_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::resp_t)+1, @@ -54,42 +45,46 @@ module pulp_soc import dm::*; #( localparam S2C_B_WIDTH = AXI_USER_WIDTH+AXI_ID_OUT_WIDTH+$bits(axi_pkg::resp_t), localparam S2C_AR_WIDTH = AXI_ID_OUT_WIDTH+AXI_ADDR_WIDTH+AXI_USER_WIDTH+$bits(axi_pkg::len_t)+$bits(axi_pkg::size_t)+$bits(axi_pkg::burst_t)+$bits(axi_pkg::cache_t)+$bits(axi_pkg::prot_t)+$bits(axi_pkg::qos_t)+$bits(axi_pkg::region_t)+1 ) ( - input logic ref_clk_i, - input logic slow_clk_i, - input logic test_clk_i, - input logic rstn_glob_i, - - input logic dft_test_mode_i, - input logic dft_cg_enable_i, - input logic mode_select_i, - input logic boot_l2_i, - input logic [1:0] bootsel_i, - - input logic fc_fetch_en_valid_i, - input logic fc_fetch_en_i, - - output logic cluster_rtc_o, - output logic cluster_fetch_enable_o, - output logic [63:0] cluster_boot_addr_o, - output logic cluster_test_en_o, - output logic cluster_pow_o, - output logic cluster_byp_o, - output logic cluster_rstn_o, - output logic cluster_irq_o, - // AXI4 SLAVE - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_aw_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_AW_WIDTH-1:0] async_data_slave_aw_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_aw_rptr_o, + input logic slow_clk_i, + /// Async reset with deassertion synced to slow_clk rising edge. Do not just + /// reset domains individually! This needs clock domain/reset domain crossing + /// safe sequencing!!! + input logic slow_clk_rstn_synced_i, + input logic soc_clk_i, + /// Async reset with deassertion synced to soc_clk rising edge. Do not just + /// reset domains individually! This needs clock domain/reset domain crossing + /// safe sequencing!!! + input logic soc_rstn_synced_i, + input logic per_clk_i, + /// Async reset with deassertion synced to per_clk rising edge. Do not just + /// reset domains individually! This needs clock domain/reset domain crossing + /// safe sequencing!!! + input logic per_rstn_synced_i, + + input logic dft_test_mode_i, + input logic dft_cg_enable_i, + input logic boot_l2_i, + input logic [1:0] bootsel_i, + + input logic fc_fetch_en_valid_i, + input logic fc_fetch_en_i, + + output logic cluster_rstn_req_o, + + // AXI4 SLAVE + input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_aw_wptr_i, + input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_AW_WIDTH-1:0] async_data_slave_aw_data_i, + output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_aw_rptr_o, // READ ADDRESS CHANNEL - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_ar_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_AR_WIDTH-1:0] async_data_slave_ar_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_ar_rptr_o, + input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_ar_wptr_i, + input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_AR_WIDTH-1:0] async_data_slave_ar_data_i, + output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_ar_rptr_o, // WRITE DATA CHANNEL - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_w_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_W_WIDTH-1:0] async_data_slave_w_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_w_rptr_o, + input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_w_wptr_i, + input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][C2S_W_WIDTH-1:0] async_data_slave_w_data_i, + output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_w_rptr_o, // READ DATA CHANNEL output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_slave_r_wptr_o, @@ -104,7 +99,7 @@ module pulp_soc import dm::*; #( // AXI4 MASTER output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_aw_wptr_o, output logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_AW_WIDTH-1:0] async_data_master_aw_data_o, - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_aw_rptr_i, + input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_aw_rptr_i, // READ ADDRESS CHANNEL output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_ar_wptr_o, @@ -117,100 +112,83 @@ module pulp_soc import dm::*; #( input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_w_rptr_i, // READ DATA CHANNEL - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_r_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_R_WIDTH-1:0] async_data_master_r_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_r_rptr_o, + input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_r_wptr_i, + input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_R_WIDTH-1:0] async_data_master_r_data_i, + output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_r_rptr_o, // WRITE RESPONSE CHANNEL - input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_b_wptr_i, - input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_B_WIDTH-1:0] async_data_master_b_data_i, - output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_b_rptr_o, + input logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_b_wptr_i, + input logic [2**CDC_FIFOS_LOG_DEPTH-1:0][S2C_B_WIDTH-1:0] async_data_master_b_data_i, + output logic [CDC_FIFOS_LOG_DEPTH:0] async_data_master_b_rptr_o, // EVENT BUS - output logic [CDC_FIFOS_LOG_DEPTH:0] async_cluster_events_wptr_o, - input logic [CDC_FIFOS_LOG_DEPTH:0] async_cluster_events_rptr_i, - output logic [EVNT_WIDTH-1:0][2**CDC_FIFOS_LOG_DEPTH-1:0] async_cluster_events_data_o, - - output logic cluster_clk_o, - input logic cluster_busy_i, - output logic dma_pe_evt_ack_o, - input logic dma_pe_evt_valid_i, - output logic dma_pe_irq_ack_o, - input logic dma_pe_irq_valid_i, - output logic pf_evt_ack_o, - input logic pf_evt_valid_i, - /////////////////////////////////////////////////// - // To I/O Controller and padframe // - /////////////////////////////////////////////////// - output logic [127:0] pad_mux_o, - output logic [383:0] pad_cfg_o, - input logic [NGPIO-1:0] gpio_in_i, - output logic [NGPIO-1:0] gpio_out_o, - output logic [NGPIO-1:0] gpio_dir_o, - output logic [191:0] gpio_cfg_o, - output logic uart_tx_o, - input logic uart_rx_i, - input logic cam_clk_i, - input logic [7:0] cam_data_i, - input logic cam_hsync_i, - input logic cam_vsync_i, - output logic [3:0] timer_ch0_o, - output logic [3:0] timer_ch1_o, - output logic [3:0] timer_ch2_o, - output logic [3:0] timer_ch3_o, - - input logic [N_I2C-1:0] i2c_scl_i, - output logic [N_I2C-1:0] i2c_scl_o, - output logic [N_I2C-1:0] i2c_scl_oe_o, - input logic [N_I2C-1:0] i2c_sda_i, - output logic [N_I2C-1:0] i2c_sda_o, - output logic [N_I2C-1:0] i2c_sda_oe_o, - - input logic i2s_slave_sd0_i, - input logic i2s_slave_sd1_i, - input logic i2s_slave_ws_i, - output logic i2s_slave_ws_o, - output logic i2s_slave_ws_oe, - input logic i2s_slave_sck_i, - output logic i2s_slave_sck_o, - output logic i2s_slave_sck_oe, - - output logic [N_SPI-1:0] spi_clk_o, - output logic [N_SPI-1:0][3:0] spi_csn_o, - output logic [N_SPI-1:0][3:0] spi_oen_o, - output logic [N_SPI-1:0][3:0] spi_sdo_o, - input logic [N_SPI-1:0][3:0] spi_sdi_i, - - output logic sdio_clk_o, - output logic sdio_cmd_o, - input logic sdio_cmd_i, - output logic sdio_cmd_oen_o, - output logic [3:0] sdio_data_o, - input logic [3:0] sdio_data_i, - output logic [3:0] sdio_data_oen_o, - - output logic [1:0] hyper_cs_no, - output logic hyper_ck_o, - output logic hyper_ck_no, - output logic [1:0] hyper_rwds_o, - input logic hyper_rwds_i, - output logic [1:0] hyper_rwds_oe_o, - input logic [15:0] hyper_dq_i, - output logic [15:0] hyper_dq_o, - output logic [1:0] hyper_dq_oe_o, - output logic hyper_reset_no, - - /////////////////////////////////////////////////// - /////////////////////////////////////////////////// - // From JTAG Tap Controller to axi_dcb module // - /////////////////////////////////////////////////// - input logic jtag_tck_i, - input logic jtag_trst_ni, - input logic jtag_tms_i, - input logic jtag_tdi_i, - output logic jtag_tdo_o, - output logic [NB_CORES-1:0] cluster_dbg_irq_valid_o - /////////////////////////////////////////////////// + output logic [CDC_FIFOS_LOG_DEPTH:0] async_cluster_events_wptr_o, + input logic [CDC_FIFOS_LOG_DEPTH:0] async_cluster_events_rptr_i, + output logic [EVNT_WIDTH-1:0][2**CDC_FIFOS_LOG_DEPTH-1:0] async_cluster_events_data_o, + + input logic cluster_busy_i, + output logic dma_pe_evt_ack_o, + input logic dma_pe_evt_valid_i, + output logic dma_pe_irq_ack_o, + input logic dma_pe_irq_valid_i, + output logic pf_evt_ack_o, + input logic pf_evt_valid_i, + + // Timer Channels + output logic [3:0] timer_ch0_o, + output logic [3:0] timer_ch1_o, + output logic [3:0] timer_ch2_o, + output logic [3:0] timer_ch3_o, + + // Peripheral Connections + // UART + output uart_pkg::uart_to_pad_t [udma_cfg_pkg::N_UART-1:0] uart_to_pad_o, + input uart_pkg::pad_to_uart_t [udma_cfg_pkg::N_UART-1:0] pad_to_uart_i, + // I2C + output i2c_pkg::i2c_to_pad_t [udma_cfg_pkg::N_I2C-1:0] i2c_to_pad_o, + input i2c_pkg::pad_to_i2c_t [udma_cfg_pkg::N_I2C-1:0] pad_to_i2c_i, + // SDIO + output sdio_pkg::sdio_to_pad_t [udma_cfg_pkg::N_SDIO-1:0] sdio_to_pad_o, + input sdio_pkg::pad_to_sdio_t [udma_cfg_pkg::N_SDIO-1:0] pad_to_sdio_i, + // I2S + output i2s_pkg::i2s_to_pad_t [udma_cfg_pkg::N_I2S-1:0] i2s_to_pad_o, + input i2s_pkg::pad_to_i2s_t [udma_cfg_pkg::N_I2S-1:0] pad_to_i2s_i, + // QSPI + output qspi_pkg::qspi_to_pad_t [udma_cfg_pkg::N_QSPIM-1:0] qspi_to_pad_o, + input qspi_pkg::pad_to_qspi_t [udma_cfg_pkg::N_QSPIM-1:0] pad_to_qspi_i, + // CPI + input cpi_pkg::pad_to_cpi_t [udma_cfg_pkg::N_CPI-1:0] pad_to_cpi_i, + // HYPER + output hyper_pkg::hyper_to_pad_t [udma_cfg_pkg::N_HYPER-1:0] hyper_to_pad_o, + input hyper_pkg::pad_to_hyper_t [udma_cfg_pkg::N_HYPER-1:0] pad_to_hyper_i, + // GPIO + input logic [NGPIO-1:0] gpio_i, + output logic [NGPIO-1:0] gpio_o, + output logic [NGPIO-1:0] gpio_tx_en_o, + + + ///////////////////////////////////////// + // Configuration ports to Chip Control // + ///////////////////////////////////////// + output logic jtag_tap_bypass_fll_clk_o, + output logic [31:0] apb_chip_ctrl_master_paddr_o, + output logic [2:0] apb_chip_ctrl_master_pprot_o, + output logic apb_chip_ctrl_master_psel_o, + output logic apb_chip_ctrl_master_penable_o, + output logic apb_chip_ctrl_master_pwrite_o, + output logic [31:0] apb_chip_ctrl_master_pwdata_o, + output logic [3:0] apb_chip_ctrl_master_pstrb_o, + input logic [31:0] apb_chip_ctrl_master_prdata_i, + input logic apb_chip_ctrl_master_pready_i, + input logic apb_chip_ctrl_master_pslverr_i, + + // JTAG signals + input logic jtag_tck_i, + input logic jtag_trst_ni, + input logic jtag_tms_i, + input logic jtag_tdi_i, + output logic jtag_tdo_o, + output logic [NB_CORES-1:0] cluster_dbg_irq_valid_o ); localparam NB_L2_BANKS = `NB_L2_CHANNELS; @@ -244,7 +222,7 @@ module pulp_soc import dm::*; #( // this is a constant expression function logic [NrHarts-1:0] SEL_HARTS_FX(); SEL_HARTS_FX = (1 << FC_CORE_MHARTID); - for (int i = 0; i < NB_CORES; i++) begin + for (bit[31:0] i = 0; i < NB_CORES; i++) begin SEL_HARTS_FX |= (1 << {CL_CORE_CLUSTER_ID, 1'b0, i[3:0]}); end endfunction @@ -278,7 +256,7 @@ module pulp_soc import dm::*; #( //***************** SIGNALS DECLARATION ****************** //******************************************************** logic [ 1:0] s_fc_hwpe_events; - logic [31:0] s_fc_events; + logic [31:0] s_fc_interrupts; logic [7:0] s_soc_events_ack; logic [7:0] s_soc_events_val; @@ -299,17 +277,6 @@ module pulp_soc import dm::*; #( logic [31:0] s_fc_bootaddr; - logic [NGPIO-1:0][NBIT_PADCFG-1:0] s_gpio_cfg; - logic [63:0][1:0] s_pad_mux; - logic [63:0][5:0] s_pad_cfg; - - logic s_periph_clk; - logic s_periph_rstn; - logic s_soc_clk; - logic s_soc_rstn; - logic s_cluster_clk; - logic s_cluster_rstn; - logic s_cluster_rstn_soc_ctrl; logic s_sel_fll_clk; logic s_dma_pe_evt; @@ -352,14 +319,29 @@ module pulp_soc import dm::*; #( logic s_jtag_shift_dr; logic s_jtag_update_dr; logic s_jtag_capture_dr; - logic s_jtag_axireg_sel; - logic s_jtag_axireg_tdi; - logic s_jtag_axireg_tdo; - - - APB_BUS s_apb_eu_bus (); - APB_BUS s_apb_hwpe_bus (); - APB_BUS s_apb_debug_bus(); + logic s_jtag_lint_sel; + logic s_jtag_lint_tdi; + logic s_jtag_lint_tdo; + + + APB #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_apb_intrpt_ctrl_bus (); + APB #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_apb_hwpe_bus (); + APB #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_apb_debug_bus(); + APB #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_apb_chip_ctrl_bus(); + + // Explode chip control APB interface to individual signals to support + // standalone synthesis/floorplaining (Many tools don't like SV interfaces + // at the toplevel and the APB structs are hard to use in a port list.) + assign apb_chip_ctrl_master_paddr_o = s_apb_chip_ctrl_bus.paddr; + assign apb_chip_ctrl_master_pprot_o = s_apb_chip_ctrl_bus.pprot; + assign apb_chip_ctrl_master_psel_o = s_apb_chip_ctrl_bus.psel; + assign apb_chip_ctrl_master_penable_o = s_apb_chip_ctrl_bus.penable; + assign apb_chip_ctrl_master_pwrite_o = s_apb_chip_ctrl_bus.pwrite; + assign apb_chip_ctrl_master_pwdata_o = s_apb_chip_ctrl_bus.pwdata; + assign apb_chip_ctrl_master_pstrb_o = s_apb_chip_ctrl_bus.pstrb; + assign s_apb_chip_ctrl_bus.prdata = apb_chip_ctrl_master_prdata_i; + assign s_apb_chip_ctrl_bus.pready = apb_chip_ctrl_master_pready_i; + assign s_apb_chip_ctrl_bus.pslverr = apb_chip_ctrl_master_pslverr_i; AXI_BUS #( @@ -379,18 +361,12 @@ module pulp_soc import dm::*; #( //assign s_data_out_bus.aw_atop = 6'b0; - FLL_BUS s_soc_fll_master (); - - FLL_BUS s_per_fll_master (); - - FLL_BUS s_cluster_fll_master (); - - APB_BUS s_apb_periph_bus (); + AXI_LITE #(.AXI_ADDR_WIDTH(32), .AXI_DATA_WIDTH(32)) s_periph_bus (); XBAR_TCDM_BUS s_mem_rom_bus (); - XBAR_TCDM_BUS s_mem_l2_bus[NB_L2_BANKS-1:0](); - XBAR_TCDM_BUS s_mem_l2_pri_bus[NB_L2_BANKS_PRI-1:0](); + XBAR_TCDM_BUS s_mem_l2_bus[NB_L2_BANKS](); + XBAR_TCDM_BUS s_mem_l2_pri_bus[NB_L2_BANKS_PRI](); XBAR_TCDM_BUS s_lint_debug_bus(); XBAR_TCDM_BUS s_lint_pulp_jtag_bus(); @@ -408,14 +384,6 @@ module pulp_soc import dm::*; #( - logic s_rstn_cluster_sync_soc; - - - assign cluster_clk_o = s_cluster_clk; - assign cluster_rstn_o = s_cluster_rstn && s_cluster_rstn_soc_ctrl; - assign s_rstn_cluster_sync_soc = s_cluster_rstn && s_cluster_rstn_soc_ctrl; - - assign cluster_rtc_o = ref_clk_i; assign cluster_test_en_o = dft_test_mode_i; // If you want to connect a real PULP cluster you also need a cluster_busy_i signal @@ -459,7 +427,7 @@ module pulp_soc import dm::*; #( .LogDepth ( 3 ) ) axi_slave_cdc_i ( .dst_rst_ni ( s_rstn_cluster_sync_soc ), - .dst_clk_i ( s_soc_clk ), + .dst_clk_i ( soc_clk_i ), .dst_req_o ( dst_req ), .dst_resp_i ( dst_resp ), .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), @@ -519,8 +487,8 @@ module pulp_soc import dm::*; #( .axi_resp_t(s2c_resp_t ), .LogDepth ( CDC_FIFOS_LOG_DEPTH ) ) axi_master_cdc_i ( - .src_rst_ni ( s_rstn_cluster_sync_soc ), - .src_clk_i ( s_soc_clk ), + .src_rst_ni ( soc_rstn_synced_i ), + .src_clk_i ( soc_clk_i ), .src_req_i ( src_req ), .src_resp_o ( src_resp ), .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), @@ -548,8 +516,8 @@ module pulp_soc import dm::*; #( .NB_BANKS ( NB_L2_BANKS ), .BANK_SIZE_INTL_SRAM ( L2_BANK_SIZE ) ) l2_ram_i ( - .clk_i ( s_soc_clk ), - .rst_ni ( s_soc_rstn ), + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), .init_ni ( 1'b1 ), .test_mode_i ( dft_test_mode_i ), .mem_slave ( s_mem_l2_bus ), @@ -564,8 +532,8 @@ module pulp_soc import dm::*; #( boot_rom #( .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH) ) boot_rom_i ( - .clk_i ( s_soc_clk ), - .rst_ni ( s_soc_rstn ), + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), .init_ni ( 1'b1 ), .mem_slave ( s_mem_rom_bus ), .test_mode_i ( dft_test_mode_i ) @@ -582,25 +550,24 @@ module pulp_soc import dm::*; #( .NB_CORES ( NB_CORES ), .NB_CLUSTERS ( `NB_CLUSTERS ), .EVNT_WIDTH ( EVNT_WIDTH ), - .NGPIO ( NGPIO ), - .NPAD ( NPAD ), - .NBIT_PADCFG ( NBIT_PADCFG ), - .NBIT_PADMUX ( NBIT_PADMUX ), - .N_UART ( N_UART ), - .N_SPI ( N_SPI ), - .N_I2C ( N_I2C ), .SIM_STDOUT ( SIM_STDOUT ) ) soc_peripherals_i ( - .clk_i ( s_soc_clk ), - .periph_clk_i ( s_periph_clk ), - .rst_ni ( s_soc_rstn ), - .sel_fll_clk_i ( s_sel_fll_clk ), - .ref_clk_i ( ref_clk_i ), + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), + .periph_clk_i ( per_clk_i ), + .periph_rstn_i ( per_rstn_synced_i ), + .slow_clk_i ( slow_clk_i ), + .slow_rstn_i ( slow_clk_rstn_synced_i ), + .sel_pll_clk_i ( s_sel_fll_clk ), .dft_test_mode_i ( dft_test_mode_i ), - .dft_cg_enable_i ( 1'b0 ), + .dft_cg_enable_i ( dft_cg_enable_i ), + .fc_bootaddr_o ( s_fc_bootaddr ), + .fc_fetchen_o ( s_fc_fetchen ), + .soc_jtag_reg_i ( soc_jtag_reg_tap ), + .soc_jtag_reg_o ( soc_jtag_reg_soc ), .boot_l2_i ( boot_l2_i ), .bootsel_i ( bootsel_i ), @@ -608,101 +575,55 @@ module pulp_soc import dm::*; #( .fc_fetch_en_valid_i ( fc_fetch_en_valid_i ), .fc_fetch_en_i ( fc_fetch_en_i ), - .fc_bootaddr_o ( s_fc_bootaddr ), - .fc_fetchen_o ( s_fc_fetchen ), - .apb_slave ( s_apb_periph_bus ), + .axi_lite_slave ( s_periph_bus ), - .apb_eu_master ( s_apb_eu_bus ), - .apb_debug_master ( s_apb_debug_bus ), + .apb_intrpt_ctrl_master ( s_apb_intrpt_ctrl_bus ), .apb_hwpe_master ( s_apb_hwpe_bus ), + .apb_debug_master ( s_apb_debug_bus ), + .apb_chip_ctrl_master ( s_apb_chip_ctrl_bus ), .l2_rx_master ( s_lint_udma_rx_bus ), .l2_tx_master ( s_lint_udma_tx_bus ), - .soc_jtag_reg_i ( soc_jtag_reg_tap ), - .soc_jtag_reg_o ( soc_jtag_reg_soc ), - - .fc_hwpe_events_i ( s_fc_hwpe_events ), - .fc_events_o ( s_fc_events ), - .dma_pe_evt_i ( s_dma_pe_evt ), .dma_pe_irq_i ( s_dma_pe_irq ), .pf_evt_i ( s_pf_evt ), + .fc_hwpe_events_i ( s_fc_hwpe_events ), + .fc_interrupts_o ( s_fc_interrupts ), - .soc_fll_master ( s_soc_fll_master ), - .per_fll_master ( s_per_fll_master ), - .cluster_fll_master ( s_cluster_fll_master ), - - .gpio_in ( gpio_in_i ), - .gpio_out ( gpio_out_o ), - .gpio_dir ( gpio_dir_o ), - .gpio_padcfg ( s_gpio_cfg ), - - .pad_mux_o ( s_pad_mux ), - .pad_cfg_o ( s_pad_cfg ), - - //CAMERA - .cam_clk_i ( cam_clk_i ), - .cam_data_i ( cam_data_i ), - .cam_hsync_i ( cam_hsync_i ), - .cam_vsync_i ( cam_vsync_i ), - - //UART - .uart_tx ( uart_tx_o ), - .uart_rx ( uart_rx_i ), - - //I2C - .i2c_scl_i ( i2c_scl_i ), - .i2c_scl_o ( i2c_scl_o ), - .i2c_scl_oe_o ( i2c_scl_oe_o ), - .i2c_sda_i ( i2c_sda_i ), - .i2c_sda_o ( i2c_sda_o ), - .i2c_sda_oe_o ( i2c_sda_oe_o ), - - //I2S - .i2s_slave_sd0_i ( i2s_slave_sd0_i ), - .i2s_slave_sd1_i ( i2s_slave_sd1_i ), - .i2s_slave_ws_i ( i2s_slave_ws_i ), - .i2s_slave_ws_o ( i2s_slave_ws_o ), - .i2s_slave_ws_oe ( i2s_slave_ws_oe ), - .i2s_slave_sck_i ( i2s_slave_sck_i ), - .i2s_slave_sck_o ( i2s_slave_sck_o ), - .i2s_slave_sck_oe ( i2s_slave_sck_oe ), - - //SPI - .spi_clk_o ( spi_clk_o ), - .spi_csn_o ( spi_csn_o ), - .spi_oen_o ( spi_oen_o ), - .spi_sdo_o ( spi_sdo_o ), - .spi_sdi_i ( spi_sdi_i ), - - //SDIO - .sdclk_o ( sdio_clk_o ), - .sdcmd_o ( sdio_cmd_o ), - .sdcmd_i ( sdio_cmd_i ), - .sdcmd_oen_o ( sdio_cmd_oen_o ), - .sddata_o ( sdio_data_o ), - .sddata_i ( sdio_data_i ), - .sddata_oen_o ( sdio_data_oen_o ), - - //Hyper Bus - .hyper_cs_no ( hyper_cs_no ), - .hyper_ck_o ( hyper_ck_o ), - .hyper_ck_no ( hyper_ck_no ), - .hyper_rwds_o ( hyper_rwds_o ), - .hyper_rwds_i ( hyper_rwds_i ), - .hyper_rwds_oe_o ( hyper_rwds_oe_o ), - .hyper_dq_i ( hyper_dq_i ), - .hyper_dq_o ( hyper_dq_o ), - .hyper_dq_oe_o ( hyper_dq_oe_o ), - .hyper_reset_no ( hyper_reset_no ), .timer_ch0_o ( timer_ch0_o ), .timer_ch1_o ( timer_ch1_o ), .timer_ch2_o ( timer_ch2_o ), .timer_ch3_o ( timer_ch3_o ), + // UART + .uart_to_pad_o, + .pad_to_uart_i, + // I2C + .i2c_to_pad_o, + .pad_to_i2c_i, + // SDIO + .sdio_to_pad_o, + .pad_to_sdio_i, + // I2S + .i2s_to_pad_o, + .pad_to_i2s_i, + // QSPI + .qspi_to_pad_o, + .pad_to_qspi_i, + // CPI + .pad_to_cpi_i, + // HYPER + .hyper_to_pad_o, + .pad_to_hyper_i, + + // GPIO + .gpio_i, + .gpio_o, + .gpio_tx_en_o, + .cl_event_data_o ( s_cl_event_data ), .cl_event_valid_o ( s_cl_event_valid ), .cl_event_ready_i ( s_cl_event_ready ), @@ -711,13 +632,7 @@ module pulp_soc import dm::*; #( .fc_event_valid_o ( s_fc_event_valid ), .fc_event_ready_i ( s_fc_event_ready ), - .cluster_pow_o ( cluster_pow_o ), - .cluster_byp_o ( cluster_byp_o ), - .cluster_boot_addr_o ( cluster_boot_addr_o ), - .cluster_fetch_enable_o ( cluster_fetch_enable_o ), - .cluster_rstn_o ( s_cluster_rstn_soc_ctrl), - .cluster_irq_o ( cluster_irq_o ) - + .cluster_rstn_req_o ); cdc_fifo_gray_src #( @@ -725,8 +640,8 @@ module pulp_soc import dm::*; #( .LOG_DEPTH(CDC_FIFOS_LOG_DEPTH), .SYNC_STAGES(2) ) i_event_cdc_src ( - .src_rst_ni ( s_rstn_cluster_sync_soc ), - .src_clk_i ( s_soc_clk ), + .src_rst_ni ( soc_rstn_synced_i ), + .src_clk_i ( soc_clk_i ), .src_data_i ( s_cl_event_data ), .src_valid_i ( s_cl_event_valid ), .src_ready_o ( s_cl_event_ready ), @@ -736,24 +651,24 @@ module pulp_soc import dm::*; #( ); edge_propagator_rx ep_dma_pe_evt_i ( - .clk_i ( s_soc_clk ), - .rstn_i ( s_rstn_cluster_sync_soc ), + .clk_i ( soc_clk_i ), + .rstn_i ( soc_rstn_synced_i ), .valid_o ( s_dma_pe_evt ), .ack_o ( dma_pe_evt_ack_o ), .valid_i ( dma_pe_evt_valid_i ) ); edge_propagator_rx ep_dma_pe_irq_i ( - .clk_i ( s_soc_clk ), - .rstn_i ( s_rstn_cluster_sync_soc ), + .clk_i ( soc_clk_i ), + .rstn_i ( soc_rstn_synced_i ), .valid_o ( s_dma_pe_irq ), .ack_o ( dma_pe_irq_ack_o ), .valid_i ( dma_pe_irq_valid_i ) ); `ifndef PULP_FPGA_EMUL edge_propagator_rx ep_pf_evt_i ( - .clk_i ( s_soc_clk ), - .rstn_i ( s_rstn_cluster_sync_soc ), + .clk_i ( soc_clk_i ), + .rstn_i ( soc_rstn_synced_i ), .valid_o ( s_pf_evt ), .ack_o ( pf_evt_ack_o ), .valid_i ( pf_evt_valid_i ) @@ -769,102 +684,61 @@ module pulp_soc import dm::*; #( .CLUSTER_ID ( FC_CORE_CLUSTER_ID ), .USE_HWPE ( USE_HWPE ) ) fc_subsystem_i ( - .clk_i ( s_soc_clk ), - .rst_ni ( s_soc_rstn ), + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), - .test_en_i ( dft_test_mode_i ), + .test_en_i ( dft_test_mode_i ), - .boot_addr_i ( s_fc_bootaddr ), + .boot_addr_i ( s_fc_bootaddr ), - .fetch_en_i ( s_fc_fetchen ), + .fetch_en_i ( s_fc_fetchen ), - .l2_data_master ( s_lint_fc_data_bus ), - .l2_instr_master ( s_lint_fc_instr_bus ), - .l2_hwpe_master ( s_lint_hwpe_bus ), - .apb_slave_eu ( s_apb_eu_bus ), - .apb_slave_hwpe ( s_apb_hwpe_bus ), - .debug_req_i ( dm_debug_req[FC_CORE_MHARTID] ), + .l2_data_master ( s_lint_fc_data_bus ), + .l2_instr_master ( s_lint_fc_instr_bus ), + .l2_hwpe_master ( s_lint_hwpe_bus ), + .apb_slave_eu ( s_apb_intrpt_ctrl_bus ), + .apb_slave_hwpe ( s_apb_hwpe_bus ), + .debug_req_i ( dm_debug_req[FC_CORE_MHARTID] ), - .event_fifo_valid_i ( s_fc_event_valid ), - .event_fifo_fulln_o ( s_fc_event_ready ), - .event_fifo_data_i ( s_fc_event_data ), - .events_i ( s_fc_events ), - .hwpe_events_o ( s_fc_hwpe_events ), + .event_fifo_valid_i ( s_fc_event_valid ), + .event_fifo_fulln_o ( s_fc_event_ready ), + .event_fifo_data_i ( s_fc_event_data ), + .interrupts_i ( s_fc_interrupts ), + .hwpe_events_o ( s_fc_hwpe_events ), - .supervisor_mode_o ( s_supervisor_mode ) - ); - - soc_clk_rst_gen i_clk_rst_gen ( - .ref_clk_i ( ref_clk_i ), - .test_clk_i ( test_clk_i ), - .sel_fll_clk_i ( s_sel_fll_clk ), - - .rstn_glob_i ( rstn_glob_i ), - .rstn_soc_sync_o ( s_soc_rstn ), - .rstn_cluster_sync_o ( s_cluster_rstn ), - - .clk_cluster_o ( s_cluster_clk ), - .test_mode_i ( dft_test_mode_i ), - .shift_enable_i ( 1'b0 ), - - .soc_fll_slave_req_i ( s_soc_fll_master.req ), - .soc_fll_slave_wrn_i ( s_soc_fll_master.wrn ), - .soc_fll_slave_add_i ( s_soc_fll_master.addr[1:0] ), - .soc_fll_slave_data_i ( s_soc_fll_master.wdata ), - .soc_fll_slave_ack_o ( s_soc_fll_master.ack ), - .soc_fll_slave_r_data_o ( s_soc_fll_master.rdata ), - .soc_fll_slave_lock_o ( s_soc_fll_master.lock ), - - .per_fll_slave_req_i ( s_per_fll_master.req ), - .per_fll_slave_wrn_i ( s_per_fll_master.wrn ), - .per_fll_slave_add_i ( s_per_fll_master.addr[1:0] ), - .per_fll_slave_data_i ( s_per_fll_master.wdata ), - .per_fll_slave_ack_o ( s_per_fll_master.ack ), - .per_fll_slave_r_data_o ( s_per_fll_master.rdata ), - .per_fll_slave_lock_o ( s_per_fll_master.lock ), - - .cluster_fll_slave_req_i ( s_cluster_fll_master.req ), - .cluster_fll_slave_wrn_i ( s_cluster_fll_master.wrn ), - .cluster_fll_slave_add_i ( s_cluster_fll_master.addr[1:0] ), - .cluster_fll_slave_data_i ( s_cluster_fll_master.wdata ), - .cluster_fll_slave_ack_o ( s_cluster_fll_master.ack ), - .cluster_fll_slave_r_data_o ( s_cluster_fll_master.rdata ), - .cluster_fll_slave_lock_o ( s_cluster_fll_master.lock ), - - .clk_soc_o ( s_soc_clk ), - .clk_per_o ( s_periph_clk ) + .supervisor_mode_o ( s_supervisor_mode ) ); soc_interconnect_wrap #( - .NR_HWPE_PORTS(NB_HWPE_PORTS), - .NR_L2_PORTS(NB_L2_BANKS), - .AXI_IN_ID_WIDTH(AXI_ID_IN_WIDTH), - .AXI_USER_WIDTH(AXI_USER_WIDTH) + .NR_HWPE_PORTS ( NB_HWPE_PORTS ), + .NR_L2_PORTS ( NB_L2_BANKS ), + .AXI_IN_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) ) i_soc_interconnect_wrap ( - .clk_i ( s_soc_clk ), - .rst_ni ( s_soc_rstn ), - .test_en_i ( dft_test_mode_i ), - .tcdm_fc_data ( s_lint_fc_data_bus ), - .tcdm_fc_instr ( s_lint_fc_instr_bus ), - .tcdm_udma_rx ( s_lint_udma_rx_bus ), - .tcdm_udma_tx ( s_lint_udma_tx_bus ), - .tcdm_debug ( s_lint_debug_bus ), - .tcdm_hwpe ( s_lint_hwpe_bus ), - .axi_master_plug ( s_data_in_bus ), - .axi_slave_plug ( s_data_out_bus ), - .apb_peripheral_bus ( s_apb_periph_bus ), - .l2_interleaved_slaves ( s_mem_l2_bus ), - .l2_private_slaves ( s_mem_l2_pri_bus ), - .boot_rom_slave ( s_mem_rom_bus ) - ); + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), + .test_en_i ( dft_test_mode_i ), + .tcdm_fc_data ( s_lint_fc_data_bus ), + .tcdm_fc_instr ( s_lint_fc_instr_bus ), + .tcdm_udma_rx ( s_lint_udma_rx_bus ), + .tcdm_udma_tx ( s_lint_udma_tx_bus ), + .tcdm_debug ( s_lint_debug_bus ), + .tcdm_hwpe ( s_lint_hwpe_bus ), + .axi_master_plug ( s_data_in_bus ), + .axi_slave_plug ( s_data_out_bus ), + .axi_lite_peripheral_bus ( s_periph_bus ), + .l2_interleaved_slaves ( s_mem_l2_bus ), + .l2_private_slaves ( s_mem_l2_pri_bus ), + .boot_rom_slave ( s_mem_rom_bus ) + ); /* Debug Subsystem */ dmi_jtag #( .IdcodeValue ( `DMI_JTAG_IDCODE ) ) i_dmi_jtag ( - .clk_i ( s_soc_clk ), - .rst_ni ( s_soc_rstn ), + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), .testmode_i ( 1'b0 ), .dmi_req_o ( jtag_dmi_req ), .dmi_req_valid_o ( jtag_req_valid ), @@ -900,14 +774,14 @@ module pulp_soc import dm::*; #( .ReadByteEnable ( 0 ) ) i_dm_top ( - .clk_i ( s_soc_clk ), - .rst_ni ( s_soc_rstn ), - .testmode_i ( 1'b0 ), - .ndmreset_o ( ), - .dmactive_o ( ), // active debug session - .debug_req_o ( dm_debug_req ), - .unavailable_i ( ~SELECTABLE_HARTS ), - .hartinfo_i ( hartinfo ), + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), + .testmode_i ( 1'b0 ), + .ndmreset_o ( ), + .dmactive_o ( ), // active debug session + .debug_req_o ( dm_debug_req ), + .unavailable_i ( ~SELECTABLE_HARTS ), + .hartinfo_i ( hartinfo ), .slave_req_i ( dm_slave_req ), .slave_we_i ( dm_slave_we ), @@ -937,6 +811,7 @@ module pulp_soc import dm::*; #( ); assign s_lint_riscv_jtag_bus.wen = ~lint_riscv_jtag_bus_master_we; + jtag_tap_top #( .IDCODE_VALUE ( `PULP_JTAG_IDCODE ) ) jtag_tap_top_i ( @@ -947,7 +822,7 @@ module pulp_soc import dm::*; #( .td_o ( jtag_tdo_o ), .test_clk_i ( 1'b0 ), - .test_rstn_i ( s_soc_rstn ), + .test_rstn_i ( soc_rstn_synced_i ), .jtag_shift_dr_o ( s_jtag_shift_dr ), .jtag_update_dr_o ( s_jtag_update_dr ), @@ -961,6 +836,8 @@ module pulp_soc import dm::*; #( .sel_fll_clk_o ( s_sel_fll_clk ) ); + assign jtag_tap_bypass_fll_clk_o = s_sel_fll_clk; + lint_jtag_wrap i_lint_jtag ( .tck_i ( jtag_tck_i ), .tdi_i ( s_jtag_axireg_tdi ), @@ -971,15 +848,15 @@ module pulp_soc import dm::*; #( .update_dr_i ( s_jtag_update_dr ), .capture_dr_i ( s_jtag_capture_dr ), .lint_select_i ( s_jtag_axireg_sel ), - .clk_i ( s_soc_clk ), - .rst_ni ( s_soc_rstn ), + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), .jtag_lint_master ( s_lint_pulp_jtag_bus ) ); tcdm_arbiter_2x1 jtag_lint_arbiter_i ( - .clk_i(s_soc_clk), - .rst_ni(s_soc_rstn), + .clk_i(soc_clk_i), + .rst_ni(soc_rstn_synced_i), .tcdm_bus_1_i(s_lint_riscv_jtag_bus), .tcdm_bus_0_i(s_lint_pulp_jtag_bus), .tcdm_bus_o(s_lint_debug_bus) @@ -989,8 +866,8 @@ module pulp_soc import dm::*; #( .PER_ADDR_WIDTH ( 32 ), .APB_ADDR_WIDTH ( 32 ) ) apb2per_newdebug_i ( - .clk_i ( s_soc_clk ), - .rst_ni ( s_soc_rstn ), + .clk_i ( soc_clk_i ), + .rst_ni ( soc_rstn_synced_i ), .PADDR ( s_apb_debug_bus.paddr ), .PWDATA ( s_apb_debug_bus.pwdata ), @@ -1013,34 +890,11 @@ module pulp_soc import dm::*; #( ); assign slave_grant = dm_slave_req; - always_ff @(posedge s_soc_clk or negedge s_soc_rstn) begin : apb2per_valid - if(~s_soc_rstn) begin + always_ff @(posedge soc_clk_i or negedge soc_rstn_synced_i) begin : apb2per_valid + if(~soc_rstn_synced_i) begin slave_valid <= 0; end else begin slave_valid <= slave_grant; end end - - //******************************************************** - //*** PAD AND GPIO CONFIGURATION SIGNALS PACK ************ - //******************************************************** - - for (genvar i = 0; i < 32; i++) begin : gen_gpio_cfg_outer - for (genvar j = 0; j < 6; j++) begin : gen_gpip_cfg_inner - assign gpio_cfg_o[j+6*i] = s_gpio_cfg[i][j]; - end - end - - for (genvar i = 0; i < 64; i++) begin : gen_pad_mux_outer - for (genvar j = 0; j < 2; j++) begin : gen_pad_mux_innter - assign pad_mux_o[j+2*i] = s_pad_mux[i][j]; - end - end - - for (genvar i = 0; i < 64; i++) begin : gen_pad_cfg_outer - for (genvar j = 0; j < 6; j++) begin : gen_pad_cfg_inner - assign pad_cfg_o[j+6*i] = s_pad_cfg[i][j]; - end - end - endmodule diff --git a/rtl/pulp_soc/soc_clk_rst_gen.sv b/rtl/pulp_soc/soc_clk_rst_gen.sv deleted file mode 100644 index c7d10c0e..00000000 --- a/rtl/pulp_soc/soc_clk_rst_gen.sv +++ /dev/null @@ -1,267 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - - -`include "pulp_soc_defines.sv" - -module soc_clk_rst_gen ( - input logic ref_clk_i, - input logic test_clk_i, - input logic rstn_glob_i, - input logic test_mode_i, - input logic sel_fll_clk_i, - input logic shift_enable_i, - input logic soc_fll_slave_req_i, - input logic soc_fll_slave_wrn_i, - input logic [1:0] soc_fll_slave_add_i, - input logic [31:0] soc_fll_slave_data_i, - output logic soc_fll_slave_ack_o, - output logic [31:0] soc_fll_slave_r_data_o, - output logic soc_fll_slave_lock_o, - - input logic per_fll_slave_req_i, - input logic per_fll_slave_wrn_i, - input logic [1:0] per_fll_slave_add_i, - input logic [31:0] per_fll_slave_data_i, - output logic per_fll_slave_ack_o, - output logic [31:0] per_fll_slave_r_data_o, - output logic per_fll_slave_lock_o, - - input logic cluster_fll_slave_req_i, - input logic cluster_fll_slave_wrn_i, - input logic [1:0] cluster_fll_slave_add_i, - input logic [31:0] cluster_fll_slave_data_i, - output logic cluster_fll_slave_ack_o, - output logic [31:0] cluster_fll_slave_r_data_o, - output logic cluster_fll_slave_lock_o, - - output logic rstn_soc_sync_o, - output logic rstn_cluster_sync_o, - - output logic clk_soc_o, - output logic clk_per_o, - output logic clk_cluster_o -); - - logic s_clk_soc; - logic s_clk_per; - logic s_clk_cluster; - - logic s_clk_fll_soc; - logic s_clk_fll_per; - logic s_clk_fll_cluster; - - logic s_rstn_soc; - - logic s_rstn_soc_sync; - logic s_rstn_cluster_sync; - - //synopsys translate_off - `ifndef SYNTHESIS - freq_meter #(.FLL_NAME("SOC_FLL"), .MAX_SAMPLE(4096)) SOC_METER (.clk(s_clk_fll_soc)); - freq_meter #(.FLL_NAME("PER_FLL"), .MAX_SAMPLE(4096)) PER_METER (.clk(s_clk_fll_per)); - freq_meter #(.FLL_NAME("CLUSTER_FLL"), .MAX_SAMPLE(4096)) CLUSTER_METER (.clk(s_clk_fll_cluster)); - `endif - //synopsys translate_on - - // currently, FLLs are not supported for FPGA emulation - `ifndef PULP_FPGA_EMUL - gf22_FLL i_fll_soc - ( - .FLLCLK ( s_clk_fll_soc ), - .FLLOE ( 1'b1 ), - .REFCLK ( ref_clk_i ), - .LOCK ( soc_fll_slave_lock_o ), - .CFGREQ ( soc_fll_slave_req_i ), - .CFGACK ( soc_fll_slave_ack_o ), - .CFGAD ( soc_fll_slave_add_i[1:0] ), - .CFGD ( soc_fll_slave_data_i ), - .CFGQ ( soc_fll_slave_r_data_o ), - .CFGWEB ( soc_fll_slave_wrn_i ), - .RSTB ( rstn_glob_i ), - .PWD ( 1'b0 ), - .RET ( 1'b0 ), - .TM ( test_mode_i ), - .TE ( shift_enable_i ), - .TD ( 1'b0 ), //TO FIX DFT - .TQ ( ), //TO FIX DFT - .JTD ( 1'b0 ), //TO FIX DFT - .JTQ ( ) //TO FIX DFT - ); - - gf22_FLL i_fll_per ( - .FLLCLK ( s_clk_fll_per ), - .FLLOE ( 1'b1 ), - .REFCLK ( ref_clk_i ), - .LOCK ( per_fll_slave_lock_o ), - .CFGREQ ( per_fll_slave_req_i ), - .CFGACK ( per_fll_slave_ack_o ), - .CFGAD ( per_fll_slave_add_i[1:0] ), - .CFGD ( per_fll_slave_data_i ), - .CFGQ ( per_fll_slave_r_data_o ), - .CFGWEB ( per_fll_slave_wrn_i ), - .RSTB ( rstn_glob_i ), - .PWD ( 1'b0 ), - .RET ( 1'b0 ), - .TM ( test_mode_i ), - .TE ( shift_enable_i ), - .TD ( 1'b0 ), //TO FIX DFT - .TQ ( ), //TO FIX DFT - .JTD ( 1'b0 ), //TO FIX DFT - .JTQ ( ) //TO FIX DFT - ); - - gf22_FLL i_fll_cluster ( - .FLLCLK ( s_clk_fll_cluster ), - .FLLOE ( 1'b1 ), - .REFCLK ( ref_clk_i ), - .LOCK ( cluster_fll_slave_lock_o ), - .CFGREQ ( cluster_fll_slave_req_i ), - .CFGACK ( cluster_fll_slave_ack_o ), - .CFGAD ( cluster_fll_slave_add_i[1:0] ), - .CFGD ( cluster_fll_slave_data_i ), - .CFGQ ( cluster_fll_slave_r_data_o ), - .CFGWEB ( cluster_fll_slave_wrn_i ), - .RSTB ( rstn_glob_i ), - .PWD ( 1'b0 ), - .RET ( 1'b0 ), - .TM ( test_mode_i ), - .TE ( shift_enable_i ), - .TD ( 1'b0 ), //TO FIX DFT - .TQ ( ), //TO FIX DFT - .JTD ( 1'b0 ), //TO FIX DFT - .JTQ ( ) //TO FIX DFT - ); - - pulp_clock_mux2 clk_mux_fll_soc_i ( - `ifdef TEST_FLL - .clk0_i ( 1'bz ), - `else - .clk0_i ( s_clk_fll_soc ), - `endif - .clk1_i ( ref_clk_i ), - .clk_sel_i ( sel_fll_clk_i ), - .clk_o ( s_clk_soc ) - ); - - pulp_clock_mux2 clk_mux_fll_per_i ( - `ifdef TEST_FLL - .clk0_i ( 1'bz ), - `else - .clk0_i ( s_clk_fll_per ), - `endif - .clk1_i ( ref_clk_i ), - .clk_sel_i ( sel_fll_clk_i ), - .clk_o ( s_clk_per ) - ); - - pulp_clock_mux2 clk_mux_fll_cluster_i ( - `ifdef TEST_FLL - .clk0_i ( 1'bz ), - `else - .clk0_i ( s_clk_fll_cluster ), - `endif - .clk1_i ( ref_clk_i ), - .clk_sel_i ( sel_fll_clk_i ), - .clk_o ( s_clk_cluster ) - ); - - `else // !`ifndef PULP_FPGA_EMUL - - // Use FPGA dependent clock generation module for both clocks - // For the FPGA port we remove the clock multiplexers since it doesn't make - // much sense to clock the circuit directly with the board reference clock - // (e.g. 200MHz for genesys2 board). - - fpga_clk_gen i_fpga_clk_gen ( - .ref_clk_i, - .rstn_glob_i, - .test_mode_i, - .shift_enable_i, - .soc_clk_o(s_clk_fll_soc), - .per_clk_o(s_clk_fll_per), - .cluster_clk_o(s_clk_cluster), - .soc_cfg_lock_o(soc_fll_slave_lock_o), - .soc_cfg_req_i(soc_fll_slave_req_i), - .soc_cfg_ack_o(soc_fll_slave_ack_o), - .soc_cfg_add_i(soc_fll_slave_add_i), - .soc_cfg_data_i(soc_fll_slave_data_i), - .soc_cfg_r_data_o(soc_fll_slave_r_data_o), - .soc_cfg_wrn_i(soc_fll_slave_wrn_i), - .per_cfg_lock_o(per_fll_slave_lock_o), - .per_cfg_req_i(per_fll_slave_req_i), - .per_cfg_ack_o(per_fll_slave_ack_o), - .per_cfg_add_i(per_fll_slave_add_i), - .per_cfg_data_i(per_fll_slave_data_i), - .per_cfg_r_data_o(per_fll_slave_r_data_o), - .per_cfg_wrn_i(per_fll_slave_wrn_i), - .cluster_cfg_lock_o(cluster_fll_slave_lock_o), - .cluster_cfg_req_i(cluster_fll_slave_req_i), - .cluster_cfg_ack_o(cluster_fll_slave_ack_o), - .cluster_cfg_add_i(cluster_fll_slave_add_i), - .cluster_cfg_data_i(cluster_fll_slave_data_i), - .cluster_cfg_r_data_o(cluster_fll_slave_r_data_o), - .cluster_cfg_wrn_i(cluster_fll_slave_wrn_i) - ); - - assign s_clk_soc = s_clk_fll_soc; - assign s_clk_cluster = s_clk_fll_cluster; - assign s_clk_per = s_clk_fll_per; - - `endif - - - - assign s_rstn_soc = rstn_glob_i; - - `ifndef PULP_FPGA_EMUL - - rstgen i_soc_rstgen ( - .clk_i ( clk_soc_o ), - .rst_ni ( s_rstn_soc ), - - .test_mode_i ( test_mode_i ), - - .rst_no ( s_rstn_soc_sync ), //to be used by logic clocked with ref clock in AO domain - .init_no ( ) //not used - ); - `else - assign s_rstn_soc_sync = s_rstn_soc; - `endif - - - `ifndef PULP_FPGA_EMUL - rstgen i_cluster_rstgen ( - .clk_i ( clk_cluster_o ), - .rst_ni ( s_rstn_soc ), - - .test_mode_i ( test_mode_i ), - - .rst_no ( s_rstn_cluster_sync ), //to be used by logic clocked with ref clock in AO domain - .init_no ( ) //not used - ); - `else - assign s_rstn_cluster_sync = s_rstn_soc; - `endif - - assign clk_soc_o = s_clk_soc; - assign clk_per_o = s_clk_per; - assign clk_cluster_o = s_clk_cluster; - - assign rstn_soc_sync_o = s_rstn_soc_sync; - assign rstn_cluster_sync_o = s_rstn_cluster_sync; - - `ifdef DO_NOT_USE_FLL - assert property ( - @(posedge clk) (soc_fll_slave_req_i == 1'b0 && per_fll_slave_req_i == 1'b0) ) else $display("There should be no FLL request (%t)", $time); - `endif - - -endmodule diff --git a/rtl/pulp_soc/soc_interconnect.sv b/rtl/pulp_soc/soc_interconnect.sv index f4dce76f..4a732cbc 100644 --- a/rtl/pulp_soc/soc_interconnect.sv +++ b/rtl/pulp_soc/soc_interconnect.sv @@ -127,8 +127,8 @@ module soc_interconnect //The tcdm demux will route all transaction that do not match any addr rule to port 0 (which we connect to an //error slave) tcdm_demux #( - .NR_OUTPUTS(2), - .NR_ADDR_MAP_RULES(NR_ADDR_RULES_SLAVE_PORTS_INTLVD) + .NR_OUTPUTS ( 2 ), + .NR_ADDR_MAP_RULES ( NR_ADDR_RULES_SLAVE_PORTS_INTLVD ) ) i_err_demux( .clk_i, .rst_ni, @@ -183,17 +183,17 @@ module soc_interconnect end interleaved_crossbar #( - .NR_MASTER_PORTS(NR_MASTER_PORTS+NR_MASTER_PORTS_INTERLEAVED_ONLY), - .NR_SLAVE_PORTS(NR_SLAVE_PORTS_INTERLEAVED) - ) i_interleaved_xbar( - // Interfaces - .master_ports (interleaved_masters), - .slave_ports (interleaved_slaves), - // Inputs - .clk_i, - .rst_ni, - .test_en_i - ); + .NR_MASTER_PORTS ( NR_MASTER_PORTS+NR_MASTER_PORTS_INTERLEAVED_ONLY ), + .NR_SLAVE_PORTS ( NR_SLAVE_PORTS_INTERLEAVED ) + ) i_interleaved_xbar( + // Interfaces + .master_ports ( interleaved_masters ), + .slave_ports ( interleaved_slaves ), + // Inputs + .clk_i, + .rst_ni, + .test_en_i + ); ///////////////////////// // Contiguous Crossbar // @@ -208,20 +208,20 @@ module soc_interconnect //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// XBAR_TCDM_BUS error_slave(); contiguous_crossbar #( - .NR_MASTER_PORTS(NR_MASTER_PORTS), - .NR_SLAVE_PORTS(NR_SLAVE_PORTS_CONTIG), - .NR_ADDR_RULES(NR_ADDR_RULES_SLAVE_PORTS_CONTIG) - ) i_contiguous_xbar( - // Interfaces - .master_ports (l2_demux_2_contiguous_xbar), - .slave_ports (contiguous_slaves), - .error_port (error_slave), - .addr_rules (addr_space_contiguous), - // Inputs - .clk_i, - .rst_ni, - .test_en_i - ); + .NR_MASTER_PORTS ( NR_MASTER_PORTS ), + .NR_SLAVE_PORTS ( NR_SLAVE_PORTS_CONTIG ), + .NR_ADDR_RULES ( NR_ADDR_RULES_SLAVE_PORTS_CONTIG ) + ) i_contiguous_xbar( + // Interfaces + .master_ports ( l2_demux_2_contiguous_xbar ), + .slave_ports ( contiguous_slaves ), + .error_port ( error_slave ), + .addr_rules ( addr_space_contiguous ), + // Inputs + .clk_i, + .rst_ni, + .test_en_i + ); //Error Slave // This dummy slave is responsible to generate the buserror described above tcdm_error_slave #( @@ -230,7 +230,7 @@ module soc_interconnect .clk_i, .rst_ni, .slave(error_slave) - ); + ); //////////////////////// @@ -239,21 +239,23 @@ module soc_interconnect // Instantiate a TCDM to AXI protocol converter for each master port from the L2 demultiplexer. The converter // // converts one 32-bit TCDM port to one 32-bit AXI port. // //////////////////////////////////////////////////////////////////////////////////////////////////////////////// - AXI_BUS #(.AXI_ADDR_WIDTH(32), - .AXI_DATA_WIDTH(32), - .AXI_ID_WIDTH(AXI_MASTER_ID_WIDTH), - .AXI_USER_WIDTH(AXI_USER_WIDTH) - ) axi_bridge_2_axi_xbar[NR_MASTER_PORTS](); + AXI_BUS #( + .AXI_ADDR_WIDTH ( 32 ), + .AXI_DATA_WIDTH ( 32 ), + .AXI_ID_WIDTH ( AXI_MASTER_ID_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) axi_bridge_2_axi_xbar[NR_MASTER_PORTS](); + for (genvar i = 0; i < NR_MASTER_PORTS; i++) begin : gen_tcdm_2_axi_bridge lint2axi_wrap #( - .AXI_ID_WIDTH(AXI_MASTER_ID_WIDTH), - .AXI_USER_WIDTH(AXI_USER_WIDTH) - ) i_lint2axi_bridge ( - .clk_i, - .rst_ni, - .master(l2_demux_2_axi_bridge[i]), - .slave(axi_bridge_2_axi_xbar[i]) - ); + .AXI_ID_WIDTH ( AXI_MASTER_ID_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) i_lint2axi_bridge ( + .clk_i, + .rst_ni, + .master ( l2_demux_2_axi_bridge[i] ), + .slave ( axi_bridge_2_axi_xbar[i] ) + ); end @@ -267,33 +269,35 @@ module soc_interconnect //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// localparam xbar_cfg_t AXI_XBAR_CFG = '{ - NoSlvPorts: NR_MASTER_PORTS, - NoMstPorts: NR_AXI_SLAVE_PORTS, - MaxMstTrans: 1, //The TCDM ports do not support - //outstanding transactiions anyways - MaxSlvTrans: 4, //Allow up to 4 in-flight transactions - //per slave port - FallThrough: 1, //Use the reccomended default config - LatencyMode: axi_pkg::CUT_MST_AX | axi_pkg::MuxW, - AxiIdWidthSlvPorts: AXI_MASTER_ID_WIDTH, - AxiIdUsedSlvPorts: AXI_MASTER_ID_WIDTH, - AxiAddrWidth: BUS_ADDR_WIDTH, - AxiDataWidth: BUS_DATA_WIDTH, - NoAddrRules: NR_ADDR_RULES_AXI_SLAVE_PORTS, - UniqueIds: 0 - }; + NoSlvPorts: NR_MASTER_PORTS, + NoMstPorts: NR_AXI_SLAVE_PORTS, + MaxMstTrans: 1, //The TCDM ports do not support + //outstanding transactiions anyways + MaxSlvTrans: 4, //Allow up to 4 in-flight transactions + //per slave port + FallThrough: 1, //Use the reccomended default config + LatencyMode: axi_pkg::CUT_MST_AX | axi_pkg::MuxW, + AxiIdWidthSlvPorts: AXI_MASTER_ID_WIDTH, + AxiIdUsedSlvPorts: AXI_MASTER_ID_WIDTH, + UniqueIds: 0, + AxiAddrWidth: BUS_ADDR_WIDTH, + AxiDataWidth: BUS_DATA_WIDTH, + NoAddrRules: NR_ADDR_RULES_AXI_SLAVE_PORTS + }; //Reverse interface array ordering since axi_xbar uses big-endian ordering of the arrays - AXI_BUS #(.AXI_ADDR_WIDTH(32), - .AXI_DATA_WIDTH(32), - .AXI_ID_WIDTH(AXI_MASTER_ID_WIDTH), - .AXI_USER_WIDTH(AXI_USER_WIDTH) - ) axi_bridge_2_axi_xbar_reversed[NR_MASTER_PORTS-1:0](); - AXI_BUS #(.AXI_ADDR_WIDTH(32), - .AXI_DATA_WIDTH(32), - .AXI_ID_WIDTH(AXI_SLAVE_ID_WIDTH), - .AXI_USER_WIDTH(AXI_USER_WIDTH) - ) axi_slaves_reversed[NR_AXI_SLAVE_PORTS-1:0](); + AXI_BUS #( + .AXI_ADDR_WIDTH (32 ), + .AXI_DATA_WIDTH (32 ), + .AXI_ID_WIDTH (AXI_MASTER_ID_WIDTH ), + .AXI_USER_WIDTH (AXI_USER_WIDTH ) + ) axi_bridge_2_axi_xbar_reversed[NR_MASTER_PORTS-1:0](); + AXI_BUS #( + .AXI_ADDR_WIDTH ( 32 ), + .AXI_DATA_WIDTH ( 32 ), + .AXI_ID_WIDTH ( AXI_SLAVE_ID_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) axi_slaves_reversed[NR_AXI_SLAVE_PORTS-1:0](); for (genvar i = 0; i < NR_MASTER_PORTS; i++) begin `AXI_ASSIGN(axi_bridge_2_axi_xbar_reversed[i], axi_bridge_2_axi_xbar[i]) @@ -303,20 +307,20 @@ module soc_interconnect `AXI_ASSIGN(axi_slaves[i], axi_slaves_reversed[i]) end - axi_xbar_intf #( - .AXI_USER_WIDTH(AXI_USER_WIDTH), - .Cfg(AXI_XBAR_CFG), - .rule_t(addr_map_rule_t) - ) i_axi_xbar ( - .clk_i, - .rst_ni, - .test_i(test_en_i), - .slv_ports(axi_bridge_2_axi_xbar_reversed), - .mst_ports(axi_slaves_reversed), - .addr_map_i(addr_space_axi), - .en_default_mst_port_i('0), - .default_mst_port_i('0) - ); + axi_xbar_intf # ( + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .Cfg ( AXI_XBAR_CFG ), + .rule_t ( addr_map_rule_t ) + ) i_axi_xbar ( + .clk_i, + .rst_ni, + .test_i ( test_en_i ), + .slv_ports ( axi_bridge_2_axi_xbar_reversed ), + .mst_ports ( axi_slaves_reversed ), + .addr_map_i ( addr_space_axi ), + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) + ); endmodule : soc_interconnect diff --git a/rtl/pulp_soc/soc_interconnect_wrap.sv b/rtl/pulp_soc/soc_interconnect_wrap.sv index 6218f480..ca84532f 100644 --- a/rtl/pulp_soc/soc_interconnect_wrap.sv +++ b/rtl/pulp_soc/soc_interconnect_wrap.sv @@ -52,8 +52,9 @@ module soc_interconnect_wrap XBAR_TCDM_BUS.Slave tcdm_debug, //Debug access port from either the legacy or the riscv-debug unit XBAR_TCDM_BUS.Slave tcdm_hwpe[NR_HWPE_PORTS], //Hardware Processing Element ports AXI_BUS.Slave axi_master_plug, // Normaly used for cluster -> SoC communication - AXI_BUS.Master axi_slave_plug, // Normaly used for SoC -> cluster communication - APB_BUS.Master apb_peripheral_bus, // Connects to all the SoC Peripherals + AXI_BUS.Master axi_slave_plug, // Normaly used for SoC -> + // cluster communication + AXI_LITE.Master axi_lite_peripheral_bus, // Connects to all the SoC Peripherals XBAR_TCDM_BUS.Master l2_interleaved_slaves[NR_L2_PORTS], // Connects to the interleaved memory banks XBAR_TCDM_BUS.Master l2_private_slaves[2], // Connects to core-private memory banks XBAR_TCDM_BUS.Master boot_rom_slave //Connects to the bootrom @@ -171,104 +172,78 @@ module soc_interconnect_wrap `TCDM_ASSIGN_INTF(l2_private_slaves[1], contiguous_slaves[1]) `TCDM_ASSIGN_INTF(boot_rom_slave, contiguous_slaves[2]) - AXI_BUS #(.AXI_ADDR_WIDTH(32), - .AXI_DATA_WIDTH(32), - .AXI_ID_WIDTH(pkg_soc_interconnect::AXI_ID_OUT_WIDTH), - .AXI_USER_WIDTH(AXI_USER_WIDTH) - ) axi_slaves[2](); + AXI_BUS #( + .AXI_ADDR_WIDTH ( 32 ), + .AXI_DATA_WIDTH ( 32 ), + .AXI_ID_WIDTH ( pkg_soc_interconnect::AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) axi_slaves[2](); + `AXI_ASSIGN(axi_slave_plug, axi_slaves[0]) `AXI_ASSIGN(axi_to_axi_lite_bridge, axi_slaves[1]) //Interconnect instantiation soc_interconnect #( - .NR_MASTER_PORTS(pkg_soc_interconnect::NR_TCDM_MASTER_PORTS), // FC instructions, FC data, uDMA RX, uDMA TX, debug access, 4 four 64-bit - // axi plug - .NR_MASTER_PORTS_INTERLEAVED_ONLY(NR_HWPE_PORTS), // HWPEs (PULP accelerators) only have access - // to the interleaved memory region - .NR_ADDR_RULES_L2_DEMUX(NR_RULES_L2_DEMUX), - .NR_SLAVE_PORTS_INTERLEAVED(NR_L2_PORTS), // Number of interleaved memory banks - .NR_ADDR_RULES_SLAVE_PORTS_INTLVD(NR_RULES_INTERLEAVED_REGION), - .NR_SLAVE_PORTS_CONTIG(3), // Bootrom + number of private memory banks (normally 1 for - // programm instructions and 1 for programm stack ) - .NR_ADDR_RULES_SLAVE_PORTS_CONTIG(NR_RULES_CONTIG_CROSSBAR), - .NR_AXI_SLAVE_PORTS(2), // 1 for AXI to cluster, 1 for SoC peripherals (converted to APB) - .NR_ADDR_RULES_AXI_SLAVE_PORTS(NR_RULES_AXI_CROSSBAR), - .AXI_MASTER_ID_WIDTH(1), //Doesn't need to be changed. All axi masters in the current - //interconnect come from a TCDM protocol converter and thus do not have and AXI ID. - //However, the unerlaying IPs do not support an ID lenght of 0, thus we use 1. - .AXI_USER_WIDTH(AXI_USER_WIDTH) - ) i_soc_interconnect ( - .clk_i, - .rst_ni, - .test_en_i, - .master_ports(master_ports), - .master_ports_interleaved_only(tcdm_hwpe), - .addr_space_l2_demux(L2_DEMUX_RULES), - .addr_space_interleaved(INTERLEAVED_ADDR_SPACE), - .interleaved_slaves(l2_interleaved_slaves), - .addr_space_contiguous(CONTIGUOUS_CROSSBAR_RULES), - .contiguous_slaves(contiguous_slaves), - .addr_space_axi(AXI_CROSSBAR_RULES), - .axi_slaves(axi_slaves) - ); + // FC instructions, FC data, uDMA RX, uDMA TX, debug access, 4 four 64-bit + // axi plug + .NR_MASTER_PORTS ( pkg_soc_interconnect::NR_TCDM_MASTER_PORTS ), + // HWPEs ( PULP accelerators ) only have access to the interleaved memory + // region + .NR_MASTER_PORTS_INTERLEAVED_ONLY ( NR_HWPE_PORTS ), + .NR_ADDR_RULES_L2_DEMUX ( NR_RULES_L2_DEMUX ), + // Number of interleaved memory banks + .NR_SLAVE_PORTS_INTERLEAVED ( NR_L2_PORTS ), + .NR_ADDR_RULES_SLAVE_PORTS_INTLVD ( NR_RULES_INTERLEAVED_REGION ), + // Bootrom + number of private memory banks + // ( normally 1 for programm instructions and 1 for programm stack ) + .NR_SLAVE_PORTS_CONTIG ( 3 ), + .NR_ADDR_RULES_SLAVE_PORTS_CONTIG ( NR_RULES_CONTIG_CROSSBAR ), + // 1 for AXI to cluster, 1 for SoC peripherals ( converted to APB ) + .NR_AXI_SLAVE_PORTS ( 2 ), + .NR_ADDR_RULES_AXI_SLAVE_PORTS ( NR_RULES_AXI_CROSSBAR ), + // Doesn't need to be changed. All axi masters in the current interconnect + // come from a TCDM protocol converter and thus do not have and AXI ID. + // However, the unerlaying IPs do not support an ID lenght of 0, thus we + // use 1. + .AXI_MASTER_ID_WIDTH ( 1 ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + ) i_soc_interconnect ( + .clk_i, + .rst_ni, + .test_en_i, + .master_ports ( master_ports ), + .master_ports_interleaved_only ( tcdm_hwpe ), + .addr_space_l2_demux ( L2_DEMUX_RULES ), + .addr_space_interleaved ( INTERLEAVED_ADDR_SPACE ), + .interleaved_slaves ( l2_interleaved_slaves ), + .addr_space_contiguous ( CONTIGUOUS_CROSSBAR_RULES ), + .contiguous_slaves ( contiguous_slaves ), + .addr_space_axi ( AXI_CROSSBAR_RULES ), + .axi_slaves ( axi_slaves ) + ); //////////////////////// // AXI4 to APB Bridge // - /////////////////////////////////////////////////////////////////////////////////////////// - // We do the conversion in two steps: We convert AXI4 to AXI4 lite and from there to APB // - /////////////////////////////////////////////////////////////////////////////////////////// - - AXI_LITE #( - .AXI_ADDR_WIDTH(32), - .AXI_DATA_WIDTH(32)) axi_lite_to_apb_bridge(); + ////////////////////////////////////////////////////////////////////////////// + // We do the conversion in two steps: We convert AXI4 to AXI4 lite and from // + // there to APB within the soc_peripherals module // + ////////////////////////////////////////////////////////////////////////////// axi_to_axi_lite_intf #( - .AXI_ADDR_WIDTH(32), - .AXI_DATA_WIDTH(32), - .AXI_ID_WIDTH(pkg_soc_interconnect::AXI_ID_OUT_WIDTH), - .AXI_USER_WIDTH(AXI_USER_WIDTH), - .AXI_MAX_WRITE_TXNS(1), - .AXI_MAX_READ_TXNS(1), - .FALL_THROUGH(1) - ) i_axi_to_axi_lite ( - .clk_i, - .rst_ni, - .testmode_i(test_en_i), - .slv(axi_to_axi_lite_bridge), - .mst(axi_lite_to_apb_bridge) - ); - - // The AXI-Lite to APB bridge is capable of connecting one AXI to multiple APB ports using address mapping rules. - // We do not use this feature and just supply a default rule that matches everything in the peripheral region - - localparam addr_map_rule_t [0:0] APB_BRIDGE_RULES = '{ - '{ idx: 0, start_addr: `SOC_MEM_MAP_PERIPHERALS_START_ADDR, end_addr: `SOC_MEM_MAP_PERIPHERALS_END_ADDR}}; - - axi_lite_to_apb_intf #( - .NoApbSlaves(1), - .NoRules(1), - .AddrWidth(32), - .DataWidth(32), - .PipelineRequest(1'b0), - .PipelineResponse(1'b0), - .rule_t(addr_map_rule_t) - ) i_axi_lite_to_apb ( - .clk_i, - .rst_ni, - .slv(axi_lite_to_apb_bridge), - .paddr_o(apb_peripheral_bus.paddr), - .pprot_o(), - .pselx_o(apb_peripheral_bus.psel), - .penable_o(apb_peripheral_bus.penable), - .pwrite_o(apb_peripheral_bus.pwrite), - .pwdata_o(apb_peripheral_bus.pwdata), - .pstrb_o(), - .pready_i(apb_peripheral_bus.pready), - .prdata_i(apb_peripheral_bus.prdata), - .pslverr_i(apb_peripheral_bus.pslverr), - .addr_map_i(APB_BRIDGE_RULES) - ); - + .AXI_ADDR_WIDTH ( 32 ), + .AXI_DATA_WIDTH ( 32 ), + .AXI_ID_WIDTH ( pkg_soc_interconnect::AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_MAX_WRITE_TXNS ( 1 ), + .AXI_MAX_READ_TXNS ( 1 ), + .FALL_THROUGH ( 1 ) + ) i_axi_to_axi_lite ( + .clk_i, + .rst_ni, + .testmode_i ( test_en_i ), + .slv ( axi_to_axi_lite_bridge ), + .mst ( axi_lite_peripheral_bus ) + ); endmodule : soc_interconnect_wrap diff --git a/rtl/pulp_soc/soc_peripherals.sv b/rtl/pulp_soc/soc_peripherals.sv index 36ca84e7..fdc40083 100644 --- a/rtl/pulp_soc/soc_peripherals.sv +++ b/rtl/pulp_soc/soc_peripherals.sv @@ -8,32 +8,37 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -`include "pulp_soc_defines.sv" - -module soc_peripherals #( +`include "soc_mem_map.svh" +`include "apb/typedef.svh" +`include "apb/assign.svh" +`include "axi/typedef.svh" +`include "axi/assign.svh" +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + +module soc_peripherals + import pkg_soc_interconnect::addr_map_rule_t; +#( parameter MEM_ADDR_WIDTH = 13, parameter APB_ADDR_WIDTH = 32, parameter APB_DATA_WIDTH = 32, parameter NB_CORES = 4, parameter NB_CLUSTERS = 0, parameter EVNT_WIDTH = 8, - parameter NGPIO = 64, - parameter NPAD = 64, - parameter NBIT_PADCFG = 4, - parameter NBIT_PADMUX = 2, - parameter N_UART = 1, - parameter N_SPI = 1, - parameter N_I2C = 2, - parameter SIM_STDOUT = 1 + parameter SIM_STDOUT = 1, + localparam NGPIO = gpio_reg_pkg::GPIOCount // Have a look at the + // README in the GPIO repo in order to change + // the number of GPIOs. ) ( input logic clk_i, - input logic periph_clk_i, input logic rst_ni, + input logic periph_clk_i, + input logic periph_rstn_i, //check the reset - input logic ref_clk_i, input logic slow_clk_i, + input logic slow_rstn_i, - input logic sel_fll_clk_i, + input logic sel_pll_clk_i, input logic dft_test_mode_i, input logic dft_cg_enable_i, output logic [31:0] fc_bootaddr_o, @@ -50,107 +55,52 @@ module soc_peripherals #( // SLAVE PORTS // APB SLAVE PORT - APB_BUS.Slave apb_slave, - APB_BUS.Master apb_eu_master, - APB_BUS.Master apb_hwpe_master, - APB_BUS.Master apb_debug_master, + AXI_LITE.Slave axi_lite_slave, + APB.Master apb_intrpt_ctrl_master, + APB.Master apb_hwpe_master, + APB.Master apb_debug_master, + APB.Master apb_chip_ctrl_master, // FABRIC CONTROLLER MASTER REFILL PORT XBAR_TCDM_BUS.Master l2_rx_master, XBAR_TCDM_BUS.Master l2_tx_master, - // MASTER PORT TO SOC FLL - FLL_BUS.out soc_fll_master, - // MASTER PORT TO PER FLL - FLL_BUS.out per_fll_master, - // MASTER PORT TO CLUSTER FLL - FLL_BUS.out cluster_fll_master, -/* - input logic jtag_req_valid_i, - output logic debug_req_ready_o, - input logic jtag_resp_ready_i, - output logic jtag_resp_valid_o, - input dm::dmi_req_t jtag_dmi_req_i, - output dm::dmi_resp_t debug_resp_o, - output logic ndmreset_o, - output logic dm_debug_req_o, -*/ + input logic dma_pe_evt_i, input logic dma_pe_irq_i, input logic pf_evt_i, input logic [1:0] fc_hwpe_events_i, - output logic [31:0] fc_events_o, - - input logic [NGPIO-1:0] gpio_in, - output logic [NGPIO-1:0] gpio_out, - output logic [NGPIO-1:0] gpio_dir, - output logic [NGPIO-1:0][NBIT_PADCFG-1:0] gpio_padcfg, - - output logic [NPAD-1:0][NBIT_PADMUX-1:0] pad_mux_o, - output logic [NPAD-1:0][NBIT_PADCFG-1:0] pad_cfg_o, + output logic [31:0] fc_interrupts_o, output logic [3:0] timer_ch0_o, output logic [3:0] timer_ch1_o, output logic [3:0] timer_ch2_o, output logic [3:0] timer_ch3_o, - //CAMERA - input logic cam_clk_i, - input logic [7:0] cam_data_i, - input logic cam_hsync_i, - input logic cam_vsync_i, - - //UART - // output logic [N_UART-1:0] uart_tx, - // input logic [N_UART-1:0] uart_rx, - output logic uart_tx, - input logic uart_rx, - - - //I2C - input logic [N_I2C-1:0] i2c_scl_i, - output logic [N_I2C-1:0] i2c_scl_o, - output logic [N_I2C-1:0] i2c_scl_oe_o, - input logic [N_I2C-1:0] i2c_sda_i, - output logic [N_I2C-1:0] i2c_sda_o, - output logic [N_I2C-1:0] i2c_sda_oe_o, - - //I2S - input logic i2s_slave_sd0_i, - input logic i2s_slave_sd1_i, - input logic i2s_slave_ws_i, - output logic i2s_slave_ws_o, - output logic i2s_slave_ws_oe, - input logic i2s_slave_sck_i, - output logic i2s_slave_sck_o, - output logic i2s_slave_sck_oe, - - //SPI - output logic [N_SPI-1:0] spi_clk_o, - output logic [N_SPI-1:0][3:0] spi_csn_o, - output logic [N_SPI-1:0][3:0] spi_oen_o, - output logic [N_SPI-1:0][3:0] spi_sdo_o, - input logic [N_SPI-1:0][3:0] spi_sdi_i, - - //SDIO - output logic sdclk_o, - output logic sdcmd_o, - input logic sdcmd_i, - output logic sdcmd_oen_o, - output logic [3:0] sddata_o, - input logic [3:0] sddata_i, - output logic [3:0] sddata_oen_o, - - // HYPERBUS - output logic [1:0] hyper_cs_no, - output logic hyper_ck_o, - output logic hyper_ck_no, - output logic [1:0] hyper_rwds_o, - input logic hyper_rwds_i, - output logic [1:0] hyper_rwds_oe_o, - input logic [15:0] hyper_dq_i, - output logic [15:0] hyper_dq_o, - output logic [1:0] hyper_dq_oe_o, - output logic hyper_reset_no, + // uDMA Connections + // UART + output uart_pkg::uart_to_pad_t [udma_cfg_pkg::N_UART-1:0] uart_to_pad_o, + input uart_pkg::pad_to_uart_t [udma_cfg_pkg::N_UART-1:0] pad_to_uart_i, + // I2C + output i2c_pkg::i2c_to_pad_t [udma_cfg_pkg::N_I2C-1:0] i2c_to_pad_o, + input i2c_pkg::pad_to_i2c_t [udma_cfg_pkg::N_I2C-1:0] pad_to_i2c_i, + // SDIO + output sdio_pkg::sdio_to_pad_t [udma_cfg_pkg::N_SDIO-1:0] sdio_to_pad_o, + input sdio_pkg::pad_to_sdio_t [udma_cfg_pkg::N_SDIO-1:0] pad_to_sdio_i, + // I2S + output i2s_pkg::i2s_to_pad_t [udma_cfg_pkg::N_I2S-1:0] i2s_to_pad_o, + input i2s_pkg::pad_to_i2s_t [udma_cfg_pkg::N_I2S-1:0] pad_to_i2s_i, + // QSPI + output qspi_pkg::qspi_to_pad_t [udma_cfg_pkg::N_QSPIM-1:0] qspi_to_pad_o, + input qspi_pkg::pad_to_qspi_t [udma_cfg_pkg::N_QSPIM-1:0] pad_to_qspi_i, + // CPI + input cpi_pkg::pad_to_cpi_t [udma_cfg_pkg::N_CPI-1:0] pad_to_cpi_i, + // HYPER + output hyper_pkg::hyper_to_pad_t [udma_cfg_pkg::N_HYPER-1:0] hyper_to_pad_o, + input hyper_pkg::pad_to_hyper_t [udma_cfg_pkg::N_HYPER-1:0] pad_to_hyper_i, + // GPIO + input logic [NGPIO-1:0] gpio_i, + output logic [NGPIO-1:0] gpio_o, + output logic [NGPIO-1:0] gpio_tx_en_o, output logic [EVNT_WIDTH-1:0] cl_event_data_o, @@ -160,35 +110,23 @@ module soc_peripherals #( output logic fc_event_valid_o, input logic fc_event_ready_i, - output logic cluster_pow_o, - output logic cluster_byp_o, // bypass cluster - output logic [63:0] cluster_boot_addr_o, - output logic cluster_fetch_enable_o, - output logic cluster_rstn_o, - output logic cluster_irq_o + output logic cluster_rstn_req_o ); - APB_BUS s_fll_bus (); - - APB_BUS s_gpio_bus (); - APB_BUS s_udma_bus (); - APB_BUS s_soc_ctrl_bus (); - APB_BUS s_adv_timer_bus (); - APB_BUS s_soc_evnt_gen_bus (); - APB_BUS s_stdout_bus (); - APB_BUS s_apb_timer_bus (); + //---------- Wiring Signals and internal parameters ---------- localparam UDMA_EVENTS = 16*8; - logic [31:0] s_gpio_sync; + logic [NGPIO-1:0] s_gpio_sync; logic s_sel_hyper_axi; - logic s_gpio_event ; - logic [1:0] s_spim_event ; - logic s_uart_event ; - logic s_i2c_event ; - logic s_i2s_event ; - logic s_i2s_cam_event ; + logic s_gpio_global_interrupt ; + logic [NGPIO-1:0] s_gpio_pin_level_interrupt; + logic [1:0] s_spim_event ; + logic s_uart_event ; + logic s_i2c_event ; + logic s_i2s_event ; + logic s_i2s_cam_event ; logic [3:0] s_adv_timer_events; logic [1:0] s_fc_hp_events; @@ -202,52 +140,57 @@ module soc_peripherals #( logic [7:0] s_pr_event_data ; logic s_pr_event_ready; - logic [UDMA_EVENTS-1:0] s_udma_events; - logic [ 159:0] s_events; + logic [31:0][3:0] s_udma_events; + logic [159:0] s_events; logic s_timer_in_lo_event; logic s_timer_in_hi_event; + //-------------------- Events Assignments -------------------- + assign s_events[UDMA_EVENTS-1:0] = s_udma_events; assign s_events[135] = s_adv_timer_events[0]; assign s_events[136] = s_adv_timer_events[1]; assign s_events[137] = s_adv_timer_events[2]; assign s_events[138] = s_adv_timer_events[3]; - assign s_events[139] = s_gpio_event; + assign s_events[139] = s_gpio_global_interrupt; assign s_events[140] = fc_hwpe_events_i[0]; assign s_events[141] = fc_hwpe_events_i[1]; assign s_events[159:142] = '0; - assign fc_events_o[7:0] = 8'h0; //RESERVED for sw events - assign fc_events_o[8] = dma_pe_evt_i; - assign fc_events_o[9] = dma_pe_irq_i; - assign fc_events_o[10] = s_timer_lo_event; - assign fc_events_o[11] = s_timer_hi_event; - assign fc_events_o[12] = pf_evt_i; - assign fc_events_o[13] = 1'b0; - assign fc_events_o[14] = s_ref_rise_event | s_ref_fall_event; - assign fc_events_o[15] = s_gpio_event; - assign fc_events_o[16] = 1'b0; - assign fc_events_o[17] = s_adv_timer_events[0]; - assign fc_events_o[18] = s_adv_timer_events[1]; - assign fc_events_o[19] = s_adv_timer_events[2]; - assign fc_events_o[20] = s_adv_timer_events[3]; - assign fc_events_o[21] = 1'b0; - assign fc_events_o[22] = 1'b0; - assign fc_events_o[23] = 1'b0; - assign fc_events_o[24] = 1'b0; - assign fc_events_o[25] = 1'b0; - assign fc_events_o[26] = 1'b0; // RESERVED for soc event FIFO + //------------------ Interrupt Assignments ------------------ + assign fc_interrupts_o[7:0] = 8'h0; //RESERVED for sw events + assign fc_interrupts_o[8] = dma_pe_evt_i; + assign fc_interrupts_o[9] = dma_pe_irq_i; + assign fc_interrupts_o[10] = s_timer_lo_event; + assign fc_interrupts_o[11] = s_timer_hi_event; + assign fc_interrupts_o[12] = pf_evt_i; + assign fc_interrupts_o[13] = 1'b0; + assign fc_interrupts_o[14] = s_ref_rise_event | s_ref_fall_event; + assign fc_interrupts_o[15] = s_gpio_global_interrupt; + assign fc_interrupts_o[16] = 1'b0; + assign fc_interrupts_o[17] = s_adv_timer_events[0]; + assign fc_interrupts_o[18] = s_adv_timer_events[1]; + assign fc_interrupts_o[19] = s_adv_timer_events[2]; + assign fc_interrupts_o[20] = s_adv_timer_events[3]; + assign fc_interrupts_o[21] = 1'b0; + assign fc_interrupts_o[22] = 1'b0; + assign fc_interrupts_o[23] = 1'b0; + assign fc_interrupts_o[24] = 1'b0; + assign fc_interrupts_o[25] = 1'b0; + assign fc_interrupts_o[26] = 1'b0; // RESERVED for soc event FIFO // (many events get implicitely muxed into // this interrupt. A user that gets such an // interrupt has to check the event unit's // registers to see what happened) - assign fc_events_o[27] = 1'b0; - assign fc_events_o[28] = 1'b0; - assign fc_events_o[29] = s_fc_err_events; - assign fc_events_o[30] = s_fc_hp_events[0]; - assign fc_events_o[31] = s_fc_hp_events[1]; - + assign fc_interrupts_o[27] = 1'b0; + assign fc_interrupts_o[28] = 1'b0; + assign fc_interrupts_o[29] = s_fc_err_events; + assign fc_interrupts_o[30] = s_fc_hp_events[0]; + assign fc_interrupts_o[31] = s_fc_hp_events[1]; + + // Synchronizer to generate synchronous ref_clk rise an fall events (used as + // interrupt 14) pulp_sync_wedge i_ref_clk_sync ( .clk_i ( clk_i ), .rstn_i ( rst_ni ), @@ -267,82 +210,83 @@ module soc_peripherals #( // ██║ ███████╗██║ ██║██║██║ ██║ ██║ ██████╔╝╚██████╔╝███████║ ╚███╔███╔╝██║ ██║██║ ██║██║ // // ╚═╝ ╚══════╝╚═╝ ╚═╝╚═╝╚═╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚══════╝ ╚══╝╚══╝ ╚═╝ ╚═╝╚═╝ ╚═╝╚═╝ // //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - periph_bus_wrap #( - .APB_ADDR_WIDTH ( 32 ), - .APB_DATA_WIDTH ( 32 ) - ) periph_bus_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .apb_slave ( apb_slave ), - - .fll_master ( s_fll_bus ), - .gpio_master ( s_gpio_bus ), - .udma_master ( s_udma_bus ), - .soc_ctrl_master ( s_soc_ctrl_bus ), - .adv_timer_master ( s_adv_timer_bus ), - .soc_evnt_gen_master ( s_soc_evnt_gen_bus ), - .eu_master ( apb_eu_master ), - .mmap_debug_master ( apb_debug_master ), - .hwpe_master ( apb_hwpe_master ), - .timer_master ( s_apb_timer_bus ), - .stdout_master ( s_stdout_bus ) - ); - ///////////////////////////////////////////////////////////////////////// - // █████╗ ██████╗ ██████╗ ███████╗██╗ ██╗ ██╗███████╗ // - // ██╔══██╗██╔══██╗██╔══██╗ ██╔════╝██║ ██║ ██║██╔════╝ // - // ███████║██████╔╝██████╔╝ █████╗ ██║ ██║ ██║█████╗ // - // ██╔══██║██╔═══╝ ██╔══██╗ ██╔══╝ ██║ ██║ ██║██╔══╝ // - // ██║ ██║██║ ██████╔╝ ██║ ███████╗███████╗ ██║██║ // - // ╚═╝ ╚═╝╚═╝ ╚═════╝ ╚═╝ ╚══════╝╚══════╝ ╚═╝╚═╝ // - ///////////////////////////////////////////////////////////////////////// - apb_fll_if #(.APB_ADDR_WIDTH(APB_ADDR_WIDTH)) apb_fll_if_i ( - .HCLK ( clk_i ), - .HRESETn ( rst_ni ), - - .PADDR ( s_fll_bus.paddr ), - .PWDATA ( s_fll_bus.pwdata ), - .PWRITE ( s_fll_bus.pwrite ), - .PSEL ( s_fll_bus.psel ), - .PENABLE ( s_fll_bus.penable ), - .PRDATA ( s_fll_bus.prdata ), - .PREADY ( s_fll_bus.pready ), - .PSLVERR ( s_fll_bus.pslverr ), - - .fll1_req_o ( soc_fll_master.req ), - .fll1_wrn_o ( soc_fll_master.wrn ), - .fll1_add_o ( soc_fll_master.addr[1:0] ), - .fll1_data_o ( soc_fll_master.wdata ), - .fll1_ack_i ( soc_fll_master.ack ), - .fll1_r_data_i ( soc_fll_master.rdata ), - .fll1_lock_i ( soc_fll_master.lock ), - - .fll2_req_o ( per_fll_master.req ), - .fll2_wrn_o ( per_fll_master.wrn ), - .fll2_add_o ( per_fll_master.addr[1:0] ), - .fll2_data_o ( per_fll_master.wdata ), - .fll2_ack_i ( per_fll_master.ack ), - .fll2_r_data_i ( per_fll_master.rdata ), - .fll2_lock_i ( per_fll_master.lock ), - - .fll3_req_o ( cluster_fll_master.req ), - .fll3_wrn_o ( cluster_fll_master.wrn ), - .fll3_add_o ( cluster_fll_master.addr[1:0] ), - .fll3_data_o ( cluster_fll_master.wdata ), - .fll3_ack_i ( cluster_fll_master.ack ), - .fll3_r_data_i ( cluster_fll_master.rdata ), - .fll3_lock_i ( cluster_fll_master.lock ), - - .bbgen_req_o (), - .bbgen_wrn_o (), - .bbgen_sel_o (), - .bbgen_data_o (), - .bbgen_ack_i (), - .bbgen_r_data_i(), - .bbgen_lock_i () + // Typedefs + typedef logic [31:0] addr_t; + typedef logic [31:0] data_t; + typedef logic [3:0] strb_t; + `APB_TYPEDEF_REQ_T(apb_req_t, addr_t, data_t, strb_t) + `APB_TYPEDEF_RESP_T(apb_resp_t, data_t) + `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t) + `REG_BUS_TYPEDEF_ALL(regbus, addr_t, data_t, strb_t); + + // Convert AXI lite interface to structs + axi_lite_req_t s_axi_lite_master_req; + axi_lite_resp_t s_axi_lite_master_resp; + `AXI_LITE_ASSIGN_TO_REQ(s_axi_lite_master_req, axi_lite_slave) + `AXI_LITE_ASSIGN_FROM_RESP(axi_lite_slave, s_axi_lite_master_resp) + + // APB Slaves + localparam NumAPBSlaves = 12; + addr_map_rule_t [NumAPBSlaves-1:0] apb_addr_ranges; + apb_req_t [NumAPBSlaves-1:0] s_apb_slaves_req; + apb_resp_t [NumAPBSlaves-1:0] s_apb_slaves_resp; + +// Helper Macro to quickly create and attach new APB slave interfaces. +// Adding a new slave: Increment value of NumAPBSlaves, call this macro +// where port_idx is an incrementing port index number (just increase the +// previously used by one), slave_name must be valid SV identifier, start/end +// address define the start and end address of the associated address space that +// will be routed to the new slave. The macro will generate a new APB interface +// instance with the name s__slave that should be hooked up to the +// APB slave module. +`define SOC_PERIPHERALS_CREATE_SLAVE(port_idx, slave_name, start_address, end_address) \ + APB #(.ADDR_WIDTH(32), .DATA_WIDTH(32)) s_``slave_name``_slave(); \ + assign apb_addr_ranges[port_idx] = '{ idx: port_idx, start_addr: start_address, end_addr: end_address}; \ + `APB_ASSIGN_FROM_REQ(s_``slave_name``_slave, s_apb_slaves_req[port_idx]) \ + `APB_ASSIGN_TO_RESP(s_apb_slaves_resp[port_idx], s_``slave_name``_slave) + + `SOC_PERIPHERALS_CREATE_SLAVE(0, gpio, `SOC_MEM_MAP_GPIO_START_ADDR, `SOC_MEM_MAP_GPIO_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(1, udma, `SOC_MEM_MAP_UDMA_START_ADDR, `SOC_MEM_MAP_UDMA_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(2, soc_ctrl, `SOC_MEM_MAP_SOC_CTRL_START_ADDR, `SOC_MEM_MAP_SOC_CTRL_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(3, adv_timer, `SOC_MEM_MAP_ADV_TIMER_START_ADDR, `SOC_MEM_MAP_ADV_TIMER_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(4, soc_event_gen, `SOC_MEM_MAP_SOC_EVENT_GEN_START_ADDR, `SOC_MEM_MAP_SOC_EVENT_GEN_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(5, interrupt_ctrl, `SOC_MEM_MAP_INTERRUPT_CTRL_START_ADDR, `SOC_MEM_MAP_INTERRUPT_CTRL_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(6, apb_timer, `SOC_MEM_MAP_APB_TIMER_START_ADDR, `SOC_MEM_MAP_APB_TIMER_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(7, hwpe, `SOC_MEM_MAP_HWPE_START_ADDR, `SOC_MEM_MAP_HWPE_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(8, virtual_stdout, `SOC_MEM_MAP_VIRTUAL_STDOUT_START_ADDR, `SOC_MEM_MAP_VIRTUAL_STDOUT_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(9, debug, `SOC_MEM_MAP_DEBUG_START_ADDR, `SOC_MEM_MAP_DEBUG_END_ADDR) + `SOC_PERIPHERALS_CREATE_SLAVE(10, chip_ctrl, `SOC_MEM_MAP_CHIP_CTRL_START_ADDR, `SOC_MEM_MAP_CHIP_CTRL_END_ADDR) + + + // AXI Lite to APB converter with integrated APB Crossbar + axi_lite_to_apb #( + .NoApbSlaves ( NumAPBSlaves ), + .NoRules ( NumAPBSlaves ), + .AddrWidth ( 32 ), + .DataWidth ( 32 ), + .PipelineRequest ( 1'b1 ), + .PipelineResponse ( 1'b1 ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_resp_t ( axi_lite_resp_t ), + .apb_req_t ( apb_req_t ), + .apb_resp_t ( apb_resp_t ), + .rule_t ( addr_map_rule_t ) + ) i_axi_lite_to_apb ( + .clk_i, + .rst_ni, + .axi_lite_req_i ( s_axi_lite_master_req ), + .axi_lite_resp_o ( s_axi_lite_master_resp ), + .apb_req_o ( s_apb_slaves_req ), + .apb_resp_i ( s_apb_slaves_resp ), + .addr_map_i ( apb_addr_ranges ) ); + // Assign internal slave signals to external APB ports + `APB_ASSIGN(apb_intrpt_ctrl_master ,s_interrupt_ctrl_slave) + `APB_ASSIGN(apb_hwpe_master, s_hwpe_slave) + `APB_ASSIGN(apb_debug_master, s_debug_slave) + `APB_ASSIGN(apb_chip_ctrl_master, s_chip_ctrl_slave) `ifdef SYNTHESIS if (SIM_STDOUT) @@ -352,8 +296,8 @@ module soc_peripherals #( if (SIM_STDOUT) begin logic pready_q; - assign s_stdout_bus.pready = pready_q; - assign s_stdout_bus.pslverr = 1'b0; + assign s_virtual_stdout_slave.pready = pready_q; + assign s_virtual_stdout_slave.pslverr = 1'b0; tb_fs_handler #( .ADDR_WIDTH ( 32 ), @@ -363,170 +307,98 @@ module soc_peripherals #( ) i_fs_handler ( .clk ( clk_i ), .rst_n ( rst_ni ), - .CSN ( ~(s_stdout_bus.psel & s_stdout_bus.penable & pready_q) ), - .WEN ( ~s_stdout_bus.pwrite ), - .ADDR ( s_stdout_bus.paddr ), - .WDATA ( s_stdout_bus.pwdata ), + .CSN ( ~(s_virtual_stdout_slave.psel & s_virtual_stdout_slave.penable & pready_q) ), + .WEN ( ~s_virtual_stdout_slave.pwrite ), + .ADDR ( s_virtual_stdout_slave.paddr ), + .WDATA ( s_virtual_stdout_slave.pwdata ), .BE ( 4'hf ), - .RDATA ( s_stdout_bus.prdata ) + .RDATA ( s_virtual_stdout_slave.prdata ) ); always_ff @(posedge clk_i or negedge rst_ni) begin if(~rst_ni) begin pready_q <= 0; end else begin - pready_q <= (s_stdout_bus.psel & s_stdout_bus.penable); + pready_q <= (s_virtual_stdout_slave.psel & s_virtual_stdout_slave.penable); end end end else begin - assign s_stdout_bus.pready = 'h1; - assign s_stdout_bus.pslverr = 1'b0; - assign s_stdout_bus.prdata = 'h0; + assign s_virtual_stdout_slave.pready = 'h1; + assign s_virtual_stdout_slave.pslverr = 1'b0; + assign s_virtual_stdout_slave.prdata = 'h0; end - /////////////////////////////////////////////////////////////// - // █████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██████╗ // - // ██╔══██╗██╔══██╗██╔══██╗ ██╔════╝ ██╔══██╗██║██╔═══██╗ // - // ███████║██████╔╝██████╔╝ ██║ ███╗██████╔╝██║██║ ██║ // - // ██╔══██║██╔═══╝ ██╔══██╗ ██║ ██║██╔═══╝ ██║██║ ██║ // - // ██║ ██║██║ ██████╔╝ ╚██████╔╝██║ ██║╚██████╔╝ // - // ╚═╝ ╚═╝╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ // - /////////////////////////////////////////////////////////////// - - apb_gpio #( - .APB_ADDR_WIDTH (APB_ADDR_WIDTH), - .PAD_NUM (NGPIO), - .NBIT_PADCFG (NBIT_PADCFG) - ) i_apb_gpio ( - .HCLK ( clk_i ), - .HRESETn ( rst_ni ), - - .dft_cg_enable_i ( dft_cg_enable_i ), - - .PADDR ( s_gpio_bus.paddr ), - .PWDATA ( s_gpio_bus.pwdata ), - .PWRITE ( s_gpio_bus.pwrite ), - .PSEL ( s_gpio_bus.psel ), - .PENABLE ( s_gpio_bus.penable ), - .PRDATA ( s_gpio_bus.prdata ), - .PREADY ( s_gpio_bus.pready ), - .PSLVERR ( s_gpio_bus.pslverr ), - - .gpio_in_sync ( s_gpio_sync ), - - .gpio_in ( gpio_in ), - .gpio_out ( gpio_out ), - .gpio_dir ( gpio_dir ), - .gpio_padcfg ( gpio_padcfg ), - .interrupt ( s_gpio_event ) - ); - - //////////////////////////////////////////////////////////////////////////////////////////////// - // ██╗ ██╗██████╗ ███╗ ███╗ █████╗ ███████╗██╗ ██╗██████╗ ███████╗██╗ ██╗███████╗ // - // ██║ ██║██╔══██╗████╗ ████║██╔══██╗ ██╔════╝██║ ██║██╔══██╗██╔════╝╚██╗ ██╔╝██╔════╝ // - // ██║ ██║██║ ██║██╔████╔██║███████║ ███████╗██║ ██║██████╔╝███████╗ ╚████╔╝ ███████╗ // - // ██║ ██║██║ ██║██║╚██╔╝██║██╔══██║ ╚════██║██║ ██║██╔══██╗╚════██║ ╚██╔╝ ╚════██║ // - // ╚██████╔╝██████╔╝██║ ╚═╝ ██║██║ ██║ ███████║╚██████╔╝██████╔╝███████║ ██║ ███████║ // - // ╚═════╝ ╚═════╝ ╚═╝ ╚═╝╚═╝ ╚═╝ ╚══════╝ ╚═════╝ ╚═════╝ ╚══════╝ ╚═╝ ╚══════╝ // - //////////////////////////////////////////////////////////////////////////////////////////////// - - udma_subsystem #( - .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ), - .L2_ADDR_WIDTH ( MEM_ADDR_WIDTH ), - .N_SPI (N_SPI), - .N_UART(N_UART), - .N_I2C (N_I2C) - ) i_udma ( - .L2_ro_req_o ( l2_tx_master.req ), - .L2_ro_gnt_i ( l2_tx_master.gnt ), - .L2_ro_wen_o ( l2_tx_master.wen ), - .L2_ro_addr_o ( l2_tx_master.add ), - .L2_ro_wdata_o ( l2_tx_master.wdata ), - .L2_ro_be_o ( l2_tx_master.be ), - .L2_ro_rdata_i ( l2_tx_master.r_rdata ), - .L2_ro_rvalid_i ( l2_tx_master.r_valid ), - - .L2_wo_req_o ( l2_rx_master.req ), - .L2_wo_gnt_i ( l2_rx_master.gnt ), - .L2_wo_wen_o ( l2_rx_master.wen ), - .L2_wo_addr_o ( l2_rx_master.add ), - .L2_wo_wdata_o ( l2_rx_master.wdata ), - .L2_wo_be_o ( l2_rx_master.be ), - .L2_wo_rdata_i ( l2_rx_master.r_rdata ), - .L2_wo_rvalid_i ( l2_rx_master.r_valid ), - - .dft_test_mode_i ( dft_test_mode_i ), - .dft_cg_enable_i ( 1'b0 ), - - .sys_clk_i ( clk_i ), - .periph_clk_i ( periph_clk_i ), - .sys_resetn_i ( rst_ni ), - - .udma_apb_paddr ( s_udma_bus.paddr ), - .udma_apb_pwdata ( s_udma_bus.pwdata ), - .udma_apb_pwrite ( s_udma_bus.pwrite ), - .udma_apb_psel ( s_udma_bus.psel ), - .udma_apb_penable ( s_udma_bus.penable ), - .udma_apb_prdata ( s_udma_bus.prdata ), - .udma_apb_pready ( s_udma_bus.pready ), - .udma_apb_pslverr ( s_udma_bus.pslverr ), - - .events_o ( s_udma_events ), - - .event_valid_i ( s_pr_event_valid ), - .event_data_i ( s_pr_event_data ), - .event_ready_o ( s_pr_event_ready ), - - .spi_clk ( spi_clk_o ), - .spi_csn ( spi_csn_o ), - .spi_oen ( spi_oen_o ), - .spi_sdo ( spi_sdo_o ), - .spi_sdi ( spi_sdi_i ), - - .sdio_clk_o ( sdclk_o ), - .sdio_cmd_o ( sdcmd_o ), - .sdio_cmd_i ( sdcmd_i ), - .sdio_cmd_oen_o ( sdcmd_oen_o ), - .sdio_data_o ( sddata_o ), - .sdio_data_i ( sddata_i ), - .sdio_data_oen_o ( sddata_oen_o ), - - .cam_clk_i ( cam_clk_i ), - .cam_data_i ( cam_data_i ), - .cam_hsync_i ( cam_hsync_i ), - .cam_vsync_i ( cam_vsync_i ), - - .i2s_slave_sd0_i ( i2s_slave_sd0_i ), - .i2s_slave_sd1_i ( i2s_slave_sd1_i ), - .i2s_slave_ws_i ( i2s_slave_ws_i ), - .i2s_slave_ws_o ( i2s_slave_ws_o ), - .i2s_slave_ws_oe ( i2s_slave_ws_oe ), - .i2s_slave_sck_i ( i2s_slave_sck_i ), - .i2s_slave_sck_o ( i2s_slave_sck_o ), - .i2s_slave_sck_oe ( i2s_slave_sck_oe ), - - .uart_rx_i ( uart_rx ), - .uart_tx_o ( uart_tx ), - - .i2c_scl_i ( i2c_scl_i ), - .i2c_scl_o ( i2c_scl_o ), - .i2c_scl_oe ( i2c_scl_oe_o ), - .i2c_sda_i ( i2c_sda_i ), - .i2c_sda_o ( i2c_sda_o ), - .i2c_sda_oe ( i2c_sda_oe_o ), - - - .hyper_cs_no ( hyper_cs_no ), - .hyper_ck_o ( hyper_ck_o ), - .hyper_ck_no ( hyper_ck_no ), - .hyper_rwds_o ( hyper_rwds_o ), - .hyper_rwds_i ( hyper_rwds_i ), - .hyper_rwds_oe_o ( hyper_rwds_oe_o ), - .hyper_dq_i ( hyper_dq_i ), - .hyper_dq_o ( hyper_dq_o ), - .hyper_dq_oe_o ( hyper_dq_oe_o ), - .hyper_reset_no ( hyper_reset_no ) - + logic sys_rst_ni; + logic sys_clk_i; + + pulp_io #(.APB_ADDR_WIDTH(APB_ADDR_WIDTH)) i_pulp_io ( + .sys_rst_ni (rst_ni ), + .sys_clk_i (clk_i ), + .periph_clk_i (periph_clk_i ), + + .L2_ro_wen_o (l2_tx_master.wen ), + .L2_ro_req_o (l2_tx_master.req ), + .L2_ro_gnt_i (l2_tx_master.gnt ), + .L2_ro_addr_o (l2_tx_master.add ), + .L2_ro_be_o (l2_tx_master.be ), + .L2_ro_wdata_o (l2_tx_master.wdata ), + .L2_ro_rvalid_i (l2_tx_master.r_valid ), + .L2_ro_rdata_i (l2_tx_master.r_rdata ), + + .L2_wo_wen_o (l2_rx_master.wen ), + .L2_wo_req_o (l2_rx_master.req ), + .L2_wo_gnt_i (l2_rx_master.gnt ), + .L2_wo_addr_o (l2_rx_master.add ), + .L2_wo_wdata_o (l2_rx_master.wdata ), + .L2_wo_be_o (l2_rx_master.be ), + .L2_wo_rvalid_i (l2_rx_master.r_valid ), + .L2_wo_rdata_i (l2_rx_master.r_rdata ), + + .dft_test_mode_i (dft_test_mode_i ), + .dft_cg_enable_i (dft_cg_enable_i ), + + .udma_apb_paddr (s_udma_slave.paddr ), + .udma_apb_pwdata (s_udma_slave.pwdata ), + .udma_apb_pwrite (s_udma_slave.pwrite ), + .udma_apb_psel (s_udma_slave.psel ), + .udma_apb_penable(s_udma_slave.penable ), + .udma_apb_prdata (s_udma_slave.prdata ), + .udma_apb_pready (s_udma_slave.pready ), + .udma_apb_pslverr(s_udma_slave.pslverr ), + + .gpio_apb_paddr (s_gpio_slave.paddr ), + .gpio_apb_pwdata (s_gpio_slave.pwdata ), + .gpio_apb_pwrite (s_gpio_slave.pwrite ), + .gpio_apb_psel (s_gpio_slave.psel ), + .gpio_apb_penable(s_gpio_slave.penable ), + .gpio_apb_prdata (s_gpio_slave.prdata ), + .gpio_apb_pready (s_gpio_slave.pready ), + .gpio_apb_pslverr(s_gpio_slave.pslverr ), + + .events_o (s_udma_events ), + .event_valid_i (s_pr_event_valid ), + .event_data_i (s_pr_event_data ), + .event_ready_o (s_pr_event_ready ), + + .uart_to_pad (uart_to_pad_o ), + .pad_to_uart (pad_to_uart_i ), + .i2c_to_pad (i2c_to_pad_o ), + .pad_to_i2c (pad_to_i2c_i ), + .sdio_to_pad (sdio_to_pad_o ), + .pad_to_sdio (pad_to_sdio_i ), + .i2s_to_pad (i2s_to_pad_o ), + .pad_to_i2s (pad_to_i2s_i ), + .qspi_to_pad (qspi_to_pad_o ), + .pad_to_qspi (pad_to_qspi_i ), + .pad_to_cpi (pad_to_cpi_i ), + .hyper_to_pad (hyper_to_pad_o ), + .pad_to_hyper (pad_to_hyper_i ), + .gpio_in (gpio_i ), + .gpio_out (gpio_o ), + .gpio_tx_en_o (gpio_tx_en_o ), + .gpio_in_sync_o (s_gpio_sync ), + .gpio_global_interrupt_o (s_gpio_global_interrupt ), + .gpio_pin_level_interrupt_o (s_gpio_pin_level_interrupt ) ); //////////////////////////////////////////////////////////////////////////////////////////////// @@ -537,28 +409,29 @@ module soc_peripherals #( // ██║ ██║██║ ██████╔╝ ███████║╚██████╔╝╚██████╗ ╚██████╗ ██║ ██║ ██║███████╗ // // ╚═╝ ╚═╝╚═╝ ╚═════╝ ╚══════╝ ╚═════╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═╝╚══════╝ // //////////////////////////////////////////////////////////////////////////////////////////////// - if (NPAD != 64) - $error("apb_soc_ctrl doesn't support any other value than NPAD=64"); apb_soc_ctrl #( .NB_CORES ( NB_CORES ), .NB_CLUSTERS ( NB_CLUSTERS ), .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ), - .NBIT_PADCFG ( NBIT_PADCFG ) + .NBIT_PADCFG ( 3 ) // APB SoC control is no longer + // responsible for pad config. This is handled + // by the padmux IP genreated by + // Padrick. The value here is thus irrelevant. ) i_apb_soc_ctrl ( .HCLK ( clk_i ), .HRESETn ( rst_ni ), - .PADDR ( s_soc_ctrl_bus.paddr ), - .PWDATA ( s_soc_ctrl_bus.pwdata ), - .PWRITE ( s_soc_ctrl_bus.pwrite ), - .PSEL ( s_soc_ctrl_bus.psel ), - .PENABLE ( s_soc_ctrl_bus.penable ), - .PRDATA ( s_soc_ctrl_bus.prdata ), - .PREADY ( s_soc_ctrl_bus.pready ), - .PSLVERR ( s_soc_ctrl_bus.pslverr ), + .PADDR ( s_soc_ctrl_slave.paddr ), + .PWDATA ( s_soc_ctrl_slave.pwdata ), + .PWRITE ( s_soc_ctrl_slave.pwrite ), + .PSEL ( s_soc_ctrl_slave.psel ), + .PENABLE ( s_soc_ctrl_slave.penable ), + .PRDATA ( s_soc_ctrl_slave.prdata ), + .PREADY ( s_soc_ctrl_slave.pready ), + .PSLVERR ( s_soc_ctrl_slave.pslverr ), - .sel_fll_clk_i ( sel_fll_clk_i ), + .sel_pll_clk_i ( sel_pll_clk_i ), .boot_l2_i ( boot_l2_i ), .bootsel_i ( bootsel_i ), .fc_fetch_en_valid_i ( fc_fetch_en_valid_i ), @@ -570,35 +443,35 @@ module soc_peripherals #( .soc_jtag_reg_i ( soc_jtag_reg_i ), .soc_jtag_reg_o ( soc_jtag_reg_o ), - .pad_mux ( pad_mux_o ), - .pad_cfg ( pad_cfg_o ), + .pad_mux ( ), // Not used. Padmuxing is handled externally. + .pad_cfg ( ), // Not used. Padmuxing is handled externally. .cluster_pow_o ( cluster_pow_o ), .sel_hyper_axi_o ( s_sel_hyper_axi ), - .cluster_byp_o ( cluster_byp_o ), - .cluster_boot_addr_o ( cluster_boot_addr_o ), - .cluster_fetch_enable_o ( cluster_fetch_enable_o ), - .cluster_rstn_o ( cluster_rstn_o ), - .cluster_irq_o ( cluster_irq_o ) + .cluster_byp_o ( ), // Not used anymore + .cluster_boot_addr_o ( ), // Not used anymore + .cluster_fetch_enable_o ( ), // Not used anymore + .cluster_rstn_o ( cluster_rstn_req_o ), + .cluster_irq_o ( ) // Not used anymore ); apb_adv_timer #( .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ), - .EXTSIG_NUM ( 32 ) + .EXTSIG_NUM ( NGPIO ) ) i_apb_adv_timer ( .HCLK ( clk_i ), .HRESETn ( rst_ni ), .dft_cg_enable_i ( dft_cg_enable_i ), - .PADDR ( s_adv_timer_bus.paddr ), - .PWDATA ( s_adv_timer_bus.pwdata ), - .PWRITE ( s_adv_timer_bus.pwrite ), - .PSEL ( s_adv_timer_bus.psel ), - .PENABLE ( s_adv_timer_bus.penable ), - .PRDATA ( s_adv_timer_bus.prdata ), - .PREADY ( s_adv_timer_bus.pready ), - .PSLVERR ( s_adv_timer_bus.pslverr ), + .PADDR ( s_adv_timer_slave.paddr ), + .PWDATA ( s_adv_timer_slave.pwdata ), + .PWRITE ( s_adv_timer_slave.pwrite ), + .PSEL ( s_adv_timer_slave.psel ), + .PENABLE ( s_adv_timer_slave.penable ), + .PRDATA ( s_adv_timer_slave.prdata ), + .PREADY ( s_adv_timer_slave.pready ), + .PSLVERR ( s_adv_timer_slave.pslverr ), .low_speed_clk_i ( slow_clk_i ), .ext_sig_i ( s_gpio_sync ), @@ -630,14 +503,14 @@ module soc_peripherals #( .HCLK ( clk_i ), .HRESETn ( rst_ni ), - .PADDR ( s_soc_evnt_gen_bus.paddr ), - .PWDATA ( s_soc_evnt_gen_bus.pwdata ), - .PWRITE ( s_soc_evnt_gen_bus.pwrite ), - .PSEL ( s_soc_evnt_gen_bus.psel ), - .PENABLE ( s_soc_evnt_gen_bus.penable ), - .PRDATA ( s_soc_evnt_gen_bus.prdata ), - .PREADY ( s_soc_evnt_gen_bus.pready ), - .PSLVERR ( s_soc_evnt_gen_bus.pslverr ), + .PADDR ( s_soc_event_gen_slave.paddr ), + .PWDATA ( s_soc_event_gen_slave.pwdata ), + .PWRITE ( s_soc_event_gen_slave.pwrite ), + .PSEL ( s_soc_event_gen_slave.psel ), + .PENABLE ( s_soc_event_gen_slave.penable ), + .PRDATA ( s_soc_event_gen_slave.prdata ), + .PREADY ( s_soc_event_gen_slave.pready ), + .PSLVERR ( s_soc_event_gen_slave.pslverr ), .low_speed_clk_i ( slow_clk_i ), .timer_event_lo_o ( s_timer_in_lo_event ), @@ -661,14 +534,14 @@ module soc_peripherals #( apb_timer_unit #(.APB_ADDR_WIDTH(APB_ADDR_WIDTH)) i_apb_timer_unit ( .HCLK ( clk_i ), .HRESETn ( rst_ni ), - .PADDR ( s_apb_timer_bus.paddr ), - .PWDATA ( s_apb_timer_bus.pwdata ), - .PWRITE ( s_apb_timer_bus.pwrite ), - .PSEL ( s_apb_timer_bus.psel ), - .PENABLE ( s_apb_timer_bus.penable ), - .PRDATA ( s_apb_timer_bus.prdata ), - .PREADY ( s_apb_timer_bus.pready ), - .PSLVERR ( s_apb_timer_bus.pslverr ), + .PADDR ( s_apb_timer_slave.paddr ), + .PWDATA ( s_apb_timer_slave.pwdata ), + .PWRITE ( s_apb_timer_slave.pwrite ), + .PSEL ( s_apb_timer_slave.psel ), + .PENABLE ( s_apb_timer_slave.penable ), + .PRDATA ( s_apb_timer_slave.prdata ), + .PREADY ( s_apb_timer_slave.pready ), + .PSLVERR ( s_apb_timer_slave.pslverr ), .ref_clk_i ( slow_clk_i ), .event_lo_i ( s_timer_in_lo_event ), .event_hi_i ( s_timer_in_hi_event ), diff --git a/rtl/udma_subsystem/src_files.yml b/rtl/udma_subsystem/src_files.yml deleted file mode 100644 index e7101195..00000000 --- a/rtl/udma_subsystem/src_files.yml +++ /dev/null @@ -1,8 +0,0 @@ -udma_subsystem: - incdirs: [ - ../includes, - ., - ] - files: [ - udma_subsystem.sv, - ] diff --git a/rtl/udma_subsystem/udma_subsystem.sv b/rtl/udma_subsystem/udma_subsystem.sv deleted file mode 100644 index eddddf1b..00000000 --- a/rtl/udma_subsystem/udma_subsystem.sv +++ /dev/null @@ -1,1082 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. - -module udma_subsystem -#( - parameter L2_DATA_WIDTH = 32, - parameter L2_ADDR_WIDTH = 19, //L2 addr space of 2MB - parameter CAM_DATA_WIDTH = 8, - parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default - parameter TRANS_SIZE = 20, //max uDMA transaction size of 1MB - parameter N_SPI = 4, - parameter N_UART = 4, - parameter N_I2C = 1, - parameter N_HYPER = 1, - - localparam N_PERIPH_MAX = 32 -) -( - output logic L2_ro_wen_o , - output logic L2_ro_req_o , - input logic L2_ro_gnt_i , - output logic [31:0] L2_ro_addr_o , - output logic [L2_DATA_WIDTH/8-1:0] L2_ro_be_o , - output logic [L2_DATA_WIDTH-1:0] L2_ro_wdata_o , - input logic L2_ro_rvalid_i , - input logic [L2_DATA_WIDTH-1:0] L2_ro_rdata_i , - - output logic L2_wo_wen_o , - output logic L2_wo_req_o , - input logic L2_wo_gnt_i , - output logic [31:0] L2_wo_addr_o , - output logic [L2_DATA_WIDTH-1:0] L2_wo_wdata_o , - output logic [L2_DATA_WIDTH/8-1:0] L2_wo_be_o , - input logic L2_wo_rvalid_i , - input logic [L2_DATA_WIDTH-1:0] L2_wo_rdata_i , - - input logic dft_test_mode_i, - input logic dft_cg_enable_i, - - input logic sys_clk_i, - input logic sys_resetn_i, - - input logic periph_clk_i, - - input logic [APB_ADDR_WIDTH-1:0] udma_apb_paddr, - input logic [31:0] udma_apb_pwdata, - input logic udma_apb_pwrite, - input logic udma_apb_psel, - input logic udma_apb_penable, - output logic [31:0] udma_apb_prdata, - output logic udma_apb_pready, - output logic udma_apb_pslverr, - - output logic [N_PERIPH_MAX*4-1:0] events_o, - - input logic event_valid_i, - input logic [7:0] event_data_i, - output logic event_ready_o, - - // SPIM - output logic [N_SPI-1:0] spi_clk, - output logic [N_SPI-1:0] [3:0] spi_csn, - output logic [N_SPI-1:0] [3:0] spi_oen, - output logic [N_SPI-1:0] [3:0] spi_sdo, - input logic [N_SPI-1:0] [3:0] spi_sdi, - - // I2C - input logic [N_I2C-1:0] i2c_scl_i, - output logic [N_I2C-1:0] i2c_scl_o, - output logic [N_I2C-1:0] i2c_scl_oe, - input logic [N_I2C-1:0] i2c_sda_i, - output logic [N_I2C-1:0] i2c_sda_o, - output logic [N_I2C-1:0] i2c_sda_oe, - - // CAM - input logic cam_clk_i, - input logic [CAM_DATA_WIDTH-1:0] cam_data_i, - input logic cam_hsync_i, - input logic cam_vsync_i, - - // UART - input logic [N_UART-1:0] uart_rx_i, - output logic [N_UART-1:0] uart_tx_o, - - // SDIO - output logic sdio_clk_o, - output logic sdio_cmd_o, - input logic sdio_cmd_i, - output logic sdio_cmd_oen_o, - output logic [3:0] sdio_data_o, - input logic [3:0] sdio_data_i, - output logic [3:0] sdio_data_oen_o, - - // I2S - input logic i2s_slave_sd0_i, - input logic i2s_slave_sd1_i, - input logic i2s_slave_ws_i, - output logic i2s_slave_ws_o, - output logic i2s_slave_ws_oe, - input logic i2s_slave_sck_i, - output logic i2s_slave_sck_o, - output logic i2s_slave_sck_oe, - - // HYPERBUS - output logic [1:0] hyper_cs_no, - output logic hyper_ck_o, - output logic hyper_ck_no, - output logic [1:0] hyper_rwds_o, - input logic hyper_rwds_i, - output logic [1:0] hyper_rwds_oe_o, - input logic [15:0] hyper_dq_i, - output logic [15:0] hyper_dq_o, - output logic [1:0] hyper_dq_oe_o, - output logic hyper_reset_no - -); - - localparam DEST_SIZE = 2; - - localparam L2_AWIDTH_NOAL = L2_ADDR_WIDTH + 2; - - localparam N_I2S = 1; - localparam N_CAM = 1; - localparam N_CSI2 = 0; - localparam N_SDIO = 1; - localparam N_JTAG = 0; - localparam N_MRAM = 0; - localparam N_FILTER = 1; - localparam N_CH_HYPER = 8; - localparam N_FPGA = 0; - localparam N_EXT_PER = 0; - - localparam N_RX_CHANNELS = N_SPI + N_HYPER + N_MRAM + N_JTAG + N_SDIO + N_UART + N_I2C + N_I2S + N_CAM + 2*N_CSI2 + N_FPGA + N_EXT_PER + N_CH_HYPER; - localparam N_TX_CHANNELS = 2*N_SPI + N_HYPER + N_MRAM + N_JTAG + N_SDIO + N_UART + 2*N_I2C + N_I2S + N_FPGA + N_EXT_PER + N_CH_HYPER; - - localparam N_RX_EXT_CHANNELS = N_FILTER; - localparam N_TX_EXT_CHANNELS = 2*N_FILTER; - localparam N_STREAMS = N_FILTER; - localparam STREAM_ID_WIDTH = 1;//$clog2(N_STREAMS) - - localparam N_PERIPHS = N_SPI + N_HYPER + N_UART + N_MRAM + N_I2C + N_CAM + N_I2S + N_CSI2 + N_SDIO + N_JTAG + N_FILTER + N_FPGA + N_EXT_PER + N_CH_HYPER; - - // Currently s_events is designed for N_PERIPH=32. If we change this then - // make sure all the events are correctly mapped and connected. - if (N_PERIPHS > N_PERIPH_MAX) - $fatal(1, "number of events is desigend for at most %d peripherals", N_PERIPH_MAX); - - // TX Channels - localparam CH_ID_TX_UART = 0; - localparam CH_ID_TX_SPIM = N_UART; - localparam CH_ID_CMD_SPIM = CH_ID_TX_SPIM + N_SPI ; - localparam CH_ID_TX_I2C = CH_ID_CMD_SPIM + N_SPI ; - localparam CH_ID_CMD_I2C = CH_ID_TX_I2C + N_I2C ; - localparam CH_ID_TX_SDIO = CH_ID_CMD_I2C + N_I2C ; - localparam CH_ID_TX_I2S = CH_ID_TX_SDIO + N_SDIO ; - localparam CH_ID_TX_CAM = CH_ID_TX_I2S + N_I2S ; - localparam CH_ID_TX_HYPER = CH_ID_TX_CAM + N_CAM ; - // Tx Ext Channel - localparam CH_ID_TX_EXT_PER = CH_ID_TX_HYPER + N_HYPER + N_CH_HYPER; - - - // RX Channels - localparam CH_ID_RX_UART = 0; - localparam CH_ID_RX_SPIM = N_UART; - localparam CH_ID_RX_I2C = CH_ID_RX_SPIM + N_SPI ; - localparam CH_ID_RX_SDIO = CH_ID_RX_I2C + N_I2C ; - localparam CH_ID_RX_I2S = CH_ID_RX_SDIO + N_SDIO ; - localparam CH_ID_RX_CAM = CH_ID_RX_I2S + N_I2S ; - localparam CH_ID_RX_HYPER = CH_ID_RX_CAM + N_CAM ; - // Rx Ext Channel - localparam CH_ID_RX_EXT_PER = CH_ID_RX_HYPER + N_HYPER + N_CH_HYPER; - - // Stream Channel - localparam STREAM_ID_FILTER = 0; - - localparam CH_ID_EXT_TX_FILTER = 0; - localparam CH_ID_EXT_RX_FILTER = 0; - - localparam PER_ID_UART = 0; - localparam PER_ID_SPIM = PER_ID_UART + N_UART ; - localparam PER_ID_I2C = PER_ID_SPIM + N_SPI ; - localparam PER_ID_SDIO = PER_ID_I2C + N_I2C ; - localparam PER_ID_I2S = PER_ID_SDIO + N_SDIO ; - localparam PER_ID_CAM = PER_ID_I2S + N_I2S ; - localparam PER_ID_FILTER = PER_ID_CAM + N_CAM ; - localparam PER_ID_HYPER = PER_ID_FILTER + N_FILTER ; - localparam PER_ID_EXT_PER = PER_ID_HYPER + N_HYPER + N_CH_HYPER; - - - - - logic [N_TX_CHANNELS-1:0] [L2_AWIDTH_NOAL-1 : 0] s_tx_cfg_startaddr; - logic [N_TX_CHANNELS-1:0] [TRANS_SIZE-1 : 0] s_tx_cfg_size; - logic [N_TX_CHANNELS-1:0] s_tx_cfg_continuous; - logic [N_TX_CHANNELS-1:0] s_tx_cfg_en; - logic [N_TX_CHANNELS-1:0] s_tx_cfg_clr; - - logic [N_TX_CHANNELS-1:0] s_tx_ch_req; - logic [N_TX_CHANNELS-1:0] s_tx_ch_gnt; - logic [N_TX_CHANNELS-1:0] [31 : 0] s_tx_ch_data; - logic [N_TX_CHANNELS-1:0] s_tx_ch_valid; - logic [N_TX_CHANNELS-1:0] s_tx_ch_ready; - logic [N_TX_CHANNELS-1:0] [1 : 0] s_tx_ch_datasize; - logic [N_TX_CHANNELS-1:0] [DEST_SIZE-1 : 0] s_tx_ch_destination; - logic [N_TX_CHANNELS-1:0] s_tx_ch_events; - logic [N_TX_CHANNELS-1:0] s_tx_ch_en; - logic [N_TX_CHANNELS-1:0] s_tx_ch_pending; - logic [N_TX_CHANNELS-1:0] [L2_AWIDTH_NOAL-1 : 0] s_tx_ch_curr_addr; - logic [N_TX_CHANNELS-1:0] [TRANS_SIZE-1 : 0] s_tx_ch_bytes_left; - - logic [N_RX_CHANNELS-1:0] [L2_AWIDTH_NOAL-1 : 0] s_rx_cfg_startaddr; - logic [N_RX_CHANNELS-1:0] [TRANS_SIZE-1 : 0] s_rx_cfg_size; - logic [N_RX_CHANNELS-1:0] s_rx_cfg_continuous; - logic [N_RX_CHANNELS-1:0] s_rx_cfg_en; - logic [N_RX_CHANNELS-1:0] s_rx_cfg_clr; - logic [N_RX_CHANNELS-1:0] [1 : 0] s_rx_cfg_stream; - logic [N_RX_CHANNELS-1:0] [STREAM_ID_WIDTH-1: 0] s_rx_cfg_stream_id; - - logic [N_RX_CHANNELS-1:0] [31 : 0] s_rx_ch_data; - logic [N_RX_CHANNELS-1:0] s_rx_ch_valid; - logic [N_RX_CHANNELS-1:0] s_rx_ch_ready; - logic [N_RX_CHANNELS-1:0] [1 : 0] s_rx_ch_datasize; - logic [N_RX_CHANNELS-1:0] [DEST_SIZE-1 : 0] s_rx_ch_destination; - logic [N_RX_CHANNELS-1:0] s_rx_ch_events; - logic [N_RX_CHANNELS-1:0] s_rx_ch_en; - logic [N_RX_CHANNELS-1:0] s_rx_ch_pending; - logic [N_RX_CHANNELS-1:0] [L2_AWIDTH_NOAL-1 : 0] s_rx_ch_curr_addr; - logic [N_RX_CHANNELS-1:0] [TRANS_SIZE-1 : 0] s_rx_ch_bytes_left; - - logic [N_RX_EXT_CHANNELS-1:0] [L2_AWIDTH_NOAL-1 : 0] s_rx_ext_addr; - logic [N_RX_EXT_CHANNELS-1:0] [1 : 0] s_rx_ext_datasize; - logic [N_RX_EXT_CHANNELS-1:0] [DEST_SIZE-1 : 0] s_rx_ext_destination; - logic [N_RX_EXT_CHANNELS-1:0] [1 : 0] s_rx_ext_stream; - logic [N_RX_EXT_CHANNELS-1:0] [STREAM_ID_WIDTH-1 : 0] s_rx_ext_stream_id; - logic [N_RX_EXT_CHANNELS-1:0] s_rx_ext_sot; - logic [N_RX_EXT_CHANNELS-1:0] s_rx_ext_eot; - logic [N_RX_EXT_CHANNELS-1:0] s_rx_ext_valid; - logic [N_RX_EXT_CHANNELS-1:0] [31 : 0] s_rx_ext_data; - logic [N_RX_EXT_CHANNELS-1:0] s_rx_ext_ready; - - logic [N_TX_EXT_CHANNELS-1:0] s_tx_ext_req; - logic [N_TX_EXT_CHANNELS-1:0] [1 : 0] s_tx_ext_datasize; - logic [N_TX_EXT_CHANNELS-1:0] [DEST_SIZE-1 : 0] s_tx_ext_destination; - logic [N_TX_EXT_CHANNELS-1:0] [L2_AWIDTH_NOAL-1 : 0] s_tx_ext_addr; - logic [N_TX_EXT_CHANNELS-1:0] s_tx_ext_gnt; - logic [N_TX_EXT_CHANNELS-1:0] s_tx_ext_valid; - logic [N_TX_EXT_CHANNELS-1:0] [31 : 0] s_tx_ext_data; - logic [N_TX_EXT_CHANNELS-1:0] s_tx_ext_ready; - - logic [N_STREAMS-1:0] [31 : 0] s_stream_data; - logic [N_STREAMS-1:0] [1 : 0] s_stream_datasize; - logic [N_STREAMS-1:0] s_stream_valid; - logic [N_STREAMS-1:0] s_stream_sot; - logic [N_STREAMS-1:0] s_stream_eot; - logic [N_STREAMS-1:0] s_stream_ready; - - logic [N_PERIPH_MAX*4-1:0] s_events; - - logic [1:0] s_rf_event; - - logic [N_PERIPHS-1:0] s_clk_periphs_core; - logic [N_PERIPHS-1:0] s_clk_periphs_per; - - logic [31:0] s_periph_data_to; - logic [4:0] s_periph_addr; - logic s_periph_rwn; - logic [N_PERIPHS-1:0] [31:0] s_periph_data_from; - logic [N_PERIPHS-1:0] s_periph_valid; - logic [N_PERIPHS-1:0] s_periph_ready; - - logic [N_SPI-1:0] s_spi_eot; - logic [N_I2C-1:0] s_i2c_err; - logic [N_I2C-1:0] s_i2c_eot; - logic [N_I2C-1:0] s_i2c_nack; - logic [N_UART-1:0] s_uart_char; - logic [N_UART-1:0] s_uart_err; - - - logic [3:0] s_trigger_events; - - logic s_cam_evt; - logic s_i2s_evt; - - logic s_filter_eot_evt; - logic s_filter_act_evt; - - - logic s_hyper_sys_clk; - logic s_hyper_periph_clk; - logic [N_CH_HYPER-1:0] s_evt_eot_hyper; - logic is_hyper_read_q; - logic is_hyper_read_d; - - integer i; - - assign s_cam_evt = 1'b0; - assign s_i2s_evt = 1'b0; - - assign events_o = s_events; - - assign L2_ro_wen_o = 1'b1; - assign L2_wo_wen_o = 1'b0; - - assign L2_ro_be_o = 'h0; - assign L2_ro_wdata_o = 'h0; - - udma_core #( - .L2_AWIDTH_NOAL ( L2_AWIDTH_NOAL ), - .L2_DATA_WIDTH ( L2_DATA_WIDTH ), - .DATA_WIDTH ( 32 ), - .N_RX_LIN_CHANNELS ( N_RX_CHANNELS ), - .N_TX_LIN_CHANNELS ( N_TX_CHANNELS ), - .N_RX_EXT_CHANNELS ( N_RX_EXT_CHANNELS ), - .N_TX_EXT_CHANNELS ( N_TX_EXT_CHANNELS ), - .N_STREAMS ( N_STREAMS ), - .STREAM_ID_WIDTH ( STREAM_ID_WIDTH ), - .TRANS_SIZE ( TRANS_SIZE ), - .N_PERIPHS ( N_PERIPHS ), - .APB_ADDR_WIDTH ( APB_ADDR_WIDTH ) - ) i_udmacore ( - .sys_clk_i ( sys_clk_i ), - .per_clk_i ( periph_clk_i ), - - .dft_cg_enable_i ( dft_cg_enable_i ), - - .HRESETn ( sys_resetn_i ), - - .PADDR ( udma_apb_paddr ), - .PWDATA ( udma_apb_pwdata ), - .PWRITE ( udma_apb_pwrite ), - .PSEL ( udma_apb_psel ), - .PENABLE ( udma_apb_penable ), - .PRDATA ( udma_apb_prdata ), - .PREADY ( udma_apb_pready ), - .PSLVERR ( udma_apb_pslverr ), - - .periph_per_clk_o ( s_clk_periphs_per ), - .periph_sys_clk_o ( s_clk_periphs_core ), - - .event_valid_i ( event_valid_i ), - .event_data_i ( event_data_i ), - .event_ready_o ( event_ready_o ), - - .event_o ( s_trigger_events ), - - .periph_data_to_o ( s_periph_data_to ), - .periph_addr_o ( s_periph_addr ), - .periph_data_from_i ( s_periph_data_from ), - .periph_ready_i ( s_periph_ready ), - .periph_valid_o ( s_periph_valid ), - .periph_rwn_o ( s_periph_rwn ), - - .tx_l2_req_o ( L2_ro_req_o ), - .tx_l2_gnt_i ( L2_ro_gnt_i ), - .tx_l2_addr_o ( L2_ro_addr_o ), - .tx_l2_rdata_i ( L2_ro_rdata_i ), - .tx_l2_rvalid_i ( L2_ro_rvalid_i ), - - .rx_l2_req_o ( L2_wo_req_o ), - .rx_l2_gnt_i ( L2_wo_gnt_i ), - .rx_l2_addr_o ( L2_wo_addr_o ), - .rx_l2_be_o ( L2_wo_be_o ), - .rx_l2_wdata_o ( L2_wo_wdata_o ), - - .stream_data_o ( s_stream_data ), - .stream_datasize_o ( s_stream_datasize ), - .stream_valid_o ( s_stream_valid ), - .stream_sot_o ( s_stream_sot ), - .stream_eot_o ( s_stream_eot ), - .stream_ready_i ( s_stream_ready ), - - .tx_lin_req_i ( s_tx_ch_req ), - .tx_lin_gnt_o ( s_tx_ch_gnt ), - .tx_lin_valid_o ( s_tx_ch_valid ), - .tx_lin_data_o ( s_tx_ch_data ), - .tx_lin_ready_i ( s_tx_ch_ready ), - .tx_lin_datasize_i ( s_tx_ch_datasize ), - .tx_lin_destination_i ( s_tx_ch_destination ), - .tx_lin_events_o ( s_tx_ch_events ), - .tx_lin_en_o ( s_tx_ch_en ), - .tx_lin_pending_o ( s_tx_ch_pending ), - .tx_lin_curr_addr_o ( s_tx_ch_curr_addr ), - .tx_lin_bytes_left_o ( s_tx_ch_bytes_left ), - .tx_lin_cfg_startaddr_i ( s_tx_cfg_startaddr ), - .tx_lin_cfg_size_i ( s_tx_cfg_size ), - .tx_lin_cfg_continuous_i ( s_tx_cfg_continuous ), - .tx_lin_cfg_en_i ( s_tx_cfg_en ), - .tx_lin_cfg_clr_i ( s_tx_cfg_clr ), - - .rx_lin_valid_i ( s_rx_ch_valid ), - .rx_lin_data_i ( s_rx_ch_data ), - .rx_lin_ready_o ( s_rx_ch_ready ), - .rx_lin_datasize_i ( s_rx_ch_datasize ), - .rx_lin_destination_i ( s_rx_ch_destination ), - .rx_lin_events_o ( s_rx_ch_events ), - .rx_lin_en_o ( s_rx_ch_en ), - .rx_lin_pending_o ( s_rx_ch_pending ), - .rx_lin_curr_addr_o ( s_rx_ch_curr_addr ), - .rx_lin_bytes_left_o ( s_rx_ch_bytes_left ), - .rx_lin_cfg_startaddr_i ( s_rx_cfg_startaddr ), - .rx_lin_cfg_size_i ( s_rx_cfg_size ), - .rx_lin_cfg_continuous_i ( s_rx_cfg_continuous ), - .rx_lin_cfg_stream_i ( s_rx_cfg_stream ), - .rx_lin_cfg_stream_id_i ( s_rx_cfg_stream_id ), - .rx_lin_cfg_en_i ( s_rx_cfg_en ), - .rx_lin_cfg_clr_i ( s_rx_cfg_clr ), - - .rx_ext_addr_i ( s_rx_ext_addr ), - .rx_ext_datasize_i ( s_rx_ext_datasize ), - .rx_ext_destination_i ( s_rx_ext_destination ), - .rx_ext_stream_i ( s_rx_ext_stream ), - .rx_ext_stream_id_i ( s_rx_ext_stream_id ), - .rx_ext_sot_i ( s_rx_ext_sot ), - .rx_ext_eot_i ( s_rx_ext_eot ), - .rx_ext_valid_i ( s_rx_ext_valid ), - .rx_ext_data_i ( s_rx_ext_data ), - .rx_ext_ready_o ( s_rx_ext_ready ), - - .tx_ext_req_i ( s_tx_ext_req ), - .tx_ext_datasize_i ( s_tx_ext_datasize ), - .tx_ext_destination_i ( s_tx_ext_destination ), - .tx_ext_addr_i ( s_tx_ext_addr ), - .tx_ext_gnt_o ( s_tx_ext_gnt ), - .tx_ext_valid_o ( s_tx_ext_valid ), - .tx_ext_data_o ( s_tx_ext_data ), - .tx_ext_ready_i ( s_tx_ext_ready ) - - ); - - //PER_ID 0 - generate - for (genvar g_uart=0;g_uart