axi_slice_dc_slave_wrap wrong instantiation of port signals

[baalabas]

There is a mistake in connecting "axi_slice_dc_slave_wrap" in pulp_cluster.sv line 856
and in "pulp_soc.sv" line 408 inputing a signal "test_cgbypass_i" which is not on the interface of the module of the slave in it's module definition.