From e4c402ba6a34a14378745d68a4c6d2c517d9cd88 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 25 Mar 2024 14:58:32 +0100 Subject: [PATCH] Moved dedicated AXI ID remappers into PULP cluster. --- Bender.lock | 2 +- Bender.yml | 2 +- hw/carfield.sv | 251 +++++++++----------------------------- hw/cheshire_wrap.sv | 288 ++++---------------------------------------- 4 files changed, 81 insertions(+), 462 deletions(-) diff --git a/Bender.lock b/Bender.lock index 43b2d4a7..202a0456 100644 --- a/Bender.lock +++ b/Bender.lock @@ -375,7 +375,7 @@ packages: - axi - common_verification pulp_cluster: - revision: de93f2001ee0a6fca1dc11f6dd95119d8e6aadfb + revision: 135d0883d82d58ac803725ef69b027c666df7115 version: null source: Git: https://github.com/pulp-platform/pulp_cluster.git diff --git a/Bender.yml b/Bender.yml index 8292cc85..f537f432 100644 --- a/Bender.yml +++ b/Bender.yml @@ -17,7 +17,7 @@ dependencies: hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh dyn_mem: { git: https://github.com/pulp-platform/dyn_spm.git, rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main safety_island: { git: https://github.com/pulp-platform/safety_island.git, rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield - pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: de93f2001ee0a6fca1dc11f6dd95119d8e6aadfb } # branch: yt/rapidrecovery + pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 135d0883d82d58ac803725ef69b027c666df7115 } # branch: yt/rapidrecovery opentitan: { git: https://github.com/pulp-platform/opentitan.git, rev: 74e7d6ca17e6a46e727ae2ae11177611232eaeb9 } # branch: carfield_soc mailbox_unit: { git: git@github.com:pulp-platform/mailbox_unit.git, version: 1.1.0 } apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.3 } diff --git a/hw/carfield.sv b/hw/carfield.sv index 5782306a..39c0790c 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -34,12 +34,8 @@ module carfield `endif parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - localparam int unsigned NumExcludedSlaves = CarfieldIslandsCfg.pulp.enable ? 2 : 1, - localparam int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - NumExcludedSlaves, - localparam int unsigned NumExcludedIsolate = CarfieldIslandsCfg.pulp.enable ? 1 : 0, - localparam int unsigned NumIsolate = Cfg.AxiExtNumSlv - NumExcludedIsolate, - localparam int unsigned NumExcludedMasters = CarfieldIslandsCfg.pulp.enable ? 1 : 0, - localparam int unsigned NumMasterCDCs = Cfg.AxiExtNumMst - NumExcludedMasters + // Having a dedicated synchronous port, the mailbox is not taken into account + localparam int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - 1 ) ( // host clock input logic host_clk_i, @@ -384,50 +380,6 @@ localparam int unsigned CarfieldAxiMstRWidth = (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth , Cfg.AxiMstIdWidth, Cfg.AxiUserWidth ); -// Integer Cluster Slave CDC Parameters -localparam int unsigned IntClusterAxiSlvAwWidth = - (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth , - IntClusterAxiIdInWidth, - Cfg.AxiUserWidth ); -localparam int unsigned IntClusterAxiSlvWWidth = - (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth); -localparam int unsigned IntClusterAxiSlvBWidth = - (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdInWidth, - Cfg.AxiUserWidth ); -localparam int unsigned IntClusterAxiSlvArWidth = - (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth , - IntClusterAxiIdInWidth, - Cfg.AxiUserWidth ); -localparam int unsigned IntClusterAxiSlvRWidth = - (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth , - IntClusterAxiIdInWidth, - Cfg.AxiUserWidth ); -// Integer Cluster Master CDC Parameters -localparam int unsigned IntClusterAxiMstAwWidth = - (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth , - IntClusterAxiIdOutWidth, - Cfg.AxiUserWidth ); -localparam int unsigned IntClusterAxiMstWWidth = - (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth); -localparam int unsigned IntClusterAxiMstBWidth = - (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdOutWidth, - Cfg.AxiUserWidth ); -localparam int unsigned IntClusterAxiMstArWidth = - (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth , - IntClusterAxiIdOutWidth, - Cfg.AxiUserWidth ); -localparam int unsigned IntClusterAxiMstRWidth = - (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth , - IntClusterAxiIdOutWidth, - Cfg.AxiUserWidth ); - -// Slave and Master Sides -// verilog_lint: waive-start line-length -`AXI_TYPEDEF_ALL_CT(axi_intcluster_slv, axi_intcluster_slv_req_t, axi_intcluster_slv_rsp_t, car_addrw_t, intclust_idin_t, car_dataw_t, car_strb_t, car_usr_t) -`AXI_TYPEDEF_ALL_CT(axi_intcluster_mst, axi_intcluster_mst_req_t, axi_intcluster_mst_rsp_t, car_addrw_t, intclust_idout_t, car_dataw_t, car_strb_t, car_usr_t) -// verilog_lint: waive-stop line-length // External register interface synchronous with Cheshire's clock domain carfield_reg_req_t [iomsb(NumSyncRegSlv):0] ext_reg_req, ext_reg_req_cut; @@ -477,10 +429,10 @@ logic [ LogDepth:0] llc_w_rptr; logic hyper_isolate_req, hyper_isolated_rsp; logic security_island_isolate_req; -logic [iomsb(NumIsolate):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; +logic [iomsb(Cfg.AxiExtNumSlv):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp; -// All AXI Slaves (except the Integer Cluster and the Mailbox) +// All AXI Slaves (the Mailbox) logic [iomsb(NumSlaveCDCs):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_aw_wptr; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_aw_rptr; @@ -497,56 +449,22 @@ logic [iomsb(NumSlaveCDCs):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_wptr ; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_rptr ; -// All AXI Masters (except the Integer Cluster) -logic [iomsb(NumMasterCDCs):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_aw_wptr; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_aw_rptr; -logic [iomsb(NumMasterCDCs):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_w_wptr ; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_w_rptr ; -logic [iomsb(NumMasterCDCs):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_b_wptr ; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_b_rptr ; -logic [iomsb(NumMasterCDCs):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_ar_wptr; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_ar_rptr; -logic [iomsb(NumMasterCDCs):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_r_wptr ; -logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_mst_ext_r_rptr ; - -// Integer Cluster Slave Bus -logic [IntClusterAxiSlvAwWidth-1:0] axi_slv_intcluster_aw_data; -logic [ LogDepth:0] axi_slv_intcluster_aw_wptr; -logic [ LogDepth:0] axi_slv_intcluster_aw_rptr; -logic [ IntClusterAxiSlvWWidth-1:0] axi_slv_intcluster_w_data ; -logic [ LogDepth:0] axi_slv_intcluster_w_wptr ; -logic [ LogDepth:0] axi_slv_intcluster_w_rptr ; -logic [ IntClusterAxiSlvBWidth-1:0] axi_slv_intcluster_b_data ; -logic [ LogDepth:0] axi_slv_intcluster_b_wptr ; -logic [ LogDepth:0] axi_slv_intcluster_b_rptr ; -logic [IntClusterAxiSlvArWidth-1:0] axi_slv_intcluster_ar_data; -logic [ LogDepth:0] axi_slv_intcluster_ar_wptr; -logic [ LogDepth:0] axi_slv_intcluster_ar_rptr; -logic [ IntClusterAxiSlvRWidth-1:0] axi_slv_intcluster_r_data ; -logic [ LogDepth:0] axi_slv_intcluster_r_wptr ; -logic [ LogDepth:0] axi_slv_intcluster_r_rptr ; - -// Integer Cluster Master Bus -logic [IntClusterAxiMstAwWidth-1:0] axi_mst_intcluster_aw_data; -logic [ LogDepth:0] axi_mst_intcluster_aw_wptr; -logic [ LogDepth:0] axi_mst_intcluster_aw_rptr; -logic [ IntClusterAxiMstWWidth-1:0] axi_mst_intcluster_w_data ; -logic [ LogDepth:0] axi_mst_intcluster_w_wptr ; -logic [ LogDepth:0] axi_mst_intcluster_w_rptr ; -logic [ IntClusterAxiMstBWidth-1:0] axi_mst_intcluster_b_data ; -logic [ LogDepth:0] axi_mst_intcluster_b_wptr ; -logic [ LogDepth:0] axi_mst_intcluster_b_rptr ; -logic [IntClusterAxiMstArWidth-1:0] axi_mst_intcluster_ar_data; -logic [ LogDepth:0] axi_mst_intcluster_ar_wptr; -logic [ LogDepth:0] axi_mst_intcluster_ar_rptr; -logic [ IntClusterAxiMstRWidth-1:0] axi_mst_intcluster_r_data ; -logic [ LogDepth:0] axi_mst_intcluster_r_wptr ; -logic [ LogDepth:0] axi_mst_intcluster_r_rptr ; +// All AXI Masters +logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_wptr; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_rptr; +logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstWWidth-1:0] axi_mst_ext_w_data ; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_wptr ; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_w_rptr ; +logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstBWidth-1:0] axi_mst_ext_b_data ; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_wptr ; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_b_rptr ; +logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstArWidth-1:0] axi_mst_ext_ar_data; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_wptr; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_ar_rptr; +logic [iomsb(Cfg.AxiExtNumMst):0][ CarfieldAxiMstRWidth-1:0] axi_mst_ext_r_data ; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_wptr ; +logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_r_rptr ; // soc reg signals carfield_reg2hw_t car_regs_reg2hw; @@ -845,24 +763,11 @@ cheshire_wrap #( .cheshire_axi_ext_slv_w_chan_t ( carfield_axi_slv_w_chan_t ), .cheshire_axi_ext_slv_req_t ( carfield_axi_slv_req_t ), .cheshire_axi_ext_slv_rsp_t ( carfield_axi_slv_rsp_t ), - .axi_intcluster_slv_ar_chan_t ( axi_intcluster_slv_ar_chan_t ), - .axi_intcluster_slv_aw_chan_t ( axi_intcluster_slv_aw_chan_t ), - .axi_intcluster_slv_b_chan_t ( axi_intcluster_slv_b_chan_t ), - .axi_intcluster_slv_r_chan_t ( axi_intcluster_slv_r_chan_t ), - .axi_intcluster_slv_w_chan_t ( axi_intcluster_slv_w_chan_t ), - .axi_intcluster_slv_req_t ( axi_intcluster_slv_req_t ), - .axi_intcluster_slv_rsp_t ( axi_intcluster_slv_rsp_t ), - .axi_intcluster_mst_ar_chan_t ( axi_intcluster_mst_ar_chan_t ), - .axi_intcluster_mst_aw_chan_t ( axi_intcluster_mst_aw_chan_t ), - .axi_intcluster_mst_b_chan_t ( axi_intcluster_mst_b_chan_t ), - .axi_intcluster_mst_r_chan_t ( axi_intcluster_mst_r_chan_t ), - .axi_intcluster_mst_w_chan_t ( axi_intcluster_mst_w_chan_t ), - .axi_intcluster_mst_req_t ( axi_intcluster_mst_req_t ), - .axi_intcluster_mst_rsp_t ( axi_intcluster_mst_rsp_t ), .cheshire_reg_ext_req_t ( carfield_reg_req_t ), .cheshire_reg_ext_rsp_t ( carfield_reg_rsp_t ), .LogDepth ( LogDepth ), .CdcSyncStages ( SyncStages ), + .NumSlaveCDCs ( NumSlaveCDCs ), .AxiIn ( AxiIn ), .AxiOut ( AxiOut ) ) i_cheshire_wrap ( @@ -926,38 +831,6 @@ cheshire i_cheshire_wrap ( .axi_ext_mst_w_data_i ( axi_mst_ext_w_data ), .axi_ext_mst_w_wptr_i ( axi_mst_ext_w_wptr ), .axi_ext_mst_w_rptr_o ( axi_mst_ext_w_rptr ), - // Integer Cluster Slave Port - .axi_slv_intcluster_aw_data_o ( axi_slv_intcluster_aw_data ), - .axi_slv_intcluster_aw_wptr_o ( axi_slv_intcluster_aw_wptr ), - .axi_slv_intcluster_aw_rptr_i ( axi_slv_intcluster_aw_rptr ), - .axi_slv_intcluster_w_data_o ( axi_slv_intcluster_w_data ), - .axi_slv_intcluster_w_wptr_o ( axi_slv_intcluster_w_wptr ), - .axi_slv_intcluster_w_rptr_i ( axi_slv_intcluster_w_rptr ), - .axi_slv_intcluster_b_data_i ( axi_slv_intcluster_b_data ), - .axi_slv_intcluster_b_wptr_i ( axi_slv_intcluster_b_wptr ), - .axi_slv_intcluster_b_rptr_o ( axi_slv_intcluster_b_rptr ), - .axi_slv_intcluster_ar_data_o ( axi_slv_intcluster_ar_data ), - .axi_slv_intcluster_ar_wptr_o ( axi_slv_intcluster_ar_wptr ), - .axi_slv_intcluster_ar_rptr_i ( axi_slv_intcluster_ar_rptr ), - .axi_slv_intcluster_r_data_i ( axi_slv_intcluster_r_data ), - .axi_slv_intcluster_r_wptr_i ( axi_slv_intcluster_r_wptr ), - .axi_slv_intcluster_r_rptr_o ( axi_slv_intcluster_r_rptr ), - // Integer Cluster Slave Port - .axi_mst_intcluster_aw_data_i ( axi_mst_intcluster_aw_data ), - .axi_mst_intcluster_aw_wptr_i ( axi_mst_intcluster_aw_wptr ), - .axi_mst_intcluster_aw_rptr_o ( axi_mst_intcluster_aw_rptr ), - .axi_mst_intcluster_w_data_i ( axi_mst_intcluster_w_data ), - .axi_mst_intcluster_w_wptr_i ( axi_mst_intcluster_w_wptr ), - .axi_mst_intcluster_w_rptr_o ( axi_mst_intcluster_w_rptr ), - .axi_mst_intcluster_b_data_o ( axi_mst_intcluster_b_data ), - .axi_mst_intcluster_b_wptr_o ( axi_mst_intcluster_b_wptr ), - .axi_mst_intcluster_b_rptr_i ( axi_mst_intcluster_b_rptr ), - .axi_mst_intcluster_ar_data_i ( axi_mst_intcluster_ar_data ), - .axi_mst_intcluster_ar_wptr_i ( axi_mst_intcluster_ar_wptr ), - .axi_mst_intcluster_ar_rptr_o ( axi_mst_intcluster_ar_rptr ), - .axi_mst_intcluster_r_data_o ( axi_mst_intcluster_r_data ), - .axi_mst_intcluster_r_wptr_o ( axi_mst_intcluster_r_wptr ), - .axi_mst_intcluster_r_rptr_i ( axi_mst_intcluster_r_rptr ), // Mailboxes .axi_mbox_slv_req_o ( axi_mbox_req ), .axi_mbox_slv_rsp_i ( axi_mbox_rsp ), @@ -1483,8 +1356,10 @@ if (CarfieldIslandsCfg.pulp.enable) begin : gen_pulp_cluster .AXI_DATA_C2S_WIDTH ( Cfg.AxiDataWidth ), .AXI_DATA_S2C_WIDTH ( Cfg.AxiDataWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), - .AXI_ID_IN_WIDTH ( IntClusterAxiIdInWidth ), - .AXI_ID_OUT_WIDTH ( IntClusterAxiIdOutWidth ), + .AXI_ID_IN_WIDTH ( AxiSlvIdWidth ), + .AXI_ID_OUT_WIDTH ( Cfg.AxiMstIdWidth ), + .AXI_MAX_IN_TRANS ( Cfg.AxiMaxSlvTrans ), + .AXI_MAX_OUT_TRANS ( Cfg.AxiMaxSlvTrans ), .LOG_DEPTH ( LogDepth ), .BaseAddr ( CarfieldIslandsCfg.pulp.base ), .CdcSynchStages ( SyncStages ) @@ -1518,37 +1393,37 @@ if (CarfieldIslandsCfg.pulp.enable) begin : gen_pulp_cluster .async_cluster_events_rptr_o ( ), .async_cluster_events_data_i ( '0 ), // AXI4 Slave port - .async_data_slave_aw_data_i ( axi_slv_intcluster_aw_data ), - .async_data_slave_aw_wptr_i ( axi_slv_intcluster_aw_wptr ), - .async_data_slave_aw_rptr_o ( axi_slv_intcluster_aw_rptr ), - .async_data_slave_ar_data_i ( axi_slv_intcluster_ar_data ), - .async_data_slave_ar_wptr_i ( axi_slv_intcluster_ar_wptr ), - .async_data_slave_ar_rptr_o ( axi_slv_intcluster_ar_rptr ), - .async_data_slave_w_data_i ( axi_slv_intcluster_w_data ), - .async_data_slave_w_wptr_i ( axi_slv_intcluster_w_wptr ), - .async_data_slave_w_rptr_o ( axi_slv_intcluster_w_rptr ), - .async_data_slave_r_data_o ( axi_slv_intcluster_r_data ), - .async_data_slave_r_wptr_o ( axi_slv_intcluster_r_wptr ), - .async_data_slave_r_rptr_i ( axi_slv_intcluster_r_rptr ), - .async_data_slave_b_data_o ( axi_slv_intcluster_b_data ), - .async_data_slave_b_wptr_o ( axi_slv_intcluster_b_wptr ), - .async_data_slave_b_rptr_i ( axi_slv_intcluster_b_rptr ), + .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [IntClusterSlvIdx] ), + .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [IntClusterSlvIdx] ), + .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [IntClusterSlvIdx] ), + .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [IntClusterSlvIdx] ), + .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [IntClusterSlvIdx] ), + .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [IntClusterSlvIdx] ), + .async_data_slave_w_data_i ( axi_slv_ext_w_data [IntClusterSlvIdx] ), + .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [IntClusterSlvIdx] ), + .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [IntClusterSlvIdx] ), + .async_data_slave_r_data_o ( axi_slv_ext_r_data [IntClusterSlvIdx] ), + .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [IntClusterSlvIdx] ), + .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [IntClusterSlvIdx] ), + .async_data_slave_b_data_o ( axi_slv_ext_b_data [IntClusterSlvIdx] ), + .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [IntClusterSlvIdx] ), + .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [IntClusterSlvIdx] ), // AXI4 Master Port - .async_data_master_aw_data_o ( axi_mst_intcluster_aw_data ), - .async_data_master_aw_wptr_o ( axi_mst_intcluster_aw_wptr ), - .async_data_master_aw_rptr_i ( axi_mst_intcluster_aw_rptr ), - .async_data_master_ar_data_o ( axi_mst_intcluster_ar_data ), - .async_data_master_ar_wptr_o ( axi_mst_intcluster_ar_wptr ), - .async_data_master_ar_rptr_i ( axi_mst_intcluster_ar_rptr ), - .async_data_master_w_data_o ( axi_mst_intcluster_w_data ), - .async_data_master_w_wptr_o ( axi_mst_intcluster_w_wptr ), - .async_data_master_w_rptr_i ( axi_mst_intcluster_w_rptr ), - .async_data_master_r_data_i ( axi_mst_intcluster_r_data ), - .async_data_master_r_wptr_i ( axi_mst_intcluster_r_wptr ), - .async_data_master_r_rptr_o ( axi_mst_intcluster_r_rptr ), - .async_data_master_b_data_i ( axi_mst_intcluster_b_data ), - .async_data_master_b_wptr_i ( axi_mst_intcluster_b_wptr ), - .async_data_master_b_rptr_o ( axi_mst_intcluster_b_rptr ) + .async_data_master_aw_data_o ( axi_mst_ext_aw_data [IntClusterMstIdx] ), + .async_data_master_aw_wptr_o ( axi_mst_ext_aw_wptr [IntClusterMstIdx] ), + .async_data_master_aw_rptr_i ( axi_mst_ext_aw_rptr [IntClusterMstIdx] ), + .async_data_master_ar_data_o ( axi_mst_ext_ar_data [IntClusterMstIdx] ), + .async_data_master_ar_wptr_o ( axi_mst_ext_ar_wptr [IntClusterMstIdx] ), + .async_data_master_ar_rptr_i ( axi_mst_ext_ar_rptr [IntClusterMstIdx] ), + .async_data_master_w_data_o ( axi_mst_ext_w_data [IntClusterMstIdx] ), + .async_data_master_w_wptr_o ( axi_mst_ext_w_wptr [IntClusterMstIdx] ), + .async_data_master_w_rptr_i ( axi_mst_ext_w_rptr [IntClusterMstIdx] ), + .async_data_master_r_data_i ( axi_mst_ext_r_data [IntClusterMstIdx] ), + .async_data_master_r_wptr_i ( axi_mst_ext_r_wptr [IntClusterMstIdx] ), + .async_data_master_r_rptr_o ( axi_mst_ext_r_rptr [IntClusterMstIdx] ), + .async_data_master_b_data_i ( axi_mst_ext_b_data [IntClusterMstIdx] ), + .async_data_master_b_wptr_i ( axi_mst_ext_b_wptr [IntClusterMstIdx] ), + .async_data_master_b_rptr_o ( axi_mst_ext_b_rptr [IntClusterMstIdx] ) ); for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_pulpcl_mbox_intrs @@ -1587,22 +1462,6 @@ end else begin : gen_no_pulp_cluster assign car_regs_hw2reg.pulp_cluster_isolate_status.d = '0; assign car_regs_hw2reg.pulp_cluster_isolate_status.de = '0; - assign axi_slv_intcluster_aw_rptr = '0; - assign axi_slv_intcluster_ar_rptr = '0; - assign axi_slv_intcluster_w_rptr = '0; - assign axi_slv_intcluster_r_data = '0; - assign axi_slv_intcluster_r_wptr = '0; - assign axi_slv_intcluster_b_data = '0; - assign axi_slv_intcluster_b_wptr = '0; - - assign axi_mst_intcluster_aw_data = '0; - assign axi_mst_intcluster_aw_wptr = '0; - assign axi_mst_intcluster_ar_data = '0; - assign axi_mst_intcluster_ar_wptr = '0; - assign axi_mst_intcluster_w_data = '0; - assign axi_mst_intcluster_w_wptr = '0; - assign axi_mst_intcluster_r_rptr = '0; - assign axi_mst_intcluster_b_rptr = '0; end // Floating Point Spatz Cluster diff --git a/hw/cheshire_wrap.sv b/hw/cheshire_wrap.sv index e0e9329f..4b185e93 100644 --- a/hw/cheshire_wrap.sv +++ b/hw/cheshire_wrap.sv @@ -39,24 +39,13 @@ module cheshire_wrap parameter type cheshire_axi_ext_slv_w_chan_t = logic, parameter type cheshire_axi_ext_slv_req_t = logic, parameter type cheshire_axi_ext_slv_rsp_t = logic, - parameter type axi_intcluster_slv_ar_chan_t = logic, - parameter type axi_intcluster_slv_aw_chan_t = logic, - parameter type axi_intcluster_slv_b_chan_t = logic, - parameter type axi_intcluster_slv_r_chan_t = logic, - parameter type axi_intcluster_slv_w_chan_t = logic, - parameter type axi_intcluster_slv_req_t = logic, - parameter type axi_intcluster_slv_rsp_t = logic, - parameter type axi_intcluster_mst_ar_chan_t = logic, - parameter type axi_intcluster_mst_aw_chan_t = logic, - parameter type axi_intcluster_mst_b_chan_t = logic, - parameter type axi_intcluster_mst_r_chan_t = logic, - parameter type axi_intcluster_mst_w_chan_t = logic, - parameter type axi_intcluster_mst_req_t = logic, - parameter type axi_intcluster_mst_rsp_t = logic, parameter type cheshire_reg_ext_req_t = logic, parameter type cheshire_reg_ext_rsp_t = logic, parameter int unsigned LogDepth = 3, parameter int unsigned CdcSyncStages = 2, + // External Slaves Parameters + // Having a dedicated synchronous port, the mailbox is not taken into account + parameter int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - 1, parameter axi_in_t AxiIn = gen_axi_in(Cfg) , parameter axi_out_t AxiOut = gen_axi_out(Cfg), // LLC Parameters @@ -81,11 +70,6 @@ module cheshire_wrap localparam int unsigned LlcWWidth = (2**LogDepth)* axi_pkg::w_width(Cfg.AxiDataWidth, Cfg.AxiUserWidth), - // External Slaves Parameters - localparam int unsigned NumExcludedSlaves = CarfieldIslandsCfg.pulp.enable ? 2 : 1, - localparam int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - NumExcludedSlaves, - localparam int unsigned NumExcludedIsolate = CarfieldIslandsCfg.pulp.enable ? 1 : 0, - localparam int unsigned NumIsolate = Cfg.AxiExtNumSlv - NumExcludedIsolate, localparam int unsigned ExtSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(AxiIn.num_in ), localparam int unsigned ExtSlvArWidth = (2**LogDepth)* @@ -107,8 +91,6 @@ module cheshire_wrap axi_pkg::w_width(Cfg.AxiDataWidth, Cfg.AxiUserWidth), // External Master Parameters - localparam int unsigned NumExcludedMasters = CarfieldIslandsCfg.pulp.enable ? 1 : 0, - localparam int unsigned NumMasterCDCs = Cfg.AxiExtNumMst - NumExcludedMasters, localparam int unsigned ExtMstArWidth = (2**LogDepth)* axi_pkg::ar_width(Cfg.AddrWidth , Cfg.AxiMstIdWidth, @@ -126,45 +108,7 @@ module cheshire_wrap Cfg.AxiUserWidth ), localparam int unsigned ExtMstWWidth = (2**LogDepth)* axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth), - // Integer Cluster slave parameters - localparam int unsigned IntClusterAxiSlvAwWidth = - (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth , - IntClusterAxiIdInWidth, - Cfg.AxiUserWidth ), - localparam int unsigned IntClusterAxiSlvWWidth = - (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth), - localparam int unsigned IntClusterAxiSlvBWidth = - (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdInWidth, - Cfg.AxiUserWidth ), - localparam int unsigned IntClusterAxiSlvArWidth = - (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth , - IntClusterAxiIdInWidth, - Cfg.AxiUserWidth ), - localparam int unsigned IntClusterAxiSlvRWidth = - (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth , - IntClusterAxiIdInWidth, - Cfg.AxiUserWidth ), - // Integer Cluster Master parameters - localparam int unsigned IntClusterAxiMstAwWidth = - (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth , - IntClusterAxiIdOutWidth, - Cfg.AxiUserWidth ), - localparam int unsigned IntClusterAxiMstWWidth = - (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth, - Cfg.AxiUserWidth), - localparam int unsigned IntClusterAxiMstBWidth = - (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdOutWidth, - Cfg.AxiUserWidth ), - localparam int unsigned IntClusterAxiMstArWidth = - (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth , - IntClusterAxiIdOutWidth, - Cfg.AxiUserWidth ), - localparam int unsigned IntClusterAxiMstRWidth = - (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth , - IntClusterAxiIdOutWidth, - Cfg.AxiUserWidth ) + Cfg.AxiUserWidth) )( input logic clk_i , input logic rst_ni , @@ -190,9 +134,9 @@ module cheshire_wrap output logic [ LogDepth:0] llc_mst_w_wptr_o , input logic [ LogDepth:0] llc_mst_w_rptr_i , // External AXI isolate slave Ports (except the Mailbox) - input logic [iomsb(NumIsolate):0] axi_ext_slv_isolate_i, - output logic [iomsb(NumIsolate):0] axi_ext_slv_isolated_o, - // External async AXI slave Ports (except the Integer Cluster and the Mailbox) + input logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolate_i, + output logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolated_o, + // External async AXI slave Ports (except the Mailbox) output logic [iomsb(NumSlaveCDCs):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o, output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_wptr_o, input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_rptr_i, @@ -208,54 +152,22 @@ module cheshire_wrap output logic [iomsb(NumSlaveCDCs):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o , output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_wptr_o , input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_rptr_i , - // External async AXI master Ports (except the Integer Cluster) - input logic [iomsb(NumMasterCDCs):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i, - input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_ar_wptr_i, - output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_ar_rptr_o, - input logic [iomsb(NumMasterCDCs):0][ExtMstAwWidth-1:0] axi_ext_mst_aw_data_i, - input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_aw_wptr_i, - output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_aw_rptr_o, - output logic [iomsb(NumMasterCDCs):0][ ExtMstBWidth-1:0] axi_ext_mst_b_data_o , - output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_b_wptr_o , - input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_b_rptr_i , - output logic [iomsb(NumMasterCDCs):0][ ExtMstRWidth-1:0] axi_ext_mst_r_data_o , - output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_r_wptr_o , - input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_r_rptr_i , - input logic [iomsb(NumMasterCDCs):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i , - input logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_w_wptr_i , - output logic [iomsb(NumMasterCDCs):0][ LogDepth:0] axi_ext_mst_w_rptr_o , - // Integer Cluster async Slave Port - output logic [IntClusterAxiSlvAwWidth-1:0] axi_slv_intcluster_aw_data_o, - output logic [ LogDepth:0] axi_slv_intcluster_aw_wptr_o, - input logic [ LogDepth:0] axi_slv_intcluster_aw_rptr_i, - output logic [ IntClusterAxiSlvWWidth-1:0] axi_slv_intcluster_w_data_o , - output logic [ LogDepth:0] axi_slv_intcluster_w_wptr_o , - input logic [ LogDepth:0] axi_slv_intcluster_w_rptr_i , - input logic [ IntClusterAxiSlvBWidth-1:0] axi_slv_intcluster_b_data_i , - input logic [ LogDepth:0] axi_slv_intcluster_b_wptr_i , - output logic [ LogDepth:0] axi_slv_intcluster_b_rptr_o , - output logic [IntClusterAxiSlvArWidth-1:0] axi_slv_intcluster_ar_data_o, - output logic [ LogDepth:0] axi_slv_intcluster_ar_wptr_o, - input logic [ LogDepth:0] axi_slv_intcluster_ar_rptr_i, - input logic [ IntClusterAxiSlvRWidth-1:0] axi_slv_intcluster_r_data_i , - input logic [ LogDepth:0] axi_slv_intcluster_r_wptr_i , - output logic [ LogDepth:0] axi_slv_intcluster_r_rptr_o , - // Integer Cluster async Master Port - input logic [IntClusterAxiMstAwWidth-1:0] axi_mst_intcluster_aw_data_i, - input logic [ LogDepth:0] axi_mst_intcluster_aw_wptr_i, - output logic [ LogDepth:0] axi_mst_intcluster_aw_rptr_o, - input logic [ IntClusterAxiMstWWidth-1:0] axi_mst_intcluster_w_data_i , - input logic [ LogDepth:0] axi_mst_intcluster_w_wptr_i , - output logic [ LogDepth:0] axi_mst_intcluster_w_rptr_o , - output logic [ IntClusterAxiMstBWidth-1:0] axi_mst_intcluster_b_data_o , - output logic [ LogDepth:0] axi_mst_intcluster_b_wptr_o , - input logic [ LogDepth:0] axi_mst_intcluster_b_rptr_i , - input logic [IntClusterAxiMstArWidth-1:0] axi_mst_intcluster_ar_data_i, - input logic [ LogDepth:0] axi_mst_intcluster_ar_wptr_i, - output logic [ LogDepth:0] axi_mst_intcluster_ar_rptr_o, - output logic [ IntClusterAxiMstRWidth-1:0] axi_mst_intcluster_r_data_o , - output logic [ LogDepth:0] axi_mst_intcluster_r_wptr_o , - input logic [ LogDepth:0] axi_mst_intcluster_r_rptr_i , + // External async AXI master Ports + input logic [iomsb(Cfg.AxiExtNumMst):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i, + input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_wptr_i, + output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_rptr_o, + input logic [iomsb(Cfg.AxiExtNumMst):0][ExtMstAwWidth-1:0] axi_ext_mst_aw_data_i, + input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_aw_wptr_i, + output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_aw_rptr_o, + output logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstBWidth-1:0] axi_ext_mst_b_data_o , + output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_b_wptr_o , + input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_b_rptr_i , + output logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstRWidth-1:0] axi_ext_mst_r_data_o , + output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_r_wptr_o , + input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_r_rptr_i , + input logic [iomsb(Cfg.AxiExtNumMst):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i , + input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_w_wptr_i , + output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_w_rptr_o , // Mailboxes output cheshire_axi_ext_slv_req_t axi_mbox_slv_req_o, input cheshire_axi_ext_slv_rsp_t axi_mbox_slv_rsp_i, @@ -506,7 +418,7 @@ for (genvar i = 0; i < NumSlaveCDCs; i++) begin: gen_ext_slv_src_cdc end // Cheshire's AXI slave cdc and isolate generation, except for the Integer Cluster (slave 7) -for (genvar i = 0; i < NumMasterCDCs; i++) begin: gen_ext_mst_dst_cdc +for (genvar i = 0; i < Cfg.AxiExtNumMst; i++) begin: gen_ext_mst_dst_cdc axi_cdc_dst #( .LogDepth ( LogDepth ), .SyncStages ( CdcSyncStages ), @@ -598,158 +510,6 @@ axi_cdc_src #( .async_data_master_r_rptr_o ( llc_mst_r_rptr_o ) ); -if (CarfieldIslandsCfg.pulp) begin : gen_pulp_cluster - // Integer Cluster slave bus - axi_intcluster_slv_req_t axi_intcluster_ser_slv_req, axi_intcluster_ser_isolated_slv_req; - axi_intcluster_slv_rsp_t axi_intcluster_ser_slv_rsp, axi_intcluster_ser_isolated_slv_rsp; - - axi_id_remap #( - .AxiSlvPortIdWidth ( ExtSlvIdWidth ), - .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), - .AxiMaxTxnsPerId ( Cfg.AxiMaxSlvTrans ), - .AxiMstPortIdWidth ( IntClusterAxiIdInWidth ), - .slv_req_t ( cheshire_axi_ext_slv_req_t ), - .slv_resp_t ( cheshire_axi_ext_slv_rsp_t ), - .mst_req_t ( axi_intcluster_slv_req_t ), - .mst_resp_t ( axi_intcluster_slv_rsp_t ) - ) i_integer_cluster_axi_slv_id_remap ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_ext_slv_req[IntClusterSlvIdx] ), - .slv_resp_o ( axi_ext_slv_rsp[IntClusterSlvIdx] ), - .mst_req_o ( axi_intcluster_ser_slv_req ), - .mst_resp_i ( axi_intcluster_ser_slv_rsp ) - ); - - axi_isolate #( - .NumPending ( Cfg.AxiMaxSlvTrans ), - .TerminateTransaction ( 1 ), - .AtopSupport ( 1 ), - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( IntClusterAxiIdInWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .axi_req_t ( axi_intcluster_slv_req_t ), - .axi_resp_t ( axi_intcluster_slv_rsp_t ) - ) i_axi_intcluster_isolate ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_intcluster_ser_slv_req ), - .slv_resp_o ( axi_intcluster_ser_slv_rsp ), - .mst_req_o ( axi_intcluster_ser_isolated_slv_req ), - .mst_resp_i ( axi_intcluster_ser_isolated_slv_rsp ), - .isolate_i ( axi_ext_slv_isolate_i [IntClusterSlvIdx] ), - .isolated_o ( axi_ext_slv_isolated_o[IntClusterSlvIdx] ) - ); - - axi_cdc_src #( - .LogDepth ( LogDepth ), - .SyncStages ( CdcSyncStages ), - .aw_chan_t ( axi_intcluster_slv_aw_chan_t ), - .w_chan_t ( axi_intcluster_slv_w_chan_t ), - .b_chan_t ( axi_intcluster_slv_b_chan_t ), - .ar_chan_t ( axi_intcluster_slv_ar_chan_t ), - .r_chan_t ( axi_intcluster_slv_r_chan_t ), - .axi_req_t ( axi_intcluster_slv_req_t ), - .axi_resp_t ( axi_intcluster_slv_rsp_t ) - ) i_intcluster_slv_cdc ( - // synchronous slave port - .src_clk_i ( clk_i ), - .src_rst_ni ( rst_ni ), - .src_req_i ( axi_intcluster_ser_isolated_slv_req ), - .src_resp_o ( axi_intcluster_ser_isolated_slv_rsp ), - // asynchronous master port - .async_data_master_aw_data_o ( axi_slv_intcluster_aw_data_o ), - .async_data_master_aw_wptr_o ( axi_slv_intcluster_aw_wptr_o ), - .async_data_master_aw_rptr_i ( axi_slv_intcluster_aw_rptr_i ), - .async_data_master_w_data_o ( axi_slv_intcluster_w_data_o ), - .async_data_master_w_wptr_o ( axi_slv_intcluster_w_wptr_o ), - .async_data_master_w_rptr_i ( axi_slv_intcluster_w_rptr_i ), - .async_data_master_b_data_i ( axi_slv_intcluster_b_data_i ), - .async_data_master_b_wptr_i ( axi_slv_intcluster_b_wptr_i ), - .async_data_master_b_rptr_o ( axi_slv_intcluster_b_rptr_o ), - .async_data_master_ar_data_o ( axi_slv_intcluster_ar_data_o ), - .async_data_master_ar_wptr_o ( axi_slv_intcluster_ar_wptr_o ), - .async_data_master_ar_rptr_i ( axi_slv_intcluster_ar_rptr_i ), - .async_data_master_r_data_i ( axi_slv_intcluster_r_data_i ), - .async_data_master_r_wptr_i ( axi_slv_intcluster_r_wptr_i ), - .async_data_master_r_rptr_o ( axi_slv_intcluster_r_rptr_o ) - ); - - // Integer Cluster master bus - axi_intcluster_mst_req_t axi_intcluster_ser_mst_req; - axi_intcluster_mst_rsp_t axi_intcluster_ser_mst_rsp; - - axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( CdcSyncStages ), - .aw_chan_t ( axi_intcluster_mst_aw_chan_t ), - .w_chan_t ( axi_intcluster_mst_w_chan_t ), - .b_chan_t ( axi_intcluster_mst_b_chan_t ), - .ar_chan_t ( axi_intcluster_mst_ar_chan_t ), - .r_chan_t ( axi_intcluster_mst_r_chan_t ), - .axi_req_t ( axi_intcluster_mst_req_t ), - .axi_resp_t ( axi_intcluster_mst_rsp_t ) - ) i_intcluster_mst_cdc ( - // asynchronous slave port - .async_data_slave_aw_data_i ( axi_mst_intcluster_aw_data_i ), - .async_data_slave_aw_wptr_i ( axi_mst_intcluster_aw_wptr_i ), - .async_data_slave_aw_rptr_o ( axi_mst_intcluster_aw_rptr_o ), - .async_data_slave_w_data_i ( axi_mst_intcluster_w_data_i ), - .async_data_slave_w_wptr_i ( axi_mst_intcluster_w_wptr_i ), - .async_data_slave_w_rptr_o ( axi_mst_intcluster_w_rptr_o ), - .async_data_slave_b_data_o ( axi_mst_intcluster_b_data_o ), - .async_data_slave_b_wptr_o ( axi_mst_intcluster_b_wptr_o ), - .async_data_slave_b_rptr_i ( axi_mst_intcluster_b_rptr_i ), - .async_data_slave_ar_data_i ( axi_mst_intcluster_ar_data_i ), - .async_data_slave_ar_wptr_i ( axi_mst_intcluster_ar_wptr_i ), - .async_data_slave_ar_rptr_o ( axi_mst_intcluster_ar_rptr_o ), - .async_data_slave_r_data_o ( axi_mst_intcluster_r_data_o ), - .async_data_slave_r_wptr_o ( axi_mst_intcluster_r_wptr_o ), - .async_data_slave_r_rptr_i ( axi_mst_intcluster_r_rptr_i ), - // synchronous master port - .dst_clk_i ( clk_i ), - .dst_rst_ni ( rst_ni ), - .dst_req_o ( axi_intcluster_ser_mst_req ), - .dst_resp_i ( axi_intcluster_ser_mst_rsp ) - ); - - axi_id_remap #( - .AxiSlvPortIdWidth ( IntClusterAxiIdOutWidth ), - .AxiSlvPortMaxUniqIds ( IntClusterMaxUniqId ), - .AxiMaxTxnsPerId ( Cfg.AxiMaxMstTrans ), - .AxiMstPortIdWidth ( Cfg.AxiMstIdWidth ), - .slv_req_t ( axi_intcluster_mst_req_t ), - .slv_resp_t ( axi_intcluster_mst_rsp_t ), - .mst_req_t ( cheshire_axi_ext_mst_req_t ), - .mst_resp_t ( cheshire_axi_ext_mst_rsp_t ) - ) i_integer_cluster_axi_mst_id_remap ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( axi_intcluster_ser_mst_req ), - .slv_resp_o ( axi_intcluster_ser_mst_rsp ), - .mst_req_o ( axi_ext_mst_req[IntClusterMstIdx] ), - .mst_resp_i ( axi_ext_mst_rsp[IntClusterMstIdx] ) - ); -end else begin: gen_no_pulp_cluster - assign axi_slv_intcluster_aw_data_o = '0; - assign axi_slv_intcluster_aw_wptr_o = '0; - assign axi_slv_intcluster_w_data_o = '0; - assign axi_slv_intcluster_w_wptr_o = '0; - assign axi_slv_intcluster_b_rptr_o = '0; - assign axi_slv_intcluster_ar_data_o = '0; - assign axi_slv_intcluster_ar_wptr_o = '0; - assign axi_slv_intcluster_r_rptr_o = '0; - - assign axi_mst_intcluster_aw_rptr_o = '0; - assign axi_mst_intcluster_w_rptr_o = '0; - assign axi_mst_intcluster_b_data_o = '0; - assign axi_mst_intcluster_b_wptr_o = '0; - assign axi_mst_intcluster_ar_rptr_o = '0; - assign axi_mst_intcluster_r_data_o = '0; - assign axi_mst_intcluster_r_wptr_o = '0; -end - // Async reg interface: // See carfield_pkg.sv for indices referring to sync and async reg interfaces. for (genvar i = 0; i < NumAsyncRegSlv; i++) begin : gen_ext_reg_async