From 4f359a06b2bdd0a4dab0bc2aedbe6b8783dae199 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Mon, 17 Jun 2024 23:53:42 +0200 Subject: [PATCH] fpga: Adding vcu118 BD support --- carfield.mk | 2 +- ...carfield_bd_vcu128.dts => carfield_bd.dts} | 0 ...anilla_vcu128.dts => carfield_vanilla.dts} | 0 .../xilinx/flavor_bd/constraints/vcu118.xdc | 40 ++ .../flavor_bd/constraints/vcu118_ext_jtag.xdc | 17 + .../flavor_bd/constraints/vcu118_hyperbus.xdc | 59 ++ .../xilinx/flavor_bd/constraints/vcu128.xdc | 6 + .../flavor_bd/constraints/vcu128_ext_jtag.xdc | 2 +- .../flavor_bd/constraints/vcu128_hyperbus.xdc | 2 +- target/xilinx/flavor_bd/flavor_bd.mk | 2 +- .../scripts/carfield_bd_ext_jtag.tcl | 5 +- .../flavor_bd/scripts/carfield_bd_vcu118.tcl | 536 ++++++++++++++++++ target/xilinx/scripts/flash_spi.tcl | 25 +- target/xilinx/scripts/program.tcl | 3 + target/xilinx/xilinx.mk | 9 +- 15 files changed, 694 insertions(+), 14 deletions(-) rename sw/boot/{carfield_bd_vcu128.dts => carfield_bd.dts} (100%) rename sw/boot/{carfield_vanilla_vcu128.dts => carfield_vanilla.dts} (100%) create mode 100644 target/xilinx/flavor_bd/constraints/vcu118.xdc create mode 100644 target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc create mode 100644 target/xilinx/flavor_bd/constraints/vcu118_hyperbus.xdc create mode 100644 target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl diff --git a/carfield.mk b/carfield.mk index 93b32098e..afac5cc44 100644 --- a/carfield.mk +++ b/carfield.mk @@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk ###################### CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:carfield/carfield-nonfree.git -CAR_NONFREE_COMMIT ?= 7d227bc7 +CAR_NONFREE_COMMIT ?= 1720d7c2 ## @section Carfield platform nonfree components ## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC diff --git a/sw/boot/carfield_bd_vcu128.dts b/sw/boot/carfield_bd.dts similarity index 100% rename from sw/boot/carfield_bd_vcu128.dts rename to sw/boot/carfield_bd.dts diff --git a/sw/boot/carfield_vanilla_vcu128.dts b/sw/boot/carfield_vanilla.dts similarity index 100% rename from sw/boot/carfield_vanilla_vcu128.dts rename to sw/boot/carfield_vanilla.dts diff --git a/target/xilinx/flavor_bd/constraints/vcu118.xdc b/target/xilinx/flavor_bd/constraints/vcu118.xdc new file mode 100644 index 000000000..9f17d43c3 --- /dev/null +++ b/target/xilinx/flavor_bd/constraints/vcu118.xdc @@ -0,0 +1,40 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +# VIOs are asynchronous +set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}] + +# Create system clocks +create_clock -period 4 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] +create_clock -period 10 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] +create_clock -period 10 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] + +# PCIe clock LOC +#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]] +#set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]] + +set_property PACKAGE_PIN AW25 [get_ports "uart_rx_i"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L9P_T1L_N4_AD12P_64 +set_property PACKAGE_PIN BB21 [get_ports "uart_tx_o"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 64 VCCO - VCC1V8_FPGA - IO_L8N_T1L_N3_AD5N_64 +#set_property PACKAGE_PIN BB22 [get_ports "uart_rts_o"] ; +#set_property IOSTANDARD LVCMOS18 [get_ports "uart_rts_o"] ; +#set_property PACKAGE_PIN AY25 [get_ports "uart_cts_i"] ; +#set_property IOSTANDARD LVCMOS18 [get_ports "uart_cts_i"] ; + +set_property PACKAGE_PIN L19 [get_ports cpu_reset] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73 +set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] ;# Bank 73 VCCO - VCC1V2_FPGA - IO_T1U_N12_73 + +set_property BOARD_PART_PIN default_250mhz_clk1_n [get_ports default_250mhz_clk1_clk_n] +set_property BOARD_PART_PIN default_250mhz_clk1_p [get_ports default_250mhz_clk1_clk_p] + +set_property PACKAGE_PIN D12 [get_ports default_250mhz_clk1_clk_n] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71 +set_property IOSTANDARD DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_n] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_71 +set_property PACKAGE_PIN E12 [get_ports default_250mhz_clk1_clk_p] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 +set_property IOSTANDARD DIFF_SSTL12 [get_ports default_250mhz_clk1_clk_p] ; # Bank 71 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_71 \ No newline at end of file diff --git a/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc new file mode 100644 index 000000000..c029c38d7 --- /dev/null +++ b/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc @@ -0,0 +1,17 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig +# +set_property PACKAGE_PIN N30 [get_ports jtag_tdo_o] +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdo_o] + +set_property PACKAGE_PIN P30 [get_ports jtag_tck_i] +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tck_i] + +set_property PACKAGE_PIN N28 [get_ports jtag_tms_i] +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tms_i] + +set_property PACKAGE_PIN M30 [get_ports jtag_tdi_i] +set_property IOSTANDARD LVCMOS12 [get_ports jtag_tdi_i] diff --git a/target/xilinx/flavor_bd/constraints/vcu118_hyperbus.xdc b/target/xilinx/flavor_bd/constraints/vcu118_hyperbus.xdc new file mode 100644 index 000000000..5a45444b5 --- /dev/null +++ b/target/xilinx/flavor_bd/constraints/vcu118_hyperbus.xdc @@ -0,0 +1,59 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O] + +# (FMCP_HSPC_LA13_N) +set_property PACKAGE_PIN AJ36 [get_ports "pad_hyper_csn[1]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20N_T3L_N3_AD1N_43 + +# (FMCP_HSPC_LA13_P) +set_property PACKAGE_PIN AJ35 [get_ports "pad_hyper_csn[0]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L20P_T3L_N2_AD1P_43 + +# (FMCP_HSPC_LA14_P) +set_property PACKAGE_PIN AG31 [get_ports "pad_hyper_rwds"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L23P_T3U_N8_43 + +# (FMCP_HSPC_LA09_N) +set_property PACKAGE_PIN AK33 [get_ports "pad_hyper_dq[2]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[2]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19N_T3L_N1_DBC_AD9N_43 + +# (FMCP_HSPC_LA10_N) +set_property PACKAGE_PIN AR35 [get_ports "pad_hyper_dq[3]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[3]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3N_T0L_N5_AD15N_43 + +# (FMCP_HSPC_LA10_P) +set_property PACKAGE_PIN AP35 [get_ports "pad_hyper_dq[0]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L3P_T0L_N4_AD15P_43 + +# (FMCP_HSPC_LA09_P) +set_property PACKAGE_PIN AJ33 [get_ports "pad_hyper_dq[4]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L19P_T3L_N0_DBC_AD9P_43 + +# (FMCP_HSPC_LA06_N) +set_property PACKAGE_PIN AT36 [get_ports "pad_hyper_dq[7]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2N_T0L_N3_43 + +# (FMCP_HSPC_LA06_P) +set_property PACKAGE_PIN AT35 [get_ports "pad_hyper_dq[1]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[1]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L2P_T0L_N2_43 + +# (FMCP_HSPC_LA01_CC_N) +set_property PACKAGE_PIN AL31 [get_ports "pad_hyper_ckn"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16N_T2U_N7_QBC_AD3N_43 + +# (FMCP_HSPC_LA01_CC_P) +set_property PACKAGE_PIN AL30 [get_ports "pad_hyper_ck"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L16P_T2U_N6_QBC_AD3P_43 + +# (FMCP_HSPC_LA05_N) +set_property PACKAGE_PIN AR38 [get_ports "pad_hyper_dq[5]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1N_T0L_N1_DBC_43 + +# (FMCP_HSPC_LA05_P) +set_property PACKAGE_PIN AP38 [get_ports "pad_hyper_dq[6]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43 +set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# Bank 43 VCCO - VADJ_1V8_FPGA - IO_L1P_T0L_N0_DBC_43 diff --git a/target/xilinx/flavor_bd/constraints/vcu128.xdc b/target/xilinx/flavor_bd/constraints/vcu128.xdc index 43f19798b..4309d2d69 100644 --- a/target/xilinx/flavor_bd/constraints/vcu128.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu128.xdc @@ -1,3 +1,9 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + # VIOs are asynchronous set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}] diff --git a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc index 69dc4e1ad..61a8a3aed 100644 --- a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc @@ -1,4 +1,4 @@ -# Copyright 2020 ETH Zurich and University of Bologna. +# Copyright 2024 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 # diff --git a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc index daffcb342..9ad4b71de 100644 --- a/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc +++ b/target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc @@ -1,4 +1,4 @@ -# Copyright 2020 ETH Zurich and University of Bologna. +# Copyright 2024 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 # diff --git a/target/xilinx/flavor_bd/flavor_bd.mk b/target/xilinx/flavor_bd/flavor_bd.mk index 1af13dfe9..18617a122 100644 --- a/target/xilinx/flavor_bd/flavor_bd.mk +++ b/target/xilinx/flavor_bd/flavor_bd.mk @@ -49,6 +49,6 @@ $(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(xilinx_ips_paths_bd) $(CAR_XIL_DIR)/flavor .PRECIOUS: $(CAR_XIL_DIR)/flavor_bd/out/%.bit car-xil-clean-bd: - cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_$(XILINX_BOARD) .Xil/ + cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_* .Xil/ .PHONY: car-xil-clean-bd diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl index cb0512831..6ea36dbc0 100644 --- a/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_ext_jtag.tcl @@ -4,15 +4,12 @@ # # Cyril Koenig -set jtag_gnd_o [ create_bd_port -dir O jtag_gnd_o ] set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ] set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ] set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ] set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ] -set jtag_vdd_o [ create_bd_port -dir O jtag_vdd_o ] -connect_bd_net -net carfield_xilinx_ip_0_jtag_gnd_o [get_bd_ports jtag_gnd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_gnd_o] + connect_bd_net -net carfield_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins carfield_xilinx_ip_0/jtag_tdo_o] -connect_bd_net -net carfield_xilinx_ip_0_jtag_vdd_o [get_bd_ports jtag_vdd_o] [get_bd_pins carfield_xilinx_ip_0/jtag_vdd_o] connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tck_i] connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tdi_i] connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins carfield_xilinx_ip_0/jtag_tms_i] diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl new file mode 100644 index 000000000..922f89c08 --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl @@ -0,0 +1,536 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# This file was generated for vivado 2020.2 + +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2020.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcvu9p-flga2104-2L-e + set_property BOARD_PART xilinx.com:vcu118:part0:2.4 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:axi_ethernet:7.2\ +ethz.ch:user:carfield_xilinx_ip:1.0\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:util_ds_buf:2.1\ +xilinx.com:ip:vio:3.0\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:xdma:4.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram_c1_062 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram_c1_062 ] + + set default_250mhz_clk1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_250mhz_clk1 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {250000000} \ + ] $default_250mhz_clk1 + + set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ] + + set pci_express_x4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x4 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $pcie_refclk + + set sgmii_lvds [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii_lvds ] + + set sgmii_phyclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sgmii_phyclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {625000000} \ + ] $sgmii_phyclk + + + # Create ports + set cpu_reset [ create_bd_port -dir I -type rst cpu_reset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $cpu_reset + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set phy_reset_out [ create_bd_port -dir O -from 0 -to 0 -type rst phy_reset_out ] + + set uart_rx_i [ create_bd_port -dir I uart_rx_i ] + set uart_tx_o [ create_bd_port -dir O uart_tx_o ] + + # Create instance: axi_dma_0, and set properties + set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] + set_property -dict [ list \ + CONFIG.c_addr_width {64} \ + CONFIG.c_include_mm2s_dre {1} \ + CONFIG.c_include_s2mm_dre {1} \ + CONFIG.c_sg_length_width {16} \ + CONFIG.c_sg_use_stsapp_length {1} \ + ] $axi_dma_0 + + # Create instance: axi_ethernet_0, and set properties + set axi_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.2 axi_ethernet_0 ] + set_property -dict [ list \ + CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk} \ + CONFIG.ENABLE_LVDS {true} \ + CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds} \ + CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} \ + CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out} \ + CONFIG.PHY_TYPE {SGMII} \ + CONFIG.gtlocation {X0Y4} \ + CONFIG.lvdsclkrate {625} \ + CONFIG.tx_in_upper_nibble {false} \ + CONFIG.txlane0_placement {DIFF_PAIR_2} \ + ] $axi_ethernet_0 + + # Create instance: carfield_xilinx_ip_0, and set properties + set carfield_xilinx_ip_0 [ create_bd_cell -type ip -vlnv ethz.ch:user:carfield_xilinx_ip:1.0 carfield_xilinx_ip_0 ] + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.CLKIN1_JITTER_PS {40.0} \ + CONFIG.CLKOUT1_JITTER {213.887} \ + CONFIG.CLKOUT1_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKOUT2_JITTER {184.746} \ + CONFIG.CLKOUT2_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_JITTER {153.164} \ + CONFIG.CLKOUT3_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_JITTER {134.506} \ + CONFIG.CLKOUT4_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.CLK_OUT1_PORT {clk_10} \ + CONFIG.CLK_OUT2_PORT {clk_20} \ + CONFIG.CLK_OUT3_PORT {clk_50} \ + CONFIG.CLK_OUT4_PORT {clk_100} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {4.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {120.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {12} \ + CONFIG.MMCM_DIVCLK_DIVIDE {5} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.PRIM_IN_FREQ {250.000} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.USE_BOARD_FLOW {true} \ + CONFIG.USE_RESET {false} \ + ] $clk_wiz_0 + + # Create instance: concat_irq, and set properties + set concat_irq [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_irq ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {12} \ + ] $concat_irq + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {None} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.DDR4_AxiAddressWidth {31} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_InputClockPeriod {4000} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16LY-062E} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {Custom} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c1_062} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.System_Clock {No_Buffer} \ + ] $ddr4_0 + + # Create instance: high, and set properties + set high [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 high ] + + # Create instance: low, and set properties + set low [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 low ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $low + + # Create instance: psr_10, and set properties + set psr_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_10 ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {1} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $psr_10 + + # Create instance: psr_300, and set properties + set psr_300 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_300 ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {1} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $psr_300 + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDS} \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf_0 + + # Create instance: util_ds_buf_1, and set properties + set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1 ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf_1 + + # Create instance: vio_0, and set properties + set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ] + set_property -dict [ list \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT0_WIDTH {2} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + ] $vio_0 + + # Create instance: xbar_dram, and set properties + set xbar_dram [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_dram ] + set_property -dict [ list \ + CONFIG.HAS_ARESETN {1} \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $xbar_dram + + # Create instance: xbar_periph_in, and set properties + set xbar_periph_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_periph_in ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {4} \ + ] $xbar_periph_in + + # Create instance: xbar_periph_out, and set properties + set xbar_periph_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_periph_out ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {4} \ + CONFIG.NUM_MI {5} \ + CONFIG.NUM_SI {1} \ + ] $xbar_periph_out + + # Create instance: xdma_0, and set properties + set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] + set_property -dict [ list \ + CONFIG.PCIE_BOARD_INTERFACE {pci_express_x4} \ + CONFIG.PF0_DEVICE_ID_mqdma {9014} \ + CONFIG.PF2_DEVICE_ID_mqdma {9014} \ + CONFIG.PF3_DEVICE_ID_mqdma {9014} \ + CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ + CONFIG.axi_addr_width {64} \ + CONFIG.axisten_freq {125} \ + CONFIG.bar_indicator {BAR_1:0} \ + CONFIG.en_gt_selection {true} \ + CONFIG.functional_mode {AXI_Bridge} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ + CONFIG.pf0_bar0_scale {Gigabytes} \ + CONFIG.pf0_bar0_size {1} \ + CONFIG.pf0_device_id {9014} \ + CONFIG.pf0_msix_cap_pba_bir {BAR_1:0} \ + CONFIG.pf0_msix_cap_table_bir {BAR_1:0} \ + CONFIG.pl_link_cap_max_link_width {X4} \ + CONFIG.ref_clk_freq {100_MHz} \ + CONFIG.xdma_axilite_slave {true} \ + ] $xdma_0 + + # Create interface connections + connect_bd_intf_net -intf_net Conn [get_bd_intf_pins carfield_xilinx_ip_0/periph_axi_m] [get_bd_intf_pins xbar_periph_out/S00_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_CNTRL [get_bd_intf_pins axi_dma_0/M_AXIS_CNTRL] [get_bd_intf_pins axi_ethernet_0/s_axis_txc] + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axi_ethernet_0/s_axis_txd] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins xbar_periph_in/S01_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins xbar_periph_in/S02_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_SG [get_bd_intf_pins axi_dma_0/M_AXI_SG] [get_bd_intf_pins xbar_periph_in/S00_AXI] + connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxd [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins axi_ethernet_0/m_axis_rxd] + connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxs [get_bd_intf_pins axi_dma_0/S_AXIS_STS] [get_bd_intf_pins axi_ethernet_0/m_axis_rxs] + connect_bd_intf_net -intf_net axi_ethernet_0_mdio [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernet_0/mdio] + connect_bd_intf_net -intf_net axi_ethernet_0_sgmii [get_bd_intf_ports sgmii_lvds] [get_bd_intf_pins axi_ethernet_0/sgmii] + connect_bd_intf_net -intf_net carfield_xilinx_ip_0_dram_axi [get_bd_intf_pins carfield_xilinx_ip_0/dram_axi] [get_bd_intf_pins xbar_dram/S00_AXI] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram_c1_062] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_250mhz_clk1_1 [get_bd_intf_ports default_250mhz_clk1] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf_1/CLK_IN_D] + connect_bd_intf_net -intf_net sgmii_phyclk_1 [get_bd_intf_ports sgmii_phyclk] [get_bd_intf_pins axi_ethernet_0/lvds_clk] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins xbar_dram/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins axi_ethernet_0/s_axi] [get_bd_intf_pins xbar_periph_out/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins carfield_xilinx_ip_0/periph_axi_s] [get_bd_intf_pins xbar_periph_in/M00_AXI] + connect_bd_intf_net -intf_net xbar_periph_out_M01_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins xbar_periph_out/M01_AXI] + connect_bd_intf_net -intf_net xbar_periph_out_M02_AXI [get_bd_intf_pins xbar_periph_out/M02_AXI] [get_bd_intf_pins xdma_0/S_AXI_B] + connect_bd_intf_net -intf_net xbar_periph_out_M03_AXI [get_bd_intf_pins xbar_periph_out/M03_AXI] [get_bd_intf_pins xdma_0/S_AXI_LITE] + connect_bd_intf_net -intf_net xdma_0_M_AXI_B [get_bd_intf_pins xbar_periph_in/S03_AXI] [get_bd_intf_pins xdma_0/M_AXI_B] + connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x4] [get_bd_intf_pins xdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net Net [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn] + connect_bd_net -net Net1 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ck] + connect_bd_net -net Net2 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ckn] + connect_bd_net -net Net3 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_rwds] + connect_bd_net -net Net4 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_dq] + connect_bd_net -net axi_dma_0_mm2s_cntrl_reset_out_n [get_bd_pins axi_dma_0/mm2s_cntrl_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txc_arstn] + connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins concat_irq/In2] + connect_bd_net -net axi_dma_0_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_0/mm2s_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txd_arstn] + connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins concat_irq/In3] + connect_bd_net -net axi_dma_0_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_0/s2mm_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_rxd_arstn] + connect_bd_net -net axi_dma_0_s2mm_sts_reset_out_n [get_bd_pins axi_dma_0/s2mm_sts_reset_out_n] [get_bd_pins axi_ethernet_0/axi_rxs_arstn] + connect_bd_net -net axi_ethernet_0_interrupt [get_bd_pins axi_ethernet_0/interrupt] [get_bd_pins concat_irq/In0] + connect_bd_net -net axi_ethernet_0_mac_irq [get_bd_pins axi_ethernet_0/mac_irq] [get_bd_pins concat_irq/In5] + connect_bd_net -net axi_ethernet_0_phy_rst_n [get_bd_ports phy_reset_out] [get_bd_pins axi_ethernet_0/phy_rst_n] + connect_bd_net -net carfield_xilinx_ip_0_dram_axi_m_aclk [get_bd_pins carfield_xilinx_ip_0/dram_axi_m_aclk] [get_bd_pins xbar_dram/aclk] + connect_bd_net -net carfield_xilinx_ip_0_periph_axi_m_aclk [get_bd_pins carfield_xilinx_ip_0/periph_axi_m_aclk] [get_bd_pins xbar_periph_out/aclk] + connect_bd_net -net carfield_xilinx_ip_0_uart_tx_o [get_bd_ports uart_tx_o] [get_bd_pins carfield_xilinx_ip_0/uart_tx_o] + connect_bd_net -net clk_wiz_0_clk_10 [get_bd_pins carfield_xilinx_ip_0/clk_10] [get_bd_pins clk_wiz_0/clk_10] [get_bd_pins psr_10/slowest_sync_clk] + connect_bd_net -net clk_wiz_0_clk_20 [get_bd_pins carfield_xilinx_ip_0/clk_20] [get_bd_pins clk_wiz_0/clk_20] + connect_bd_net -net clk_wiz_0_clk_50 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_ethernet_0/axis_clk] [get_bd_pins axi_ethernet_0/s_axi_lite_clk] [get_bd_pins carfield_xilinx_ip_0/clk_50] [get_bd_pins clk_wiz_0/clk_50] [get_bd_pins vio_0/clk] [get_bd_pins xbar_periph_in/aclk] [get_bd_pins xbar_periph_out/aclk1] + connect_bd_net -net clk_wiz_0_clk_100 [get_bd_pins carfield_xilinx_ip_0/clk_100] [get_bd_pins clk_wiz_0/clk_100] + connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins psr_10/dcm_locked] + connect_bd_net -net concat_irq_dout [get_bd_pins carfield_xilinx_ip_0/gpio_i] [get_bd_pins concat_irq/dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins psr_300/slowest_sync_clk] [get_bd_pins xbar_dram/aclk1] [get_bd_pins xbar_periph_out/aclk3] + connect_bd_net -net high_dout [get_bd_pins carfield_xilinx_ip_0/jtag_trst_ni] [get_bd_pins high/dout] + connect_bd_net -net low_dout [get_bd_pins carfield_xilinx_ip_0/testmode_i] [get_bd_pins low/dout] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] + connect_bd_net -net psr_10_interconnect_aresetn [get_bd_pins psr_10/interconnect_aresetn] [get_bd_pins xbar_dram/aresetn] [get_bd_pins xbar_periph_in/aresetn] [get_bd_pins xbar_periph_out/aresetn] + connect_bd_net -net psr_300_peripheral_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins psr_300/peripheral_aresetn] + connect_bd_net -net psr_300_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins psr_300/peripheral_reset] + connect_bd_net -net psr_50_mb_reset [get_bd_pins carfield_xilinx_ip_0/cpu_reset] [get_bd_pins psr_10/mb_reset] + connect_bd_net -net reset_1 [get_bd_ports cpu_reset] [get_bd_pins psr_10/ext_reset_in] [get_bd_pins psr_300/ext_reset_in] + connect_bd_net -net uart_rx_i_1 [get_bd_ports uart_rx_i] [get_bd_pins carfield_xilinx_ip_0/uart_rx_i] + connect_bd_net -net util_ds_buf_0_IBUF_OUT [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_sys_clk_i] [get_bd_pins util_ds_buf_0/IBUF_OUT] + connect_bd_net -net util_ds_buf_1_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf_1/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] + connect_bd_net -net util_ds_buf_1_IBUF_OUT [get_bd_pins util_ds_buf_1/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] + connect_bd_net -net vio_0_probe_out0 [get_bd_pins carfield_xilinx_ip_0/boot_mode_i] [get_bd_pins vio_0/probe_out0] + connect_bd_net -net vio_0_probe_out1 [get_bd_pins carfield_xilinx_ip_0/boot_mode_safety_i] [get_bd_pins vio_0/probe_out1] + connect_bd_net -net vio_0_probe_out2 [get_bd_pins psr_10/aux_reset_in] [get_bd_pins psr_300/aux_reset_in] [get_bd_pins vio_0/probe_out2] + connect_bd_net -net xdma_0_axi_aclk [get_bd_pins xbar_periph_in/aclk1] [get_bd_pins xbar_periph_out/aclk2] [get_bd_pins xdma_0/axi_aclk] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force + assign_bd_address -offset 0x41E00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x40C00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_ethernet_0/s_axi/Reg0] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/dram_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_B/BAR0] -force + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_B] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force + + # Exclude Address Segments + exclude_bd_addr_seg -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_LITE/CTL0] + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + +common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." + diff --git a/target/xilinx/scripts/flash_spi.tcl b/target/xilinx/scripts/flash_spi.tcl index e6d6c3606..586b411c4 100644 --- a/target/xilinx/scripts/flash_spi.tcl +++ b/target/xilinx/scripts/flash_spi.tcl @@ -1,4 +1,4 @@ -# Copyright 2020 ETH Zurich and University of Bologna. +# Copyright 2024 ETH Zurich and University of Bologna. # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 # @@ -14,23 +14,40 @@ set file $::env(FILE) set offset $::env(OFFSET) set mcs_file image.mcs +if {$::env(XILINX_BOARD) eq "vcu118"} { + set mcs_primary_file image_primary.mcs + set mcs_secondary_file image_secondary.mcs + set hw_device [get_hw_devices xcvu9p_0] + set hw_mem_device [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0] +} + if {$::env(XILINX_BOARD) eq "vcu128"} { set hw_device [get_hw_devices xcvu37p_0] set hw_mem_device [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0] } -# Create flash configuration file -write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ +if {$::env(XILINX_BOARD) eq "vcu118"} { + write_cfgmem -force -format mcs -size 256 -interface SPIx8 \ -loaddata "up $offset $file" \ -checksum \ -file $mcs_file +} else { + write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ + -loaddata "up $offset $file" \ + -checksum \ + -file $mcs_file +} set_property PARAM.FREQUENCY 15000000 [get_hw_targets *] create_hw_cfgmem -hw_device $hw_device $hw_mem_device set hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_device] +if {$::env(XILINX_BOARD) eq "vcu118"} { + set_property PROGRAM.FILES [list $mcs_primary_file $mcs_secondary_file] $hw_cfgmem +} else { + set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem +} set_property PROGRAM.ADDRESS_RANGE {use_file} $hw_cfgmem -set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem set_property PROGRAM.PRM_FILE {} $hw_cfgmem set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $hw_cfgmem set_property PROGRAM.BLANK_CHECK 0 $hw_cfgmem diff --git a/target/xilinx/scripts/program.tcl b/target/xilinx/scripts/program.tcl index bf442c04f..a789a475d 100644 --- a/target/xilinx/scripts/program.tcl +++ b/target/xilinx/scripts/program.tcl @@ -14,6 +14,9 @@ open_hw_target $::env(XILINX_HOST):$::env(XILINX_PORT)/$::env(XILINX_FPGA_PATH) if {$::env(XILINX_BOARD) eq "genesys2"} { set hw_device [get_hw_devices xc7k325t_0] } +if {$::env(XILINX_BOARD) eq "vcu118"} { + set hw_device [get_hw_devices xcvu9p_0] +} if {$::env(XILINX_BOARD) eq "vcu128"} { set hw_device [get_hw_devices xcvu37p_0] } diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 14fb43475..182d90c87 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -15,7 +15,7 @@ VIVADO ?= vitis-2020.2 vivado XILINX_PROJECT ?= carfield # XILINX_FLAVOR in {vanilla,bd} see carfield_bd.mk XILINX_FLAVOR ?= bd -# Board in {vcu128} +# Board in {vcu128, vcu118} XILINX_BOARD ?= vcu128 XILINX_PORT ?= 3121 @@ -28,6 +28,11 @@ ifeq ($(XILINX_BOARD),vcu128) xilinx_board_long := xilinx.com:vcu128:part0:1.0 endif +ifeq ($(XILINX_BOARD),vcu118) + xilinx_part := xcvu9p-flga2104-2L-e + xilinx_board_long := xilinx.com:vcu118:part0:2.4 +endif + XILINX_USE_ARTIFACTS ?= 0 XILINX_ARTIFACTS_ROOT ?= XILINX_ELABORATION_ONLY ?= 0 @@ -94,7 +99,7 @@ car-xil-program: ## @param XILINX_BOARD The target Xilinx board to be programmed ## @param XILINX_FLAVOR= The flavor of the implementation. ## @param VIVADO_FLAGS Some flags for Vivado, such as batch or gui mode -car-xil-flash: $(CAR_SW_DIR)/boot/linux_carfield_$(XILINX_FLAVOR)_$(XILINX_BOARD).gpt.bin +car-xil-flash: $(CAR_SW_DIR)/boot/linux_carfield_$(XILINX_FLAVOR).gpt.bin $(vivado_env) FILE=$< OFFSET=0 $(VIVADO) $(VIVADO_FLAGS) -source $(CAR_XIL_DIR)/scripts/flash_spi.tcl ## Clean Xilinx artifacts for all implementations