diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 000000000..27f78d733
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "sw/deps/cva6-sdk"]
+ path = sw/deps/cva6-sdk
+ url = https://github.com/pulp-platform/cva6-sdk.git
diff --git a/Bender.yml b/Bender.yml
index f537f4326..4fa95efc5 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -59,6 +59,10 @@ sources:
files:
- hw/configs/carfield_l2dual_safe_periph.sv
+ - target: carfield_l2dual_safe_spatz_periph
+ files:
+ - hw/configs/carfield_l2dual_safe_spatz_periph.sv
+
- target: carfield_l2dual_spatz_periph
files:
- hw/configs/carfield_l2dual_spatz_periph.sv
diff --git a/carfield.mk b/carfield.mk
index 715f81284..ecef21e2b 100644
--- a/carfield.mk
+++ b/carfield.mk
@@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk
######################
CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= 54ce7e49
+CAR_NONFREE_COMMIT ?= 59e531343b31c4787c1ff72ab0e18365ea97fbb9
## @section Carfield platform nonfree components
## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC
diff --git a/docs/tg/xilinx.md b/docs/tg/xilinx.md
index 243fc248d..4b07761e0 100644
--- a/docs/tg/xilinx.md
+++ b/docs/tg/xilinx.md
@@ -60,7 +60,7 @@ See below some typical building time for reference:
| Config | Board | Duration |
|----------------------------------------|--------|------------|
-| carfield_l2dual_pulp_periph | vcu128 | __ISSUE__ |
+| carfield_l2dual_pulp_periph | vcu128 | __TODO ADDME__ |
| carfield_l2dual_safe_periph | vcu128 | 6h01min |
| carfield_l2dual_spatz_periph | vcu128 | 3h31min |
| carfield_l2dual_secure_periph | vcu128 | __ISSUE__ |
@@ -104,12 +104,13 @@ See the argument list below:
| GEN_EXT_JTAG | vcu128 | `0` Connect the JTAG debugger to the board's JTAG (see [vcu128](#xilinx-vcu128))
`1` Connect the JTAG debugger to an external JTAG chain |
| CARFIELD_CONFIG | all | Select the Carfield configuration to implement. See below for supported configs. |
| VIVADO_MODE | all | `batch` Compile in Vivado shell
`gui` Compile in Vivado gui |
+| XILINX_BOOT_ETH | all | `0` Boot via SPI flash only (see [booting Linux](#booting_linux))
`1` Boot via SPI flash and Ethernet |
See below some typical building time for reference:
| Config | Board | Duration |
|----------------------------------------|--------|------------|
-| carfield_l2dual_pulp_periph | vcu128 | __ISSUE__ |
+| carfield_l2dual_pulp_periph | vcu128 | __TODO ADDME__ |
| carfield_l2dual_safe_periph | vcu128 | 3h49min |
| carfield_l2dual_spatz_periph | vcu128 | 5h40min |
| carfield_l2dual_secure_periph | vcu128 | __ISSUE__ |
@@ -124,6 +125,10 @@ Note that the `make` command above will first package a Carfield ip before compi
## Board specificities
+### All
+> #### Ethernet
+> As the MAC address of each FPGA is unique (but reconfigurable), if you wish to use the Ethernet
+> IP (`bd` flavor) you will need to add the MAC address of your board in `sw/boot/mac_address.dtsi`.
### Xilinx VCU128
> #### Bootmodes and VIOs
>
@@ -198,10 +203,6 @@ Tbd
Tbd
-### JTAG Preloading
-
-Tbd
-
## Booting Linux
To boot Linux, we must load the *OpenSBI* firmware, which takes over M mode and launches the U-boot
@@ -211,8 +212,8 @@ Clone the `carfield` branch of CVA6 SDK at the root of this repository and build
(OpenSBI + U-boot) and Linux images (*this will take about 30 minutes*):
```bash
-git clone https://github.com/pulp-platform/cva6-sdk.git --branch carfield
-make -C cva6-sdk images
+git submodule update --init --recursive sw/deps/cva6-sdk
+make -C sw/deps/cva6-sdk images
```
In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI,
@@ -227,16 +228,14 @@ To create a full Linux disk image from the ZSL, device tree, firmware, and Linux
```bash
# Place the cva6-sdk where they are expected:
-ln -s cva6-sdk/install64 sw/boot/install64
-# Optional: Pre-uild explicitely the image
+ln -s sw/deps/cva6-sdk/install64 sw/boot/install64
+# Optional: Pre-build explicitely the image
make CAR_ROOT=. sw/boot/linux_carfield_bd_vcu128.gpt.bin
```
-You can now recompile the board, it should start booting automatically!
-
-### Xilinx VCU128
+### Via SPI flash
>
-> This board does not offer a SD card reader. We need to load the image in the
+> Boards like VCU128 does not offer a SD card reader. We need to load the image in the
integrated flash:
>
> ```
@@ -248,6 +247,21 @@ integrated flash:
>
> This script will erase your bitstream, once the flash has been written (c.a.
10min) you will need to re-program the bitstream on the board.
+> You can attach the UART port of the FPGA to minicom and see the boot process!
+### Via Ethernet
+>
+> As flashing and reading the kernel from SPI can take a few minutes, a faster way is to
+> [ask U-Boot to fetch the image from the network](https://www.emcraft.com/som/using-dhcp).
+> This feature can be enabled in the Carfield `bd` flavor. You will need to add the MAC
+> address of your FPGA in `sw/boot/mac_address.dtsi` and the path to your Linux image (on a FTP server)
+> in `sw/boot/remote_boot.dtsi`.
+> You will still need to flash u-boot but it will be now faster:
+> ```
+> make chs-xil-flash VIVADO_MODE=batch XILINX_BOARD=vcu128 XILINX_FLAVOR=bd XILINX_BOOT_ETH=1
+> ```
+### Via Ethernet
+
+Tbd
## Add your own board
diff --git a/hw/carfield.sv b/hw/carfield.sv
index 39c0790cf..c87093e4e 100644
--- a/hw/carfield.sv
+++ b/hw/carfield.sv
@@ -1288,7 +1288,7 @@ else begin : gen_no_safety_island
assign safed_secd_mbox_intr = '0;
assign safed_dbg_reqs = '0;
- assign jtag_safety_island_tdo_o = '0;
+ assign jtag_safety_island_tdo_o = jtag_safety_island_tdi_i;
end
// PULP integer cluster
@@ -1756,7 +1756,7 @@ end else begin : gen_no_secure_subsystem
assign car_regs_hw2reg.security_island_isolate_status.d = '0;
assign car_regs_hw2reg.security_island_isolate_status.de = '0;
- assign jtag_ot_tdo_o = '0;
+ assign jtag_ot_tdo_o = jtag_ot_tdi_i;
end
// Mailbox unit
diff --git a/hw/configs/carfield_l2dual_safe_spatz_periph.sv b/hw/configs/carfield_l2dual_safe_spatz_periph.sv
new file mode 100644
index 000000000..2814dd1f4
--- /dev/null
+++ b/hw/configs/carfield_l2dual_safe_spatz_periph.sv
@@ -0,0 +1,84 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Yvan Tortorella
+
+package carfield_configuration;
+
+import cheshire_pkg::*;
+/*********************
+ * AXI Configuration *
+ ********************/
+//L2, port 0
+localparam bit L2Port0Enable = 1;
+localparam doub_bt L2Port0Base = 'h78000000;
+localparam doub_bt L2Port0Size = 'h00200000;
+// L2, port 1
+localparam bit L2Port1Enable = 1;
+localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size;
+localparam doub_bt L2Port1Size = L2Port0Size;
+// Safety Island
+localparam bit SafetyIslandEnable = 1;
+localparam doub_bt SafetyIslandBase = 'h60000000;
+localparam doub_bt SafetyIslandSize = 'h00800000;
+// Ethernet
+localparam bit EthernetEnable = 0;
+localparam doub_bt EthernetBase = 'h20000000;
+localparam doub_bt EthernetSize = 'h00001000;
+// Peripherals
+localparam bit PeriphEnable = 1;
+localparam doub_bt PeriphBase = 'h20001000;
+localparam doub_bt PeriphSize = 'h00009000;
+// Spatz cluster
+localparam bit SpatzClusterEnable = 1;
+localparam doub_bt SpatzClusterBase = 'h51000000;
+localparam doub_bt SpatzClusterSize = 'h00800000;
+// PULP cluster
+localparam bit PulpClusterEnable = 0;
+localparam doub_bt PulpClusterBase = 'h50000000;
+localparam doub_bt PulpClusterSize = 'h00800000;
+// Security Island
+localparam bit SecurityIslandEnable = 0;
+localparam doub_bt SecurityIslandBase = 'h0;
+localparam doub_bt SecurityIslandSize = 'h0;
+// Mailbox
+localparam bit MailboxEnable = 1;
+localparam doub_bt MailboxBase = 'h40000000;
+localparam doub_bt MailboxSize = 'h00001000;
+// Can
+localparam bit CanEnable = 0;
+localparam doub_bt CanBase = 'h20001000;
+localparam doub_bt CanSize = 'h00001000;
+// System Timer
+localparam doub_bt SystemTimerBase = 'h20004000;
+localparam doub_bt SystemTimerSize = 'h00001000;
+// System Advanced Timer
+localparam doub_bt SystemAdvancedTimerBase = 'h20005000;
+localparam doub_bt SystemAdvancedTimerSize = 'h00001000;
+// System Watchdog
+localparam doub_bt SystemWatchdogBase = 'h20007000;
+localparam doub_bt SystemWatchdogSize = 'h00001000;
+// Hyperbus Config
+localparam doub_bt HyperBusBase = 'h20009000;
+localparam doub_bt HyperBusSize = 'h00001000;
+/************************
+ * RegBus Configuration *
+ ***********************/
+// Platform control registers
+localparam doub_bt PcrsBase = 'h20010000;
+localparam doub_bt PcrsSize = 'h00001000;
+// PLL
+localparam bit PllCfgEnable = 1;
+localparam doub_bt PllCfgBase = 'h20020000;
+localparam doub_bt PllCfgSize = 'h00001000;
+// Padframe
+localparam bit PadframeCfgEnable = 1;
+localparam doub_bt PadframeCfgBase = 'h200A0000;
+localparam doub_bt PadframeCfgSize = 'h00001000;
+// L2 ECC
+localparam bit L2EccCfgEnable = 1;
+localparam doub_bt L2EccCfgBase = 'h200B0000;
+localparam doub_bt L2EccCfgSize = 'h00001000;
+
+endpackage
diff --git a/sw/boot/carfield.dtsi b/sw/boot/carfield.dtsi
index 771b83169..039746ba7 100644
--- a/sw/boot/carfield.dtsi
+++ b/sw/boot/carfield.dtsi
@@ -14,149 +14,11 @@
stdout-path = "/soc/serial@3002000:38400";
};
memory@80000000 {
+ // Give 1GiB to Linux management
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- timebase-frequency = <1000000>; // 1 MHz
- CPU0: cpu@0 {
- device_type = "cpu";
- status = "okay";
- compatible = "eth,ariane", "riscv";
- clock-frequency = <50000000>; // 50 MHz
- riscv,isa = "rv64imafdc";
- mmu-type = "riscv,sv39";
- tlb-split;
- reg = <0>;
- CPU0_intc: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- };
- };
- };
- sysclk: virt_50mhz {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- };
- soc: soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "eth,carfield-soc", "eth,cheshire-bare-soc", "simple-bus";
- ranges;
- debug@0 {
- compatible = "riscv,debug-013";
- reg-names = "control";
- reg = <0x0 0x0 0x0 0x1000>;
- };
- ctrl-regs@3000000 {
- compatible = "eth,control-regs";
- reg = <0x0 0x3000000 0x0 0x1000>;
- };
- axi_llc@3001000 {
- compatible = "eth,axi-llc";
- reg = <0x0 0x3001000 0x0 0x5000>;
- };
- ddr_link: memory-controller@3006000 {
- compatible = "eth,ddr-link";
- reg = <0x0 0x3006000 0x0 0x1000>;
- };
- serial@3002000 {
- compatible = "ns16550a";
- clock-frequency = <50000000>; // 50 MHz
- current-speed = <38400>;
- interrupt-parent = <&PLIC0>;
- interrupts = <1>;
- reg = <0x0 0x3002000 0x0 0x1000>;
- reg-shift = <2>; // regs are spaced on 32 bit boundary
- reg-io-width = <4>; // only 32-bit access are supported
- };
- spi@3004000 {
- compatible = "opentitan,spi-host", "lowrisc,spi";
- interrupt-parent = <&PLIC0>;
- interrupts = <17 18>;
- reg = <0x0 0x3004000 0x0 0x1000>;
- clock-frequency = <50000000>;
- max-frequency = <20000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- boot-with = <1>;
- nor@1 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- // Note : u-boot does not find mt25qu02g
- compatible = "mt25qu02g", "jedec,spi-nor";
- reg = <0x1>; // CS
- spi-max-frequency = <20000000>;
- spi-rx-bus-width = <0x1>;
- spi-tx-bus-width = <0x1>;
- disable-wp;
- partition@0 {
- label = "all";
- reg = <0x0 0x6000000>; // 96 MB
- read-only;
- };
- };
- };
- clint@2040000 {
- compatible = "riscv,clint0";
- interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
- reg-names = "control";
- reg = <0x0 0x2040000 0x0 0x040000>;
- };
- PLIC0: interrupt-controller@4000000 {
- compatible = "riscv,plic0";
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
- riscv,max-priority = <7>;
- riscv,ndev = <51>;
- reg = <0x0 0x4000000 0x0 0x4000000>;
- };
- gpio@3005000 {
- compatible = "gpio,carfield";
- reg = <0x0 0x3005000 0x0 0x1000>;
- interrupts-extended = <&PLIC0 19 &PLIC0 21 &PLIC0 22 &PLIC0 24>;
- };
- tcdm@10000000 {
- reg = <0x0 0x10000000 0x0 0x400000>;
- };
- soc-ctrl@20010000 {
- compatible = "soc-ctrl,carfield";
- reg = <0x0 0x20010000 0x0 0x1000>;
- };
- l2-intl-0@78000000 {
- compatible = "l2-intl,carfield";
- reg = <0x0 0x78000000 0x0 0x100000>;
- };
- l2-cont-0@78100000 {
- compatible = "l2-cont,carfield";
- reg = <0x0 0x78100000 0x0 0x100000>;
- };
- l2-intl-1@78200000 {
- compatible = "l2-intl,carfield";
- reg = <0x0 0x78200000 0x0 0x100000>;
- };
- l2-cont-1@78300000 {
- compatible = "l2-cont,carfield";
- reg = <0x0 0x78300000 0x0 0x100000>;
- };
- safety-island@60000000 {
- compatible = "safety-island,carfield";
- reg = <0x0 0x60000000 0x0 0x800000>;
- };
- integer-cluster@50000000 {
- compatible = "integer-cluster,carfield";
- reg = <0x0 0x50000000 0x0 0x800000>;
- };
- spatz-cluster@51000000 {
- compatible = "spatz-cluster,carfield";
- reg = <0x0 0x51000000 0x0 0x800000>;
- };
- };
+
+ /include/ "carfield_soc.dtsi"
+
};
diff --git a/sw/boot/carfield_bd_vcu118.dts b/sw/boot/carfield_bd_vcu118.dts
new file mode 100644
index 000000000..c3d2805d8
--- /dev/null
+++ b/sw/boot/carfield_bd_vcu118.dts
@@ -0,0 +1,8 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig
+
+
+/include/ "carfield.dtsi"
diff --git a/sw/boot/carfield_bd_vcu128.dts b/sw/boot/carfield_bd_vcu128.dts
index 52f9121bd..090ee6a42 100644
--- a/sw/boot/carfield_bd_vcu128.dts
+++ b/sw/boot/carfield_bd_vcu128.dts
@@ -44,9 +44,8 @@
clock-names = "s_axi_lite_clk", "axis_clk";
// interrupt and mac_irq
interrupts-extended = <&PLIC0 19 &PLIC0 24>;
- //local-mac-address = [ 00 0A 35 04 E1 60 ]; // hero-vcu128-01
- local-mac-address = [ 00 0A 35 04 E1 52 ]; // hero-vcu128-02
- mac-address = [ 00 0A 35 04 E1 52 ];
+ /include/ "mac_address.dtsi"
+ /include/ "remote_boot.dtsi"
device_type = "network";
axistream-connected = <ð_dma0>;
axistream-control-connected = <ð_dma0>;
diff --git a/sw/boot/carfield_pcie.dts b/sw/boot/carfield_pcie.dts
new file mode 100644
index 000000000..b9e0d640d
--- /dev/null
+++ b/sw/boot/carfield_pcie.dts
@@ -0,0 +1,26 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig
+
+/dts-v1/;
+/plugin/;
+&{/dev@0,0} {
+ axi-bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ /include/ "carfield_soc.dtsi"
+
+ };
+};
+
+&soc {
+ pcie-axi-bar@180000000 {
+ compatible = "xlnx,pcie-axi-bar";
+ reg = <0x1 0x80000000 0x0 0x80000000>;
+ };
+};
diff --git a/sw/boot/carfield_soc.dtsi b/sw/boot/carfield_soc.dtsi
new file mode 100644
index 000000000..a8fd8a33c
--- /dev/null
+++ b/sw/boot/carfield_soc.dtsi
@@ -0,0 +1,177 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig
+
+ reserved-memory {
+ ranges;
+ // Keep 1GiB memory for explicit management
+ reserved_dev_buffer: l3_buffer@0xc0000000 {
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <1000000>; // 1 MHz
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ status = "okay";
+ compatible = "eth,ariane", "riscv";
+ clock-frequency = <50000000>; // 50 MHz
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ tlb-split;
+ reg = <0>;
+ CPU0_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ };
+
+ sysclk: virt_50mhz {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ soc: soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "eth,carfield-soc", "eth,cheshire-bare-soc", "simple-bus";
+ ranges;
+ debug@0 {
+ compatible = "riscv,debug-013";
+ reg-names = "control";
+ reg = <0x0 0x0 0x0 0x1000>;
+ };
+ idma@1000000 {
+ compatible = "eth,idma";
+ reg = <0x0 0x1000000 0x0 0x1000>;
+ };
+ ctrl-regs@3000000 {
+ compatible = "eth,control-regs";
+ reg = <0x0 0x3000000 0x0 0x1000>;
+ };
+ axi_llc@3001000 {
+ compatible = "eth,axi-llc";
+ reg = <0x0 0x3001000 0x0 0x5000>;
+ };
+ ddr_link: memory-controller@3006000 {
+ compatible = "eth,ddr-link";
+ reg = <0x0 0x3006000 0x0 0x1000>;
+ };
+ serial@3002000 {
+ compatible = "ns16550a";
+ clock-frequency = <50000000>; // 50 MHz
+ current-speed = <38400>;
+ interrupt-parent = <&PLIC0>;
+ interrupts = <1>;
+ reg = <0x0 0x3002000 0x0 0x1000>;
+ reg-shift = <2>; // regs are spaced on 32 bit boundary
+ reg-io-width = <4>; // only 32-bit access are supported
+ };
+ spi@3004000 {
+ compatible = "opentitan,spi-host", "lowrisc,spi";
+ interrupt-parent = <&PLIC0>;
+ interrupts = <17 18>;
+ reg = <0x0 0x3004000 0x0 0x1000>;
+ clock-frequency = <50000000>;
+ max-frequency = <20000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ boot-with = <1>;
+ nor@1 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ // Note : u-boot does not find mt25qu02g
+ compatible = "mt25qu02g", "jedec,spi-nor";
+ reg = <0x1>; // CS
+ spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <0x1>;
+ spi-tx-bus-width = <0x1>;
+ disable-wp;
+ partition@0 {
+ label = "all";
+ reg = <0x0 0x6000000>; // 96 MB
+ read-only;
+ };
+ };
+ };
+ clint@2040000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
+ reg-names = "control";
+ reg = <0x0 0x2040000 0x0 0x040000>;
+ };
+ PLIC0: interrupt-controller@4000000 {
+ compatible = "riscv,plic0";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+ riscv,max-priority = <7>;
+ riscv,ndev = <51>;
+ reg = <0x0 0x4000000 0x0 0x4000000>;
+ };
+ gpio@3005000 {
+ compatible = "gpio,carfield";
+ reg = <0x0 0x3005000 0x0 0x1000>;
+ interrupts-extended = <&PLIC0 19 &PLIC0 21 &PLIC0 22 &PLIC0 24>;
+ };
+ tcdm@10000000 {
+ reg = <0x0 0x10000000 0x0 0x400000>;
+ };
+ soc-ctrl@20010000 {
+ compatible = "soc-ctrl,carfield";
+ reg = <0x0 0x20010000 0x0 0x1000>;
+ };
+ mboxes@40000000 {
+ compatible = "mboxes,carfield";
+ reg = <0x0 0x40000000 0x0 0x1000>;
+ };
+ l2-intl-0@78000000 {
+ compatible = "l2-intl,carfield";
+ reg = <0x0 0x78000000 0x0 0x100000>;
+ };
+ l2-cont-0@78100000 {
+ compatible = "l2-cont,carfield";
+ reg = <0x0 0x78100000 0x0 0x100000>;
+ };
+ l2-intl-1@78200000 {
+ compatible = "l2-intl,carfield";
+ reg = <0x0 0x78200000 0x0 0x100000>;
+ };
+ l2-cont-1@78300000 {
+ compatible = "l2-cont,carfield";
+ reg = <0x0 0x78300000 0x0 0x100000>;
+ };
+ safety-island@60000000 {
+ compatible = "safety-island,carfield";
+ reg = <0x0 0x60000000 0x0 0x800000>;
+ // Link to the buffer for this device
+ memory-region = <&reserved_dev_buffer>;
+ };
+ integer-cluster@50000000 {
+ compatible = "integer-cluster,carfield";
+ reg = <0x0 0x50000000 0x0 0x800000>;
+ // Link to the buffer for this device
+ memory-region = <&reserved_dev_buffer>;
+ };
+ spatz-cluster@51000000 {
+ compatible = "spatz-cluster,carfield";
+ reg = <0x0 0x51000000 0x0 0x800000>;
+ // Link to the buffer for this device
+ memory-region = <&reserved_dev_buffer>;
+ };
+ l3_buffer@c0000000 {
+ compatible = "l3-buffer,carfield";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ memory-region = <&reserved_dev_buffer>;
+ };
+ };
diff --git a/sw/boot/mac_address.dtsi b/sw/boot/mac_address.dtsi
new file mode 100644
index 000000000..8ad365a59
--- /dev/null
+++ b/sw/boot/mac_address.dtsi
@@ -0,0 +1,2 @@
+local-mac-address = [ 00 00 00 00 00 00 ];
+mac-address = [ 00 00 00 00 00 00 ];
diff --git a/sw/boot/remote_boot.dtsi b/sw/boot/remote_boot.dtsi
new file mode 100644
index 000000000..dde661eae
--- /dev/null
+++ b/sw/boot/remote_boot.dtsi
@@ -0,0 +1,2 @@
+// Uncomment below for remote boot
+// remote-boot = "0.0.0.0:vcu128-01/carfield/uImage-ci";
\ No newline at end of file
diff --git a/sw/deps/cva6-sdk b/sw/deps/cva6-sdk
new file mode 160000
index 000000000..0aa24f5c1
--- /dev/null
+++ b/sw/deps/cva6-sdk
@@ -0,0 +1 @@
+Subproject commit 0aa24f5c16ea6986a271e648777ae1d47c52449c
diff --git a/sw/sw.mk b/sw/sw.mk
index 1fc4b13a4..52f243c57 100644
--- a/sw/sw.mk
+++ b/sw/sw.mk
@@ -34,9 +34,8 @@ $(CAR_SW_DIR)/lib/libcarfield.a: $(CAR_SW_LIB_SRCS_O)
car-sw-libs: $(CAR_SW_LIBS)
# Compilation
-
-carfield_%.dtb: carfield_%.dts
- $(CHS_SW_DTC) -I dts -O dtb -i $(CAR_SW_DIR)/boot -o $@ $<
+carfield_%.dtb: carfield_%.dts $(wildcard $(CAR_SW_DIR)/boot/*.dtsi)
+ $(CHS_SW_DTC) -@ -I dts -O dtb -i $(CAR_SW_DIR)/boot -o $@ $<
# All objects require up-to-date patches and headers
%.car.o: %.c
@@ -165,13 +164,18 @@ $(CAR_SW_DIR)/boot/linux_carfield_%.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CA
dd if=$(word 1,$^) of=$@ bs=512 seek=64 conv=notrunc
dd if=$(word 2,$^) of=$@ bs=512 seek=128 conv=notrunc
dd if=$(word 3,$^) of=$@ bs=512 seek=2048 conv=notrunc
+ifneq ($(XILINX_BOOT_ETH),1)
dd if=$(word 4,$^) of=$@ bs=512 seek=8192 conv=notrunc
+else
+# If we plan in booting over ethernet do not add Linux
+ truncate -s 4M $@
+endif
#########################
# Linux app compilation #
#########################
-CAR_CVA6_SDK ?= $(realpath cva6-sdk)
+CAR_CVA6_SDK ?= $(realpath sw/deps/cva6-sdk)
CAR_CROSS_COMPILE := $(CAR_CVA6_SDK)/buildroot/output/host/bin/riscv64-buildroot-linux-gnu-
CAR_APP_CC := $(CAR_CROSS_COMPILE)gcc
CAR_APP_OBJDUMP := $(CAR_CROSS_COMPILE)objdump
diff --git a/target/xilinx/constraints/carfield.xdc b/target/xilinx/constraints/carfield.xdc
index 6b05a2179..9039f9900 100644
--- a/target/xilinx/constraints/carfield.xdc
+++ b/target/xilinx/constraints/carfield.xdc
@@ -47,6 +47,18 @@ set_max_delay -through [get_nets *isolat*] $SOC_TCK
# Host pwr_on_reset is resynch by the domains
set_max_delay -datapath -from [get_pins i_host_rstgen/i_rstgen_bypass/synch_regs_q_reg[3]/C] -through [get_pins -of_object [get_cells -hier -filter {REF_NAME==clk_mux_glitch_free || ORIG_REF_NAME==clk_mux_glitch_free}] -filter { NAME =~*async* }] $SOC_TCK
+# Reset synchronizers are themselves reset by the host synch reset
+set_max_delay -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ "*i_carfield_rstgen/*/i_rstgen_bypass/synch*"}] -filter {REF_PIN_NAME == CLR}] $SOC_TCK
+set_false_path -hold -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ "*i_carfield_rstgen/*/i_rstgen_bypass/synch*"}] -filter {REF_PIN_NAME == CLR}]
+
+###################
+# Carfield regtop #
+###################
+
+# Most of these paths go through proper synchronizers, but not all of them
+set_max_delay -datapath_only -through [get_cells i_carfield_reg_top] -from [get_clocks -filter {NAME !~ "*clk_50*"}] -to [get_clocks *clk_50*] $SOC_TCK
+set_max_delay -datapath_only -through [get_cells i_carfield_reg_top] -from [get_clocks *clk_50*] -to [get_clocks -filter {NAME !~ "*clk_50*"}] $SOC_TCK
+
#################
# Carfield CDCs #
#################
diff --git a/target/xilinx/constraints/carfield_islands.tcl b/target/xilinx/constraints/carfield_islands.tcl
index d83028fb9..bbd77c93a 100644
--- a/target/xilinx/constraints/carfield_islands.tcl
+++ b/target/xilinx/constraints/carfield_islands.tcl
@@ -47,23 +47,23 @@ handle_domain_clock_mux [get_cells -hier u_l2_clk_sel] 0 l2_domain_clk
proc handle_slv_cdc { slv_cdc_path } {
upvar SOC_TCK SOC_TCK
# Start from a known slv cdc_dst and get fanout to find the mst cdc_src
- set mst_cdc_path [lindex [regexp -inline {.*gen_ext_slv_src_cdc\[[0-9]*\]} [lindex [filter [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] -filter {NAME =~ *gen_ext_slv_src_cdc*}] 0]] 0]
+ set mst_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_slv_cdc_src|.*i_intcluster_slv_cdc} [lindex [filter [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] -filter {NAME =~ *gen_ext_slv_src_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0]
if { $mst_cdc_path != "" } {
set_max_delay -datapath \
- -from [get_pins $mst_cdc_path.i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \
+ -from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
-to [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \
"$SOC_TCK"
set_max_delay -datapath \
-from [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
- -to [get_pins $mst_cdc_path.i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \
+ -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \
"$SOC_TCK"
set_max_delay -datapath \
- -from [get_pins $mst_cdc_path.i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*reg*/C] \
+ -from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
-to [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
"$SOC_TCK"
set_max_delay -datapath \
-from [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
- -to [get_pins $mst_cdc_path.i_cheshire_ext_slv_cdc_src/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
+ -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
"$SOC_TCK"
}
@@ -80,23 +80,24 @@ handle_slv_cdc [get_cells -hier gen_l2.i_reconfigurable_l2]/gen_cdc_fifos[0].i_d
proc handle_mst_cdc { mst_cdc_path } {
upvar SOC_TCK SOC_TCK
# Get the dst_cdc in cheshire
- set slv_cdc_path [lindex [regexp -inline {.*gen_ext_mst_dst_cdc\[[0-9]*\]} [lindex [filter [all_fanout -flat [get_pins $mst_cdc_path/*wptr*]] -filter {NAME =~ *gen_ext_mst_dst_cdc*}] 0]] 0]
+ set slv_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_mst_cdc_dst|.*i_intcluster_mst_cdc} [lindex [filter [all_fanout -flat [get_pins $mst_cdc_path/*wptr*]] -filter {NAME =~ *gen_ext_mst_dst_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0]
+
if { $slv_cdc_path != "" } {
# From Safety Island master
set_max_delay -datapath \
-from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
- -to [get_pins $slv_cdc_path.i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \
+ -to [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \
"$SOC_TCK"
set_max_delay -datapath \
- -from [get_pins $slv_cdc_path.i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \
+ -from [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
-to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] \
"$SOC_TCK"
set_max_delay -datapath \
-from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
- -to [get_pins $slv_cdc_path.i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
+ -to [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
"$SOC_TCK"
set_max_delay -datapath \
- -from [get_pins $slv_cdc_path.i_cheshire_ext_mst_cdc_dst/i_cdc_fifo_gray_*/*reg*/C] \
+ -from [get_pins $slv_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
-to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
"$SOC_TCK"
}
diff --git a/target/xilinx/flavor_bd/flavor_bd.mk b/target/xilinx/flavor_bd/flavor_bd.mk
index 4a21fc3bb..1af13dfe9 100644
--- a/target/xilinx/flavor_bd/flavor_bd.mk
+++ b/target/xilinx/flavor_bd/flavor_bd.mk
@@ -45,7 +45,7 @@ $(CAR_XIL_DIR)/flavor_bd/scripts/add_includes.tcl:
$(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(xilinx_ips_paths_bd) $(CAR_XIL_DIR)/flavor_bd/scripts/add_includes.tcl
mkdir -p $(CAR_XIL_DIR)/flavor_bd/out
cd $(CAR_XIL_DIR)/flavor_bd && $(vivado_env_bd) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl
- find $(CAR_XIL_DIR)/flavor_bd -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_bd/out
+ find $(CAR_XIL_DIR)/flavor_bd/carfield* -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_bd/out
.PRECIOUS: $(CAR_XIL_DIR)/flavor_bd/out/%.bit
car-xil-clean-bd:
diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
index fcf40ed66..8557d77db 100644
--- a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
+++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
@@ -406,10 +406,10 @@ proc create_root_design { parentCell } {
# Create instance: xdma_0, and set properties
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
set_property -dict [ list \
- CONFIG.PCIE_BOARD_INTERFACE {pci_express_x2} \
- CONFIG.PF0_DEVICE_ID_mqdma {9012} \
- CONFIG.PF2_DEVICE_ID_mqdma {9012} \
- CONFIG.PF3_DEVICE_ID_mqdma {9012} \
+ CONFIG.PCIE_BOARD_INTERFACE {pci_express_x4} \
+ CONFIG.PF0_DEVICE_ID_mqdma {9014} \
+ CONFIG.PF2_DEVICE_ID_mqdma {9014} \
+ CONFIG.PF3_DEVICE_ID_mqdma {9014} \
CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \
CONFIG.axi_addr_width {64} \
CONFIG.axisten_freq {125} \
@@ -419,18 +419,19 @@ proc create_root_design { parentCell } {
CONFIG.functional_mode {AXI_Bridge} \
CONFIG.mode_selection {Advanced} \
CONFIG.pf0_bar0_64bit {true} \
+ CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Gigabytes} \
CONFIG.pf0_bar0_size {4} \
- CONFIG.pf0_base_class_menu {Processing_accelerators} \
- CONFIG.pf0_class_code {120000} \
- CONFIG.pf0_class_code_base {12} \
- CONFIG.pf0_class_code_interface {00} \
- CONFIG.pf0_device_id {9012} \
+ CONFIG.pf0_base_class_menu {Simple_communication_controllers} \
+ CONFIG.pf0_class_code {070001} \
+ CONFIG.pf0_class_code_base {07} \
+ CONFIG.pf0_class_code_interface {01} \
+ CONFIG.pf0_device_id {9014} \
CONFIG.pf0_msix_cap_pba_bir {BAR_1:0} \
CONFIG.pf0_msix_cap_table_bir {BAR_1:0} \
- CONFIG.pf0_sub_class_interface_menu {Unknown} \
+ CONFIG.pf0_sub_class_interface_menu {16450_compatible_serial_controller} \
CONFIG.pl_link_cap_max_link_speed {2.5_GT/s} \
- CONFIG.pl_link_cap_max_link_width {X2} \
+ CONFIG.pl_link_cap_max_link_width {X4} \
CONFIG.plltype {CPLL} \
CONFIG.xdma_axilite_slave {true} \
] $xdma_0
@@ -511,11 +512,11 @@ proc create_root_design { parentCell } {
assign_bd_address -offset 0x41E00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
assign_bd_address -offset 0x40C00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_ethernet_0/s_axi/Reg0] -force
assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/dram_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force
+ assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_B/BAR0] -force
assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_B] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force
# Exclude Address Segments
- exclude_bd_addr_seg -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG]
- exclude_bd_addr_seg -offset 0x76000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_B/BAR0]
+ exclude_bd_addr_seg -offset 0x78000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG]
exclude_bd_addr_seg -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces carfield_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs xdma_0/S_AXI_LITE/CTL0]
diff --git a/target/xilinx/flavor_vanilla/flavor_vanilla.mk b/target/xilinx/flavor_vanilla/flavor_vanilla.mk
index 4302e9514..ecbf97af5 100644
--- a/target/xilinx/flavor_vanilla/flavor_vanilla.mk
+++ b/target/xilinx/flavor_vanilla/flavor_vanilla.mk
@@ -48,7 +48,7 @@ $(CAR_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl: Bender.yml
$(CAR_XIL_DIR)/flavor_vanilla/out/%.bit: $(xilinx_ips_paths_vanilla) $(CAR_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl
@mkdir -p $(CAR_XIL_DIR)/flavor_vanilla/out
cd $(CAR_XIL_DIR)/flavor_vanilla && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl
- find $(CAR_XIL_DIR)/flavor_vanilla -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_vanilla/out
+ find $(CAR_XIL_DIR)/flavor_vanilla/carfield* -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_vanilla/out
.PRECIOUS: $(CAR_XIL_DIR)/flavor_vanilla/out/%.bit
car-xil-clean-vanilla:
diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk
index 14424794e..14fb43475 100644
--- a/target/xilinx/xilinx.mk
+++ b/target/xilinx/xilinx.mk
@@ -18,12 +18,14 @@ XILINX_FLAVOR ?= bd
# Board in {vcu128}
XILINX_BOARD ?= vcu128
+XILINX_PORT ?= 3121
+XILINX_FPGA_PATH ?= xilinx_tcf/Xilinx/*
+XILINX_HOST ?= localhost
+XILINX_BOOT_ETH ?= 0
+
ifeq ($(XILINX_BOARD),vcu128)
xilinx_part := xcvu37p-fsvh2892-2L-e
xilinx_board_long := xilinx.com:vcu128:part0:1.0
- XILINX_PORT ?= 3232
- XILINX_FPGA_PATH ?= xilinx_tcf/Xilinx/091847100638A
- XILINX_HOST ?= bordcomputer
endif
XILINX_USE_ARTIFACTS ?= 0