diff --git a/hw/carfield.sv b/hw/carfield.sv index c8488cc60..65713a24d 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -432,7 +432,7 @@ logic security_island_isolate_req; logic [iomsb(Cfg.AxiExtNumSlv):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp; -// All AXI Slaves (except the Integer Cluster and the Mailbox) +// All AXI Slaves (except the Mailbox) logic [iomsb(NumSlaveCDCs):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_aw_wptr; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_aw_rptr; @@ -449,7 +449,7 @@ logic [iomsb(NumSlaveCDCs):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_wptr ; logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_slv_ext_r_rptr ; -// All AXI Masters (except the Integer Cluster) +// All AXI Masters logic [iomsb(Cfg.AxiExtNumMst):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data; logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_wptr; logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_mst_ext_aw_rptr; @@ -767,6 +767,7 @@ cheshire_wrap #( .cheshire_reg_ext_rsp_t ( carfield_reg_rsp_t ), .LogDepth ( LogDepth ), .CdcSyncStages ( SyncStages ), + . ( NumSlaveCDCs ), .AxiIn ( AxiIn ), .AxiOut ( AxiOut ) ) i_cheshire_wrap ( @@ -796,7 +797,7 @@ cheshire i_cheshire_wrap ( .llc_mst_w_data_o ( llc_w_data ), .llc_mst_w_wptr_o ( llc_w_wptr ), .llc_mst_w_rptr_i ( llc_w_rptr ), - // External AXI slave devices (except the Integer Cluster) + // External AXI slave devices .axi_ext_slv_isolate_i ( slave_isolate_req ), .axi_ext_slv_isolated_o ( slave_isolated_rsp ), .axi_ext_slv_ar_data_o ( axi_slv_ext_ar_data ), @@ -814,7 +815,7 @@ cheshire i_cheshire_wrap ( .axi_ext_slv_w_data_o ( axi_slv_ext_w_data ), .axi_ext_slv_w_wptr_o ( axi_slv_ext_w_wptr ), .axi_ext_slv_w_rptr_i ( axi_slv_ext_w_rptr ), - // External AXI master devices (except the Integer Cluster) + // External AXI master devices .axi_ext_mst_ar_data_i ( axi_mst_ext_ar_data ), .axi_ext_mst_ar_wptr_i ( axi_mst_ext_ar_wptr ), .axi_ext_mst_ar_rptr_o ( axi_mst_ext_ar_rptr ), diff --git a/hw/cheshire_wrap.sv b/hw/cheshire_wrap.sv index eb3e822be..58882b7de 100644 --- a/hw/cheshire_wrap.sv +++ b/hw/cheshire_wrap.sv @@ -43,6 +43,9 @@ module cheshire_wrap parameter type cheshire_reg_ext_rsp_t = logic, parameter int unsigned LogDepth = 3, parameter int unsigned CdcSyncStages = 2, + // External Slaves Parameters + // Having a dedicated synchronous port, the mailbox is not taken into account + parameter int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - 1, parameter axi_in_t AxiIn = gen_axi_in(Cfg) , parameter axi_out_t AxiOut = gen_axi_out(Cfg), // LLC Parameters @@ -67,9 +70,6 @@ module cheshire_wrap localparam int unsigned LlcWWidth = (2**LogDepth)* axi_pkg::w_width(Cfg.AxiDataWidth, Cfg.AxiUserWidth), - // External Slaves Parameters - // Having a dedicated synchronous port, the mailbox is not taken into account - localparam int unsigned NumSlaveCDCs = Cfg.AxiExtNumSlv - 1, localparam int unsigned ExtSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(AxiIn.num_in ), localparam int unsigned ExtSlvArWidth = (2**LogDepth)* @@ -136,7 +136,7 @@ module cheshire_wrap // External AXI isolate slave Ports (except the Mailbox) input logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolate_i, output logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolated_o, - // External async AXI slave Ports (except the Integer Cluster and the Mailbox) + // External async AXI slave Ports (except the Mailbox) output logic [iomsb(NumSlaveCDCs):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o, output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_wptr_o, input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_ar_rptr_i, @@ -152,7 +152,7 @@ module cheshire_wrap output logic [iomsb(NumSlaveCDCs):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o , output logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_wptr_o , input logic [iomsb(NumSlaveCDCs):0][ LogDepth:0] axi_ext_slv_w_rptr_i , - // External async AXI master Ports (except the Integer Cluster) + // External async AXI master Ports input logic [iomsb(Cfg.AxiExtNumMst):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i, input logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_wptr_i, output logic [iomsb(Cfg.AxiExtNumMst):0][ LogDepth:0] axi_ext_mst_ar_rptr_o, @@ -358,8 +358,7 @@ cheshire_soc #( .vga_blue_o ); -// Cheshire's AXI master cdc generation, except for the Integer Cluster (slave 6) and the Mailbox -// (slave 7) +// Cheshire's AXI master cdc generation, the Mailbox (slave 7) for (genvar i = 0; i < NumSlaveCDCs; i++) begin: gen_ext_slv_src_cdc axi_isolate #( .NumPending ( Cfg.AxiMaxSlvTrans ), @@ -417,7 +416,7 @@ for (genvar i = 0; i < NumSlaveCDCs; i++) begin: gen_ext_slv_src_cdc ); end -// Cheshire's AXI slave cdc and isolate generation, except for the Integer Cluster (slave 7) +// Cheshire's AXI slave cdc and isolate generation for (genvar i = 0; i < Cfg.AxiExtNumMst; i++) begin: gen_ext_mst_dst_cdc axi_cdc_dst #( .LogDepth ( LogDepth ),