From ebdce0ea52b14338dc4060133ed91b91943ba462 Mon Sep 17 00:00:00 2001
From: Yvan Tortorella <48508508+yvantor@users.noreply.github.com>
Date: Tue, 12 Mar 2024 18:22:06 +0100
Subject: [PATCH] Fix configurable top level bugs and integrate CI flow. (#2)

* Bump dependencies and align testbench with new Cheshire JTAG tasks.

* Fix connections.

* Align cache-enable CSR with OpenHW recent changes...

* Add draft CI flow.

* Use normal printf in `Helloworld`.

* Update nonfree rules.

* Fix parameter declaration in L2 Ecc asyncronoys buses.

* Fix PULP cluster EOC and busy enable connections.

* Update nonfree.

* Bump nonfree.

* Bump nonfree to copy uImage in dedicated `astral` folder.

* Apply suggestions from code review

Co-authored-by: Michael Rogenmoser <michael@rogenmoser.us>

---------

Co-authored-by: Yvan Tortorella <ytortorella@lagrev3.ee.ethz.ch>
Co-authored-by: Michael Rogenmoser <michael@rogenmoser.us>
---
 hw/carfield.sv                | 4 +---
 target/sim/src/carfield_tb.sv | 4 ++--
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/hw/carfield.sv b/hw/carfield.sv
index d4972acb1..89302e829 100644
--- a/hw/carfield.sv
+++ b/hw/carfield.sv
@@ -669,7 +669,7 @@ for (genvar i=0; i<NumSyncRegSlv; i++ ) begin : gen_chs_ext_reg_cut
   );
 end
 
-// Passsing the `ext_reg_req_cut[CarfieldRegBusSlvIdx.pcrs]` value to the
+// Passing the `ext_reg_req_cut[CarfieldRegBusSlvIdx.pcrs]` value to the
 // reg_req_i/rsp_o buses results in Questa's `Fatal: Unexpected signal: 11.`
 // at compile time. Direct casting 'int(CarfieldRegBusSlvIdx.pcrs) also does
 // not work resulting in the ext_reg_rsp_cut bus being all X. The localparam
@@ -1098,14 +1098,12 @@ if (CarfieldIslandsCfg.l2_port0.enable) begin: gen_l2
     .slvport_w_data_i    ( axi_slv_ext_w_data  [NumL2Ports-1:0] ),
     .slvport_w_wptr_i    ( axi_slv_ext_w_wptr  [NumL2Ports-1:0] ),
     .slvport_w_rptr_o    ( axi_slv_ext_w_rptr  [NumL2Ports-1:0] ),
-    // verilog_lint: waive-start line-length
     .l2_ecc_reg_async_mst_req_i  ( ext_reg_async_slv_req_out [EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_ack_o  ( ext_reg_async_slv_ack_in  [EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_data_i ( ext_reg_async_slv_data_out[EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_req_o  ( ext_reg_async_slv_req_in  [EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_ack_i  ( ext_reg_async_slv_ack_out [EccAsyncIdx] ),
     .l2_ecc_reg_async_mst_data_o ( ext_reg_async_slv_data_in [EccAsyncIdx] ),
-    // verilog_lint: waive-stop line-length
     .ecc_error_o         ( l2_ecc_err                           )
   );
 end else begin: gen_no_l2
diff --git a/target/sim/src/carfield_tb.sv b/target/sim/src/carfield_tb.sv
index 5887e60b4..fcbc442d7 100644
--- a/target/sim/src/carfield_tb.sv
+++ b/target/sim/src/carfield_tb.sv
@@ -485,8 +485,8 @@ module tb_carfield_soc;
             fix.chs_vip.jtag_elf_halt_load(spatzd_preload_elf, spatzd_binary_entry );
 
             // write start address into the csr
-            $display("[JTAG SPATZD] write the CSR %x of spatz with the entry point %x", SpatzClusterPeriphStartAddr + SpatzClusterPeripheralBootControlOffset, spatzd_binary_entry);
-            fix.chs_vip.jtag_write_reg32(SpatzClusterPeriphStartAddr + SpatzClusterPeripheralBootControlOffset, spatzd_binary_entry, jtag_check_write);
+            $display("[JTAG SPATZD] write the CSR %x of spatz with the entry point %x", spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry);
+            fix.chs_vip.jtag_write_reg32(spatz_cluster_pkg::PeriStartAddr + spatz_cluster_peripheral_reg_pkg::SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET, spatzd_binary_entry, jtag_check_write);
 
             // Set interrupt on mailbox mailbox id MBOX_SPATZD_CORE0_ID and MBOX_SPATZD_CORE1_ID
             spatzd_reg_value = 64'h1;