From e35f79c5c4e5f723beb6500194d51cb68048b5eb Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 10 Sep 2024 18:31:40 +0200 Subject: [PATCH] Fix Ethernet test. --- Bender.lock | 2 +- Bender.yml | 2 +- sw/include/fll.h | 9 ++++- sw/tests/bare-metal/hostd/ethernet.c | 51 ++++++++++++++-------------- target/sim/src/astral_fix.sv | 10 +----- target/sim/src/vip_carfield_soc.sv | 19 +++++++---- 6 files changed, 48 insertions(+), 45 deletions(-) diff --git a/Bender.lock b/Bender.lock index 1860e87e..fb6f5492 100644 --- a/Bender.lock +++ b/Bender.lock @@ -409,7 +409,7 @@ packages: dependencies: - axi_slice pulp-ethernet: - revision: 1f8f1776ec494773f8e6c48e16685eb35d5f445e + revision: 2bea11658d2bc368ae2af0a3f71b4253ba4f713f version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index c4d657e8..69fac9c3 100644 --- a/Bender.yml +++ b/Bender.yml @@ -26,7 +26,7 @@ dependencies: can_bus: { git: https://github.com/AlSaqr-platform/can_bus.git, rev: 0ec0bf8b7dab6d5e4b3f7ec58338a8efee066379 } # branch: pulp spatz: { git: https://github.com/pulp-platform/spatz.git, rev: 98de97f24fe42675c9b4a8cc08354a03af57400a } # branch: yt/astral common_cells: { git: https://github.com/pulp-platform/common_cells.git, version: 1.37.0 } # branch: master - pulp-ethernet: { git: https://github.com/pulp-platform/pulp-ethernet.git, rev: 1f8f1776ec494773f8e6c48e16685eb35d5f445e } # branch: handshake + pulp-ethernet: { git: https://github.com/pulp-platform/pulp-ethernet.git, rev: 2bea11658d2bc368ae2af0a3f71b4253ba4f713f } # branch: handshake riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg.git, version: =0.8.0 } streamer: { path: /usr/scratch2/lagrev5/mciani/astral-project/streamer } spacewire: { path: /usr/scratch2/lagrev5/mciani/astral-project/spacewire } diff --git a/sw/include/fll.h b/sw/include/fll.h index e68d37d5..c30e6e40 100644 --- a/sw/include/fll.h +++ b/sw/include/fll.h @@ -66,9 +66,16 @@ void set_fll_clk_mul(uint32_t clk_mul, uint8_t fll_id){ // The following API uses a default divider by 2 to program the peripheral FLL void set_periph_fll_div2(uint32_t clk_freq){ unsigned int divdier = 2; - fll_normal(FLL_PERIPH_ID); set_fll_clk_mul((divdier*clk_freq) - 1, FLL_PERIPH_ID); set_fll_clk_div(divdier, FLL_PERIPH_ID); + fll_normal(FLL_PERIPH_ID); +} + +void set_host_fll_div2(uint32_t clk_freq){ + unsigned int divdier = 2; + set_fll_clk_mul((divdier*clk_freq) - 1, FLL_HOST_ID); + set_fll_clk_div(divdier, FLL_HOST_ID); + fll_normal(FLL_HOST_ID); } #endif /*__FLL_H*/ diff --git a/sw/tests/bare-metal/hostd/ethernet.c b/sw/tests/bare-metal/hostd/ethernet.c index cde3c2c4..2245fefb 100644 --- a/sw/tests/bare-metal/hostd/ethernet.c +++ b/sw/tests/bare-metal/hostd/ethernet.c @@ -8,7 +8,6 @@ #include "car_memory_map.h" #include "io.h" #include "sw/device/lib/dif/dif_rv_plic.h" -#include "regs/system_timer.h" #include #include #include @@ -24,16 +23,16 @@ static dif_rv_plic_t plic0; #define MACLO_OFFSET 0x0 #define MACHI_OFFSET 0x4 -#define IRQ_OFFSET 0x10 -#define IDMA_SRC_ADDR_OFFSET 0x14 -#define IDMA_DST_ADDR_OFFSET 0x18 -#define IDMA_LENGTH_OFFSET 0x1c -#define IDMA_SRC_PROTO_OFFSET 0x20 -#define IDMA_DST_PROTO_OFFSET 0x24 -#define IDMA_REQ_VALID_OFFSET 0x3c -#define IDMA_REQ_READY_OFFSET 0x40 -#define IDMA_RSP_READY_OFFSET 0x44 -#define IDMA_RSP_VALID_OFFSET 0x48 +#define IDMA_SRC_ADDR_OFFSET 0x1c +#define IDMA_DST_ADDR_OFFSET 0x20 +#define IDMA_LENGTH_OFFSET 0x24 +#define IDMA_SRC_PROTO_OFFSET 0x28 +#define IDMA_DST_PROTO_OFFSET 0x2c +#define IDMA_REQ_VALID_OFFSET 0x44 +#define IDMA_REQ_READY_OFFSET 0x48 +#define IDMA_RSP_READY_OFFSET 0x4c +#define IDMA_RSP_VALID_OFFSET 0x50 +#define IDMA_RX_EN_OFFSET 0x54 #define RV_PLIC_PRIO87_REG_OFFSET 0x15c #define RV_PLIC_IE0_2_REG_OFFSET 0x2008 @@ -49,7 +48,7 @@ static dif_rv_plic_t plic0; #define L2_TX_BASE 0x78000000 #define L2_RX_BASE 0x78001000 -#define FLL_WAIT_CYCLES 10000 +#define FLL_WAIT_CYCLES 50000 int main(void) { @@ -60,6 +59,7 @@ int main(void) { padframe_ethernet_cfg(); // Setup the peripheral FLL to work at 500 MHz + set_host_fll_div2(500 /* MHz */); set_periph_fll_div2(500 /* MHz */); // Wait for FLL clk out to stabilize @@ -82,8 +82,8 @@ int main(void) { t = dif_rv_plic_irq_set_enabled(&plic0, IRQID, 0, kDifToggleEnabled); volatile uint64_t data_to_write[DATA_CHUNK] = { - 0x1032207098001032, - 0x3210E20020709800, + 0x0207230100890702, + 0x3210400020709800, 0x1716151413121110, 0x2726252423222120, 0x3736353433323130, @@ -99,38 +99,37 @@ int main(void) { } fencei(); - //// TX test + // TX test // Low 32 bit MAC Address - *reg32(CAR_ETHERNET_BASE_ADDR, MACLO_OFFSET) = 0x98001032; + *reg32(CAR_ETHERNET_BASE_ADDR, MACLO_OFFSET) = 0x00890702; // High 16 bit Mac Address - *reg32(CAR_ETHERNET_BASE_ADDR, MACHI_OFFSET) = 0x00002070; + *reg32(CAR_ETHERNET_BASE_ADDR, MACHI_OFFSET) = 0x00002301; // DMA Source Address *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_ADDR_OFFSET) = L2_TX_BASE; // DMA Destination Address - *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_DST_ADDR_OFFSET) = 0x14000000; + *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_DST_ADDR_OFFSET) = 0x0; // Data length *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; // Source Protocol - *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_PROTO_OFFSET) = 0x5; + *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_PROTO_OFFSET) = 0x0; // Destination Protocol *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_DST_PROTO_OFFSET) = 0x5; // Validate Request to DMA *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_REQ_VALID_OFFSET) = 0x1; - - wfi(); // rx irq // RX test - // Low 32 bit MAC Address - *reg32(CAR_ETHERNET_BASE_ADDR, MACLO_OFFSET) = 0x98001032; + wfi(); // rx irq + // Low 32 bit MAC Address + *reg32(CAR_ETHERNET_BASE_ADDR, MACLO_OFFSET) = 0x00890702; // High 16 bit Mac Address - *reg32(CAR_ETHERNET_BASE_ADDR, MACHI_OFFSET) = 0x00002070; + *reg32(CAR_ETHERNET_BASE_ADDR, MACHI_OFFSET) = 0x00002301; + // dma length ready, dma can be configured now + while (!(*reg32(CAR_ETHERNET_BASE_ADDR,IDMA_RX_EN_OFFSET))); // DMA Source Address *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_ADDR_OFFSET) = 0x0; // DMA Destination Address *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_DST_ADDR_OFFSET) = L2_RX_BASE; - // Data length - *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; // Source Protocol *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_PROTO_OFFSET) = 0x5; // Destination Protocol diff --git a/target/sim/src/astral_fix.sv b/target/sim/src/astral_fix.sv index 40f545e9..5e7a3315 100644 --- a/target/sim/src/astral_fix.sv +++ b/target/sim/src/astral_fix.sv @@ -372,14 +372,6 @@ module astral_fixture; // CAN // TODO connect assign w_can_rx = '0; - // Ethernet - // TODO connect - assign w_eth_rxck = '0; - assign w_eth_rxctl = '0; - assign w_eth_rxd0 = '0; - assign w_eth_rxd1 = '0; - assign w_eth_rxd2 = '0; - assign w_eth_rxd3 = '0; // PLL JTAG assign w_jtag_pll_tck = jtag_pll_tck; assign w_jtag_pll_tms = jtag_pll_tms; @@ -778,7 +770,7 @@ module astral_fixture; .eth_rxd ( w_eth_rxd ), .eth_txck ( w_eth_txck ), .eth_rxck ( w_eth_rxck ), - .eth_txctl ( w_eth_rxctl ), + .eth_txctl ( w_eth_txctl ), .eth_rxctl ( w_eth_rxctl ), .eth_rstn ( w_eth_rst ), .eth_mdio ( w_eth_md ), diff --git a/target/sim/src/vip_carfield_soc.sv b/target/sim/src/vip_carfield_soc.sv index b6edb10e..420e3e71 100644 --- a/target/sim/src/vip_carfield_soc.sv +++ b/target/sim/src/vip_carfield_soc.sv @@ -125,6 +125,7 @@ module vip_carfield_soc logic reg_error; logic [RegDw-1:0] rx_rsp_valid; + logic dma_rx_en; typedef reg_test::reg_driver #( .AW(RegAw), @@ -218,21 +219,25 @@ module vip_carfield_soc @(posedge periph_clk); @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACLO_ADDR_OFFSET, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_LOW_ADDR_OFFSET, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_MDIO_OFFSET, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_OFFSET, 32'h00002301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge periph_clk); + while(1) begin + reg_drv_rx.send_read( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DMA_RX_EN_OFFSET, dma_rx_en, reg_error); // req ready + if( dma_rx_en ) + break; + @(posedge periph_clk); + end + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_ADDR_OFFSET, 32'h0, 'hf, reg_error ); // SRC_ADDR @(posedge periph_clk); reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_ADDR_OFFSET, 32'h0, 'hf, reg_error); // DST_ADDR @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_LENGTH_OFFSET, 32'h40,'hf , reg_error); // Size in bytes - @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_PROTOCOL_OFFSET, 32'h5, 'hf , reg_error); // src protocol @(posedge periph_clk); @@ -253,10 +258,10 @@ module vip_carfield_soc // Tx test starts here: external back to core @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACLO_ADDR_OFFSET, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_LOW_ADDR_OFFSET, 32'h00890702, 'hf, reg_error); //lower 32bits of MAC address @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_MDIO_OFFSET, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_OFFSET, 32'h00002301, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 @(posedge periph_clk); reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_ADDR_OFFSET, 32'h0, 'hf, reg_error ); // SRC_ADDR