Please add missing Verilog files

[Ringel]

Could You please add the files in projects/DE2_115_NIOS_Ethernet_Test/src/cpu

[progranism]

DE2-115 NIOS with Ethernet support is experimental and currently under development. The CPU code is generated by SOPC Builder and is quite bloated. It may also be proprietary, depending on Altera's policies. So, I have not committed that code.

When I have finished that particular variation of the project, I will check Altera's policy and commit if possible. I will also be looking for an open-source alternative to SOPC and NIOS and replace them both when I can.

[db4rne]

I'm almost sure it is not possible to open source a NIOS design. instead, you could use a open source core such as openrisc (http://opencores.org/project,or1k) or pacoblaze (http://bleyer.org/pacoblaze/).

[sjaeckel]

In my opinion you can open source the sopc configuration and everybody can generate his own cpu with the altera toolchain (sopc builder/qsys).

[aaronferrucci]

Adding the minimal set of files needed to generate the design is a good way to go. In other words, don't check in the generated HDL from SOPC Builder - check in the .sopc file instead. Think of the generated HDL as object files - you'd include your .c files for the software application, but not your .o, .a, et al.