Writing My Own TestBench

[izaakwhite]

Hi, I am currently working on researching CGRAs. I was wondering if you had any tips for writing a test harness. My goal is to have the MemUnit tile send out a bit called accessBit that checks if a memory address is in bounds and then sends it to the next tile.

[tancheng]

For CGRA research, you can use this repo instead: https://github.com/tancheng/VectorCGRA

For unit test, you can see how systolic array for matmul is configured: https://github.com/tancheng/VectorCGRA/blob/37456a3f15503e8de5d1a592330ff68bd249872b/systolic/test/SystolicCL_test.py#L109

You can also take a look at the fir mapping config signals: https://github.com/tancheng/VectorCGRA/blob/master/cgra/test/config_fir.json

We don't have a straightforward way to manually set the config signals for e2e test yet. I suggest you start from simple (e.g., single cycle or two cycles) config and carefully set the signals like this: https://github.com/tancheng/VectorCGRA/blob/37456a3f15503e8de5d1a592330ff68bd249872b/cgra/test/CGRARTL_test.py#L138